hw/intc/xics_spapr.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "cpu.h"
  30 #include "hw/hw.h"
  31 #include "trace.h"
  32 #include "qemu/timer.h"
  33 #include "hw/ppc/spapr.h"
  34 #include "hw/ppc/xics.h"
  35 #include "qapi/visitor.h"
  36 #include "qapi/error.h"
  37
  38 /*
  39  * Guest interfaces
  40  */
  41
  42 static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
  43                            target_ulong opcode, target_ulong *args)
  44 {
  45     CPUState *cs = CPU(cpu);
  46     target_ulong cppr = args[0];
  47
  48     icp_set_cppr(spapr->xics, cs->cpu_index, cppr);
  49     return H_SUCCESS;
  50 }
  51
  52 static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
  53                           target_ulong opcode, target_ulong *args)
  54 {
  55     target_ulong server = xics_get_cpu_index_by_dt_id(args[0]);
  56     target_ulong mfrr = args[1];
  57
  58     if (server >= spapr->xics->nr_servers) {
  59         return H_PARAMETER;
  60     }
  61
  62     icp_set_mfrr(spapr->xics, server, mfrr);
  63     return H_SUCCESS;
  64 }
  65
  66 static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
  67                            target_ulong opcode, target_ulong *args)
  68 {
  69     CPUState *cs = CPU(cpu);
  70     uint32_t xirr = icp_accept(spapr->xics->ss + cs->cpu_index);
  71
  72     args[0] = xirr;
  73     return H_SUCCESS;
  74 }
  75
  76 static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
  77                              target_ulong opcode, target_ulong *args)
  78 {
  79     CPUState *cs = CPU(cpu);
  80     ICPState *ss = &spapr->xics->ss[cs->cpu_index];
  81     uint32_t xirr = icp_accept(ss);
  82
  83     args[0] = xirr;
  84     args[1] = cpu_get_host_ticks();
  85     return H_SUCCESS;
  86 }
  87
  88 static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
  89                           target_ulong opcode, target_ulong *args)
  90 {
  91     CPUState *cs = CPU(cpu);
  92     target_ulong xirr = args[0];
  93
  94     icp_eoi(spapr->xics, cs->cpu_index, xirr);
  95     return H_SUCCESS;
  96 }
  97
  98 static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
  99                             target_ulong opcode, target_ulong *args)
 100 {
 101     CPUState *cs = CPU(cpu);
 102     uint32_t mfrr;
 103     uint32_t xirr = icp_ipoll(spapr->xics->ss + cs->cpu_index, &mfrr);
 104
 105     args[0] = xirr;
 106     args[1] = mfrr;
 107
 108     return H_SUCCESS;
 109 }
 110
 111 static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 112                           uint32_t token,
 113                           uint32_t nargs, target_ulong args,
 114                           uint32_t nret, target_ulong rets)
 115 {
 116     ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
 117     uint32_t nr, srcno, server, priority;
 118
 119     if ((nargs != 3) || (nret != 1)) {
 120         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 121         return;
 122     }
 123     if (!ics) {
 124         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 125         return;
 126     }
 127
 128     nr = rtas_ld(args, 0);
 129     server = xics_get_cpu_index_by_dt_id(rtas_ld(args, 1));
 130     priority = rtas_ld(args, 2);
 131
 132     if (!ics_valid_irq(ics, nr) || (server >= ics->xics->nr_servers)
 133         || (priority > 0xff)) {
 134         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 135         return;
 136     }
 137
 138     srcno = nr - ics->offset;
 139     ics_simple_write_xive(ics, srcno, server, priority, priority);
 140
 141     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 142 }
 143
 144 static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 145                           uint32_t token,
 146                           uint32_t nargs, target_ulong args,
 147                           uint32_t nret, target_ulong rets)
 148 {
 149     ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
 150     uint32_t nr, srcno;
 151
 152     if ((nargs != 1) || (nret != 3)) {
 153         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 154         return;
 155     }
 156     if (!ics) {
 157         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 158         return;
 159     }
 160
 161     nr = rtas_ld(args, 0);
 162
 163     if (!ics_valid_irq(ics, nr)) {
 164         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 165         return;
 166     }
 167
 168     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 169     srcno = nr - ics->offset;
 170     rtas_st(rets, 1, ics->irqs[srcno].server);
 171     rtas_st(rets, 2, ics->irqs[srcno].priority);
 172 }
 173
 174 static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 175                          uint32_t token,
 176                          uint32_t nargs, target_ulong args,
 177                          uint32_t nret, target_ulong rets)
 178 {
 179     ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
 180     uint32_t nr, srcno;
 181
 182     if ((nargs != 1) || (nret != 1)) {
 183         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 184         return;
 185     }
 186     if (!ics) {
 187         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 188         return;
 189     }
 190
 191     nr = rtas_ld(args, 0);
 192
 193     if (!ics_valid_irq(ics, nr)) {
 194         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 195         return;
 196     }
 197
 198     srcno = nr - ics->offset;
 199     ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
 200                           ics->irqs[srcno].priority);
 201
 202     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 203 }
 204
 205 static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
 206                         uint32_t token,
 207                         uint32_t nargs, target_ulong args,
 208                         uint32_t nret, target_ulong rets)
 209 {
 210     ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
 211     uint32_t nr, srcno;
 212
 213     if ((nargs != 1) || (nret != 1)) {
 214         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 215         return;
 216     }
 217     if (!ics) {
 218         rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
 219         return;
 220     }
 221
 222     nr = rtas_ld(args, 0);
 223
 224     if (!ics_valid_irq(ics, nr)) {
 225         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 226         return;
 227     }
 228
 229     srcno = nr - ics->offset;
 230     ics_simple_write_xive(ics, srcno, ics->irqs[srcno].server,
 231                           ics->irqs[srcno].saved_priority,
 232                           ics->irqs[srcno].saved_priority);
 233
 234     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 235 }
 236
 237 static void xics_spapr_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
 238                                    Error **errp)
 239 {
 240     ICSState *ics = QLIST_FIRST(&xics->ics);
 241
 242     /* This needs to be deprecated ... */
 243     xics->nr_irqs = nr_irqs;
 244     if (ics) {
 245         ics->nr_irqs = nr_irqs;
 246     }
 247 }
 248
 249 static void xics_spapr_set_nr_servers(XICSState *xics, uint32_t nr_servers,
 250                                       Error **errp)
 251 {
 252     int i;
 253
 254     xics->nr_servers = nr_servers;
 255
 256     xics->ss = g_malloc0(xics->nr_servers * sizeof(ICPState));
 257     for (i = 0; i < xics->nr_servers; i++) {
 258         char buffer[32];
 259         object_initialize(&xics->ss[i], sizeof(xics->ss[i]), TYPE_ICP);
 260         snprintf(buffer, sizeof(buffer), "icp[%d]", i);
 261         object_property_add_child(OBJECT(xics), buffer, OBJECT(&xics->ss[i]),
 262                                   errp);
 263     }
 264 }
 265
 266 static void xics_spapr_realize(DeviceState *dev, Error **errp)
 267 {
 268     XICSState *xics = XICS_SPAPR(dev);
 269     ICSState *ics;
 270     Error *error = NULL;
 271     int i;
 272
 273     if (!xics->nr_servers) {
 274         error_setg(errp, "Number of servers needs to be greater 0");
 275         return;
 276     }
 277
 278     /* Registration of global state belongs into realize */
 279     spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
 280     spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
 281     spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
 282     spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
 283
 284     spapr_register_hypercall(H_CPPR, h_cppr);
 285     spapr_register_hypercall(H_IPI, h_ipi);
 286     spapr_register_hypercall(H_XIRR, h_xirr);
 287     spapr_register_hypercall(H_XIRR_X, h_xirr_x);
 288     spapr_register_hypercall(H_EOI, h_eoi);
 289     spapr_register_hypercall(H_IPOLL, h_ipoll);
 290
 291     QLIST_FOREACH(ics, &xics->ics, list) {
 292         object_property_set_bool(OBJECT(ics), true, "realized", &error);
 293         if (error) {
 294             error_propagate(errp, error);
 295             return;
 296         }
 297     }
 298
 299     for (i = 0; i < xics->nr_servers; i++) {
 300         object_property_set_bool(OBJECT(&xics->ss[i]), true, "realized",
 301                                  &error);
 302         if (error) {
 303             error_propagate(errp, error);
 304             return;
 305         }
 306     }
 307 }
 308
 309 static void xics_spapr_initfn(Object *obj)
 310 {
 311     XICSState *xics = XICS_SPAPR(obj);
 312     ICSState *ics;
 313
 314     ics = ICS_SIMPLE(object_new(TYPE_ICS_SIMPLE));
 315     object_property_add_child(obj, "ics", OBJECT(ics), NULL);
 316     ics->xics = xics;
 317     QLIST_INSERT_HEAD(&xics->ics, ics, list);
 318 }
 319
 320 static void xics_spapr_class_init(ObjectClass *oc, void *data)
 321 {
 322     DeviceClass *dc = DEVICE_CLASS(oc);
 323     XICSStateClass *xsc = XICS_SPAPR_CLASS(oc);
 324
 325     dc->realize = xics_spapr_realize;
 326     xsc->set_nr_irqs = xics_spapr_set_nr_irqs;
 327     xsc->set_nr_servers = xics_spapr_set_nr_servers;
 328 }
 329
 330 static const TypeInfo xics_spapr_info = {
 331     .name          = TYPE_XICS_SPAPR,
 332     .parent        = TYPE_XICS_COMMON,
 333     .instance_size = sizeof(XICSState),
 334     .class_size = sizeof(XICSStateClass),
 335     .class_init    = xics_spapr_class_init,
 336     .instance_init = xics_spapr_initfn,
 337 };
 338
 339 #define ICS_IRQ_FREE(ics, srcno)   \
 340     (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
 341
 342 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
 343 {
 344     int first, i;
 345
 346     for (first = 0; first < ics->nr_irqs; first += alignnum) {
 347         if (num > (ics->nr_irqs - first)) {
 348             return -1;
 349         }
 350         for (i = first; i < first + num; ++i) {
 351             if (!ICS_IRQ_FREE(ics, i)) {
 352                 break;
 353             }
 354         }
 355         if (i == (first + num)) {
 356             return first;
 357         }
 358     }
 359
 360     return -1;
 361 }
 362
 363 int xics_spapr_alloc(XICSState *xics, int irq_hint, bool lsi, Error **errp)
 364 {
 365     ICSState *ics = QLIST_FIRST(&xics->ics);
 366     int irq;
 367
 368     if (!ics) {
 369         return -1;
 370     }
 371     if (irq_hint) {
 372         if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
 373             error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
 374             return -1;
 375         }
 376         irq = irq_hint;
 377     } else {
 378         irq = ics_find_free_block(ics, 1, 1);
 379         if (irq < 0) {
 380             error_setg(errp, "can't allocate IRQ: no IRQ left");
 381             return -1;
 382         }
 383         irq += ics->offset;
 384     }
 385
 386     ics_set_irq_type(ics, irq - ics->offset, lsi);
 387     trace_xics_alloc(irq);
 388
 389     return irq;
 390 }
 391
 392 /*
 393  * Allocate block of consecutive IRQs, and return the number of the first IRQ in
 394  * the block. If align==true, aligns the first IRQ number to num.
 395  */
 396 int xics_spapr_alloc_block(XICSState *xics, int num, bool lsi, bool align,
 397                            Error **errp)
 398 {
 399     ICSState *ics = QLIST_FIRST(&xics->ics);
 400     int i, first = -1;
 401
 402     if (!ics) {
 403         return -1;
 404     }
 405
 406     /*
 407      * MSIMesage::data is used for storing VIRQ so
 408      * it has to be aligned to num to support multiple
 409      * MSI vectors. MSI-X is not affected by this.
 410      * The hint is used for the first IRQ, the rest should
 411      * be allocated continuously.
 412      */
 413     if (align) {
 414         assert((num == 1) || (num == 2) || (num == 4) ||
 415                (num == 8) || (num == 16) || (num == 32));
 416         first = ics_find_free_block(ics, num, num);
 417     } else {
 418         first = ics_find_free_block(ics, num, 1);
 419     }
 420     if (first < 0) {
 421         error_setg(errp, "can't find a free %d-IRQ block", num);
 422         return -1;
 423     }
 424
 425     if (first >= 0) {
 426         for (i = first; i < first + num; ++i) {
 427             ics_set_irq_type(ics, i, lsi);
 428         }
 429     }
 430     first += ics->offset;
 431
 432     trace_xics_alloc_block(first, num, lsi, align);
 433
 434     return first;
 435 }
 436
 437 static void ics_free(ICSState *ics, int srcno, int num)
 438 {
 439     int i;
 440
 441     for (i = srcno; i < srcno + num; ++i) {
 442         if (ICS_IRQ_FREE(ics, i)) {
 443             trace_xics_ics_free_warn(0, i + ics->offset);
 444         }
 445         memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
 446     }
 447 }
 448
 449 void xics_spapr_free(XICSState *xics, int irq, int num)
 450 {
 451     ICSState *ics = xics_find_source(xics, irq);
 452
 453     if (ics) {
 454         trace_xics_ics_free(0, irq, num);
 455         ics_free(ics, irq - ics->offset, num);
 456     }
 457 }
 458
 459 static void xics_spapr_register_types(void)
 460 {
 461     type_register_static(&xics_spapr_info);
 462 }
 463
 464 type_init(xics_spapr_register_types)