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From: John Arbuckle <programmingkidx@gmail.com>
[qemu.git] / linux-user / main.c
blob2c9658e90de48abf6d2a0d57d70a6e6b648f14ca
1 /*
2 * qemu user main
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <stdarg.h>
22 #include <string.h>
23 #include <errno.h>
24 #include <unistd.h>
25 #include <sys/mman.h>
26 #include <sys/syscall.h>
27 #include <sys/resource.h>
28
29 #include "qemu.h"
30 #include "qemu-common.h"
31 #include "cpu.h"
32 #include "tcg.h"
33 #include "qemu/timer.h"
34 #include "qemu/envlist.h"
35 #include "elf.h"
36
37 char *exec_path;
38
39 int singlestep;
40 const char *filename;
41 const char *argv0;
42 int gdbstub_port;
43 envlist_t *envlist;
44 static const char *cpu_model;
45 unsigned long mmap_min_addr;
46 unsigned long guest_base;
47 int have_guest_base;
48 #if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)
49 /*
50 * When running 32-on-64 we should make sure we can fit all of the possible
51 * guest address space into a contiguous chunk of virtual host memory.
52 *
53 * This way we will never overlap with our own libraries or binaries or stack
54 * or anything else that QEMU maps.
55 */
56 # ifdef TARGET_MIPS
57 /* MIPS only supports 31 bits of virtual address space for user space */
58 unsigned long reserved_va = 0x77000000;
59 # else
60 unsigned long reserved_va = 0xf7000000;
61 # endif
62 #else
63 unsigned long reserved_va;
64 #endif
65
66 static void usage(void);
67
68 static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;
69 const char *qemu_uname_release;
70
71 /* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so
72 we allocate a bigger stack. Need a better solution, for example
73 by remapping the process stack directly at the right place */
74 unsigned long guest_stack_size = 8 * 1024 * 1024UL;
75
76 void gemu_log(const char *fmt, ...)
77 {
78 va_list ap;
79
80 va_start(ap, fmt);
81 vfprintf(stderr, fmt, ap);
82 va_end(ap);
83 }
84
85 #if defined(TARGET_I386)
86 int cpu_get_pic_interrupt(CPUX86State *env)
87 {
88 return -1;
89 }
90 #endif
91
92 /***********************************************************/
93 /* Helper routines for implementing atomic operations. */
94
95 /* To implement exclusive operations we force all cpus to syncronise.
96 We don't require a full sync, only that no cpus are executing guest code.
97 The alternative is to map target atomic ops onto host equivalents,
98 which requires quite a lot of per host/target work. */
99 static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;
100 static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;
101 static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;
102 static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;
103 static int pending_cpus;
104
105 /* Make sure everything is in a consistent state for calling fork(). */
106 void fork_start(void)
107 {
108 pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);
109 pthread_mutex_lock(&exclusive_lock);
110 mmap_fork_start();
111 }
112
113 void fork_end(int child)
114 {
115 mmap_fork_end(child);
116 if (child) {
117 CPUState *cpu, *next_cpu;
118 /* Child processes created by fork() only have a single thread.
119 Discard information about the parent threads. */
120 CPU_FOREACH_SAFE(cpu, next_cpu) {
121 if (cpu != thread_cpu) {
122 QTAILQ_REMOVE(&cpus, thread_cpu, node);
123 }
124 }
125 pending_cpus = 0;
126 pthread_mutex_init(&exclusive_lock, NULL);
127 pthread_mutex_init(&cpu_list_mutex, NULL);
128 pthread_cond_init(&exclusive_cond, NULL);
129 pthread_cond_init(&exclusive_resume, NULL);
130 pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);
131 gdbserver_fork(thread_cpu);
132 } else {
133 pthread_mutex_unlock(&exclusive_lock);
134 pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);
135 }
136 }
137
138 /* Wait for pending exclusive operations to complete. The exclusive lock
139 must be held. */
140 static inline void exclusive_idle(void)
141 {
142 while (pending_cpus) {
143 pthread_cond_wait(&exclusive_resume, &exclusive_lock);
144 }
145 }
146
147 /* Start an exclusive operation.
148 Must only be called from outside cpu_arm_exec. */
149 static inline void start_exclusive(void)
150 {
151 CPUState *other_cpu;
152
153 pthread_mutex_lock(&exclusive_lock);
154 exclusive_idle();
155
156 pending_cpus = 1;
157 /* Make all other cpus stop executing. */
158 CPU_FOREACH(other_cpu) {
159 if (other_cpu->running) {
160 pending_cpus++;
161 cpu_exit(other_cpu);
162 }
163 }
164 if (pending_cpus > 1) {
165 pthread_cond_wait(&exclusive_cond, &exclusive_lock);
166 }
167 }
168
169 /* Finish an exclusive operation. */
170 static inline void __attribute__((unused)) end_exclusive(void)
171 {
172 pending_cpus = 0;
173 pthread_cond_broadcast(&exclusive_resume);
174 pthread_mutex_unlock(&exclusive_lock);
175 }
176
177 /* Wait for exclusive ops to finish, and begin cpu execution. */
178 static inline void cpu_exec_start(CPUState *cpu)
179 {
180 pthread_mutex_lock(&exclusive_lock);
181 exclusive_idle();
182 cpu->running = true;
183 pthread_mutex_unlock(&exclusive_lock);
184 }
185
186 /* Mark cpu as not executing, and release pending exclusive ops. */
187 static inline void cpu_exec_end(CPUState *cpu)
188 {
189 pthread_mutex_lock(&exclusive_lock);
190 cpu->running = false;
191 if (pending_cpus > 1) {
192 pending_cpus--;
193 if (pending_cpus == 1) {
194 pthread_cond_signal(&exclusive_cond);
195 }
196 }
197 exclusive_idle();
198 pthread_mutex_unlock(&exclusive_lock);
199 }
200
201 void cpu_list_lock(void)
202 {
203 pthread_mutex_lock(&cpu_list_mutex);
204 }
205
206 void cpu_list_unlock(void)
207 {
208 pthread_mutex_unlock(&cpu_list_mutex);
209 }
210
211
212 #ifdef TARGET_I386
213 /***********************************************************/
214 /* CPUX86 core interface */
215
216 uint64_t cpu_get_tsc(CPUX86State *env)
217 {
218 return cpu_get_real_ticks();
219 }
220
221 static void write_dt(void *ptr, unsigned long addr, unsigned long limit,
222 int flags)
223 {
224 unsigned int e1, e2;
225 uint32_t *p;
226 e1 = (addr << 16) | (limit & 0xffff);
227 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);
228 e2 |= flags;
229 p = ptr;
230 p[0] = tswap32(e1);
231 p[1] = tswap32(e2);
232 }
233
234 static uint64_t *idt_table;
235 #ifdef TARGET_X86_64
236 static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,
237 uint64_t addr, unsigned int sel)
238 {
239 uint32_t *p, e1, e2;
240 e1 = (addr & 0xffff) | (sel << 16);
241 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
242 p = ptr;
243 p[0] = tswap32(e1);
244 p[1] = tswap32(e2);
245 p[2] = tswap32(addr >> 32);
246 p[3] = 0;
247 }
248 /* only dpl matters as we do only user space emulation */
249 static void set_idt(int n, unsigned int dpl)
250 {
251 set_gate64(idt_table + n * 2, 0, dpl, 0, 0);
252 }
253 #else
254 static void set_gate(void *ptr, unsigned int type, unsigned int dpl,
255 uint32_t addr, unsigned int sel)
256 {
257 uint32_t *p, e1, e2;
258 e1 = (addr & 0xffff) | (sel << 16);
259 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);
260 p = ptr;
261 p[0] = tswap32(e1);
262 p[1] = tswap32(e2);
263 }
264
265 /* only dpl matters as we do only user space emulation */
266 static void set_idt(int n, unsigned int dpl)
267 {
268 set_gate(idt_table + n, 0, dpl, 0, 0);
269 }
270 #endif
271
272 void cpu_loop(CPUX86State *env)
273 {
274 CPUState *cs = CPU(x86_env_get_cpu(env));
275 int trapnr;
276 abi_ulong pc;
277 target_siginfo_t info;
278
279 for(;;) {
280 cpu_exec_start(cs);
281 trapnr = cpu_x86_exec(cs);
282 cpu_exec_end(cs);
283 switch(trapnr) {
284 case 0x80:
285 /* linux syscall from int $0x80 */
286 env->regs[R_EAX] = do_syscall(env,
287 env->regs[R_EAX],
288 env->regs[R_EBX],
289 env->regs[R_ECX],
290 env->regs[R_EDX],
291 env->regs[R_ESI],
292 env->regs[R_EDI],
293 env->regs[R_EBP],
294 0, 0);
295 break;
296 #ifndef TARGET_ABI32
297 case EXCP_SYSCALL:
298 /* linux syscall from syscall instruction */
299 env->regs[R_EAX] = do_syscall(env,
300 env->regs[R_EAX],
301 env->regs[R_EDI],
302 env->regs[R_ESI],
303 env->regs[R_EDX],
304 env->regs[10],
305 env->regs[8],
306 env->regs[9],
307 0, 0);
308 break;
309 #endif
310 case EXCP0B_NOSEG:
311 case EXCP0C_STACK:
312 info.si_signo = TARGET_SIGBUS;
313 info.si_errno = 0;
314 info.si_code = TARGET_SI_KERNEL;
315 info._sifields._sigfault._addr = 0;
316 queue_signal(env, info.si_signo, &info);
317 break;
318 case EXCP0D_GPF:
319 /* XXX: potential problem if ABI32 */
320 #ifndef TARGET_X86_64
321 if (env->eflags & VM_MASK) {
322 handle_vm86_fault(env);
323 } else
324 #endif
325 {
326 info.si_signo = TARGET_SIGSEGV;
327 info.si_errno = 0;
328 info.si_code = TARGET_SI_KERNEL;
329 info._sifields._sigfault._addr = 0;
330 queue_signal(env, info.si_signo, &info);
331 }
332 break;
333 case EXCP0E_PAGE:
334 info.si_signo = TARGET_SIGSEGV;
335 info.si_errno = 0;
336 if (!(env->error_code & 1))
337 info.si_code = TARGET_SEGV_MAPERR;
338 else
339 info.si_code = TARGET_SEGV_ACCERR;
340 info._sifields._sigfault._addr = env->cr[2];
341 queue_signal(env, info.si_signo, &info);
342 break;
343 case EXCP00_DIVZ:
344 #ifndef TARGET_X86_64
345 if (env->eflags & VM_MASK) {
346 handle_vm86_trap(env, trapnr);
347 } else
348 #endif
349 {
350 /* division by zero */
351 info.si_signo = TARGET_SIGFPE;
352 info.si_errno = 0;
353 info.si_code = TARGET_FPE_INTDIV;
354 info._sifields._sigfault._addr = env->eip;
355 queue_signal(env, info.si_signo, &info);
356 }
357 break;
358 case EXCP01_DB:
359 case EXCP03_INT3:
360 #ifndef TARGET_X86_64
361 if (env->eflags & VM_MASK) {
362 handle_vm86_trap(env, trapnr);
363 } else
364 #endif
365 {
366 info.si_signo = TARGET_SIGTRAP;
367 info.si_errno = 0;
368 if (trapnr == EXCP01_DB) {
369 info.si_code = TARGET_TRAP_BRKPT;
370 info._sifields._sigfault._addr = env->eip;
371 } else {
372 info.si_code = TARGET_SI_KERNEL;
373 info._sifields._sigfault._addr = 0;
374 }
375 queue_signal(env, info.si_signo, &info);
376 }
377 break;
378 case EXCP04_INTO:
379 case EXCP05_BOUND:
380 #ifndef TARGET_X86_64
381 if (env->eflags & VM_MASK) {
382 handle_vm86_trap(env, trapnr);
383 } else
384 #endif
385 {
386 info.si_signo = TARGET_SIGSEGV;
387 info.si_errno = 0;
388 info.si_code = TARGET_SI_KERNEL;
389 info._sifields._sigfault._addr = 0;
390 queue_signal(env, info.si_signo, &info);
391 }
392 break;
393 case EXCP06_ILLOP:
394 info.si_signo = TARGET_SIGILL;
395 info.si_errno = 0;
396 info.si_code = TARGET_ILL_ILLOPN;
397 info._sifields._sigfault._addr = env->eip;
398 queue_signal(env, info.si_signo, &info);
399 break;
400 case EXCP_INTERRUPT:
401 /* just indicate that signals should be handled asap */
402 break;
403 case EXCP_DEBUG:
404 {
405 int sig;
406
407 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
408 if (sig)
409 {
410 info.si_signo = sig;
411 info.si_errno = 0;
412 info.si_code = TARGET_TRAP_BRKPT;
413 queue_signal(env, info.si_signo, &info);
414 }
415 }
416 break;
417 default:
418 pc = env->segs[R_CS].base + env->eip;
419 fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",
420 (long)pc, trapnr);
421 abort();
422 }
423 process_pending_signals(env);
424 }
425 }
426 #endif
427
428 #ifdef TARGET_ARM
429
430 #define get_user_code_u32(x, gaddr, doswap) \
431 ({ abi_long __r = get_user_u32((x), (gaddr)); \
432 if (!__r && (doswap)) { \
433 (x) = bswap32(x); \
434 } \
435 __r; \
436 })
437
438 #define get_user_code_u16(x, gaddr, doswap) \
439 ({ abi_long __r = get_user_u16((x), (gaddr)); \
440 if (!__r && (doswap)) { \
441 (x) = bswap16(x); \
442 } \
443 __r; \
444 })
445
446 #ifdef TARGET_ABI32
447 /* Commpage handling -- there is no commpage for AArch64 */
448
449 /*
450 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt
451 * Input:
452 * r0 = pointer to oldval
453 * r1 = pointer to newval
454 * r2 = pointer to target value
455 *
456 * Output:
457 * r0 = 0 if *ptr was changed, non-0 if no exchange happened
458 * C set if *ptr was changed, clear if no exchange happened
459 *
460 * Note segv's in kernel helpers are a bit tricky, we can set the
461 * data address sensibly but the PC address is just the entry point.
462 */
463 static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
464 {
465 uint64_t oldval, newval, val;
466 uint32_t addr, cpsr;
467 target_siginfo_t info;
468
469 /* Based on the 32 bit code in do_kernel_trap */
470
471 /* XXX: This only works between threads, not between processes.
472 It's probably possible to implement this with native host
473 operations. However things like ldrex/strex are much harder so
474 there's not much point trying. */
475 start_exclusive();
476 cpsr = cpsr_read(env);
477 addr = env->regs[2];
478
479 if (get_user_u64(oldval, env->regs[0])) {
480 env->exception.vaddress = env->regs[0];
481 goto segv;
482 };
483
484 if (get_user_u64(newval, env->regs[1])) {
485 env->exception.vaddress = env->regs[1];
486 goto segv;
487 };
488
489 if (get_user_u64(val, addr)) {
490 env->exception.vaddress = addr;
491 goto segv;
492 }
493
494 if (val == oldval) {
495 val = newval;
496
497 if (put_user_u64(val, addr)) {
498 env->exception.vaddress = addr;
499 goto segv;
500 };
501
502 env->regs[0] = 0;
503 cpsr |= CPSR_C;
504 } else {
505 env->regs[0] = -1;
506 cpsr &= ~CPSR_C;
507 }
508 cpsr_write(env, cpsr, CPSR_C);
509 end_exclusive();
510 return;
511
512 segv:
513 end_exclusive();
514 /* We get the PC of the entry address - which is as good as anything,
515 on a real kernel what you get depends on which mode it uses. */
516 info.si_signo = TARGET_SIGSEGV;
517 info.si_errno = 0;
518 /* XXX: check env->error_code */
519 info.si_code = TARGET_SEGV_MAPERR;
520 info._sifields._sigfault._addr = env->exception.vaddress;
521 queue_signal(env, info.si_signo, &info);
522 }
523
524 /* Handle a jump to the kernel code page. */
525 static int
526 do_kernel_trap(CPUARMState *env)
527 {
528 uint32_t addr;
529 uint32_t cpsr;
530 uint32_t val;
531
532 switch (env->regs[15]) {
533 case 0xffff0fa0: /* __kernel_memory_barrier */
534 /* ??? No-op. Will need to do better for SMP. */
535 break;
536 case 0xffff0fc0: /* __kernel_cmpxchg */
537 /* XXX: This only works between threads, not between processes.
538 It's probably possible to implement this with native host
539 operations. However things like ldrex/strex are much harder so
540 there's not much point trying. */
541 start_exclusive();
542 cpsr = cpsr_read(env);
543 addr = env->regs[2];
544 /* FIXME: This should SEGV if the access fails. */
545 if (get_user_u32(val, addr))
546 val = ~env->regs[0];
547 if (val == env->regs[0]) {
548 val = env->regs[1];
549 /* FIXME: Check for segfaults. */
550 put_user_u32(val, addr);
551 env->regs[0] = 0;
552 cpsr |= CPSR_C;
553 } else {
554 env->regs[0] = -1;
555 cpsr &= ~CPSR_C;
556 }
557 cpsr_write(env, cpsr, CPSR_C);
558 end_exclusive();
559 break;
560 case 0xffff0fe0: /* __kernel_get_tls */
561 env->regs[0] = cpu_get_tls(env);
562 break;
563 case 0xffff0f60: /* __kernel_cmpxchg64 */
564 arm_kernel_cmpxchg64_helper(env);
565 break;
566
567 default:
568 return 1;
569 }
570 /* Jump back to the caller. */
571 addr = env->regs[14];
572 if (addr & 1) {
573 env->thumb = 1;
574 addr &= ~1;
575 }
576 env->regs[15] = addr;
577
578 return 0;
579 }
580
581 /* Store exclusive handling for AArch32 */
582 static int do_strex(CPUARMState *env)
583 {
584 uint64_t val;
585 int size;
586 int rc = 1;
587 int segv = 0;
588 uint32_t addr;
589 start_exclusive();
590 if (env->exclusive_addr != env->exclusive_test) {
591 goto fail;
592 }
593 /* We know we're always AArch32 so the address is in uint32_t range
594 * unless it was the -1 exclusive-monitor-lost value (which won't
595 * match exclusive_test above).
596 */
597 assert(extract64(env->exclusive_addr, 32, 32) == 0);
598 addr = env->exclusive_addr;
599 size = env->exclusive_info & 0xf;
600 switch (size) {
601 case 0:
602 segv = get_user_u8(val, addr);
603 break;
604 case 1:
605 segv = get_user_u16(val, addr);
606 break;
607 case 2:
608 case 3:
609 segv = get_user_u32(val, addr);
610 break;
611 default:
612 abort();
613 }
614 if (segv) {
615 env->exception.vaddress = addr;
616 goto done;
617 }
618 if (size == 3) {
619 uint32_t valhi;
620 segv = get_user_u32(valhi, addr + 4);
621 if (segv) {
622 env->exception.vaddress = addr + 4;
623 goto done;
624 }
625 val = deposit64(val, 32, 32, valhi);
626 }
627 if (val != env->exclusive_val) {
628 goto fail;
629 }
630
631 val = env->regs[(env->exclusive_info >> 8) & 0xf];
632 switch (size) {
633 case 0:
634 segv = put_user_u8(val, addr);
635 break;
636 case 1:
637 segv = put_user_u16(val, addr);
638 break;
639 case 2:
640 case 3:
641 segv = put_user_u32(val, addr);
642 break;
643 }
644 if (segv) {
645 env->exception.vaddress = addr;
646 goto done;
647 }
648 if (size == 3) {
649 val = env->regs[(env->exclusive_info >> 12) & 0xf];
650 segv = put_user_u32(val, addr + 4);
651 if (segv) {
652 env->exception.vaddress = addr + 4;
653 goto done;
654 }
655 }
656 rc = 0;
657 fail:
658 env->regs[15] += 4;
659 env->regs[(env->exclusive_info >> 4) & 0xf] = rc;
660 done:
661 end_exclusive();
662 return segv;
663 }
664
665 void cpu_loop(CPUARMState *env)
666 {
667 CPUState *cs = CPU(arm_env_get_cpu(env));
668 int trapnr;
669 unsigned int n, insn;
670 target_siginfo_t info;
671 uint32_t addr;
672
673 for(;;) {
674 cpu_exec_start(cs);
675 trapnr = cpu_arm_exec(cs);
676 cpu_exec_end(cs);
677 switch(trapnr) {
678 case EXCP_UDEF:
679 {
680 TaskState *ts = cs->opaque;
681 uint32_t opcode;
682 int rc;
683
684 /* we handle the FPU emulation here, as Linux */
685 /* we get the opcode */
686 /* FIXME - what to do if get_user() fails? */
687 get_user_code_u32(opcode, env->regs[15], env->bswap_code);
688
689 rc = EmulateAll(opcode, &ts->fpa, env);
690 if (rc == 0) { /* illegal instruction */
691 info.si_signo = TARGET_SIGILL;
692 info.si_errno = 0;
693 info.si_code = TARGET_ILL_ILLOPN;
694 info._sifields._sigfault._addr = env->regs[15];
695 queue_signal(env, info.si_signo, &info);
696 } else if (rc < 0) { /* FP exception */
697 int arm_fpe=0;
698
699 /* translate softfloat flags to FPSR flags */
700 if (-rc & float_flag_invalid)
701 arm_fpe |= BIT_IOC;
702 if (-rc & float_flag_divbyzero)
703 arm_fpe |= BIT_DZC;
704 if (-rc & float_flag_overflow)
705 arm_fpe |= BIT_OFC;
706 if (-rc & float_flag_underflow)
707 arm_fpe |= BIT_UFC;
708 if (-rc & float_flag_inexact)
709 arm_fpe |= BIT_IXC;
710
711 FPSR fpsr = ts->fpa.fpsr;
712 //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);
713
714 if (fpsr & (arm_fpe << 16)) { /* exception enabled? */
715 info.si_signo = TARGET_SIGFPE;
716 info.si_errno = 0;
717
718 /* ordered by priority, least first */
719 if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;
720 if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;
721 if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;
722 if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;
723 if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;
724
725 info._sifields._sigfault._addr = env->regs[15];
726 queue_signal(env, info.si_signo, &info);
727 } else {
728 env->regs[15] += 4;
729 }
730
731 /* accumulate unenabled exceptions */
732 if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))
733 fpsr |= BIT_IXC;
734 if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))
735 fpsr |= BIT_UFC;
736 if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))
737 fpsr |= BIT_OFC;
738 if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))
739 fpsr |= BIT_DZC;
740 if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))
741 fpsr |= BIT_IOC;
742 ts->fpa.fpsr=fpsr;
743 } else { /* everything OK */
744 /* increment PC */
745 env->regs[15] += 4;
746 }
747 }
748 break;
749 case EXCP_SWI:
750 case EXCP_BKPT:
751 {
752 env->eabi = 1;
753 /* system call */
754 if (trapnr == EXCP_BKPT) {
755 if (env->thumb) {
756 /* FIXME - what to do if get_user() fails? */
757 get_user_code_u16(insn, env->regs[15], env->bswap_code);
758 n = insn & 0xff;
759 env->regs[15] += 2;
760 } else {
761 /* FIXME - what to do if get_user() fails? */
762 get_user_code_u32(insn, env->regs[15], env->bswap_code);
763 n = (insn & 0xf) | ((insn >> 4) & 0xff0);
764 env->regs[15] += 4;
765 }
766 } else {
767 if (env->thumb) {
768 /* FIXME - what to do if get_user() fails? */
769 get_user_code_u16(insn, env->regs[15] - 2,
770 env->bswap_code);
771 n = insn & 0xff;
772 } else {
773 /* FIXME - what to do if get_user() fails? */
774 get_user_code_u32(insn, env->regs[15] - 4,
775 env->bswap_code);
776 n = insn & 0xffffff;
777 }
778 }
779
780 if (n == ARM_NR_cacheflush) {
781 /* nop */
782 } else if (n == ARM_NR_semihosting
783 || n == ARM_NR_thumb_semihosting) {
784 env->regs[0] = do_arm_semihosting (env);
785 } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {
786 /* linux syscall */
787 if (env->thumb || n == 0) {
788 n = env->regs[7];
789 } else {
790 n -= ARM_SYSCALL_BASE;
791 env->eabi = 0;
792 }
793 if ( n > ARM_NR_BASE) {
794 switch (n) {
795 case ARM_NR_cacheflush:
796 /* nop */
797 break;
798 case ARM_NR_set_tls:
799 cpu_set_tls(env, env->regs[0]);
800 env->regs[0] = 0;
801 break;
802 case ARM_NR_breakpoint:
803 env->regs[15] -= env->thumb ? 2 : 4;
804 goto excp_debug;
805 default:
806 gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",
807 n);
808 env->regs[0] = -TARGET_ENOSYS;
809 break;
810 }
811 } else {
812 env->regs[0] = do_syscall(env,
813 n,
814 env->regs[0],
815 env->regs[1],
816 env->regs[2],
817 env->regs[3],
818 env->regs[4],
819 env->regs[5],
820 0, 0);
821 }
822 } else {
823 goto error;
824 }
825 }
826 break;
827 case EXCP_INTERRUPT:
828 /* just indicate that signals should be handled asap */
829 break;
830 case EXCP_STREX:
831 if (!do_strex(env)) {
832 break;
833 }
834 /* fall through for segv */
835 case EXCP_PREFETCH_ABORT:
836 case EXCP_DATA_ABORT:
837 addr = env->exception.vaddress;
838 {
839 info.si_signo = TARGET_SIGSEGV;
840 info.si_errno = 0;
841 /* XXX: check env->error_code */
842 info.si_code = TARGET_SEGV_MAPERR;
843 info._sifields._sigfault._addr = addr;
844 queue_signal(env, info.si_signo, &info);
845 }
846 break;
847 case EXCP_DEBUG:
848 excp_debug:
849 {
850 int sig;
851
852 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
853 if (sig)
854 {
855 info.si_signo = sig;
856 info.si_errno = 0;
857 info.si_code = TARGET_TRAP_BRKPT;
858 queue_signal(env, info.si_signo, &info);
859 }
860 }
861 break;
862 case EXCP_KERNEL_TRAP:
863 if (do_kernel_trap(env))
864 goto error;
865 break;
866 default:
867 error:
868 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
869 trapnr);
870 cpu_dump_state(cs, stderr, fprintf, 0);
871 abort();
872 }
873 process_pending_signals(env);
874 }
875 }
876
877 #else
878
879 /*
880 * Handle AArch64 store-release exclusive
881 *
882 * rs = gets the status result of store exclusive
883 * rt = is the register that is stored
884 * rt2 = is the second register store (in STP)
885 *
886 */
887 static int do_strex_a64(CPUARMState *env)
888 {
889 uint64_t val;
890 int size;
891 bool is_pair;
892 int rc = 1;
893 int segv = 0;
894 uint64_t addr;
895 int rs, rt, rt2;
896
897 start_exclusive();
898 /* size | is_pair << 2 | (rs << 4) | (rt << 9) | (rt2 << 14)); */
899 size = extract32(env->exclusive_info, 0, 2);
900 is_pair = extract32(env->exclusive_info, 2, 1);
901 rs = extract32(env->exclusive_info, 4, 5);
902 rt = extract32(env->exclusive_info, 9, 5);
903 rt2 = extract32(env->exclusive_info, 14, 5);
904
905 addr = env->exclusive_addr;
906
907 if (addr != env->exclusive_test) {
908 goto finish;
909 }
910
911 switch (size) {
912 case 0:
913 segv = get_user_u8(val, addr);
914 break;
915 case 1:
916 segv = get_user_u16(val, addr);
917 break;
918 case 2:
919 segv = get_user_u32(val, addr);
920 break;
921 case 3:
922 segv = get_user_u64(val, addr);
923 break;
924 default:
925 abort();
926 }
927 if (segv) {
928 env->exception.vaddress = addr;
929 goto error;
930 }
931 if (val != env->exclusive_val) {
932 goto finish;
933 }
934 if (is_pair) {
935 if (size == 2) {
936 segv = get_user_u32(val, addr + 4);
937 } else {
938 segv = get_user_u64(val, addr + 8);
939 }
940 if (segv) {
941 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
942 goto error;
943 }
944 if (val != env->exclusive_high) {
945 goto finish;
946 }
947 }
948 /* handle the zero register */
949 val = rt == 31 ? 0 : env->xregs[rt];
950 switch (size) {
951 case 0:
952 segv = put_user_u8(val, addr);
953 break;
954 case 1:
955 segv = put_user_u16(val, addr);
956 break;
957 case 2:
958 segv = put_user_u32(val, addr);
959 break;
960 case 3:
961 segv = put_user_u64(val, addr);
962 break;
963 }
964 if (segv) {
965 goto error;
966 }
967 if (is_pair) {
968 /* handle the zero register */
969 val = rt2 == 31 ? 0 : env->xregs[rt2];
970 if (size == 2) {
971 segv = put_user_u32(val, addr + 4);
972 } else {
973 segv = put_user_u64(val, addr + 8);
974 }
975 if (segv) {
976 env->exception.vaddress = addr + (size == 2 ? 4 : 8);
977 goto error;
978 }
979 }
980 rc = 0;
981 finish:
982 env->pc += 4;
983 /* rs == 31 encodes a write to the ZR, thus throwing away
984 * the status return. This is rather silly but valid.
985 */
986 if (rs < 31) {
987 env->xregs[rs] = rc;
988 }
989 error:
990 /* instruction faulted, PC does not advance */
991 /* either way a strex releases any exclusive lock we have */
992 env->exclusive_addr = -1;
993 end_exclusive();
994 return segv;
995 }
996
997 /* AArch64 main loop */
998 void cpu_loop(CPUARMState *env)
999 {
1000 CPUState *cs = CPU(arm_env_get_cpu(env));
1001 int trapnr, sig;
1002 target_siginfo_t info;
1003
1004 for (;;) {
1005 cpu_exec_start(cs);
1006 trapnr = cpu_arm_exec(cs);
1007 cpu_exec_end(cs);
1008
1009 switch (trapnr) {
1010 case EXCP_SWI:
1011 env->xregs[0] = do_syscall(env,
1012 env->xregs[8],
1013 env->xregs[0],
1014 env->xregs[1],
1015 env->xregs[2],
1016 env->xregs[3],
1017 env->xregs[4],
1018 env->xregs[5],
1019 0, 0);
1020 break;
1021 case EXCP_INTERRUPT:
1022 /* just indicate that signals should be handled asap */
1023 break;
1024 case EXCP_UDEF:
1025 info.si_signo = TARGET_SIGILL;
1026 info.si_errno = 0;
1027 info.si_code = TARGET_ILL_ILLOPN;
1028 info._sifields._sigfault._addr = env->pc;
1029 queue_signal(env, info.si_signo, &info);
1030 break;
1031 case EXCP_STREX:
1032 if (!do_strex_a64(env)) {
1033 break;
1034 }
1035 /* fall through for segv */
1036 case EXCP_PREFETCH_ABORT:
1037 case EXCP_DATA_ABORT:
1038 info.si_signo = TARGET_SIGSEGV;
1039 info.si_errno = 0;
1040 /* XXX: check env->error_code */
1041 info.si_code = TARGET_SEGV_MAPERR;
1042 info._sifields._sigfault._addr = env->exception.vaddress;
1043 queue_signal(env, info.si_signo, &info);
1044 break;
1045 case EXCP_DEBUG:
1046 case EXCP_BKPT:
1047 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1048 if (sig) {
1049 info.si_signo = sig;
1050 info.si_errno = 0;
1051 info.si_code = TARGET_TRAP_BRKPT;
1052 queue_signal(env, info.si_signo, &info);
1053 }
1054 break;
1055 default:
1056 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
1057 trapnr);
1058 cpu_dump_state(cs, stderr, fprintf, 0);
1059 abort();
1060 }
1061 process_pending_signals(env);
1062 /* Exception return on AArch64 always clears the exclusive monitor,
1063 * so any return to running guest code implies this.
1064 * A strex (successful or otherwise) also clears the monitor, so
1065 * we don't need to specialcase EXCP_STREX.
1066 */
1067 env->exclusive_addr = -1;
1068 }
1069 }
1070 #endif /* ndef TARGET_ABI32 */
1071
1072 #endif
1073
1074 #ifdef TARGET_UNICORE32
1075
1076 void cpu_loop(CPUUniCore32State *env)
1077 {
1078 CPUState *cs = CPU(uc32_env_get_cpu(env));
1079 int trapnr;
1080 unsigned int n, insn;
1081 target_siginfo_t info;
1082
1083 for (;;) {
1084 cpu_exec_start(cs);
1085 trapnr = uc32_cpu_exec(cs);
1086 cpu_exec_end(cs);
1087 switch (trapnr) {
1088 case UC32_EXCP_PRIV:
1089 {
1090 /* system call */
1091 get_user_u32(insn, env->regs[31] - 4);
1092 n = insn & 0xffffff;
1093
1094 if (n >= UC32_SYSCALL_BASE) {
1095 /* linux syscall */
1096 n -= UC32_SYSCALL_BASE;
1097 if (n == UC32_SYSCALL_NR_set_tls) {
1098 cpu_set_tls(env, env->regs[0]);
1099 env->regs[0] = 0;
1100 } else {
1101 env->regs[0] = do_syscall(env,
1102 n,
1103 env->regs[0],
1104 env->regs[1],
1105 env->regs[2],
1106 env->regs[3],
1107 env->regs[4],
1108 env->regs[5],
1109 0, 0);
1110 }
1111 } else {
1112 goto error;
1113 }
1114 }
1115 break;
1116 case UC32_EXCP_DTRAP:
1117 case UC32_EXCP_ITRAP:
1118 info.si_signo = TARGET_SIGSEGV;
1119 info.si_errno = 0;
1120 /* XXX: check env->error_code */
1121 info.si_code = TARGET_SEGV_MAPERR;
1122 info._sifields._sigfault._addr = env->cp0.c4_faultaddr;
1123 queue_signal(env, info.si_signo, &info);
1124 break;
1125 case EXCP_INTERRUPT:
1126 /* just indicate that signals should be handled asap */
1127 break;
1128 case EXCP_DEBUG:
1129 {
1130 int sig;
1131
1132 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1133 if (sig) {
1134 info.si_signo = sig;
1135 info.si_errno = 0;
1136 info.si_code = TARGET_TRAP_BRKPT;
1137 queue_signal(env, info.si_signo, &info);
1138 }
1139 }
1140 break;
1141 default:
1142 goto error;
1143 }
1144 process_pending_signals(env);
1145 }
1146
1147 error:
1148 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
1149 cpu_dump_state(cs, stderr, fprintf, 0);
1150 abort();
1151 }
1152 #endif
1153
1154 #ifdef TARGET_SPARC
1155 #define SPARC64_STACK_BIAS 2047
1156
1157 //#define DEBUG_WIN
1158
1159 /* WARNING: dealing with register windows _is_ complicated. More info
1160 can be found at http://www.sics.se/~psm/sparcstack.html */
1161 static inline int get_reg_index(CPUSPARCState *env, int cwp, int index)
1162 {
1163 index = (index + cwp * 16) % (16 * env->nwindows);
1164 /* wrap handling : if cwp is on the last window, then we use the
1165 registers 'after' the end */
1166 if (index < 8 && env->cwp == env->nwindows - 1)
1167 index += 16 * env->nwindows;
1168 return index;
1169 }
1170
1171 /* save the register window 'cwp1' */
1172 static inline void save_window_offset(CPUSPARCState *env, int cwp1)
1173 {
1174 unsigned int i;
1175 abi_ulong sp_ptr;
1176
1177 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1178 #ifdef TARGET_SPARC64
1179 if (sp_ptr & 3)
1180 sp_ptr += SPARC64_STACK_BIAS;
1181 #endif
1182 #if defined(DEBUG_WIN)
1183 printf("win_overflow: sp_ptr=0x" TARGET_ABI_FMT_lx " save_cwp=%d\n",
1184 sp_ptr, cwp1);
1185 #endif
1186 for(i = 0; i < 16; i++) {
1187 /* FIXME - what to do if put_user() fails? */
1188 put_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1189 sp_ptr += sizeof(abi_ulong);
1190 }
1191 }
1192
1193 static void save_window(CPUSPARCState *env)
1194 {
1195 #ifndef TARGET_SPARC64
1196 unsigned int new_wim;
1197 new_wim = ((env->wim >> 1) | (env->wim << (env->nwindows - 1))) &
1198 ((1LL << env->nwindows) - 1);
1199 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1200 env->wim = new_wim;
1201 #else
1202 save_window_offset(env, cpu_cwp_dec(env, env->cwp - 2));
1203 env->cansave++;
1204 env->canrestore--;
1205 #endif
1206 }
1207
1208 static void restore_window(CPUSPARCState *env)
1209 {
1210 #ifndef TARGET_SPARC64
1211 unsigned int new_wim;
1212 #endif
1213 unsigned int i, cwp1;
1214 abi_ulong sp_ptr;
1215
1216 #ifndef TARGET_SPARC64
1217 new_wim = ((env->wim << 1) | (env->wim >> (env->nwindows - 1))) &
1218 ((1LL << env->nwindows) - 1);
1219 #endif
1220
1221 /* restore the invalid window */
1222 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1223 sp_ptr = env->regbase[get_reg_index(env, cwp1, 6)];
1224 #ifdef TARGET_SPARC64
1225 if (sp_ptr & 3)
1226 sp_ptr += SPARC64_STACK_BIAS;
1227 #endif
1228 #if defined(DEBUG_WIN)
1229 printf("win_underflow: sp_ptr=0x" TARGET_ABI_FMT_lx " load_cwp=%d\n",
1230 sp_ptr, cwp1);
1231 #endif
1232 for(i = 0; i < 16; i++) {
1233 /* FIXME - what to do if get_user() fails? */
1234 get_user_ual(env->regbase[get_reg_index(env, cwp1, 8 + i)], sp_ptr);
1235 sp_ptr += sizeof(abi_ulong);
1236 }
1237 #ifdef TARGET_SPARC64
1238 env->canrestore++;
1239 if (env->cleanwin < env->nwindows - 1)
1240 env->cleanwin++;
1241 env->cansave--;
1242 #else
1243 env->wim = new_wim;
1244 #endif
1245 }
1246
1247 static void flush_windows(CPUSPARCState *env)
1248 {
1249 int offset, cwp1;
1250
1251 offset = 1;
1252 for(;;) {
1253 /* if restore would invoke restore_window(), then we can stop */
1254 cwp1 = cpu_cwp_inc(env, env->cwp + offset);
1255 #ifndef TARGET_SPARC64
1256 if (env->wim & (1 << cwp1))
1257 break;
1258 #else
1259 if (env->canrestore == 0)
1260 break;
1261 env->cansave++;
1262 env->canrestore--;
1263 #endif
1264 save_window_offset(env, cwp1);
1265 offset++;
1266 }
1267 cwp1 = cpu_cwp_inc(env, env->cwp + 1);
1268 #ifndef TARGET_SPARC64
1269 /* set wim so that restore will reload the registers */
1270 env->wim = 1 << cwp1;
1271 #endif
1272 #if defined(DEBUG_WIN)
1273 printf("flush_windows: nb=%d\n", offset - 1);
1274 #endif
1275 }
1276
1277 void cpu_loop (CPUSPARCState *env)
1278 {
1279 CPUState *cs = CPU(sparc_env_get_cpu(env));
1280 int trapnr;
1281 abi_long ret;
1282 target_siginfo_t info;
1283
1284 while (1) {
1285 cpu_exec_start(cs);
1286 trapnr = cpu_sparc_exec(cs);
1287 cpu_exec_end(cs);
1288
1289 /* Compute PSR before exposing state. */
1290 if (env->cc_op != CC_OP_FLAGS) {
1291 cpu_get_psr(env);
1292 }
1293
1294 switch (trapnr) {
1295 #ifndef TARGET_SPARC64
1296 case 0x88:
1297 case 0x90:
1298 #else
1299 case 0x110:
1300 case 0x16d:
1301 #endif
1302 ret = do_syscall (env, env->gregs[1],
1303 env->regwptr[0], env->regwptr[1],
1304 env->regwptr[2], env->regwptr[3],
1305 env->regwptr[4], env->regwptr[5],
1306 0, 0);
1307 if ((abi_ulong)ret >= (abi_ulong)(-515)) {
1308 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1309 env->xcc |= PSR_CARRY;
1310 #else
1311 env->psr |= PSR_CARRY;
1312 #endif
1313 ret = -ret;
1314 } else {
1315 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
1316 env->xcc &= ~PSR_CARRY;
1317 #else
1318 env->psr &= ~PSR_CARRY;
1319 #endif
1320 }
1321 env->regwptr[0] = ret;
1322 /* next instruction */
1323 env->pc = env->npc;
1324 env->npc = env->npc + 4;
1325 break;
1326 case 0x83: /* flush windows */
1327 #ifdef TARGET_ABI32
1328 case 0x103:
1329 #endif
1330 flush_windows(env);
1331 /* next instruction */
1332 env->pc = env->npc;
1333 env->npc = env->npc + 4;
1334 break;
1335 #ifndef TARGET_SPARC64
1336 case TT_WIN_OVF: /* window overflow */
1337 save_window(env);
1338 break;
1339 case TT_WIN_UNF: /* window underflow */
1340 restore_window(env);
1341 break;
1342 case TT_TFAULT:
1343 case TT_DFAULT:
1344 {
1345 info.si_signo = TARGET_SIGSEGV;
1346 info.si_errno = 0;
1347 /* XXX: check env->error_code */
1348 info.si_code = TARGET_SEGV_MAPERR;
1349 info._sifields._sigfault._addr = env->mmuregs[4];
1350 queue_signal(env, info.si_signo, &info);
1351 }
1352 break;
1353 #else
1354 case TT_SPILL: /* window overflow */
1355 save_window(env);
1356 break;
1357 case TT_FILL: /* window underflow */
1358 restore_window(env);
1359 break;
1360 case TT_TFAULT:
1361 case TT_DFAULT:
1362 {
1363 info.si_signo = TARGET_SIGSEGV;
1364 info.si_errno = 0;
1365 /* XXX: check env->error_code */
1366 info.si_code = TARGET_SEGV_MAPERR;
1367 if (trapnr == TT_DFAULT)
1368 info._sifields._sigfault._addr = env->dmmuregs[4];
1369 else
1370 info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
1371 queue_signal(env, info.si_signo, &info);
1372 }
1373 break;
1374 #ifndef TARGET_ABI32
1375 case 0x16e:
1376 flush_windows(env);
1377 sparc64_get_context(env);
1378 break;
1379 case 0x16f:
1380 flush_windows(env);
1381 sparc64_set_context(env);
1382 break;
1383 #endif
1384 #endif
1385 case EXCP_INTERRUPT:
1386 /* just indicate that signals should be handled asap */
1387 break;
1388 case TT_ILL_INSN:
1389 {
1390 info.si_signo = TARGET_SIGILL;
1391 info.si_errno = 0;
1392 info.si_code = TARGET_ILL_ILLOPC;
1393 info._sifields._sigfault._addr = env->pc;
1394 queue_signal(env, info.si_signo, &info);
1395 }
1396 break;
1397 case EXCP_DEBUG:
1398 {
1399 int sig;
1400
1401 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1402 if (sig)
1403 {
1404 info.si_signo = sig;
1405 info.si_errno = 0;
1406 info.si_code = TARGET_TRAP_BRKPT;
1407 queue_signal(env, info.si_signo, &info);
1408 }
1409 }
1410 break;
1411 default:
1412 printf ("Unhandled trap: 0x%x\n", trapnr);
1413 cpu_dump_state(cs, stderr, fprintf, 0);
1414 exit (1);
1415 }
1416 process_pending_signals (env);
1417 }
1418 }
1419
1420 #endif
1421
1422 #ifdef TARGET_PPC
1423 static inline uint64_t cpu_ppc_get_tb(CPUPPCState *env)
1424 {
1425 return cpu_get_real_ticks();
1426 }
1427
1428 uint64_t cpu_ppc_load_tbl(CPUPPCState *env)
1429 {
1430 return cpu_ppc_get_tb(env);
1431 }
1432
1433 uint32_t cpu_ppc_load_tbu(CPUPPCState *env)
1434 {
1435 return cpu_ppc_get_tb(env) >> 32;
1436 }
1437
1438 uint64_t cpu_ppc_load_atbl(CPUPPCState *env)
1439 {
1440 return cpu_ppc_get_tb(env);
1441 }
1442
1443 uint32_t cpu_ppc_load_atbu(CPUPPCState *env)
1444 {
1445 return cpu_ppc_get_tb(env) >> 32;
1446 }
1447
1448 uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env)
1449 __attribute__ (( alias ("cpu_ppc_load_tbu") ));
1450
1451 uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env)
1452 {
1453 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1454 }
1455
1456 /* XXX: to be fixed */
1457 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1458 {
1459 return -1;
1460 }
1461
1462 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1463 {
1464 return -1;
1465 }
1466
1467 #define EXCP_DUMP(env, fmt, ...) \
1468 do { \
1469 CPUState *cs = ENV_GET_CPU(env); \
1470 fprintf(stderr, fmt , ## __VA_ARGS__); \
1471 cpu_dump_state(cs, stderr, fprintf, 0); \
1472 qemu_log(fmt, ## __VA_ARGS__); \
1473 if (qemu_log_enabled()) { \
1474 log_cpu_state(cs, 0); \
1475 } \
1476 } while (0)
1477
1478 static int do_store_exclusive(CPUPPCState *env)
1479 {
1480 target_ulong addr;
1481 target_ulong page_addr;
1482 target_ulong val, val2 __attribute__((unused)) = 0;
1483 int flags;
1484 int segv = 0;
1485
1486 addr = env->reserve_ea;
1487 page_addr = addr & TARGET_PAGE_MASK;
1488 start_exclusive();
1489 mmap_lock();
1490 flags = page_get_flags(page_addr);
1491 if ((flags & PAGE_READ) == 0) {
1492 segv = 1;
1493 } else {
1494 int reg = env->reserve_info & 0x1f;
1495 int size = env->reserve_info >> 5;
1496 int stored = 0;
1497
1498 if (addr == env->reserve_addr) {
1499 switch (size) {
1500 case 1: segv = get_user_u8(val, addr); break;
1501 case 2: segv = get_user_u16(val, addr); break;
1502 case 4: segv = get_user_u32(val, addr); break;
1503 #if defined(TARGET_PPC64)
1504 case 8: segv = get_user_u64(val, addr); break;
1505 case 16: {
1506 segv = get_user_u64(val, addr);
1507 if (!segv) {
1508 segv = get_user_u64(val2, addr + 8);
1509 }
1510 break;
1511 }
1512 #endif
1513 default: abort();
1514 }
1515 if (!segv && val == env->reserve_val) {
1516 val = env->gpr[reg];
1517 switch (size) {
1518 case 1: segv = put_user_u8(val, addr); break;
1519 case 2: segv = put_user_u16(val, addr); break;
1520 case 4: segv = put_user_u32(val, addr); break;
1521 #if defined(TARGET_PPC64)
1522 case 8: segv = put_user_u64(val, addr); break;
1523 case 16: {
1524 if (val2 == env->reserve_val2) {
1525 if (msr_le) {
1526 val2 = val;
1527 val = env->gpr[reg+1];
1528 } else {
1529 val2 = env->gpr[reg+1];
1530 }
1531 segv = put_user_u64(val, addr);
1532 if (!segv) {
1533 segv = put_user_u64(val2, addr + 8);
1534 }
1535 }
1536 break;
1537 }
1538 #endif
1539 default: abort();
1540 }
1541 if (!segv) {
1542 stored = 1;
1543 }
1544 }
1545 }
1546 env->crf[0] = (stored << 1) | xer_so;
1547 env->reserve_addr = (target_ulong)-1;
1548 }
1549 if (!segv) {
1550 env->nip += 4;
1551 }
1552 mmap_unlock();
1553 end_exclusive();
1554 return segv;
1555 }
1556
1557 void cpu_loop(CPUPPCState *env)
1558 {
1559 CPUState *cs = CPU(ppc_env_get_cpu(env));
1560 target_siginfo_t info;
1561 int trapnr;
1562 target_ulong ret;
1563
1564 for(;;) {
1565 cpu_exec_start(cs);
1566 trapnr = cpu_ppc_exec(cs);
1567 cpu_exec_end(cs);
1568 switch(trapnr) {
1569 case POWERPC_EXCP_NONE:
1570 /* Just go on */
1571 break;
1572 case POWERPC_EXCP_CRITICAL: /* Critical input */
1573 cpu_abort(cs, "Critical interrupt while in user mode. "
1574 "Aborting\n");
1575 break;
1576 case POWERPC_EXCP_MCHECK: /* Machine check exception */
1577 cpu_abort(cs, "Machine check exception while in user mode. "
1578 "Aborting\n");
1579 break;
1580 case POWERPC_EXCP_DSI: /* Data storage exception */
1581 EXCP_DUMP(env, "Invalid data memory access: 0x" TARGET_FMT_lx "\n",
1582 env->spr[SPR_DAR]);
1583 /* XXX: check this. Seems bugged */
1584 switch (env->error_code & 0xFF000000) {
1585 case 0x40000000:
1586 info.si_signo = TARGET_SIGSEGV;
1587 info.si_errno = 0;
1588 info.si_code = TARGET_SEGV_MAPERR;
1589 break;
1590 case 0x04000000:
1591 info.si_signo = TARGET_SIGILL;
1592 info.si_errno = 0;
1593 info.si_code = TARGET_ILL_ILLADR;
1594 break;
1595 case 0x08000000:
1596 info.si_signo = TARGET_SIGSEGV;
1597 info.si_errno = 0;
1598 info.si_code = TARGET_SEGV_ACCERR;
1599 break;
1600 default:
1601 /* Let's send a regular segfault... */
1602 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1603 env->error_code);
1604 info.si_signo = TARGET_SIGSEGV;
1605 info.si_errno = 0;
1606 info.si_code = TARGET_SEGV_MAPERR;
1607 break;
1608 }
1609 info._sifields._sigfault._addr = env->nip;
1610 queue_signal(env, info.si_signo, &info);
1611 break;
1612 case POWERPC_EXCP_ISI: /* Instruction storage exception */
1613 EXCP_DUMP(env, "Invalid instruction fetch: 0x\n" TARGET_FMT_lx
1614 "\n", env->spr[SPR_SRR0]);
1615 /* XXX: check this */
1616 switch (env->error_code & 0xFF000000) {
1617 case 0x40000000:
1618 info.si_signo = TARGET_SIGSEGV;
1619 info.si_errno = 0;
1620 info.si_code = TARGET_SEGV_MAPERR;
1621 break;
1622 case 0x10000000:
1623 case 0x08000000:
1624 info.si_signo = TARGET_SIGSEGV;
1625 info.si_errno = 0;
1626 info.si_code = TARGET_SEGV_ACCERR;
1627 break;
1628 default:
1629 /* Let's send a regular segfault... */
1630 EXCP_DUMP(env, "Invalid segfault errno (%02x)\n",
1631 env->error_code);
1632 info.si_signo = TARGET_SIGSEGV;
1633 info.si_errno = 0;
1634 info.si_code = TARGET_SEGV_MAPERR;
1635 break;
1636 }
1637 info._sifields._sigfault._addr = env->nip - 4;
1638 queue_signal(env, info.si_signo, &info);
1639 break;
1640 case POWERPC_EXCP_EXTERNAL: /* External input */
1641 cpu_abort(cs, "External interrupt while in user mode. "
1642 "Aborting\n");
1643 break;
1644 case POWERPC_EXCP_ALIGN: /* Alignment exception */
1645 EXCP_DUMP(env, "Unaligned memory access\n");
1646 /* XXX: check this */
1647 info.si_signo = TARGET_SIGBUS;
1648 info.si_errno = 0;
1649 info.si_code = TARGET_BUS_ADRALN;
1650 info._sifields._sigfault._addr = env->nip - 4;
1651 queue_signal(env, info.si_signo, &info);
1652 break;
1653 case POWERPC_EXCP_PROGRAM: /* Program exception */
1654 /* XXX: check this */
1655 switch (env->error_code & ~0xF) {
1656 case POWERPC_EXCP_FP:
1657 EXCP_DUMP(env, "Floating point program exception\n");
1658 info.si_signo = TARGET_SIGFPE;
1659 info.si_errno = 0;
1660 switch (env->error_code & 0xF) {
1661 case POWERPC_EXCP_FP_OX:
1662 info.si_code = TARGET_FPE_FLTOVF;
1663 break;
1664 case POWERPC_EXCP_FP_UX:
1665 info.si_code = TARGET_FPE_FLTUND;
1666 break;
1667 case POWERPC_EXCP_FP_ZX:
1668 case POWERPC_EXCP_FP_VXZDZ:
1669 info.si_code = TARGET_FPE_FLTDIV;
1670 break;
1671 case POWERPC_EXCP_FP_XX:
1672 info.si_code = TARGET_FPE_FLTRES;
1673 break;
1674 case POWERPC_EXCP_FP_VXSOFT:
1675 info.si_code = TARGET_FPE_FLTINV;
1676 break;
1677 case POWERPC_EXCP_FP_VXSNAN:
1678 case POWERPC_EXCP_FP_VXISI:
1679 case POWERPC_EXCP_FP_VXIDI:
1680 case POWERPC_EXCP_FP_VXIMZ:
1681 case POWERPC_EXCP_FP_VXVC:
1682 case POWERPC_EXCP_FP_VXSQRT:
1683 case POWERPC_EXCP_FP_VXCVI:
1684 info.si_code = TARGET_FPE_FLTSUB;
1685 break;
1686 default:
1687 EXCP_DUMP(env, "Unknown floating point exception (%02x)\n",
1688 env->error_code);
1689 break;
1690 }
1691 break;
1692 case POWERPC_EXCP_INVAL:
1693 EXCP_DUMP(env, "Invalid instruction\n");
1694 info.si_signo = TARGET_SIGILL;
1695 info.si_errno = 0;
1696 switch (env->error_code & 0xF) {
1697 case POWERPC_EXCP_INVAL_INVAL:
1698 info.si_code = TARGET_ILL_ILLOPC;
1699 break;
1700 case POWERPC_EXCP_INVAL_LSWX:
1701 info.si_code = TARGET_ILL_ILLOPN;
1702 break;
1703 case POWERPC_EXCP_INVAL_SPR:
1704 info.si_code = TARGET_ILL_PRVREG;
1705 break;
1706 case POWERPC_EXCP_INVAL_FP:
1707 info.si_code = TARGET_ILL_COPROC;
1708 break;
1709 default:
1710 EXCP_DUMP(env, "Unknown invalid operation (%02x)\n",
1711 env->error_code & 0xF);
1712 info.si_code = TARGET_ILL_ILLADR;
1713 break;
1714 }
1715 break;
1716 case POWERPC_EXCP_PRIV:
1717 EXCP_DUMP(env, "Privilege violation\n");
1718 info.si_signo = TARGET_SIGILL;
1719 info.si_errno = 0;
1720 switch (env->error_code & 0xF) {
1721 case POWERPC_EXCP_PRIV_OPC:
1722 info.si_code = TARGET_ILL_PRVOPC;
1723 break;
1724 case POWERPC_EXCP_PRIV_REG:
1725 info.si_code = TARGET_ILL_PRVREG;
1726 break;
1727 default:
1728 EXCP_DUMP(env, "Unknown privilege violation (%02x)\n",
1729 env->error_code & 0xF);
1730 info.si_code = TARGET_ILL_PRVOPC;
1731 break;
1732 }
1733 break;
1734 case POWERPC_EXCP_TRAP:
1735 cpu_abort(cs, "Tried to call a TRAP\n");
1736 break;
1737 default:
1738 /* Should not happen ! */
1739 cpu_abort(cs, "Unknown program exception (%02x)\n",
1740 env->error_code);
1741 break;
1742 }
1743 info._sifields._sigfault._addr = env->nip - 4;
1744 queue_signal(env, info.si_signo, &info);
1745 break;
1746 case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
1747 EXCP_DUMP(env, "No floating point allowed\n");
1748 info.si_signo = TARGET_SIGILL;
1749 info.si_errno = 0;
1750 info.si_code = TARGET_ILL_COPROC;
1751 info._sifields._sigfault._addr = env->nip - 4;
1752 queue_signal(env, info.si_signo, &info);
1753 break;
1754 case POWERPC_EXCP_SYSCALL: /* System call exception */
1755 cpu_abort(cs, "Syscall exception while in user mode. "
1756 "Aborting\n");
1757 break;
1758 case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
1759 EXCP_DUMP(env, "No APU instruction allowed\n");
1760 info.si_signo = TARGET_SIGILL;
1761 info.si_errno = 0;
1762 info.si_code = TARGET_ILL_COPROC;
1763 info._sifields._sigfault._addr = env->nip - 4;
1764 queue_signal(env, info.si_signo, &info);
1765 break;
1766 case POWERPC_EXCP_DECR: /* Decrementer exception */
1767 cpu_abort(cs, "Decrementer interrupt while in user mode. "
1768 "Aborting\n");
1769 break;
1770 case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
1771 cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
1772 "Aborting\n");
1773 break;
1774 case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
1775 cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
1776 "Aborting\n");
1777 break;
1778 case POWERPC_EXCP_DTLB: /* Data TLB error */
1779 cpu_abort(cs, "Data TLB exception while in user mode. "
1780 "Aborting\n");
1781 break;
1782 case POWERPC_EXCP_ITLB: /* Instruction TLB error */
1783 cpu_abort(cs, "Instruction TLB exception while in user mode. "
1784 "Aborting\n");
1785 break;
1786 case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
1787 EXCP_DUMP(env, "No SPE/floating-point instruction allowed\n");
1788 info.si_signo = TARGET_SIGILL;
1789 info.si_errno = 0;
1790 info.si_code = TARGET_ILL_COPROC;
1791 info._sifields._sigfault._addr = env->nip - 4;
1792 queue_signal(env, info.si_signo, &info);
1793 break;
1794 case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
1795 cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
1796 break;
1797 case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
1798 cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
1799 break;
1800 case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
1801 cpu_abort(cs, "Performance monitor exception not handled\n");
1802 break;
1803 case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
1804 cpu_abort(cs, "Doorbell interrupt while in user mode. "
1805 "Aborting\n");
1806 break;
1807 case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
1808 cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
1809 "Aborting\n");
1810 break;
1811 case POWERPC_EXCP_RESET: /* System reset exception */
1812 cpu_abort(cs, "Reset interrupt while in user mode. "
1813 "Aborting\n");
1814 break;
1815 case POWERPC_EXCP_DSEG: /* Data segment exception */
1816 cpu_abort(cs, "Data segment exception while in user mode. "
1817 "Aborting\n");
1818 break;
1819 case POWERPC_EXCP_ISEG: /* Instruction segment exception */
1820 cpu_abort(cs, "Instruction segment exception "
1821 "while in user mode. Aborting\n");
1822 break;
1823 /* PowerPC 64 with hypervisor mode support */
1824 case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
1825 cpu_abort(cs, "Hypervisor decrementer interrupt "
1826 "while in user mode. Aborting\n");
1827 break;
1828 case POWERPC_EXCP_TRACE: /* Trace exception */
1829 /* Nothing to do:
1830 * we use this exception to emulate step-by-step execution mode.
1831 */
1832 break;
1833 /* PowerPC 64 with hypervisor mode support */
1834 case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
1835 cpu_abort(cs, "Hypervisor data storage exception "
1836 "while in user mode. Aborting\n");
1837 break;
1838 case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
1839 cpu_abort(cs, "Hypervisor instruction storage exception "
1840 "while in user mode. Aborting\n");
1841 break;
1842 case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
1843 cpu_abort(cs, "Hypervisor data segment exception "
1844 "while in user mode. Aborting\n");
1845 break;
1846 case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
1847 cpu_abort(cs, "Hypervisor instruction segment exception "
1848 "while in user mode. Aborting\n");
1849 break;
1850 case POWERPC_EXCP_VPU: /* Vector unavailable exception */
1851 EXCP_DUMP(env, "No Altivec instructions allowed\n");
1852 info.si_signo = TARGET_SIGILL;
1853 info.si_errno = 0;
1854 info.si_code = TARGET_ILL_COPROC;
1855 info._sifields._sigfault._addr = env->nip - 4;
1856 queue_signal(env, info.si_signo, &info);
1857 break;
1858 case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
1859 cpu_abort(cs, "Programmable interval timer interrupt "
1860 "while in user mode. Aborting\n");
1861 break;
1862 case POWERPC_EXCP_IO: /* IO error exception */
1863 cpu_abort(cs, "IO error exception while in user mode. "
1864 "Aborting\n");
1865 break;
1866 case POWERPC_EXCP_RUNM: /* Run mode exception */
1867 cpu_abort(cs, "Run mode exception while in user mode. "
1868 "Aborting\n");
1869 break;
1870 case POWERPC_EXCP_EMUL: /* Emulation trap exception */
1871 cpu_abort(cs, "Emulation trap exception not handled\n");
1872 break;
1873 case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
1874 cpu_abort(cs, "Instruction fetch TLB exception "
1875 "while in user-mode. Aborting");
1876 break;
1877 case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
1878 cpu_abort(cs, "Data load TLB exception while in user-mode. "
1879 "Aborting");
1880 break;
1881 case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
1882 cpu_abort(cs, "Data store TLB exception while in user-mode. "
1883 "Aborting");
1884 break;
1885 case POWERPC_EXCP_FPA: /* Floating-point assist exception */
1886 cpu_abort(cs, "Floating-point assist exception not handled\n");
1887 break;
1888 case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
1889 cpu_abort(cs, "Instruction address breakpoint exception "
1890 "not handled\n");
1891 break;
1892 case POWERPC_EXCP_SMI: /* System management interrupt */
1893 cpu_abort(cs, "System management interrupt while in user mode. "
1894 "Aborting\n");
1895 break;
1896 case POWERPC_EXCP_THERM: /* Thermal interrupt */
1897 cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
1898 "Aborting\n");
1899 break;
1900 case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
1901 cpu_abort(cs, "Performance monitor exception not handled\n");
1902 break;
1903 case POWERPC_EXCP_VPUA: /* Vector assist exception */
1904 cpu_abort(cs, "Vector assist exception not handled\n");
1905 break;
1906 case POWERPC_EXCP_SOFTP: /* Soft patch exception */
1907 cpu_abort(cs, "Soft patch exception not handled\n");
1908 break;
1909 case POWERPC_EXCP_MAINT: /* Maintenance exception */
1910 cpu_abort(cs, "Maintenance exception while in user mode. "
1911 "Aborting\n");
1912 break;
1913 case POWERPC_EXCP_STOP: /* stop translation */
1914 /* We did invalidate the instruction cache. Go on */
1915 break;
1916 case POWERPC_EXCP_BRANCH: /* branch instruction: */
1917 /* We just stopped because of a branch. Go on */
1918 break;
1919 case POWERPC_EXCP_SYSCALL_USER:
1920 /* system call in user-mode emulation */
1921 /* WARNING:
1922 * PPC ABI uses overflow flag in cr0 to signal an error
1923 * in syscalls.
1924 */
1925 env->crf[0] &= ~0x1;
1926 ret = do_syscall(env, env->gpr[0], env->gpr[3], env->gpr[4],
1927 env->gpr[5], env->gpr[6], env->gpr[7],
1928 env->gpr[8], 0, 0);
1929 if (ret == (target_ulong)(-TARGET_QEMU_ESIGRETURN)) {
1930 /* Returning from a successful sigreturn syscall.
1931 Avoid corrupting register state. */
1932 break;
1933 }
1934 if (ret > (target_ulong)(-515)) {
1935 env->crf[0] |= 0x1;
1936 ret = -ret;
1937 }
1938 env->gpr[3] = ret;
1939 break;
1940 case POWERPC_EXCP_STCX:
1941 if (do_store_exclusive(env)) {
1942 info.si_signo = TARGET_SIGSEGV;
1943 info.si_errno = 0;
1944 info.si_code = TARGET_SEGV_MAPERR;
1945 info._sifields._sigfault._addr = env->nip;
1946 queue_signal(env, info.si_signo, &info);
1947 }
1948 break;
1949 case EXCP_DEBUG:
1950 {
1951 int sig;
1952
1953 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
1954 if (sig) {
1955 info.si_signo = sig;
1956 info.si_errno = 0;
1957 info.si_code = TARGET_TRAP_BRKPT;
1958 queue_signal(env, info.si_signo, &info);
1959 }
1960 }
1961 break;
1962 case EXCP_INTERRUPT:
1963 /* just indicate that signals should be handled asap */
1964 break;
1965 default:
1966 cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
1967 break;
1968 }
1969 process_pending_signals(env);
1970 }
1971 }
1972 #endif
1973
1974 #ifdef TARGET_MIPS
1975
1976 # ifdef TARGET_ABI_MIPSO32
1977 # define MIPS_SYS(name, args) args,
1978 static const uint8_t mips_syscall_args[] = {
1979 MIPS_SYS(sys_syscall , 8) /* 4000 */
1980 MIPS_SYS(sys_exit , 1)
1981 MIPS_SYS(sys_fork , 0)
1982 MIPS_SYS(sys_read , 3)
1983 MIPS_SYS(sys_write , 3)
1984 MIPS_SYS(sys_open , 3) /* 4005 */
1985 MIPS_SYS(sys_close , 1)
1986 MIPS_SYS(sys_waitpid , 3)
1987 MIPS_SYS(sys_creat , 2)
1988 MIPS_SYS(sys_link , 2)
1989 MIPS_SYS(sys_unlink , 1) /* 4010 */
1990 MIPS_SYS(sys_execve , 0)
1991 MIPS_SYS(sys_chdir , 1)
1992 MIPS_SYS(sys_time , 1)
1993 MIPS_SYS(sys_mknod , 3)
1994 MIPS_SYS(sys_chmod , 2) /* 4015 */
1995 MIPS_SYS(sys_lchown , 3)
1996 MIPS_SYS(sys_ni_syscall , 0)
1997 MIPS_SYS(sys_ni_syscall , 0) /* was sys_stat */
1998 MIPS_SYS(sys_lseek , 3)
1999 MIPS_SYS(sys_getpid , 0) /* 4020 */
2000 MIPS_SYS(sys_mount , 5)
2001 MIPS_SYS(sys_umount , 1)
2002 MIPS_SYS(sys_setuid , 1)
2003 MIPS_SYS(sys_getuid , 0)
2004 MIPS_SYS(sys_stime , 1) /* 4025 */
2005 MIPS_SYS(sys_ptrace , 4)
2006 MIPS_SYS(sys_alarm , 1)
2007 MIPS_SYS(sys_ni_syscall , 0) /* was sys_fstat */
2008 MIPS_SYS(sys_pause , 0)
2009 MIPS_SYS(sys_utime , 2) /* 4030 */
2010 MIPS_SYS(sys_ni_syscall , 0)
2011 MIPS_SYS(sys_ni_syscall , 0)
2012 MIPS_SYS(sys_access , 2)
2013 MIPS_SYS(sys_nice , 1)
2014 MIPS_SYS(sys_ni_syscall , 0) /* 4035 */
2015 MIPS_SYS(sys_sync , 0)
2016 MIPS_SYS(sys_kill , 2)
2017 MIPS_SYS(sys_rename , 2)
2018 MIPS_SYS(sys_mkdir , 2)
2019 MIPS_SYS(sys_rmdir , 1) /* 4040 */
2020 MIPS_SYS(sys_dup , 1)
2021 MIPS_SYS(sys_pipe , 0)
2022 MIPS_SYS(sys_times , 1)
2023 MIPS_SYS(sys_ni_syscall , 0)
2024 MIPS_SYS(sys_brk , 1) /* 4045 */
2025 MIPS_SYS(sys_setgid , 1)
2026 MIPS_SYS(sys_getgid , 0)
2027 MIPS_SYS(sys_ni_syscall , 0) /* was signal(2) */
2028 MIPS_SYS(sys_geteuid , 0)
2029 MIPS_SYS(sys_getegid , 0) /* 4050 */
2030 MIPS_SYS(sys_acct , 0)
2031 MIPS_SYS(sys_umount2 , 2)
2032 MIPS_SYS(sys_ni_syscall , 0)
2033 MIPS_SYS(sys_ioctl , 3)
2034 MIPS_SYS(sys_fcntl , 3) /* 4055 */
2035 MIPS_SYS(sys_ni_syscall , 2)
2036 MIPS_SYS(sys_setpgid , 2)
2037 MIPS_SYS(sys_ni_syscall , 0)
2038 MIPS_SYS(sys_olduname , 1)
2039 MIPS_SYS(sys_umask , 1) /* 4060 */
2040 MIPS_SYS(sys_chroot , 1)
2041 MIPS_SYS(sys_ustat , 2)
2042 MIPS_SYS(sys_dup2 , 2)
2043 MIPS_SYS(sys_getppid , 0)
2044 MIPS_SYS(sys_getpgrp , 0) /* 4065 */
2045 MIPS_SYS(sys_setsid , 0)
2046 MIPS_SYS(sys_sigaction , 3)
2047 MIPS_SYS(sys_sgetmask , 0)
2048 MIPS_SYS(sys_ssetmask , 1)
2049 MIPS_SYS(sys_setreuid , 2) /* 4070 */
2050 MIPS_SYS(sys_setregid , 2)
2051 MIPS_SYS(sys_sigsuspend , 0)
2052 MIPS_SYS(sys_sigpending , 1)
2053 MIPS_SYS(sys_sethostname , 2)
2054 MIPS_SYS(sys_setrlimit , 2) /* 4075 */
2055 MIPS_SYS(sys_getrlimit , 2)
2056 MIPS_SYS(sys_getrusage , 2)
2057 MIPS_SYS(sys_gettimeofday, 2)
2058 MIPS_SYS(sys_settimeofday, 2)
2059 MIPS_SYS(sys_getgroups , 2) /* 4080 */
2060 MIPS_SYS(sys_setgroups , 2)
2061 MIPS_SYS(sys_ni_syscall , 0) /* old_select */
2062 MIPS_SYS(sys_symlink , 2)
2063 MIPS_SYS(sys_ni_syscall , 0) /* was sys_lstat */
2064 MIPS_SYS(sys_readlink , 3) /* 4085 */
2065 MIPS_SYS(sys_uselib , 1)
2066 MIPS_SYS(sys_swapon , 2)
2067 MIPS_SYS(sys_reboot , 3)
2068 MIPS_SYS(old_readdir , 3)
2069 MIPS_SYS(old_mmap , 6) /* 4090 */
2070 MIPS_SYS(sys_munmap , 2)
2071 MIPS_SYS(sys_truncate , 2)
2072 MIPS_SYS(sys_ftruncate , 2)
2073 MIPS_SYS(sys_fchmod , 2)
2074 MIPS_SYS(sys_fchown , 3) /* 4095 */
2075 MIPS_SYS(sys_getpriority , 2)
2076 MIPS_SYS(sys_setpriority , 3)
2077 MIPS_SYS(sys_ni_syscall , 0)
2078 MIPS_SYS(sys_statfs , 2)
2079 MIPS_SYS(sys_fstatfs , 2) /* 4100 */
2080 MIPS_SYS(sys_ni_syscall , 0) /* was ioperm(2) */
2081 MIPS_SYS(sys_socketcall , 2)
2082 MIPS_SYS(sys_syslog , 3)
2083 MIPS_SYS(sys_setitimer , 3)
2084 MIPS_SYS(sys_getitimer , 2) /* 4105 */
2085 MIPS_SYS(sys_newstat , 2)
2086 MIPS_SYS(sys_newlstat , 2)
2087 MIPS_SYS(sys_newfstat , 2)
2088 MIPS_SYS(sys_uname , 1)
2089 MIPS_SYS(sys_ni_syscall , 0) /* 4110 was iopl(2) */
2090 MIPS_SYS(sys_vhangup , 0)
2091 MIPS_SYS(sys_ni_syscall , 0) /* was sys_idle() */
2092 MIPS_SYS(sys_ni_syscall , 0) /* was sys_vm86 */
2093 MIPS_SYS(sys_wait4 , 4)
2094 MIPS_SYS(sys_swapoff , 1) /* 4115 */
2095 MIPS_SYS(sys_sysinfo , 1)
2096 MIPS_SYS(sys_ipc , 6)
2097 MIPS_SYS(sys_fsync , 1)
2098 MIPS_SYS(sys_sigreturn , 0)
2099 MIPS_SYS(sys_clone , 6) /* 4120 */
2100 MIPS_SYS(sys_setdomainname, 2)
2101 MIPS_SYS(sys_newuname , 1)
2102 MIPS_SYS(sys_ni_syscall , 0) /* sys_modify_ldt */
2103 MIPS_SYS(sys_adjtimex , 1)
2104 MIPS_SYS(sys_mprotect , 3) /* 4125 */
2105 MIPS_SYS(sys_sigprocmask , 3)
2106 MIPS_SYS(sys_ni_syscall , 0) /* was create_module */
2107 MIPS_SYS(sys_init_module , 5)
2108 MIPS_SYS(sys_delete_module, 1)
2109 MIPS_SYS(sys_ni_syscall , 0) /* 4130 was get_kernel_syms */
2110 MIPS_SYS(sys_quotactl , 0)
2111 MIPS_SYS(sys_getpgid , 1)
2112 MIPS_SYS(sys_fchdir , 1)
2113 MIPS_SYS(sys_bdflush , 2)
2114 MIPS_SYS(sys_sysfs , 3) /* 4135 */
2115 MIPS_SYS(sys_personality , 1)
2116 MIPS_SYS(sys_ni_syscall , 0) /* for afs_syscall */
2117 MIPS_SYS(sys_setfsuid , 1)
2118 MIPS_SYS(sys_setfsgid , 1)
2119 MIPS_SYS(sys_llseek , 5) /* 4140 */
2120 MIPS_SYS(sys_getdents , 3)
2121 MIPS_SYS(sys_select , 5)
2122 MIPS_SYS(sys_flock , 2)
2123 MIPS_SYS(sys_msync , 3)
2124 MIPS_SYS(sys_readv , 3) /* 4145 */
2125 MIPS_SYS(sys_writev , 3)
2126 MIPS_SYS(sys_cacheflush , 3)
2127 MIPS_SYS(sys_cachectl , 3)
2128 MIPS_SYS(sys_sysmips , 4)
2129 MIPS_SYS(sys_ni_syscall , 0) /* 4150 */
2130 MIPS_SYS(sys_getsid , 1)
2131 MIPS_SYS(sys_fdatasync , 0)
2132 MIPS_SYS(sys_sysctl , 1)
2133 MIPS_SYS(sys_mlock , 2)
2134 MIPS_SYS(sys_munlock , 2) /* 4155 */
2135 MIPS_SYS(sys_mlockall , 1)
2136 MIPS_SYS(sys_munlockall , 0)
2137 MIPS_SYS(sys_sched_setparam, 2)
2138 MIPS_SYS(sys_sched_getparam, 2)
2139 MIPS_SYS(sys_sched_setscheduler, 3) /* 4160 */
2140 MIPS_SYS(sys_sched_getscheduler, 1)
2141 MIPS_SYS(sys_sched_yield , 0)
2142 MIPS_SYS(sys_sched_get_priority_max, 1)
2143 MIPS_SYS(sys_sched_get_priority_min, 1)
2144 MIPS_SYS(sys_sched_rr_get_interval, 2) /* 4165 */
2145 MIPS_SYS(sys_nanosleep, 2)
2146 MIPS_SYS(sys_mremap , 5)
2147 MIPS_SYS(sys_accept , 3)
2148 MIPS_SYS(sys_bind , 3)
2149 MIPS_SYS(sys_connect , 3) /* 4170 */
2150 MIPS_SYS(sys_getpeername , 3)
2151 MIPS_SYS(sys_getsockname , 3)
2152 MIPS_SYS(sys_getsockopt , 5)
2153 MIPS_SYS(sys_listen , 2)
2154 MIPS_SYS(sys_recv , 4) /* 4175 */
2155 MIPS_SYS(sys_recvfrom , 6)
2156 MIPS_SYS(sys_recvmsg , 3)
2157 MIPS_SYS(sys_send , 4)
2158 MIPS_SYS(sys_sendmsg , 3)
2159 MIPS_SYS(sys_sendto , 6) /* 4180 */
2160 MIPS_SYS(sys_setsockopt , 5)
2161 MIPS_SYS(sys_shutdown , 2)
2162 MIPS_SYS(sys_socket , 3)
2163 MIPS_SYS(sys_socketpair , 4)
2164 MIPS_SYS(sys_setresuid , 3) /* 4185 */
2165 MIPS_SYS(sys_getresuid , 3)
2166 MIPS_SYS(sys_ni_syscall , 0) /* was sys_query_module */
2167 MIPS_SYS(sys_poll , 3)
2168 MIPS_SYS(sys_nfsservctl , 3)
2169 MIPS_SYS(sys_setresgid , 3) /* 4190 */
2170 MIPS_SYS(sys_getresgid , 3)
2171 MIPS_SYS(sys_prctl , 5)
2172 MIPS_SYS(sys_rt_sigreturn, 0)
2173 MIPS_SYS(sys_rt_sigaction, 4)
2174 MIPS_SYS(sys_rt_sigprocmask, 4) /* 4195 */
2175 MIPS_SYS(sys_rt_sigpending, 2)
2176 MIPS_SYS(sys_rt_sigtimedwait, 4)
2177 MIPS_SYS(sys_rt_sigqueueinfo, 3)
2178 MIPS_SYS(sys_rt_sigsuspend, 0)
2179 MIPS_SYS(sys_pread64 , 6) /* 4200 */
2180 MIPS_SYS(sys_pwrite64 , 6)
2181 MIPS_SYS(sys_chown , 3)
2182 MIPS_SYS(sys_getcwd , 2)
2183 MIPS_SYS(sys_capget , 2)
2184 MIPS_SYS(sys_capset , 2) /* 4205 */
2185 MIPS_SYS(sys_sigaltstack , 2)
2186 MIPS_SYS(sys_sendfile , 4)
2187 MIPS_SYS(sys_ni_syscall , 0)
2188 MIPS_SYS(sys_ni_syscall , 0)
2189 MIPS_SYS(sys_mmap2 , 6) /* 4210 */
2190 MIPS_SYS(sys_truncate64 , 4)
2191 MIPS_SYS(sys_ftruncate64 , 4)
2192 MIPS_SYS(sys_stat64 , 2)
2193 MIPS_SYS(sys_lstat64 , 2)
2194 MIPS_SYS(sys_fstat64 , 2) /* 4215 */
2195 MIPS_SYS(sys_pivot_root , 2)
2196 MIPS_SYS(sys_mincore , 3)
2197 MIPS_SYS(sys_madvise , 3)
2198 MIPS_SYS(sys_getdents64 , 3)
2199 MIPS_SYS(sys_fcntl64 , 3) /* 4220 */
2200 MIPS_SYS(sys_ni_syscall , 0)
2201 MIPS_SYS(sys_gettid , 0)
2202 MIPS_SYS(sys_readahead , 5)
2203 MIPS_SYS(sys_setxattr , 5)
2204 MIPS_SYS(sys_lsetxattr , 5) /* 4225 */
2205 MIPS_SYS(sys_fsetxattr , 5)
2206 MIPS_SYS(sys_getxattr , 4)
2207 MIPS_SYS(sys_lgetxattr , 4)
2208 MIPS_SYS(sys_fgetxattr , 4)
2209 MIPS_SYS(sys_listxattr , 3) /* 4230 */
2210 MIPS_SYS(sys_llistxattr , 3)
2211 MIPS_SYS(sys_flistxattr , 3)
2212 MIPS_SYS(sys_removexattr , 2)
2213 MIPS_SYS(sys_lremovexattr, 2)
2214 MIPS_SYS(sys_fremovexattr, 2) /* 4235 */
2215 MIPS_SYS(sys_tkill , 2)
2216 MIPS_SYS(sys_sendfile64 , 5)
2217 MIPS_SYS(sys_futex , 6)
2218 MIPS_SYS(sys_sched_setaffinity, 3)
2219 MIPS_SYS(sys_sched_getaffinity, 3) /* 4240 */
2220 MIPS_SYS(sys_io_setup , 2)
2221 MIPS_SYS(sys_io_destroy , 1)
2222 MIPS_SYS(sys_io_getevents, 5)
2223 MIPS_SYS(sys_io_submit , 3)
2224 MIPS_SYS(sys_io_cancel , 3) /* 4245 */
2225 MIPS_SYS(sys_exit_group , 1)
2226 MIPS_SYS(sys_lookup_dcookie, 3)
2227 MIPS_SYS(sys_epoll_create, 1)
2228 MIPS_SYS(sys_epoll_ctl , 4)
2229 MIPS_SYS(sys_epoll_wait , 3) /* 4250 */
2230 MIPS_SYS(sys_remap_file_pages, 5)
2231 MIPS_SYS(sys_set_tid_address, 1)
2232 MIPS_SYS(sys_restart_syscall, 0)
2233 MIPS_SYS(sys_fadvise64_64, 7)
2234 MIPS_SYS(sys_statfs64 , 3) /* 4255 */
2235 MIPS_SYS(sys_fstatfs64 , 2)
2236 MIPS_SYS(sys_timer_create, 3)
2237 MIPS_SYS(sys_timer_settime, 4)
2238 MIPS_SYS(sys_timer_gettime, 2)
2239 MIPS_SYS(sys_timer_getoverrun, 1) /* 4260 */
2240 MIPS_SYS(sys_timer_delete, 1)
2241 MIPS_SYS(sys_clock_settime, 2)
2242 MIPS_SYS(sys_clock_gettime, 2)
2243 MIPS_SYS(sys_clock_getres, 2)
2244 MIPS_SYS(sys_clock_nanosleep, 4) /* 4265 */
2245 MIPS_SYS(sys_tgkill , 3)
2246 MIPS_SYS(sys_utimes , 2)
2247 MIPS_SYS(sys_mbind , 4)
2248 MIPS_SYS(sys_ni_syscall , 0) /* sys_get_mempolicy */
2249 MIPS_SYS(sys_ni_syscall , 0) /* 4270 sys_set_mempolicy */
2250 MIPS_SYS(sys_mq_open , 4)
2251 MIPS_SYS(sys_mq_unlink , 1)
2252 MIPS_SYS(sys_mq_timedsend, 5)
2253 MIPS_SYS(sys_mq_timedreceive, 5)
2254 MIPS_SYS(sys_mq_notify , 2) /* 4275 */
2255 MIPS_SYS(sys_mq_getsetattr, 3)
2256 MIPS_SYS(sys_ni_syscall , 0) /* sys_vserver */
2257 MIPS_SYS(sys_waitid , 4)
2258 MIPS_SYS(sys_ni_syscall , 0) /* available, was setaltroot */
2259 MIPS_SYS(sys_add_key , 5)
2260 MIPS_SYS(sys_request_key, 4)
2261 MIPS_SYS(sys_keyctl , 5)
2262 MIPS_SYS(sys_set_thread_area, 1)
2263 MIPS_SYS(sys_inotify_init, 0)
2264 MIPS_SYS(sys_inotify_add_watch, 3) /* 4285 */
2265 MIPS_SYS(sys_inotify_rm_watch, 2)
2266 MIPS_SYS(sys_migrate_pages, 4)
2267 MIPS_SYS(sys_openat, 4)
2268 MIPS_SYS(sys_mkdirat, 3)
2269 MIPS_SYS(sys_mknodat, 4) /* 4290 */
2270 MIPS_SYS(sys_fchownat, 5)
2271 MIPS_SYS(sys_futimesat, 3)
2272 MIPS_SYS(sys_fstatat64, 4)
2273 MIPS_SYS(sys_unlinkat, 3)
2274 MIPS_SYS(sys_renameat, 4) /* 4295 */
2275 MIPS_SYS(sys_linkat, 5)
2276 MIPS_SYS(sys_symlinkat, 3)
2277 MIPS_SYS(sys_readlinkat, 4)
2278 MIPS_SYS(sys_fchmodat, 3)
2279 MIPS_SYS(sys_faccessat, 3) /* 4300 */
2280 MIPS_SYS(sys_pselect6, 6)
2281 MIPS_SYS(sys_ppoll, 5)
2282 MIPS_SYS(sys_unshare, 1)
2283 MIPS_SYS(sys_splice, 6)
2284 MIPS_SYS(sys_sync_file_range, 7) /* 4305 */
2285 MIPS_SYS(sys_tee, 4)
2286 MIPS_SYS(sys_vmsplice, 4)
2287 MIPS_SYS(sys_move_pages, 6)
2288 MIPS_SYS(sys_set_robust_list, 2)
2289 MIPS_SYS(sys_get_robust_list, 3) /* 4310 */
2290 MIPS_SYS(sys_kexec_load, 4)
2291 MIPS_SYS(sys_getcpu, 3)
2292 MIPS_SYS(sys_epoll_pwait, 6)
2293 MIPS_SYS(sys_ioprio_set, 3)
2294 MIPS_SYS(sys_ioprio_get, 2)
2295 MIPS_SYS(sys_utimensat, 4)
2296 MIPS_SYS(sys_signalfd, 3)
2297 MIPS_SYS(sys_ni_syscall, 0) /* was timerfd */
2298 MIPS_SYS(sys_eventfd, 1)
2299 MIPS_SYS(sys_fallocate, 6) /* 4320 */
2300 MIPS_SYS(sys_timerfd_create, 2)
2301 MIPS_SYS(sys_timerfd_gettime, 2)
2302 MIPS_SYS(sys_timerfd_settime, 4)
2303 MIPS_SYS(sys_signalfd4, 4)
2304 MIPS_SYS(sys_eventfd2, 2) /* 4325 */
2305 MIPS_SYS(sys_epoll_create1, 1)
2306 MIPS_SYS(sys_dup3, 3)
2307 MIPS_SYS(sys_pipe2, 2)
2308 MIPS_SYS(sys_inotify_init1, 1)
2309 MIPS_SYS(sys_preadv, 6) /* 4330 */
2310 MIPS_SYS(sys_pwritev, 6)
2311 MIPS_SYS(sys_rt_tgsigqueueinfo, 4)
2312 MIPS_SYS(sys_perf_event_open, 5)
2313 MIPS_SYS(sys_accept4, 4)
2314 MIPS_SYS(sys_recvmmsg, 5) /* 4335 */
2315 MIPS_SYS(sys_fanotify_init, 2)
2316 MIPS_SYS(sys_fanotify_mark, 6)
2317 MIPS_SYS(sys_prlimit64, 4)
2318 MIPS_SYS(sys_name_to_handle_at, 5)
2319 MIPS_SYS(sys_open_by_handle_at, 3) /* 4340 */
2320 MIPS_SYS(sys_clock_adjtime, 2)
2321 MIPS_SYS(sys_syncfs, 1)
2322 };
2323 # undef MIPS_SYS
2324 # endif /* O32 */
2325
2326 static int do_store_exclusive(CPUMIPSState *env)
2327 {
2328 target_ulong addr;
2329 target_ulong page_addr;
2330 target_ulong val;
2331 int flags;
2332 int segv = 0;
2333 int reg;
2334 int d;
2335
2336 addr = env->lladdr;
2337 page_addr = addr & TARGET_PAGE_MASK;
2338 start_exclusive();
2339 mmap_lock();
2340 flags = page_get_flags(page_addr);
2341 if ((flags & PAGE_READ) == 0) {
2342 segv = 1;
2343 } else {
2344 reg = env->llreg & 0x1f;
2345 d = (env->llreg & 0x20) != 0;
2346 if (d) {
2347 segv = get_user_s64(val, addr);
2348 } else {
2349 segv = get_user_s32(val, addr);
2350 }
2351 if (!segv) {
2352 if (val != env->llval) {
2353 env->active_tc.gpr[reg] = 0;
2354 } else {
2355 if (d) {
2356 segv = put_user_u64(env->llnewval, addr);
2357 } else {
2358 segv = put_user_u32(env->llnewval, addr);
2359 }
2360 if (!segv) {
2361 env->active_tc.gpr[reg] = 1;
2362 }
2363 }
2364 }
2365 }
2366 env->lladdr = -1;
2367 if (!segv) {
2368 env->active_tc.PC += 4;
2369 }
2370 mmap_unlock();
2371 end_exclusive();
2372 return segv;
2373 }
2374
2375 /* Break codes */
2376 enum {
2377 BRK_OVERFLOW = 6,
2378 BRK_DIVZERO = 7
2379 };
2380
2381 static int do_break(CPUMIPSState *env, target_siginfo_t *info,
2382 unsigned int code)
2383 {
2384 int ret = -1;
2385
2386 switch (code) {
2387 case BRK_OVERFLOW:
2388 case BRK_DIVZERO:
2389 info->si_signo = TARGET_SIGFPE;
2390 info->si_errno = 0;
2391 info->si_code = (code == BRK_OVERFLOW) ? FPE_INTOVF : FPE_INTDIV;
2392 queue_signal(env, info->si_signo, &*info);
2393 ret = 0;
2394 break;
2395 default:
2396 info->si_signo = TARGET_SIGTRAP;
2397 info->si_errno = 0;
2398 queue_signal(env, info->si_signo, &*info);
2399 ret = 0;
2400 break;
2401 }
2402
2403 return ret;
2404 }
2405
2406 void cpu_loop(CPUMIPSState *env)
2407 {
2408 CPUState *cs = CPU(mips_env_get_cpu(env));
2409 target_siginfo_t info;
2410 int trapnr;
2411 abi_long ret;
2412 # ifdef TARGET_ABI_MIPSO32
2413 unsigned int syscall_num;
2414 # endif
2415
2416 for(;;) {
2417 cpu_exec_start(cs);
2418 trapnr = cpu_mips_exec(cs);
2419 cpu_exec_end(cs);
2420 switch(trapnr) {
2421 case EXCP_SYSCALL:
2422 env->active_tc.PC += 4;
2423 # ifdef TARGET_ABI_MIPSO32
2424 syscall_num = env->active_tc.gpr[2] - 4000;
2425 if (syscall_num >= sizeof(mips_syscall_args)) {
2426 ret = -TARGET_ENOSYS;
2427 } else {
2428 int nb_args;
2429 abi_ulong sp_reg;
2430 abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
2431
2432 nb_args = mips_syscall_args[syscall_num];
2433 sp_reg = env->active_tc.gpr[29];
2434 switch (nb_args) {
2435 /* these arguments are taken from the stack */
2436 case 8:
2437 if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
2438 goto done_syscall;
2439 }
2440 case 7:
2441 if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
2442 goto done_syscall;
2443 }
2444 case 6:
2445 if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
2446 goto done_syscall;
2447 }
2448 case 5:
2449 if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
2450 goto done_syscall;
2451 }
2452 default:
2453 break;
2454 }
2455 ret = do_syscall(env, env->active_tc.gpr[2],
2456 env->active_tc.gpr[4],
2457 env->active_tc.gpr[5],
2458 env->active_tc.gpr[6],
2459 env->active_tc.gpr[7],
2460 arg5, arg6, arg7, arg8);
2461 }
2462 done_syscall:
2463 # else
2464 ret = do_syscall(env, env->active_tc.gpr[2],
2465 env->active_tc.gpr[4], env->active_tc.gpr[5],
2466 env->active_tc.gpr[6], env->active_tc.gpr[7],
2467 env->active_tc.gpr[8], env->active_tc.gpr[9],
2468 env->active_tc.gpr[10], env->active_tc.gpr[11]);
2469 # endif /* O32 */
2470 if (ret == -TARGET_QEMU_ESIGRETURN) {
2471 /* Returning from a successful sigreturn syscall.
2472 Avoid clobbering register state. */
2473 break;
2474 }
2475 if ((abi_ulong)ret >= (abi_ulong)-1133) {
2476 env->active_tc.gpr[7] = 1; /* error flag */
2477 ret = -ret;
2478 } else {
2479 env->active_tc.gpr[7] = 0; /* error flag */
2480 }
2481 env->active_tc.gpr[2] = ret;
2482 break;
2483 case EXCP_TLBL:
2484 case EXCP_TLBS:
2485 case EXCP_AdEL:
2486 case EXCP_AdES:
2487 info.si_signo = TARGET_SIGSEGV;
2488 info.si_errno = 0;
2489 /* XXX: check env->error_code */
2490 info.si_code = TARGET_SEGV_MAPERR;
2491 info._sifields._sigfault._addr = env->CP0_BadVAddr;
2492 queue_signal(env, info.si_signo, &info);
2493 break;
2494 case EXCP_CpU:
2495 case EXCP_RI:
2496 info.si_signo = TARGET_SIGILL;
2497 info.si_errno = 0;
2498 info.si_code = 0;
2499 queue_signal(env, info.si_signo, &info);
2500 break;
2501 case EXCP_INTERRUPT:
2502 /* just indicate that signals should be handled asap */
2503 break;
2504 case EXCP_DEBUG:
2505 {
2506 int sig;
2507
2508 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2509 if (sig)
2510 {
2511 info.si_signo = sig;
2512 info.si_errno = 0;
2513 info.si_code = TARGET_TRAP_BRKPT;
2514 queue_signal(env, info.si_signo, &info);
2515 }
2516 }
2517 break;
2518 case EXCP_SC:
2519 if (do_store_exclusive(env)) {
2520 info.si_signo = TARGET_SIGSEGV;
2521 info.si_errno = 0;
2522 info.si_code = TARGET_SEGV_MAPERR;
2523 info._sifields._sigfault._addr = env->active_tc.PC;
2524 queue_signal(env, info.si_signo, &info);
2525 }
2526 break;
2527 case EXCP_DSPDIS:
2528 info.si_signo = TARGET_SIGILL;
2529 info.si_errno = 0;
2530 info.si_code = TARGET_ILL_ILLOPC;
2531 queue_signal(env, info.si_signo, &info);
2532 break;
2533 /* The code below was inspired by the MIPS Linux kernel trap
2534 * handling code in arch/mips/kernel/traps.c.
2535 */
2536 case EXCP_BREAK:
2537 {
2538 abi_ulong trap_instr;
2539 unsigned int code;
2540
2541 if (env->hflags & MIPS_HFLAG_M16) {
2542 if (env->insn_flags & ASE_MICROMIPS) {
2543 /* microMIPS mode */
2544 ret = get_user_u16(trap_instr, env->active_tc.PC);
2545 if (ret != 0) {
2546 goto error;
2547 }
2548
2549 if ((trap_instr >> 10) == 0x11) {
2550 /* 16-bit instruction */
2551 code = trap_instr & 0xf;
2552 } else {
2553 /* 32-bit instruction */
2554 abi_ulong instr_lo;
2555
2556 ret = get_user_u16(instr_lo,
2557 env->active_tc.PC + 2);
2558 if (ret != 0) {
2559 goto error;
2560 }
2561 trap_instr = (trap_instr << 16) | instr_lo;
2562 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2563 /* Unfortunately, microMIPS also suffers from
2564 the old assembler bug... */
2565 if (code >= (1 << 10)) {
2566 code >>= 10;
2567 }
2568 }
2569 } else {
2570 /* MIPS16e mode */
2571 ret = get_user_u16(trap_instr, env->active_tc.PC);
2572 if (ret != 0) {
2573 goto error;
2574 }
2575 code = (trap_instr >> 6) & 0x3f;
2576 }
2577 } else {
2578 ret = get_user_u32(trap_instr, env->active_tc.PC);
2579 if (ret != 0) {
2580 goto error;
2581 }
2582
2583 /* As described in the original Linux kernel code, the
2584 * below checks on 'code' are to work around an old
2585 * assembly bug.
2586 */
2587 code = ((trap_instr >> 6) & ((1 << 20) - 1));
2588 if (code >= (1 << 10)) {
2589 code >>= 10;
2590 }
2591 }
2592
2593 if (do_break(env, &info, code) != 0) {
2594 goto error;
2595 }
2596 }
2597 break;
2598 case EXCP_TRAP:
2599 {
2600 abi_ulong trap_instr;
2601 unsigned int code = 0;
2602
2603 if (env->hflags & MIPS_HFLAG_M16) {
2604 /* microMIPS mode */
2605 abi_ulong instr[2];
2606
2607 ret = get_user_u16(instr[0], env->active_tc.PC) ||
2608 get_user_u16(instr[1], env->active_tc.PC + 2);
2609
2610 trap_instr = (instr[0] << 16) | instr[1];
2611 } else {
2612 ret = get_user_u32(trap_instr, env->active_tc.PC);
2613 }
2614
2615 if (ret != 0) {
2616 goto error;
2617 }
2618
2619 /* The immediate versions don't provide a code. */
2620 if (!(trap_instr & 0xFC000000)) {
2621 if (env->hflags & MIPS_HFLAG_M16) {
2622 /* microMIPS mode */
2623 code = ((trap_instr >> 12) & ((1 << 4) - 1));
2624 } else {
2625 code = ((trap_instr >> 6) & ((1 << 10) - 1));
2626 }
2627 }
2628
2629 if (do_break(env, &info, code) != 0) {
2630 goto error;
2631 }
2632 }
2633 break;
2634 default:
2635 error:
2636 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
2637 trapnr);
2638 cpu_dump_state(cs, stderr, fprintf, 0);
2639 abort();
2640 }
2641 process_pending_signals(env);
2642 }
2643 }
2644 #endif
2645
2646 #ifdef TARGET_OPENRISC
2647
2648 void cpu_loop(CPUOpenRISCState *env)
2649 {
2650 CPUState *cs = CPU(openrisc_env_get_cpu(env));
2651 int trapnr, gdbsig;
2652
2653 for (;;) {
2654 cpu_exec_start(cs);
2655 trapnr = cpu_openrisc_exec(cs);
2656 cpu_exec_end(cs);
2657 gdbsig = 0;
2658
2659 switch (trapnr) {
2660 case EXCP_RESET:
2661 qemu_log("\nReset request, exit, pc is %#x\n", env->pc);
2662 exit(1);
2663 break;
2664 case EXCP_BUSERR:
2665 qemu_log("\nBus error, exit, pc is %#x\n", env->pc);
2666 gdbsig = TARGET_SIGBUS;
2667 break;
2668 case EXCP_DPF:
2669 case EXCP_IPF:
2670 cpu_dump_state(cs, stderr, fprintf, 0);
2671 gdbsig = TARGET_SIGSEGV;
2672 break;
2673 case EXCP_TICK:
2674 qemu_log("\nTick time interrupt pc is %#x\n", env->pc);
2675 break;
2676 case EXCP_ALIGN:
2677 qemu_log("\nAlignment pc is %#x\n", env->pc);
2678 gdbsig = TARGET_SIGBUS;
2679 break;
2680 case EXCP_ILLEGAL:
2681 qemu_log("\nIllegal instructionpc is %#x\n", env->pc);
2682 gdbsig = TARGET_SIGILL;
2683 break;
2684 case EXCP_INT:
2685 qemu_log("\nExternal interruptpc is %#x\n", env->pc);
2686 break;
2687 case EXCP_DTLBMISS:
2688 case EXCP_ITLBMISS:
2689 qemu_log("\nTLB miss\n");
2690 break;
2691 case EXCP_RANGE:
2692 qemu_log("\nRange\n");
2693 gdbsig = TARGET_SIGSEGV;
2694 break;
2695 case EXCP_SYSCALL:
2696 env->pc += 4; /* 0xc00; */
2697 env->gpr[11] = do_syscall(env,
2698 env->gpr[11], /* return value */
2699 env->gpr[3], /* r3 - r7 are params */
2700 env->gpr[4],
2701 env->gpr[5],
2702 env->gpr[6],
2703 env->gpr[7],
2704 env->gpr[8], 0, 0);
2705 break;
2706 case EXCP_FPE:
2707 qemu_log("\nFloating point error\n");
2708 break;
2709 case EXCP_TRAP:
2710 qemu_log("\nTrap\n");
2711 gdbsig = TARGET_SIGTRAP;
2712 break;
2713 case EXCP_NR:
2714 qemu_log("\nNR\n");
2715 break;
2716 default:
2717 qemu_log("\nqemu: unhandled CPU exception %#x - aborting\n",
2718 trapnr);
2719 cpu_dump_state(cs, stderr, fprintf, 0);
2720 gdbsig = TARGET_SIGILL;
2721 break;
2722 }
2723 if (gdbsig) {
2724 gdb_handlesig(cs, gdbsig);
2725 if (gdbsig != TARGET_SIGTRAP) {
2726 exit(1);
2727 }
2728 }
2729
2730 process_pending_signals(env);
2731 }
2732 }
2733
2734 #endif /* TARGET_OPENRISC */
2735
2736 #ifdef TARGET_SH4
2737 void cpu_loop(CPUSH4State *env)
2738 {
2739 CPUState *cs = CPU(sh_env_get_cpu(env));
2740 int trapnr, ret;
2741 target_siginfo_t info;
2742
2743 while (1) {
2744 cpu_exec_start(cs);
2745 trapnr = cpu_sh4_exec(cs);
2746 cpu_exec_end(cs);
2747
2748 switch (trapnr) {
2749 case 0x160:
2750 env->pc += 2;
2751 ret = do_syscall(env,
2752 env->gregs[3],
2753 env->gregs[4],
2754 env->gregs[5],
2755 env->gregs[6],
2756 env->gregs[7],
2757 env->gregs[0],
2758 env->gregs[1],
2759 0, 0);
2760 env->gregs[0] = ret;
2761 break;
2762 case EXCP_INTERRUPT:
2763 /* just indicate that signals should be handled asap */
2764 break;
2765 case EXCP_DEBUG:
2766 {
2767 int sig;
2768
2769 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2770 if (sig)
2771 {
2772 info.si_signo = sig;
2773 info.si_errno = 0;
2774 info.si_code = TARGET_TRAP_BRKPT;
2775 queue_signal(env, info.si_signo, &info);
2776 }
2777 }
2778 break;
2779 case 0xa0:
2780 case 0xc0:
2781 info.si_signo = TARGET_SIGSEGV;
2782 info.si_errno = 0;
2783 info.si_code = TARGET_SEGV_MAPERR;
2784 info._sifields._sigfault._addr = env->tea;
2785 queue_signal(env, info.si_signo, &info);
2786 break;
2787
2788 default:
2789 printf ("Unhandled trap: 0x%x\n", trapnr);
2790 cpu_dump_state(cs, stderr, fprintf, 0);
2791 exit (1);
2792 }
2793 process_pending_signals (env);
2794 }
2795 }
2796 #endif
2797
2798 #ifdef TARGET_CRIS
2799 void cpu_loop(CPUCRISState *env)
2800 {
2801 CPUState *cs = CPU(cris_env_get_cpu(env));
2802 int trapnr, ret;
2803 target_siginfo_t info;
2804
2805 while (1) {
2806 cpu_exec_start(cs);
2807 trapnr = cpu_cris_exec(cs);
2808 cpu_exec_end(cs);
2809 switch (trapnr) {
2810 case 0xaa:
2811 {
2812 info.si_signo = TARGET_SIGSEGV;
2813 info.si_errno = 0;
2814 /* XXX: check env->error_code */
2815 info.si_code = TARGET_SEGV_MAPERR;
2816 info._sifields._sigfault._addr = env->pregs[PR_EDA];
2817 queue_signal(env, info.si_signo, &info);
2818 }
2819 break;
2820 case EXCP_INTERRUPT:
2821 /* just indicate that signals should be handled asap */
2822 break;
2823 case EXCP_BREAK:
2824 ret = do_syscall(env,
2825 env->regs[9],
2826 env->regs[10],
2827 env->regs[11],
2828 env->regs[12],
2829 env->regs[13],
2830 env->pregs[7],
2831 env->pregs[11],
2832 0, 0);
2833 env->regs[10] = ret;
2834 break;
2835 case EXCP_DEBUG:
2836 {
2837 int sig;
2838
2839 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2840 if (sig)
2841 {
2842 info.si_signo = sig;
2843 info.si_errno = 0;
2844 info.si_code = TARGET_TRAP_BRKPT;
2845 queue_signal(env, info.si_signo, &info);
2846 }
2847 }
2848 break;
2849 default:
2850 printf ("Unhandled trap: 0x%x\n", trapnr);
2851 cpu_dump_state(cs, stderr, fprintf, 0);
2852 exit (1);
2853 }
2854 process_pending_signals (env);
2855 }
2856 }
2857 #endif
2858
2859 #ifdef TARGET_MICROBLAZE
2860 void cpu_loop(CPUMBState *env)
2861 {
2862 CPUState *cs = CPU(mb_env_get_cpu(env));
2863 int trapnr, ret;
2864 target_siginfo_t info;
2865
2866 while (1) {
2867 cpu_exec_start(cs);
2868 trapnr = cpu_mb_exec(cs);
2869 cpu_exec_end(cs);
2870 switch (trapnr) {
2871 case 0xaa:
2872 {
2873 info.si_signo = TARGET_SIGSEGV;
2874 info.si_errno = 0;
2875 /* XXX: check env->error_code */
2876 info.si_code = TARGET_SEGV_MAPERR;
2877 info._sifields._sigfault._addr = 0;
2878 queue_signal(env, info.si_signo, &info);
2879 }
2880 break;
2881 case EXCP_INTERRUPT:
2882 /* just indicate that signals should be handled asap */
2883 break;
2884 case EXCP_BREAK:
2885 /* Return address is 4 bytes after the call. */
2886 env->regs[14] += 4;
2887 env->sregs[SR_PC] = env->regs[14];
2888 ret = do_syscall(env,
2889 env->regs[12],
2890 env->regs[5],
2891 env->regs[6],
2892 env->regs[7],
2893 env->regs[8],
2894 env->regs[9],
2895 env->regs[10],
2896 0, 0);
2897 env->regs[3] = ret;
2898 break;
2899 case EXCP_HW_EXCP:
2900 env->regs[17] = env->sregs[SR_PC] + 4;
2901 if (env->iflags & D_FLAG) {
2902 env->sregs[SR_ESR] |= 1 << 12;
2903 env->sregs[SR_PC] -= 4;
2904 /* FIXME: if branch was immed, replay the imm as well. */
2905 }
2906
2907 env->iflags &= ~(IMM_FLAG | D_FLAG);
2908
2909 switch (env->sregs[SR_ESR] & 31) {
2910 case ESR_EC_DIVZERO:
2911 info.si_signo = TARGET_SIGFPE;
2912 info.si_errno = 0;
2913 info.si_code = TARGET_FPE_FLTDIV;
2914 info._sifields._sigfault._addr = 0;
2915 queue_signal(env, info.si_signo, &info);
2916 break;
2917 case ESR_EC_FPU:
2918 info.si_signo = TARGET_SIGFPE;
2919 info.si_errno = 0;
2920 if (env->sregs[SR_FSR] & FSR_IO) {
2921 info.si_code = TARGET_FPE_FLTINV;
2922 }
2923 if (env->sregs[SR_FSR] & FSR_DZ) {
2924 info.si_code = TARGET_FPE_FLTDIV;
2925 }
2926 info._sifields._sigfault._addr = 0;
2927 queue_signal(env, info.si_signo, &info);
2928 break;
2929 default:
2930 printf ("Unhandled hw-exception: 0x%x\n",
2931 env->sregs[SR_ESR] & ESR_EC_MASK);
2932 cpu_dump_state(cs, stderr, fprintf, 0);
2933 exit (1);
2934 break;
2935 }
2936 break;
2937 case EXCP_DEBUG:
2938 {
2939 int sig;
2940
2941 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
2942 if (sig)
2943 {
2944 info.si_signo = sig;
2945 info.si_errno = 0;
2946 info.si_code = TARGET_TRAP_BRKPT;
2947 queue_signal(env, info.si_signo, &info);
2948 }
2949 }
2950 break;
2951 default:
2952 printf ("Unhandled trap: 0x%x\n", trapnr);
2953 cpu_dump_state(cs, stderr, fprintf, 0);
2954 exit (1);
2955 }
2956 process_pending_signals (env);
2957 }
2958 }
2959 #endif
2960
2961 #ifdef TARGET_M68K
2962
2963 void cpu_loop(CPUM68KState *env)
2964 {
2965 CPUState *cs = CPU(m68k_env_get_cpu(env));
2966 int trapnr;
2967 unsigned int n;
2968 target_siginfo_t info;
2969 TaskState *ts = cs->opaque;
2970
2971 for(;;) {
2972 cpu_exec_start(cs);
2973 trapnr = cpu_m68k_exec(cs);
2974 cpu_exec_end(cs);
2975 switch(trapnr) {
2976 case EXCP_ILLEGAL:
2977 {
2978 if (ts->sim_syscalls) {
2979 uint16_t nr;
2980 get_user_u16(nr, env->pc + 2);
2981 env->pc += 4;
2982 do_m68k_simcall(env, nr);
2983 } else {
2984 goto do_sigill;
2985 }
2986 }
2987 break;
2988 case EXCP_HALT_INSN:
2989 /* Semihosing syscall. */
2990 env->pc += 4;
2991 do_m68k_semihosting(env, env->dregs[0]);
2992 break;
2993 case EXCP_LINEA:
2994 case EXCP_LINEF:
2995 case EXCP_UNSUPPORTED:
2996 do_sigill:
2997 info.si_signo = TARGET_SIGILL;
2998 info.si_errno = 0;
2999 info.si_code = TARGET_ILL_ILLOPN;
3000 info._sifields._sigfault._addr = env->pc;
3001 queue_signal(env, info.si_signo, &info);
3002 break;
3003 case EXCP_TRAP0:
3004 {
3005 ts->sim_syscalls = 0;
3006 n = env->dregs[0];
3007 env->pc += 2;
3008 env->dregs[0] = do_syscall(env,
3009 n,
3010 env->dregs[1],
3011 env->dregs[2],
3012 env->dregs[3],
3013 env->dregs[4],
3014 env->dregs[5],
3015 env->aregs[0],
3016 0, 0);
3017 }
3018 break;
3019 case EXCP_INTERRUPT:
3020 /* just indicate that signals should be handled asap */
3021 break;
3022 case EXCP_ACCESS:
3023 {
3024 info.si_signo = TARGET_SIGSEGV;
3025 info.si_errno = 0;
3026 /* XXX: check env->error_code */
3027 info.si_code = TARGET_SEGV_MAPERR;
3028 info._sifields._sigfault._addr = env->mmu.ar;
3029 queue_signal(env, info.si_signo, &info);
3030 }
3031 break;
3032 case EXCP_DEBUG:
3033 {
3034 int sig;
3035
3036 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3037 if (sig)
3038 {
3039 info.si_signo = sig;
3040 info.si_errno = 0;
3041 info.si_code = TARGET_TRAP_BRKPT;
3042 queue_signal(env, info.si_signo, &info);
3043 }
3044 }
3045 break;
3046 default:
3047 fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",
3048 trapnr);
3049 cpu_dump_state(cs, stderr, fprintf, 0);
3050 abort();
3051 }
3052 process_pending_signals(env);
3053 }
3054 }
3055 #endif /* TARGET_M68K */
3056
3057 #ifdef TARGET_ALPHA
3058 static void do_store_exclusive(CPUAlphaState *env, int reg, int quad)
3059 {
3060 target_ulong addr, val, tmp;
3061 target_siginfo_t info;
3062 int ret = 0;
3063
3064 addr = env->lock_addr;
3065 tmp = env->lock_st_addr;
3066 env->lock_addr = -1;
3067 env->lock_st_addr = 0;
3068
3069 start_exclusive();
3070 mmap_lock();
3071
3072 if (addr == tmp) {
3073 if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
3074 goto do_sigsegv;
3075 }
3076
3077 if (val == env->lock_value) {
3078 tmp = env->ir[reg];
3079 if (quad ? put_user_u64(tmp, addr) : put_user_u32(tmp, addr)) {
3080 goto do_sigsegv;
3081 }
3082 ret = 1;
3083 }
3084 }
3085 env->ir[reg] = ret;
3086 env->pc += 4;
3087
3088 mmap_unlock();
3089 end_exclusive();
3090 return;
3091
3092 do_sigsegv:
3093 mmap_unlock();
3094 end_exclusive();
3095
3096 info.si_signo = TARGET_SIGSEGV;
3097 info.si_errno = 0;
3098 info.si_code = TARGET_SEGV_MAPERR;
3099 info._sifields._sigfault._addr = addr;
3100 queue_signal(env, TARGET_SIGSEGV, &info);
3101 }
3102
3103 void cpu_loop(CPUAlphaState *env)
3104 {
3105 CPUState *cs = CPU(alpha_env_get_cpu(env));
3106 int trapnr;
3107 target_siginfo_t info;
3108 abi_long sysret;
3109
3110 while (1) {
3111 cpu_exec_start(cs);
3112 trapnr = cpu_alpha_exec(cs);
3113 cpu_exec_end(cs);
3114
3115 /* All of the traps imply a transition through PALcode, which
3116 implies an REI instruction has been executed. Which means
3117 that the intr_flag should be cleared. */
3118 env->intr_flag = 0;
3119
3120 switch (trapnr) {
3121 case EXCP_RESET:
3122 fprintf(stderr, "Reset requested. Exit\n");
3123 exit(1);
3124 break;
3125 case EXCP_MCHK:
3126 fprintf(stderr, "Machine check exception. Exit\n");
3127 exit(1);
3128 break;
3129 case EXCP_SMP_INTERRUPT:
3130 case EXCP_CLK_INTERRUPT:
3131 case EXCP_DEV_INTERRUPT:
3132 fprintf(stderr, "External interrupt. Exit\n");
3133 exit(1);
3134 break;
3135 case EXCP_MMFAULT:
3136 env->lock_addr = -1;
3137 info.si_signo = TARGET_SIGSEGV;
3138 info.si_errno = 0;
3139 info.si_code = (page_get_flags(env->trap_arg0) & PAGE_VALID
3140 ? TARGET_SEGV_ACCERR : TARGET_SEGV_MAPERR);
3141 info._sifields._sigfault._addr = env->trap_arg0;
3142 queue_signal(env, info.si_signo, &info);
3143 break;
3144 case EXCP_UNALIGN:
3145 env->lock_addr = -1;
3146 info.si_signo = TARGET_SIGBUS;
3147 info.si_errno = 0;
3148 info.si_code = TARGET_BUS_ADRALN;
3149 info._sifields._sigfault._addr = env->trap_arg0;
3150 queue_signal(env, info.si_signo, &info);
3151 break;
3152 case EXCP_OPCDEC:
3153 do_sigill:
3154 env->lock_addr = -1;
3155 info.si_signo = TARGET_SIGILL;
3156 info.si_errno = 0;
3157 info.si_code = TARGET_ILL_ILLOPC;
3158 info._sifields._sigfault._addr = env->pc;
3159 queue_signal(env, info.si_signo, &info);
3160 break;
3161 case EXCP_ARITH:
3162 env->lock_addr = -1;
3163 info.si_signo = TARGET_SIGFPE;
3164 info.si_errno = 0;
3165 info.si_code = TARGET_FPE_FLTINV;
3166 info._sifields._sigfault._addr = env->pc;
3167 queue_signal(env, info.si_signo, &info);
3168 break;
3169 case EXCP_FEN:
3170 /* No-op. Linux simply re-enables the FPU. */
3171 break;
3172 case EXCP_CALL_PAL:
3173 env->lock_addr = -1;
3174 switch (env->error_code) {
3175 case 0x80:
3176 /* BPT */
3177 info.si_signo = TARGET_SIGTRAP;
3178 info.si_errno = 0;
3179 info.si_code = TARGET_TRAP_BRKPT;
3180 info._sifields._sigfault._addr = env->pc;
3181 queue_signal(env, info.si_signo, &info);
3182 break;
3183 case 0x81:
3184 /* BUGCHK */
3185 info.si_signo = TARGET_SIGTRAP;
3186 info.si_errno = 0;
3187 info.si_code = 0;
3188 info._sifields._sigfault._addr = env->pc;
3189 queue_signal(env, info.si_signo, &info);
3190 break;
3191 case 0x83:
3192 /* CALLSYS */
3193 trapnr = env->ir[IR_V0];
3194 sysret = do_syscall(env, trapnr,
3195 env->ir[IR_A0], env->ir[IR_A1],
3196 env->ir[IR_A2], env->ir[IR_A3],
3197 env->ir[IR_A4], env->ir[IR_A5],
3198 0, 0);
3199 if (trapnr == TARGET_NR_sigreturn
3200 || trapnr == TARGET_NR_rt_sigreturn) {
3201 break;
3202 }
3203 /* Syscall writes 0 to V0 to bypass error check, similar
3204 to how this is handled internal to Linux kernel.
3205 (Ab)use trapnr temporarily as boolean indicating error. */
3206 trapnr = (env->ir[IR_V0] != 0 && sysret < 0);
3207 env->ir[IR_V0] = (trapnr ? -sysret : sysret);
3208 env->ir[IR_A3] = trapnr;
3209 break;
3210 case 0x86:
3211 /* IMB */
3212 /* ??? We can probably elide the code using page_unprotect
3213 that is checking for self-modifying code. Instead we
3214 could simply call tb_flush here. Until we work out the
3215 changes required to turn off the extra write protection,
3216 this can be a no-op. */
3217 break;
3218 case 0x9E:
3219 /* RDUNIQUE */
3220 /* Handled in the translator for usermode. */
3221 abort();
3222 case 0x9F:
3223 /* WRUNIQUE */
3224 /* Handled in the translator for usermode. */
3225 abort();
3226 case 0xAA:
3227 /* GENTRAP */
3228 info.si_signo = TARGET_SIGFPE;
3229 switch (env->ir[IR_A0]) {
3230 case TARGET_GEN_INTOVF:
3231 info.si_code = TARGET_FPE_INTOVF;
3232 break;
3233 case TARGET_GEN_INTDIV:
3234 info.si_code = TARGET_FPE_INTDIV;
3235 break;
3236 case TARGET_GEN_FLTOVF:
3237 info.si_code = TARGET_FPE_FLTOVF;
3238 break;
3239 case TARGET_GEN_FLTUND:
3240 info.si_code = TARGET_FPE_FLTUND;
3241 break;
3242 case TARGET_GEN_FLTINV:
3243 info.si_code = TARGET_FPE_FLTINV;
3244 break;
3245 case TARGET_GEN_FLTINE:
3246 info.si_code = TARGET_FPE_FLTRES;
3247 break;
3248 case TARGET_GEN_ROPRAND:
3249 info.si_code = 0;
3250 break;
3251 default:
3252 info.si_signo = TARGET_SIGTRAP;
3253 info.si_code = 0;
3254 break;
3255 }
3256 info.si_errno = 0;
3257 info._sifields._sigfault._addr = env->pc;
3258 queue_signal(env, info.si_signo, &info);
3259 break;
3260 default:
3261 goto do_sigill;
3262 }
3263 break;
3264 case EXCP_DEBUG:
3265 info.si_signo = gdb_handlesig(cs, TARGET_SIGTRAP);
3266 if (info.si_signo) {
3267 env->lock_addr = -1;
3268 info.si_errno = 0;
3269 info.si_code = TARGET_TRAP_BRKPT;
3270 queue_signal(env, info.si_signo, &info);
3271 }
3272 break;
3273 case EXCP_STL_C:
3274 case EXCP_STQ_C:
3275 do_store_exclusive(env, env->error_code, trapnr - EXCP_STL_C);
3276 break;
3277 case EXCP_INTERRUPT:
3278 /* Just indicate that signals should be handled asap. */
3279 break;
3280 default:
3281 printf ("Unhandled trap: 0x%x\n", trapnr);
3282 cpu_dump_state(cs, stderr, fprintf, 0);
3283 exit (1);
3284 }
3285 process_pending_signals (env);
3286 }
3287 }
3288 #endif /* TARGET_ALPHA */
3289
3290 #ifdef TARGET_S390X
3291 void cpu_loop(CPUS390XState *env)
3292 {
3293 CPUState *cs = CPU(s390_env_get_cpu(env));
3294 int trapnr, n, sig;
3295 target_siginfo_t info;
3296 target_ulong addr;
3297
3298 while (1) {
3299 cpu_exec_start(cs);
3300 trapnr = cpu_s390x_exec(cs);
3301 cpu_exec_end(cs);
3302 switch (trapnr) {
3303 case EXCP_INTERRUPT:
3304 /* Just indicate that signals should be handled asap. */
3305 break;
3306
3307 case EXCP_SVC:
3308 n = env->int_svc_code;
3309 if (!n) {
3310 /* syscalls > 255 */
3311 n = env->regs[1];
3312 }
3313 env->psw.addr += env->int_svc_ilen;
3314 env->regs[2] = do_syscall(env, n, env->regs[2], env->regs[3],
3315 env->regs[4], env->regs[5],
3316 env->regs[6], env->regs[7], 0, 0);
3317 break;
3318
3319 case EXCP_DEBUG:
3320 sig = gdb_handlesig(cs, TARGET_SIGTRAP);
3321 if (sig) {
3322 n = TARGET_TRAP_BRKPT;
3323 goto do_signal_pc;
3324 }
3325 break;
3326 case EXCP_PGM:
3327 n = env->int_pgm_code;
3328 switch (n) {
3329 case PGM_OPERATION:
3330 case PGM_PRIVILEGED:
3331 sig = TARGET_SIGILL;
3332 n = TARGET_ILL_ILLOPC;
3333 goto do_signal_pc;
3334 case PGM_PROTECTION:
3335 case PGM_ADDRESSING:
3336 sig = TARGET_SIGSEGV;
3337 /* XXX: check env->error_code */
3338 n = TARGET_SEGV_MAPERR;
3339 addr = env->__excp_addr;
3340 goto do_signal;
3341 case PGM_EXECUTE:
3342 case PGM_SPECIFICATION:
3343 case PGM_SPECIAL_OP:
3344 case PGM_OPERAND:
3345 do_sigill_opn:
3346 sig = TARGET_SIGILL;
3347 n = TARGET_ILL_ILLOPN;
3348 goto do_signal_pc;
3349
3350 case PGM_FIXPT_OVERFLOW:
3351 sig = TARGET_SIGFPE;
3352 n = TARGET_FPE_INTOVF;
3353 goto do_signal_pc;
3354 case PGM_FIXPT_DIVIDE:
3355 sig = TARGET_SIGFPE;
3356 n = TARGET_FPE_INTDIV;
3357 goto do_signal_pc;
3358
3359 case PGM_DATA:
3360 n = (env->fpc >> 8) & 0xff;
3361 if (n == 0xff) {
3362 /* compare-and-trap */
3363 goto do_sigill_opn;
3364 } else {
3365 /* An IEEE exception, simulated or otherwise. */
3366 if (n & 0x80) {
3367 n = TARGET_FPE_FLTINV;
3368 } else if (n & 0x40) {
3369 n = TARGET_FPE_FLTDIV;
3370 } else if (n & 0x20) {
3371 n = TARGET_FPE_FLTOVF;
3372 } else if (n & 0x10) {
3373 n = TARGET_FPE_FLTUND;
3374 } else if (n & 0x08) {
3375 n = TARGET_FPE_FLTRES;
3376 } else {
3377 /* ??? Quantum exception; BFP, DFP error. */
3378 goto do_sigill_opn;
3379 }
3380 sig = TARGET_SIGFPE;
3381 goto do_signal_pc;
3382 }
3383
3384 default:
3385 fprintf(stderr, "Unhandled program exception: %#x\n", n);
3386 cpu_dump_state(cs, stderr, fprintf, 0);
3387 exit(1);
3388 }
3389 break;
3390
3391 do_signal_pc:
3392 addr = env->psw.addr;
3393 do_signal:
3394 info.si_signo = sig;
3395 info.si_errno = 0;
3396 info.si_code = n;
3397 info._sifields._sigfault._addr = addr;
3398 queue_signal(env, info.si_signo, &info);
3399 break;
3400
3401 default:
3402 fprintf(stderr, "Unhandled trap: 0x%x\n", trapnr);
3403 cpu_dump_state(cs, stderr, fprintf, 0);
3404 exit(1);
3405 }
3406 process_pending_signals (env);
3407 }
3408 }
3409
3410 #endif /* TARGET_S390X */
3411
3412 THREAD CPUState *thread_cpu;
3413
3414 void task_settid(TaskState *ts)
3415 {
3416 if (ts->ts_tid == 0) {
3417 ts->ts_tid = (pid_t)syscall(SYS_gettid);
3418 }
3419 }
3420
3421 void stop_all_tasks(void)
3422 {
3423 /*
3424 * We trust that when using NPTL, start_exclusive()
3425 * handles thread stopping correctly.
3426 */
3427 start_exclusive();
3428 }
3429
3430 /* Assumes contents are already zeroed. */
3431 void init_task_state(TaskState *ts)
3432 {
3433 int i;
3434
3435 ts->used = 1;
3436 ts->first_free = ts->sigqueue_table;
3437 for (i = 0; i < MAX_SIGQUEUE_SIZE - 1; i++) {
3438 ts->sigqueue_table[i].next = &ts->sigqueue_table[i + 1];
3439 }
3440 ts->sigqueue_table[i].next = NULL;
3441 }
3442
3443 CPUArchState *cpu_copy(CPUArchState *env)
3444 {
3445 CPUState *cpu = ENV_GET_CPU(env);
3446 CPUState *new_cpu = cpu_init(cpu_model);
3447 CPUArchState *new_env = new_cpu->env_ptr;
3448 CPUBreakpoint *bp;
3449 CPUWatchpoint *wp;
3450
3451 /* Reset non arch specific state */
3452 cpu_reset(new_cpu);
3453
3454 memcpy(new_env, env, sizeof(CPUArchState));
3455
3456 /* Clone all break/watchpoints.
3457 Note: Once we support ptrace with hw-debug register access, make sure
3458 BP_CPU break/watchpoints are handled correctly on clone. */
3459 QTAILQ_INIT(&new_cpu->breakpoints);
3460 QTAILQ_INIT(&new_cpu->watchpoints);
3461 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
3462 cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
3463 }
3464 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
3465 cpu_watchpoint_insert(new_cpu, wp->vaddr, wp->len, wp->flags, NULL);
3466 }
3467
3468 return new_env;
3469 }
3470
3471 static void handle_arg_help(const char *arg)
3472 {
3473 usage();
3474 }
3475
3476 static void handle_arg_log(const char *arg)
3477 {
3478 int mask;
3479
3480 mask = qemu_str_to_log_mask(arg);
3481 if (!mask) {
3482 qemu_print_log_usage(stdout);
3483 exit(1);
3484 }
3485 qemu_set_log(mask);
3486 }
3487
3488 static void handle_arg_log_filename(const char *arg)
3489 {
3490 qemu_set_log_filename(arg);
3491 }
3492
3493 static void handle_arg_set_env(const char *arg)
3494 {
3495 char *r, *p, *token;
3496 r = p = strdup(arg);
3497 while ((token = strsep(&p, ",")) != NULL) {
3498 if (envlist_setenv(envlist, token) != 0) {
3499 usage();
3500 }
3501 }
3502 free(r);
3503 }
3504
3505 static void handle_arg_unset_env(const char *arg)
3506 {
3507 char *r, *p, *token;
3508 r = p = strdup(arg);
3509 while ((token = strsep(&p, ",")) != NULL) {
3510 if (envlist_unsetenv(envlist, token) != 0) {
3511 usage();
3512 }
3513 }
3514 free(r);
3515 }
3516
3517 static void handle_arg_argv0(const char *arg)
3518 {
3519 argv0 = strdup(arg);
3520 }
3521
3522 static void handle_arg_stack_size(const char *arg)
3523 {
3524 char *p;
3525 guest_stack_size = strtoul(arg, &p, 0);
3526 if (guest_stack_size == 0) {
3527 usage();
3528 }
3529
3530 if (*p == 'M') {
3531 guest_stack_size *= 1024 * 1024;
3532 } else if (*p == 'k' || *p == 'K') {
3533 guest_stack_size *= 1024;
3534 }
3535 }
3536
3537 static void handle_arg_ld_prefix(const char *arg)
3538 {
3539 interp_prefix = strdup(arg);
3540 }
3541
3542 static void handle_arg_pagesize(const char *arg)
3543 {
3544 qemu_host_page_size = atoi(arg);
3545 if (qemu_host_page_size == 0 ||
3546 (qemu_host_page_size & (qemu_host_page_size - 1)) != 0) {
3547 fprintf(stderr, "page size must be a power of two\n");
3548 exit(1);
3549 }
3550 }
3551
3552 static void handle_arg_randseed(const char *arg)
3553 {
3554 unsigned long long seed;
3555
3556 if (parse_uint_full(arg, &seed, 0) != 0 || seed > UINT_MAX) {
3557 fprintf(stderr, "Invalid seed number: %s\n", arg);
3558 exit(1);
3559 }
3560 srand(seed);
3561 }
3562
3563 static void handle_arg_gdb(const char *arg)
3564 {
3565 gdbstub_port = atoi(arg);
3566 }
3567
3568 static void handle_arg_uname(const char *arg)
3569 {
3570 qemu_uname_release = strdup(arg);
3571 }
3572
3573 static void handle_arg_cpu(const char *arg)
3574 {
3575 cpu_model = strdup(arg);
3576 if (cpu_model == NULL || is_help_option(cpu_model)) {
3577 /* XXX: implement xxx_cpu_list for targets that still miss it */
3578 #if defined(cpu_list)
3579 cpu_list(stdout, &fprintf);
3580 #endif
3581 exit(1);
3582 }
3583 }
3584
3585 static void handle_arg_guest_base(const char *arg)
3586 {
3587 guest_base = strtol(arg, NULL, 0);
3588 have_guest_base = 1;
3589 }
3590
3591 static void handle_arg_reserved_va(const char *arg)
3592 {
3593 char *p;
3594 int shift = 0;
3595 reserved_va = strtoul(arg, &p, 0);
3596 switch (*p) {
3597 case 'k':
3598 case 'K':
3599 shift = 10;
3600 break;
3601 case 'M':
3602 shift = 20;
3603 break;
3604 case 'G':
3605 shift = 30;
3606 break;
3607 }
3608 if (shift) {
3609 unsigned long unshifted = reserved_va;
3610 p++;
3611 reserved_va <<= shift;
3612 if (((reserved_va >> shift) != unshifted)
3613 #if HOST_LONG_BITS > TARGET_VIRT_ADDR_SPACE_BITS
3614 || (reserved_va > (1ul << TARGET_VIRT_ADDR_SPACE_BITS))
3615 #endif
3616 ) {
3617 fprintf(stderr, "Reserved virtual address too big\n");
3618 exit(1);
3619 }
3620 }
3621 if (*p) {
3622 fprintf(stderr, "Unrecognised -R size suffix '%s'\n", p);
3623 exit(1);
3624 }
3625 }
3626
3627 static void handle_arg_singlestep(const char *arg)
3628 {
3629 singlestep = 1;
3630 }
3631
3632 static void handle_arg_strace(const char *arg)
3633 {
3634 do_strace = 1;
3635 }
3636
3637 static void handle_arg_version(const char *arg)
3638 {
3639 printf("qemu-" TARGET_NAME " version " QEMU_VERSION QEMU_PKGVERSION
3640 ", Copyright (c) 2003-2008 Fabrice Bellard\n");
3641 exit(0);
3642 }
3643
3644 struct qemu_argument {
3645 const char *argv;
3646 const char *env;
3647 bool has_arg;
3648 void (*handle_opt)(const char *arg);
3649 const char *example;
3650 const char *help;
3651 };
3652
3653 static const struct qemu_argument arg_table[] = {
3654 {"h", "", false, handle_arg_help,
3655 "", "print this help"},
3656 {"g", "QEMU_GDB", true, handle_arg_gdb,
3657 "port", "wait gdb connection to 'port'"},
3658 {"L", "QEMU_LD_PREFIX", true, handle_arg_ld_prefix,
3659 "path", "set the elf interpreter prefix to 'path'"},
3660 {"s", "QEMU_STACK_SIZE", true, handle_arg_stack_size,
3661 "size", "set the stack size to 'size' bytes"},
3662 {"cpu", "QEMU_CPU", true, handle_arg_cpu,
3663 "model", "select CPU (-cpu help for list)"},
3664 {"E", "QEMU_SET_ENV", true, handle_arg_set_env,
3665 "var=value", "sets targets environment variable (see below)"},
3666 {"U", "QEMU_UNSET_ENV", true, handle_arg_unset_env,
3667 "var", "unsets targets environment variable (see below)"},
3668 {"0", "QEMU_ARGV0", true, handle_arg_argv0,
3669 "argv0", "forces target process argv[0] to be 'argv0'"},
3670 {"r", "QEMU_UNAME", true, handle_arg_uname,
3671 "uname", "set qemu uname release string to 'uname'"},
3672 {"B", "QEMU_GUEST_BASE", true, handle_arg_guest_base,
3673 "address", "set guest_base address to 'address'"},
3674 {"R", "QEMU_RESERVED_VA", true, handle_arg_reserved_va,
3675 "size", "reserve 'size' bytes for guest virtual address space"},
3676 {"d", "QEMU_LOG", true, handle_arg_log,
3677 "item[,...]", "enable logging of specified items "
3678 "(use '-d help' for a list of items)"},
3679 {"D", "QEMU_LOG_FILENAME", true, handle_arg_log_filename,
3680 "logfile", "write logs to 'logfile' (default stderr)"},
3681 {"p", "QEMU_PAGESIZE", true, handle_arg_pagesize,
3682 "pagesize", "set the host page size to 'pagesize'"},
3683 {"singlestep", "QEMU_SINGLESTEP", false, handle_arg_singlestep,
3684 "", "run in singlestep mode"},
3685 {"strace", "QEMU_STRACE", false, handle_arg_strace,
3686 "", "log system calls"},
3687 {"seed", "QEMU_RAND_SEED", true, handle_arg_randseed,
3688 "", "Seed for pseudo-random number generator"},
3689 {"version", "QEMU_VERSION", false, handle_arg_version,
3690 "", "display version information and exit"},
3691 {NULL, NULL, false, NULL, NULL, NULL}
3692 };
3693
3694 static void usage(void)
3695 {
3696 const struct qemu_argument *arginfo;
3697 int maxarglen;
3698 int maxenvlen;
3699
3700 printf("usage: qemu-" TARGET_NAME " [options] program [arguments...]\n"
3701 "Linux CPU emulator (compiled for " TARGET_NAME " emulation)\n"
3702 "\n"
3703 "Options and associated environment variables:\n"
3704 "\n");
3705
3706 /* Calculate column widths. We must always have at least enough space
3707 * for the column header.
3708 */
3709 maxarglen = strlen("Argument");
3710 maxenvlen = strlen("Env-variable");
3711
3712 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3713 int arglen = strlen(arginfo->argv);
3714 if (arginfo->has_arg) {
3715 arglen += strlen(arginfo->example) + 1;
3716 }
3717 if (strlen(arginfo->env) > maxenvlen) {
3718 maxenvlen = strlen(arginfo->env);
3719 }
3720 if (arglen > maxarglen) {
3721 maxarglen = arglen;
3722 }
3723 }
3724
3725 printf("%-*s %-*s Description\n", maxarglen+1, "Argument",
3726 maxenvlen, "Env-variable");
3727
3728 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3729 if (arginfo->has_arg) {
3730 printf("-%s %-*s %-*s %s\n", arginfo->argv,
3731 (int)(maxarglen - strlen(arginfo->argv) - 1),
3732 arginfo->example, maxenvlen, arginfo->env, arginfo->help);
3733 } else {
3734 printf("-%-*s %-*s %s\n", maxarglen, arginfo->argv,
3735 maxenvlen, arginfo->env,
3736 arginfo->help);
3737 }
3738 }
3739
3740 printf("\n"
3741 "Defaults:\n"
3742 "QEMU_LD_PREFIX = %s\n"
3743 "QEMU_STACK_SIZE = %ld byte\n",
3744 interp_prefix,
3745 guest_stack_size);
3746
3747 printf("\n"
3748 "You can use -E and -U options or the QEMU_SET_ENV and\n"
3749 "QEMU_UNSET_ENV environment variables to set and unset\n"
3750 "environment variables for the target process.\n"
3751 "It is possible to provide several variables by separating them\n"
3752 "by commas in getsubopt(3) style. Additionally it is possible to\n"
3753 "provide the -E and -U options multiple times.\n"
3754 "The following lines are equivalent:\n"
3755 " -E var1=val2 -E var2=val2 -U LD_PRELOAD -U LD_DEBUG\n"
3756 " -E var1=val2,var2=val2 -U LD_PRELOAD,LD_DEBUG\n"
3757 " QEMU_SET_ENV=var1=val2,var2=val2 QEMU_UNSET_ENV=LD_PRELOAD,LD_DEBUG\n"
3758 "Note that if you provide several changes to a single variable\n"
3759 "the last change will stay in effect.\n");
3760
3761 exit(1);
3762 }
3763
3764 static int parse_args(int argc, char **argv)
3765 {
3766 const char *r;
3767 int optind;
3768 const struct qemu_argument *arginfo;
3769
3770 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3771 if (arginfo->env == NULL) {
3772 continue;
3773 }
3774
3775 r = getenv(arginfo->env);
3776 if (r != NULL) {
3777 arginfo->handle_opt(r);
3778 }
3779 }
3780
3781 optind = 1;
3782 for (;;) {
3783 if (optind >= argc) {
3784 break;
3785 }
3786 r = argv[optind];
3787 if (r[0] != '-') {
3788 break;
3789 }
3790 optind++;
3791 r++;
3792 if (!strcmp(r, "-")) {
3793 break;
3794 }
3795
3796 for (arginfo = arg_table; arginfo->handle_opt != NULL; arginfo++) {
3797 if (!strcmp(r, arginfo->argv)) {
3798 if (arginfo->has_arg) {
3799 if (optind >= argc) {
3800 usage();
3801 }
3802 arginfo->handle_opt(argv[optind]);
3803 optind++;
3804 } else {
3805 arginfo->handle_opt(NULL);
3806 }
3807 break;
3808 }
3809 }
3810
3811 /* no option matched the current argv */
3812 if (arginfo->handle_opt == NULL) {
3813 usage();
3814 }
3815 }
3816
3817 if (optind >= argc) {
3818 usage();
3819 }
3820
3821 filename = argv[optind];
3822 exec_path = argv[optind];
3823
3824 return optind;
3825 }
3826
3827 int main(int argc, char **argv, char **envp)
3828 {
3829 struct target_pt_regs regs1, *regs = &regs1;
3830 struct image_info info1, *info = &info1;
3831 struct linux_binprm bprm;
3832 TaskState *ts;
3833 CPUArchState *env;
3834 CPUState *cpu;
3835 int optind;
3836 char **target_environ, **wrk;
3837 char **target_argv;
3838 int target_argc;
3839 int i;
3840 int ret;
3841 int execfd;
3842
3843 module_call_init(MODULE_INIT_QOM);
3844
3845 if ((envlist = envlist_create()) == NULL) {
3846 (void) fprintf(stderr, "Unable to allocate envlist\n");
3847 exit(1);
3848 }
3849
3850 /* add current environment into the list */
3851 for (wrk = environ; *wrk != NULL; wrk++) {
3852 (void) envlist_setenv(envlist, *wrk);
3853 }
3854
3855 /* Read the stack limit from the kernel. If it's "unlimited",
3856 then we can do little else besides use the default. */
3857 {
3858 struct rlimit lim;
3859 if (getrlimit(RLIMIT_STACK, &lim) == 0
3860 && lim.rlim_cur != RLIM_INFINITY
3861 && lim.rlim_cur == (target_long)lim.rlim_cur) {
3862 guest_stack_size = lim.rlim_cur;
3863 }
3864 }
3865
3866 cpu_model = NULL;
3867 #if defined(cpudef_setup)
3868 cpudef_setup(); /* parse cpu definitions in target config file (TBD) */
3869 #endif
3870
3871 srand(time(NULL));
3872
3873 optind = parse_args(argc, argv);
3874
3875 /* Zero out regs */
3876 memset(regs, 0, sizeof(struct target_pt_regs));
3877
3878 /* Zero out image_info */
3879 memset(info, 0, sizeof(struct image_info));
3880
3881 memset(&bprm, 0, sizeof (bprm));
3882
3883 /* Scan interp_prefix dir for replacement files. */
3884 init_paths(interp_prefix);
3885
3886 init_qemu_uname_release();
3887
3888 if (cpu_model == NULL) {
3889 #if defined(TARGET_I386)
3890 #ifdef TARGET_X86_64
3891 cpu_model = "qemu64";
3892 #else
3893 cpu_model = "qemu32";
3894 #endif
3895 #elif defined(TARGET_ARM)
3896 cpu_model = "any";
3897 #elif defined(TARGET_UNICORE32)
3898 cpu_model = "any";
3899 #elif defined(TARGET_M68K)
3900 cpu_model = "any";
3901 #elif defined(TARGET_SPARC)
3902 #ifdef TARGET_SPARC64
3903 cpu_model = "TI UltraSparc II";
3904 #else
3905 cpu_model = "Fujitsu MB86904";
3906 #endif
3907 #elif defined(TARGET_MIPS)
3908 #if defined(TARGET_ABI_MIPSN32) || defined(TARGET_ABI_MIPSN64)
3909 cpu_model = "5KEf";
3910 #else
3911 cpu_model = "24Kf";
3912 #endif
3913 #elif defined TARGET_OPENRISC
3914 cpu_model = "or1200";
3915 #elif defined(TARGET_PPC)
3916 # ifdef TARGET_PPC64
3917 cpu_model = "POWER7";
3918 # else
3919 cpu_model = "750";
3920 # endif
3921 #elif defined TARGET_SH4
3922 cpu_model = TYPE_SH7785_CPU;
3923 #else
3924 cpu_model = "any";
3925 #endif
3926 }
3927 tcg_exec_init(0);
3928 /* NOTE: we need to init the CPU at this stage to get
3929 qemu_host_page_size */
3930 cpu = cpu_init(cpu_model);
3931 if (!cpu) {
3932 fprintf(stderr, "Unable to find CPU definition\n");
3933 exit(1);
3934 }
3935 env = cpu->env_ptr;
3936 cpu_reset(cpu);
3937
3938 thread_cpu = cpu;
3939
3940 if (getenv("QEMU_STRACE")) {
3941 do_strace = 1;
3942 }
3943
3944 if (getenv("QEMU_RAND_SEED")) {
3945 handle_arg_randseed(getenv("QEMU_RAND_SEED"));
3946 }
3947
3948 target_environ = envlist_to_environ(envlist, NULL);
3949 envlist_free(envlist);
3950
3951 /*
3952 * Now that page sizes are configured in cpu_init() we can do
3953 * proper page alignment for guest_base.
3954 */
3955 guest_base = HOST_PAGE_ALIGN(guest_base);
3956
3957 if (reserved_va || have_guest_base) {
3958 guest_base = init_guest_space(guest_base, reserved_va, 0,
3959 have_guest_base);
3960 if (guest_base == (unsigned long)-1) {
3961 fprintf(stderr, "Unable to reserve 0x%lx bytes of virtual address "
3962 "space for use as guest address space (check your virtual "
3963 "memory ulimit setting or reserve less using -R option)\n",
3964 reserved_va);
3965 exit(1);
3966 }
3967
3968 if (reserved_va) {
3969 mmap_next_start = reserved_va;
3970 }
3971 }
3972
3973 /*
3974 * Read in mmap_min_addr kernel parameter. This value is used
3975 * When loading the ELF image to determine whether guest_base
3976 * is needed. It is also used in mmap_find_vma.
3977 */
3978 {
3979 FILE *fp;
3980
3981 if ((fp = fopen("/proc/sys/vm/mmap_min_addr", "r")) != NULL) {
3982 unsigned long tmp;
3983 if (fscanf(fp, "%lu", &tmp) == 1) {
3984 mmap_min_addr = tmp;
3985 qemu_log("host mmap_min_addr=0x%lx\n", mmap_min_addr);
3986 }
3987 fclose(fp);
3988 }
3989 }
3990
3991 /*
3992 * Prepare copy of argv vector for target.
3993 */
3994 target_argc = argc - optind;
3995 target_argv = calloc(target_argc + 1, sizeof (char *));
3996 if (target_argv == NULL) {
3997 (void) fprintf(stderr, "Unable to allocate memory for target_argv\n");
3998 exit(1);
3999 }
4000
4001 /*
4002 * If argv0 is specified (using '-0' switch) we replace
4003 * argv[0] pointer with the given one.
4004 */
4005 i = 0;
4006 if (argv0 != NULL) {
4007 target_argv[i++] = strdup(argv0);
4008 }
4009 for (; i < target_argc; i++) {
4010 target_argv[i] = strdup(argv[optind + i]);
4011 }
4012 target_argv[target_argc] = NULL;
4013
4014 ts = g_malloc0 (sizeof(TaskState));
4015 init_task_state(ts);
4016 /* build Task State */
4017 ts->info = info;
4018 ts->bprm = &bprm;
4019 cpu->opaque = ts;
4020 task_settid(ts);
4021
4022 execfd = qemu_getauxval(AT_EXECFD);
4023 if (execfd == 0) {
4024 execfd = open(filename, O_RDONLY);
4025 if (execfd < 0) {
4026 printf("Error while loading %s: %s\n", filename, strerror(errno));
4027 _exit(1);
4028 }
4029 }
4030
4031 ret = loader_exec(execfd, filename, target_argv, target_environ, regs,
4032 info, &bprm);
4033 if (ret != 0) {
4034 printf("Error while loading %s: %s\n", filename, strerror(-ret));
4035 _exit(1);
4036 }
4037
4038 for (wrk = target_environ; *wrk; wrk++) {
4039 free(*wrk);
4040 }
4041
4042 free(target_environ);
4043
4044 if (qemu_log_enabled()) {
4045 qemu_log("guest_base 0x%lx\n", guest_base);
4046 log_page_dump();
4047
4048 qemu_log("start_brk 0x" TARGET_ABI_FMT_lx "\n", info->start_brk);
4049 qemu_log("end_code 0x" TARGET_ABI_FMT_lx "\n", info->end_code);
4050 qemu_log("start_code 0x" TARGET_ABI_FMT_lx "\n",
4051 info->start_code);
4052 qemu_log("start_data 0x" TARGET_ABI_FMT_lx "\n",
4053 info->start_data);
4054 qemu_log("end_data 0x" TARGET_ABI_FMT_lx "\n", info->end_data);
4055 qemu_log("start_stack 0x" TARGET_ABI_FMT_lx "\n",
4056 info->start_stack);
4057 qemu_log("brk 0x" TARGET_ABI_FMT_lx "\n", info->brk);
4058 qemu_log("entry 0x" TARGET_ABI_FMT_lx "\n", info->entry);
4059 }
4060
4061 target_set_brk(info->brk);
4062 syscall_init();
4063 signal_init();
4064
4065 /* Now that we've loaded the binary, GUEST_BASE is fixed. Delay
4066 generating the prologue until now so that the prologue can take
4067 the real value of GUEST_BASE into account. */
4068 tcg_prologue_init(&tcg_ctx);
4069
4070 #if defined(TARGET_I386)
4071 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK;
4072 env->hflags |= HF_PE_MASK | HF_CPL_MASK;
4073 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4074 env->cr[4] |= CR4_OSFXSR_MASK;
4075 env->hflags |= HF_OSFXSR_MASK;
4076 }
4077 #ifndef TARGET_ABI32
4078 /* enable 64 bit mode if possible */
4079 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) {
4080 fprintf(stderr, "The selected x86 CPU does not support 64 bit mode\n");
4081 exit(1);
4082 }
4083 env->cr[4] |= CR4_PAE_MASK;
4084 env->efer |= MSR_EFER_LMA | MSR_EFER_LME;
4085 env->hflags |= HF_LMA_MASK;
4086 #endif
4087
4088 /* flags setup : we activate the IRQs by default as in user mode */
4089 env->eflags |= IF_MASK;
4090
4091 /* linux register setup */
4092 #ifndef TARGET_ABI32
4093 env->regs[R_EAX] = regs->rax;
4094 env->regs[R_EBX] = regs->rbx;
4095 env->regs[R_ECX] = regs->rcx;
4096 env->regs[R_EDX] = regs->rdx;
4097 env->regs[R_ESI] = regs->rsi;
4098 env->regs[R_EDI] = regs->rdi;
4099 env->regs[R_EBP] = regs->rbp;
4100 env->regs[R_ESP] = regs->rsp;
4101 env->eip = regs->rip;
4102 #else
4103 env->regs[R_EAX] = regs->eax;
4104 env->regs[R_EBX] = regs->ebx;
4105 env->regs[R_ECX] = regs->ecx;
4106 env->regs[R_EDX] = regs->edx;
4107 env->regs[R_ESI] = regs->esi;
4108 env->regs[R_EDI] = regs->edi;
4109 env->regs[R_EBP] = regs->ebp;
4110 env->regs[R_ESP] = regs->esp;
4111 env->eip = regs->eip;
4112 #endif
4113
4114 /* linux interrupt setup */
4115 #ifndef TARGET_ABI32
4116 env->idt.limit = 511;
4117 #else
4118 env->idt.limit = 255;
4119 #endif
4120 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1),
4121 PROT_READ|PROT_WRITE,
4122 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4123 idt_table = g2h(env->idt.base);
4124 set_idt(0, 0);
4125 set_idt(1, 0);
4126 set_idt(2, 0);
4127 set_idt(3, 3);
4128 set_idt(4, 3);
4129 set_idt(5, 0);
4130 set_idt(6, 0);
4131 set_idt(7, 0);
4132 set_idt(8, 0);
4133 set_idt(9, 0);
4134 set_idt(10, 0);
4135 set_idt(11, 0);
4136 set_idt(12, 0);
4137 set_idt(13, 0);
4138 set_idt(14, 0);
4139 set_idt(15, 0);
4140 set_idt(16, 0);
4141 set_idt(17, 0);
4142 set_idt(18, 0);
4143 set_idt(19, 0);
4144 set_idt(0x80, 3);
4145
4146 /* linux segment setup */
4147 {
4148 uint64_t *gdt_table;
4149 env->gdt.base = target_mmap(0, sizeof(uint64_t) * TARGET_GDT_ENTRIES,
4150 PROT_READ|PROT_WRITE,
4151 MAP_ANONYMOUS|MAP_PRIVATE, -1, 0);
4152 env->gdt.limit = sizeof(uint64_t) * TARGET_GDT_ENTRIES - 1;
4153 gdt_table = g2h(env->gdt.base);
4154 #ifdef TARGET_ABI32
4155 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4156 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4157 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4158 #else
4159 /* 64 bit code segment */
4160 write_dt(&gdt_table[__USER_CS >> 3], 0, 0xfffff,
4161 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4162 DESC_L_MASK |
4163 (3 << DESC_DPL_SHIFT) | (0xa << DESC_TYPE_SHIFT));
4164 #endif
4165 write_dt(&gdt_table[__USER_DS >> 3], 0, 0xfffff,
4166 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | DESC_S_MASK |
4167 (3 << DESC_DPL_SHIFT) | (0x2 << DESC_TYPE_SHIFT));
4168 }
4169 cpu_x86_load_seg(env, R_CS, __USER_CS);
4170 cpu_x86_load_seg(env, R_SS, __USER_DS);
4171 #ifdef TARGET_ABI32
4172 cpu_x86_load_seg(env, R_DS, __USER_DS);
4173 cpu_x86_load_seg(env, R_ES, __USER_DS);
4174 cpu_x86_load_seg(env, R_FS, __USER_DS);
4175 cpu_x86_load_seg(env, R_GS, __USER_DS);
4176 /* This hack makes Wine work... */
4177 env->segs[R_FS].selector = 0;
4178 #else
4179 cpu_x86_load_seg(env, R_DS, 0);
4180 cpu_x86_load_seg(env, R_ES, 0);
4181 cpu_x86_load_seg(env, R_FS, 0);
4182 cpu_x86_load_seg(env, R_GS, 0);
4183 #endif
4184 #elif defined(TARGET_AARCH64)
4185 {
4186 int i;
4187
4188 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
4189 fprintf(stderr,
4190 "The selected ARM CPU does not support 64 bit mode\n");
4191 exit(1);
4192 }
4193
4194 for (i = 0; i < 31; i++) {
4195 env->xregs[i] = regs->regs[i];
4196 }
4197 env->pc = regs->pc;
4198 env->xregs[31] = regs->sp;
4199 }
4200 #elif defined(TARGET_ARM)
4201 {
4202 int i;
4203 cpsr_write(env, regs->uregs[16], 0xffffffff);
4204 for(i = 0; i < 16; i++) {
4205 env->regs[i] = regs->uregs[i];
4206 }
4207 /* Enable BE8. */
4208 if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
4209 && (info->elf_flags & EF_ARM_BE8)) {
4210 env->bswap_code = 1;
4211 }
4212 }
4213 #elif defined(TARGET_UNICORE32)
4214 {
4215 int i;
4216 cpu_asr_write(env, regs->uregs[32], 0xffffffff);
4217 for (i = 0; i < 32; i++) {
4218 env->regs[i] = regs->uregs[i];
4219 }
4220 }
4221 #elif defined(TARGET_SPARC)
4222 {
4223 int i;
4224 env->pc = regs->pc;
4225 env->npc = regs->npc;
4226 env->y = regs->y;
4227 for(i = 0; i < 8; i++)
4228 env->gregs[i] = regs->u_regs[i];
4229 for(i = 0; i < 8; i++)
4230 env->regwptr[i] = regs->u_regs[i + 8];
4231 }
4232 #elif defined(TARGET_PPC)
4233 {
4234 int i;
4235
4236 #if defined(TARGET_PPC64)
4237 #if defined(TARGET_ABI32)
4238 env->msr &= ~((target_ulong)1 << MSR_SF);
4239 #else
4240 env->msr |= (target_ulong)1 << MSR_SF;
4241 #endif
4242 #endif
4243 env->nip = regs->nip;
4244 for(i = 0; i < 32; i++) {
4245 env->gpr[i] = regs->gpr[i];
4246 }
4247 }
4248 #elif defined(TARGET_M68K)
4249 {
4250 env->pc = regs->pc;
4251 env->dregs[0] = regs->d0;
4252 env->dregs[1] = regs->d1;
4253 env->dregs[2] = regs->d2;
4254 env->dregs[3] = regs->d3;
4255 env->dregs[4] = regs->d4;
4256 env->dregs[5] = regs->d5;
4257 env->dregs[6] = regs->d6;
4258 env->dregs[7] = regs->d7;
4259 env->aregs[0] = regs->a0;
4260 env->aregs[1] = regs->a1;
4261 env->aregs[2] = regs->a2;
4262 env->aregs[3] = regs->a3;
4263 env->aregs[4] = regs->a4;
4264 env->aregs[5] = regs->a5;
4265 env->aregs[6] = regs->a6;
4266 env->aregs[7] = regs->usp;
4267 env->sr = regs->sr;
4268 ts->sim_syscalls = 1;
4269 }
4270 #elif defined(TARGET_MICROBLAZE)
4271 {
4272 env->regs[0] = regs->r0;
4273 env->regs[1] = regs->r1;
4274 env->regs[2] = regs->r2;
4275 env->regs[3] = regs->r3;
4276 env->regs[4] = regs->r4;
4277 env->regs[5] = regs->r5;
4278 env->regs[6] = regs->r6;
4279 env->regs[7] = regs->r7;
4280 env->regs[8] = regs->r8;
4281 env->regs[9] = regs->r9;
4282 env->regs[10] = regs->r10;
4283 env->regs[11] = regs->r11;
4284 env->regs[12] = regs->r12;
4285 env->regs[13] = regs->r13;
4286 env->regs[14] = regs->r14;
4287 env->regs[15] = regs->r15;
4288 env->regs[16] = regs->r16;
4289 env->regs[17] = regs->r17;
4290 env->regs[18] = regs->r18;
4291 env->regs[19] = regs->r19;
4292 env->regs[20] = regs->r20;
4293 env->regs[21] = regs->r21;
4294 env->regs[22] = regs->r22;
4295 env->regs[23] = regs->r23;
4296 env->regs[24] = regs->r24;
4297 env->regs[25] = regs->r25;
4298 env->regs[26] = regs->r26;
4299 env->regs[27] = regs->r27;
4300 env->regs[28] = regs->r28;
4301 env->regs[29] = regs->r29;
4302 env->regs[30] = regs->r30;
4303 env->regs[31] = regs->r31;
4304 env->sregs[SR_PC] = regs->pc;
4305 }
4306 #elif defined(TARGET_MIPS)
4307 {
4308 int i;
4309
4310 for(i = 0; i < 32; i++) {
4311 env->active_tc.gpr[i] = regs->regs[i];
4312 }
4313 env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
4314 if (regs->cp0_epc & 1) {
4315 env->hflags |= MIPS_HFLAG_M16;
4316 }
4317 }
4318 #elif defined(TARGET_OPENRISC)
4319 {
4320 int i;
4321
4322 for (i = 0; i < 32; i++) {
4323 env->gpr[i] = regs->gpr[i];
4324 }
4325
4326 env->sr = regs->sr;
4327 env->pc = regs->pc;
4328 }
4329 #elif defined(TARGET_SH4)
4330 {
4331 int i;
4332
4333 for(i = 0; i < 16; i++) {
4334 env->gregs[i] = regs->regs[i];
4335 }
4336 env->pc = regs->pc;
4337 }
4338 #elif defined(TARGET_ALPHA)
4339 {
4340 int i;
4341
4342 for(i = 0; i < 28; i++) {
4343 env->ir[i] = ((abi_ulong *)regs)[i];
4344 }
4345 env->ir[IR_SP] = regs->usp;
4346 env->pc = regs->pc;
4347 }
4348 #elif defined(TARGET_CRIS)
4349 {
4350 env->regs[0] = regs->r0;
4351 env->regs[1] = regs->r1;
4352 env->regs[2] = regs->r2;
4353 env->regs[3] = regs->r3;
4354 env->regs[4] = regs->r4;
4355 env->regs[5] = regs->r5;
4356 env->regs[6] = regs->r6;
4357 env->regs[7] = regs->r7;
4358 env->regs[8] = regs->r8;
4359 env->regs[9] = regs->r9;
4360 env->regs[10] = regs->r10;
4361 env->regs[11] = regs->r11;
4362 env->regs[12] = regs->r12;
4363 env->regs[13] = regs->r13;
4364 env->regs[14] = info->start_stack;
4365 env->regs[15] = regs->acr;
4366 env->pc = regs->erp;
4367 }
4368 #elif defined(TARGET_S390X)
4369 {
4370 int i;
4371 for (i = 0; i < 16; i++) {
4372 env->regs[i] = regs->gprs[i];
4373 }
4374 env->psw.mask = regs->psw.mask;
4375 env->psw.addr = regs->psw.addr;
4376 }
4377 #else
4378 #error unsupported target CPU
4379 #endif
4380
4381 #if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
4382 ts->stack_base = info->start_stack;
4383 ts->heap_base = info->brk;
4384 /* This will be filled in on the first SYS_HEAPINFO call. */
4385 ts->heap_limit = 0;
4386 #endif
4387
4388 if (gdbstub_port) {
4389 if (gdbserver_start(gdbstub_port) < 0) {
4390 fprintf(stderr, "qemu: could not open gdbserver on port %d\n",
4391 gdbstub_port);
4392 exit(1);
4393 }
4394 gdb_handlesig(cpu, 0);
4395 }
4396 cpu_loop(env);
4397 /* never exits */
4398 return 0;
4399 }
QEmu