2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "hw/sysbus.h"
32 #include "hw/arm/arm.h"
33 #include "hw/arm/primecell.h"
34 #include "hw/devices.h"
36 #include "sysemu/block-backend.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/sysemu.h"
39 #include "sysemu/kvm.h"
40 #include "hw/boards.h"
41 #include "hw/loader.h"
42 #include "exec/address-spaces.h"
43 #include "qemu/bitops.h"
44 #include "qemu/error-report.h"
46 #define NUM_VIRTIO_TRANSPORTS 32
48 /* Number of external interrupt lines to configure the GIC with */
51 #define GIC_FDT_IRQ_TYPE_SPI 0
52 #define GIC_FDT_IRQ_TYPE_PPI 1
54 #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1
55 #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2
56 #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4
57 #define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8
59 #define GIC_FDT_IRQ_PPI_CPU_START 8
60 #define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
73 typedef struct MemMapEntry
{
78 typedef struct VirtBoardInfo
{
79 struct arm_boot_info bootinfo
;
80 const char *cpu_model
;
81 const MemMapEntry
*memmap
;
86 uint32_t clock_phandle
;
89 /* Addresses and sizes of our components.
90 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
91 * 128MB..256MB is used for miscellaneous device I/O.
92 * 256MB..1GB is reserved for possible future PCI support (ie where the
93 * PCI memory window will go if we add a PCI host controller).
94 * 1GB and up is RAM (which may happily spill over into the
95 * high memory region beyond 4GB).
96 * This represents a compromise between how much RAM can be given to
97 * a 32 bit VM and leaving space for expansion and in particular for PCI.
98 * Note that devices should generally be placed at multiples of 0x10000,
99 * to accommodate guests using 64K pages.
101 static const MemMapEntry a15memmap
[] = {
102 /* Space up to 0x8000000 is reserved for a boot ROM */
103 [VIRT_FLASH
] = { 0, 0x08000000 },
104 [VIRT_CPUPERIPHS
] = { 0x08000000, 0x00020000 },
105 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
106 [VIRT_GIC_DIST
] = { 0x08000000, 0x00010000 },
107 [VIRT_GIC_CPU
] = { 0x08010000, 0x00010000 },
108 [VIRT_UART
] = { 0x09000000, 0x00001000 },
109 [VIRT_RTC
] = { 0x09010000, 0x00001000 },
110 [VIRT_MMIO
] = { 0x0a000000, 0x00000200 },
111 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
112 /* 0x10000000 .. 0x40000000 reserved for PCI */
113 [VIRT_MEM
] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
116 static const int a15irqmap
[] = {
119 [VIRT_MMIO
] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
122 static VirtBoardInfo machines
[] = {
124 .cpu_model
= "cortex-a15",
129 .cpu_model
= "cortex-a57",
140 static VirtBoardInfo
*find_machine_info(const char *cpu
)
144 for (i
= 0; i
< ARRAY_SIZE(machines
); i
++) {
145 if (strcmp(cpu
, machines
[i
].cpu_model
) == 0) {
152 static void create_fdt(VirtBoardInfo
*vbi
)
154 void *fdt
= create_device_tree(&vbi
->fdt_size
);
157 error_report("create_device_tree() failed");
164 qemu_fdt_setprop_string(fdt
, "/", "compatible", "linux,dummy-virt");
165 qemu_fdt_setprop_cell(fdt
, "/", "#address-cells", 0x2);
166 qemu_fdt_setprop_cell(fdt
, "/", "#size-cells", 0x2);
169 * /chosen and /memory nodes must exist for load_dtb
170 * to fill in necessary properties later
172 qemu_fdt_add_subnode(fdt
, "/chosen");
173 qemu_fdt_add_subnode(fdt
, "/memory");
174 qemu_fdt_setprop_string(fdt
, "/memory", "device_type", "memory");
176 /* Clock node, for the benefit of the UART. The kernel device tree
177 * binding documentation claims the PL011 node clock properties are
178 * optional but in practice if you omit them the kernel refuses to
179 * probe for the device.
181 vbi
->clock_phandle
= qemu_fdt_alloc_phandle(fdt
);
182 qemu_fdt_add_subnode(fdt
, "/apb-pclk");
183 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "compatible", "fixed-clock");
184 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "#clock-cells", 0x0);
185 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "clock-frequency", 24000000);
186 qemu_fdt_setprop_string(fdt
, "/apb-pclk", "clock-output-names",
188 qemu_fdt_setprop_cell(fdt
, "/apb-pclk", "phandle", vbi
->clock_phandle
);
192 static void fdt_add_psci_node(const VirtBoardInfo
*vbi
)
194 void *fdt
= vbi
->fdt
;
195 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(0));
197 /* No PSCI for TCG yet */
199 uint32_t cpu_suspend_fn
;
204 qemu_fdt_add_subnode(fdt
, "/psci");
205 if (armcpu
->psci_version
== 2) {
206 const char comp
[] = "arm,psci-0.2\0arm,psci";
207 qemu_fdt_setprop(fdt
, "/psci", "compatible", comp
, sizeof(comp
));
209 cpu_off_fn
= QEMU_PSCI_0_2_FN_CPU_OFF
;
210 if (arm_feature(&armcpu
->env
, ARM_FEATURE_AARCH64
)) {
211 cpu_suspend_fn
= QEMU_PSCI_0_2_FN64_CPU_SUSPEND
;
212 cpu_on_fn
= QEMU_PSCI_0_2_FN64_CPU_ON
;
213 migrate_fn
= QEMU_PSCI_0_2_FN64_MIGRATE
;
215 cpu_suspend_fn
= QEMU_PSCI_0_2_FN_CPU_SUSPEND
;
216 cpu_on_fn
= QEMU_PSCI_0_2_FN_CPU_ON
;
217 migrate_fn
= QEMU_PSCI_0_2_FN_MIGRATE
;
220 qemu_fdt_setprop_string(fdt
, "/psci", "compatible", "arm,psci");
222 cpu_suspend_fn
= QEMU_PSCI_0_1_FN_CPU_SUSPEND
;
223 cpu_off_fn
= QEMU_PSCI_0_1_FN_CPU_OFF
;
224 cpu_on_fn
= QEMU_PSCI_0_1_FN_CPU_ON
;
225 migrate_fn
= QEMU_PSCI_0_1_FN_MIGRATE
;
228 qemu_fdt_setprop_string(fdt
, "/psci", "method", "hvc");
230 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_suspend", cpu_suspend_fn
);
231 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_off", cpu_off_fn
);
232 qemu_fdt_setprop_cell(fdt
, "/psci", "cpu_on", cpu_on_fn
);
233 qemu_fdt_setprop_cell(fdt
, "/psci", "migrate", migrate_fn
);
237 static void fdt_add_timer_nodes(const VirtBoardInfo
*vbi
)
239 /* Note that on A15 h/w these interrupts are level-triggered,
240 * but for the GIC implementation provided by both QEMU and KVM
241 * they are edge-triggered.
244 uint32_t irqflags
= GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
;
246 irqflags
= deposit32(irqflags
, GIC_FDT_IRQ_PPI_CPU_START
,
247 GIC_FDT_IRQ_PPI_CPU_WIDTH
, (1 << vbi
->smp_cpus
) - 1);
249 qemu_fdt_add_subnode(vbi
->fdt
, "/timer");
251 armcpu
= ARM_CPU(qemu_get_cpu(0));
252 if (arm_feature(&armcpu
->env
, ARM_FEATURE_V8
)) {
253 const char compat
[] = "arm,armv8-timer\0arm,armv7-timer";
254 qemu_fdt_setprop(vbi
->fdt
, "/timer", "compatible",
255 compat
, sizeof(compat
));
257 qemu_fdt_setprop_string(vbi
->fdt
, "/timer", "compatible",
260 qemu_fdt_setprop_cells(vbi
->fdt
, "/timer", "interrupts",
261 GIC_FDT_IRQ_TYPE_PPI
, 13, irqflags
,
262 GIC_FDT_IRQ_TYPE_PPI
, 14, irqflags
,
263 GIC_FDT_IRQ_TYPE_PPI
, 11, irqflags
,
264 GIC_FDT_IRQ_TYPE_PPI
, 10, irqflags
);
267 static void fdt_add_cpu_nodes(const VirtBoardInfo
*vbi
)
271 qemu_fdt_add_subnode(vbi
->fdt
, "/cpus");
272 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#address-cells", 0x1);
273 qemu_fdt_setprop_cell(vbi
->fdt
, "/cpus", "#size-cells", 0x0);
275 for (cpu
= vbi
->smp_cpus
- 1; cpu
>= 0; cpu
--) {
276 char *nodename
= g_strdup_printf("/cpus/cpu@%d", cpu
);
277 ARMCPU
*armcpu
= ARM_CPU(qemu_get_cpu(cpu
));
279 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
280 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "device_type", "cpu");
281 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible",
282 armcpu
->dtb_compatible
);
284 if (vbi
->smp_cpus
> 1) {
285 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
286 "enable-method", "psci");
289 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "reg", cpu
);
294 static void fdt_add_gic_node(const VirtBoardInfo
*vbi
)
296 uint32_t gic_phandle
;
298 gic_phandle
= qemu_fdt_alloc_phandle(vbi
->fdt
);
299 qemu_fdt_setprop_cell(vbi
->fdt
, "/", "interrupt-parent", gic_phandle
);
301 qemu_fdt_add_subnode(vbi
->fdt
, "/intc");
302 /* 'cortex-a15-gic' means 'GIC v2' */
303 qemu_fdt_setprop_string(vbi
->fdt
, "/intc", "compatible",
304 "arm,cortex-a15-gic");
305 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "#interrupt-cells", 3);
306 qemu_fdt_setprop(vbi
->fdt
, "/intc", "interrupt-controller", NULL
, 0);
307 qemu_fdt_setprop_sized_cells(vbi
->fdt
, "/intc", "reg",
308 2, vbi
->memmap
[VIRT_GIC_DIST
].base
,
309 2, vbi
->memmap
[VIRT_GIC_DIST
].size
,
310 2, vbi
->memmap
[VIRT_GIC_CPU
].base
,
311 2, vbi
->memmap
[VIRT_GIC_CPU
].size
);
312 qemu_fdt_setprop_cell(vbi
->fdt
, "/intc", "phandle", gic_phandle
);
315 static void create_gic(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
317 /* We create a standalone GIC v2 */
319 SysBusDevice
*gicbusdev
;
320 const char *gictype
= "arm_gic";
323 if (kvm_irqchip_in_kernel()) {
324 gictype
= "kvm-arm-gic";
327 gicdev
= qdev_create(NULL
, gictype
);
328 qdev_prop_set_uint32(gicdev
, "revision", 2);
329 qdev_prop_set_uint32(gicdev
, "num-cpu", smp_cpus
);
330 /* Note that the num-irq property counts both internal and external
331 * interrupts; there are always 32 of the former (mandated by GIC spec).
333 qdev_prop_set_uint32(gicdev
, "num-irq", NUM_IRQS
+ 32);
334 qdev_init_nofail(gicdev
);
335 gicbusdev
= SYS_BUS_DEVICE(gicdev
);
336 sysbus_mmio_map(gicbusdev
, 0, vbi
->memmap
[VIRT_GIC_DIST
].base
);
337 sysbus_mmio_map(gicbusdev
, 1, vbi
->memmap
[VIRT_GIC_CPU
].base
);
339 /* Wire the outputs from each CPU's generic timer to the
340 * appropriate GIC PPI inputs, and the GIC's IRQ output to
341 * the CPU's IRQ input.
343 for (i
= 0; i
< smp_cpus
; i
++) {
344 DeviceState
*cpudev
= DEVICE(qemu_get_cpu(i
));
345 int ppibase
= NUM_IRQS
+ i
* 32;
346 /* physical timer; we wire it up to the non-secure timer's ID,
347 * since a real A15 always has TrustZone but QEMU doesn't.
349 qdev_connect_gpio_out(cpudev
, 0,
350 qdev_get_gpio_in(gicdev
, ppibase
+ 30));
352 qdev_connect_gpio_out(cpudev
, 1,
353 qdev_get_gpio_in(gicdev
, ppibase
+ 27));
355 sysbus_connect_irq(gicbusdev
, i
, qdev_get_gpio_in(cpudev
, ARM_CPU_IRQ
));
358 for (i
= 0; i
< NUM_IRQS
; i
++) {
359 pic
[i
] = qdev_get_gpio_in(gicdev
, i
);
362 fdt_add_gic_node(vbi
);
365 static void create_uart(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
368 hwaddr base
= vbi
->memmap
[VIRT_UART
].base
;
369 hwaddr size
= vbi
->memmap
[VIRT_UART
].size
;
370 int irq
= vbi
->irqmap
[VIRT_UART
];
371 const char compat
[] = "arm,pl011\0arm,primecell";
372 const char clocknames
[] = "uartclk\0apb_pclk";
374 sysbus_create_simple("pl011", base
, pic
[irq
]);
376 nodename
= g_strdup_printf("/pl011@%" PRIx64
, base
);
377 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
378 /* Note that we can't use setprop_string because of the embedded NUL */
379 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible",
380 compat
, sizeof(compat
));
381 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
383 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
384 GIC_FDT_IRQ_TYPE_SPI
, irq
,
385 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
386 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "clocks",
387 vbi
->clock_phandle
, vbi
->clock_phandle
);
388 qemu_fdt_setprop(vbi
->fdt
, nodename
, "clock-names",
389 clocknames
, sizeof(clocknames
));
391 qemu_fdt_setprop_string(vbi
->fdt
, "/chosen", "linux,stdout-path", nodename
);
395 static void create_rtc(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
398 hwaddr base
= vbi
->memmap
[VIRT_RTC
].base
;
399 hwaddr size
= vbi
->memmap
[VIRT_RTC
].size
;
400 int irq
= vbi
->irqmap
[VIRT_RTC
];
401 const char compat
[] = "arm,pl031\0arm,primecell";
403 sysbus_create_simple("pl031", base
, pic
[irq
]);
405 nodename
= g_strdup_printf("/pl031@%" PRIx64
, base
);
406 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
407 qemu_fdt_setprop(vbi
->fdt
, nodename
, "compatible", compat
, sizeof(compat
));
408 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
410 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
411 GIC_FDT_IRQ_TYPE_SPI
, irq
,
412 GIC_FDT_IRQ_FLAGS_LEVEL_HI
);
413 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "clocks", vbi
->clock_phandle
);
414 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "clock-names", "apb_pclk");
418 static void create_virtio_devices(const VirtBoardInfo
*vbi
, qemu_irq
*pic
)
421 hwaddr size
= vbi
->memmap
[VIRT_MMIO
].size
;
423 /* Note that we have to create the transports in forwards order
424 * so that command line devices are inserted lowest address first,
425 * and then add dtb nodes in reverse order so that they appear in
426 * the finished device tree lowest address first.
428 for (i
= 0; i
< NUM_VIRTIO_TRANSPORTS
; i
++) {
429 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
430 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
432 sysbus_create_simple("virtio-mmio", base
, pic
[irq
]);
435 for (i
= NUM_VIRTIO_TRANSPORTS
- 1; i
>= 0; i
--) {
437 int irq
= vbi
->irqmap
[VIRT_MMIO
] + i
;
438 hwaddr base
= vbi
->memmap
[VIRT_MMIO
].base
+ i
* size
;
440 nodename
= g_strdup_printf("/virtio_mmio@%" PRIx64
, base
);
441 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
442 qemu_fdt_setprop_string(vbi
->fdt
, nodename
,
443 "compatible", "virtio,mmio");
444 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
446 qemu_fdt_setprop_cells(vbi
->fdt
, nodename
, "interrupts",
447 GIC_FDT_IRQ_TYPE_SPI
, irq
,
448 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI
);
453 static void create_one_flash(const char *name
, hwaddr flashbase
,
456 /* Create and map a single flash device. We use the same
457 * parameters as the flash devices on the Versatile Express board.
459 DriveInfo
*dinfo
= drive_get_next(IF_PFLASH
);
460 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
461 const uint64_t sectorlength
= 256 * 1024;
463 if (dinfo
&& qdev_prop_set_drive(dev
, "drive",
464 blk_by_legacy_dinfo(dinfo
))) {
468 qdev_prop_set_uint32(dev
, "num-blocks", flashsize
/ sectorlength
);
469 qdev_prop_set_uint64(dev
, "sector-length", sectorlength
);
470 qdev_prop_set_uint8(dev
, "width", 4);
471 qdev_prop_set_uint8(dev
, "device-width", 2);
472 qdev_prop_set_uint8(dev
, "big-endian", 0);
473 qdev_prop_set_uint16(dev
, "id0", 0x89);
474 qdev_prop_set_uint16(dev
, "id1", 0x18);
475 qdev_prop_set_uint16(dev
, "id2", 0x00);
476 qdev_prop_set_uint16(dev
, "id3", 0x00);
477 qdev_prop_set_string(dev
, "name", name
);
478 qdev_init_nofail(dev
);
480 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, flashbase
);
483 static void create_flash(const VirtBoardInfo
*vbi
)
485 /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
486 * Any file passed via -bios goes in the first of these.
488 hwaddr flashsize
= vbi
->memmap
[VIRT_FLASH
].size
/ 2;
489 hwaddr flashbase
= vbi
->memmap
[VIRT_FLASH
].base
;
495 if (drive_get(IF_PFLASH
, 0, 0)) {
496 error_report("The contents of the first flash device may be "
497 "specified with -bios or with -drive if=pflash... "
498 "but you cannot use both options at once");
501 fn
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
502 if (!fn
|| load_image_targphys(fn
, flashbase
, flashsize
) < 0) {
503 error_report("Could not load ROM image '%s'", bios_name
);
508 create_one_flash("virt.flash0", flashbase
, flashsize
);
509 create_one_flash("virt.flash1", flashbase
+ flashsize
, flashsize
);
511 nodename
= g_strdup_printf("/flash@%" PRIx64
, flashbase
);
512 qemu_fdt_add_subnode(vbi
->fdt
, nodename
);
513 qemu_fdt_setprop_string(vbi
->fdt
, nodename
, "compatible", "cfi-flash");
514 qemu_fdt_setprop_sized_cells(vbi
->fdt
, nodename
, "reg",
515 2, flashbase
, 2, flashsize
,
516 2, flashbase
+ flashsize
, 2, flashsize
);
517 qemu_fdt_setprop_cell(vbi
->fdt
, nodename
, "bank-width", 4);
521 static void *machvirt_dtb(const struct arm_boot_info
*binfo
, int *fdt_size
)
523 const VirtBoardInfo
*board
= (const VirtBoardInfo
*)binfo
;
525 *fdt_size
= board
->fdt_size
;
529 static void machvirt_init(MachineState
*machine
)
531 qemu_irq pic
[NUM_IRQS
];
532 MemoryRegion
*sysmem
= get_system_memory();
534 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
535 const char *cpu_model
= machine
->cpu_model
;
539 cpu_model
= "cortex-a15";
542 vbi
= find_machine_info(cpu_model
);
545 error_report("mach-virt: CPU %s not supported", cpu_model
);
549 vbi
->smp_cpus
= smp_cpus
;
552 * Only supported method of starting secondary CPUs is PSCI and
553 * PSCI is not yet supported with TCG, so limit smp_cpus to 1
554 * if we're not using KVM.
556 if (!kvm_enabled() && smp_cpus
> 1) {
557 error_report("mach-virt: must enable KVM to use multiple CPUs");
561 if (machine
->ram_size
> vbi
->memmap
[VIRT_MEM
].size
) {
562 error_report("mach-virt: cannot model more than 30GB RAM");
568 for (n
= 0; n
< smp_cpus
; n
++) {
569 ObjectClass
*oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpu_model
);
573 fprintf(stderr
, "Unable to find CPU definition\n");
576 cpuobj
= object_new(object_class_get_name(oc
));
578 /* Secondary CPUs start in PSCI powered-down state */
580 object_property_set_bool(cpuobj
, true, "start-powered-off", NULL
);
583 if (object_property_find(cpuobj
, "reset-cbar", NULL
)) {
584 object_property_set_int(cpuobj
, vbi
->memmap
[VIRT_CPUPERIPHS
].base
,
585 "reset-cbar", &error_abort
);
588 object_property_set_bool(cpuobj
, true, "realized", NULL
);
590 fdt_add_timer_nodes(vbi
);
591 fdt_add_cpu_nodes(vbi
);
592 fdt_add_psci_node(vbi
);
594 memory_region_init_ram(ram
, NULL
, "mach-virt.ram", machine
->ram_size
,
596 vmstate_register_ram_global(ram
);
597 memory_region_add_subregion(sysmem
, vbi
->memmap
[VIRT_MEM
].base
, ram
);
601 create_gic(vbi
, pic
);
603 create_uart(vbi
, pic
);
605 create_rtc(vbi
, pic
);
607 /* Create mmio transports, so the user can create virtio backends
608 * (which will be automatically plugged in to the transports). If
609 * no backend is created the transport will just sit harmlessly idle.
611 create_virtio_devices(vbi
, pic
);
613 vbi
->bootinfo
.ram_size
= machine
->ram_size
;
614 vbi
->bootinfo
.kernel_filename
= machine
->kernel_filename
;
615 vbi
->bootinfo
.kernel_cmdline
= machine
->kernel_cmdline
;
616 vbi
->bootinfo
.initrd_filename
= machine
->initrd_filename
;
617 vbi
->bootinfo
.nb_cpus
= smp_cpus
;
618 vbi
->bootinfo
.board_id
= -1;
619 vbi
->bootinfo
.loader_start
= vbi
->memmap
[VIRT_MEM
].base
;
620 vbi
->bootinfo
.get_dtb
= machvirt_dtb
;
621 arm_load_kernel(ARM_CPU(first_cpu
), &vbi
->bootinfo
);
624 static QEMUMachine machvirt_a15_machine
= {
626 .desc
= "ARM Virtual Machine",
627 .init
= machvirt_init
,
631 static void machvirt_machine_init(void)
633 qemu_register_machine(&machvirt_a15_machine
);
636 machine_init(machvirt_machine_init
);