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eepro100: Use symbolic names for bits in EEPROM id
[qemu.git] / hw / eepro100.c
blob2a871b826438427d46c2532e773dce49d1b9cec0
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2010 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559):
23 * PXE boot (i386) ok
24 * Linux networking (i386) ok
25 *
26 * Untested:
27 * non-i386 platforms
28 * Windows networking
29 *
30 * References:
31 *
32 * Intel 8255x 10/100 Mbps Ethernet Controller Family
33 * Open Source Software Developer Manual
34 *
35 * TODO:
36 * * PHY emulation should be separated from nic emulation.
37 * Most nic emulations could share the same phy code.
38 * * i82550 is untested. It is programmed like the i82559.
39 * * i82562 is untested. It is programmed like the i82559.
40 * * Power management (i82558 and later) is not implemented.
41 * * Wake-on-LAN is not implemented.
42 */
43
44 #include <stddef.h> /* offsetof */
45 #include <stdbool.h>
46 #include "hw.h"
47 #include "pci.h"
48 #include "net.h"
49 #include "eeprom93xx.h"
50
51 /* Common declarations for all PCI devices. */
52
53 #define PCI_CONFIG_8(offset, value) \
54 (pci_conf[offset] = (value))
55 #define PCI_CONFIG_16(offset, value) \
56 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
57 #define PCI_CONFIG_32(offset, value) \
58 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
59
60 #define KiB 1024
61
62 /* Debug EEPRO100 card. */
63 #if 0
64 # define DEBUG_EEPRO100
65 #endif
66
67 #ifdef DEBUG_EEPRO100
68 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
69 #else
70 #define logout(fmt, ...) ((void)0)
71 #endif
72
73 /* Set flags to 0 to disable debug output. */
74 #define INT 1 /* interrupt related actions */
75 #define MDI 1 /* mdi related actions */
76 #define OTHER 1
77 #define RXTX 1
78 #define EEPROM 1 /* eeprom related actions */
79
80 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
81
82 #define missing(text) fprintf(stderr, "eepro100: feature is missing in this emulation: " text "\n")
83
84 #define MAX_ETH_FRAME_SIZE 1514
85
86 /* This driver supports several different devices which are declared here. */
87 #define i82550 0x82550
88 #define i82551 0x82551
89 #define i82557A 0x82557a
90 #define i82557B 0x82557b
91 #define i82557C 0x82557c
92 #define i82558A 0x82558a
93 #define i82558B 0x82558b
94 #define i82559A 0x82559a
95 #define i82559B 0x82559b
96 #define i82559C 0x82559c
97 #define i82559ER 0x82559e
98 #define i82562 0x82562
99
100 /* Use 64 word EEPROM. TODO: could be a runtime option. */
101 #define EEPROM_SIZE 64
102
103 #define PCI_MEM_SIZE (4 * KiB)
104 #define PCI_IO_SIZE 64
105 #define PCI_FLASH_SIZE (128 * KiB)
106
107 #define BIT(n) (1 << (n))
108 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
109
110 /* The SCB accepts the following controls for the Tx and Rx units: */
111 #define CU_NOP 0x0000 /* No operation. */
112 #define CU_START 0x0010 /* CU start. */
113 #define CU_RESUME 0x0020 /* CU resume. */
114 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
115 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
116 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
117 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
118 #define CU_SRESUME 0x00a0 /* CU static resume. */
119
120 #define RU_NOP 0x0000
121 #define RX_START 0x0001
122 #define RX_RESUME 0x0002
123 #define RX_ABORT 0x0004
124 #define RX_ADDR_LOAD 0x0006
125 #define RX_RESUMENR 0x0007
126 #define INT_MASK 0x0100
127 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
128
129 /* Offsets to the various registers.
130 All accesses need not be longword aligned. */
131 enum speedo_offsets {
132 SCBStatus = 0, /* Status Word. */
133 SCBAck = 1,
134 SCBCmd = 2, /* Rx/Command Unit command and status. */
135 SCBIntmask = 3,
136 SCBPointer = 4, /* General purpose pointer. */
137 SCBPort = 8, /* Misc. commands and operands. */
138 SCBflash = 12, /* Flash memory control. */
139 SCBeeprom = 14, /* EEPROM control. */
140 SCBCtrlMDI = 16, /* MDI interface control. */
141 SCBEarlyRx = 20, /* Early receive byte count. */
142 SCBFlow = 24, /* Flow Control. */
143 SCBpmdr = 27, /* Power Management Driver. */
144 SCBgctrl = 28, /* General Control. */
145 SCBgstat = 29, /* General Status. */
146 };
147
148 /* A speedo3 transmit buffer descriptor with two buffers... */
149 typedef struct {
150 uint16_t status;
151 uint16_t command;
152 uint32_t link; /* void * */
153 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
154 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
155 uint8_t tx_threshold; /* transmit threshold */
156 uint8_t tbd_count; /* TBD number */
157 //~ /* This constitutes two "TBD" entries: hdr and data */
158 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
159 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
160 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
161 //~ int32_t tx_buf_size1; /* Length of Tx data. */
162 } eepro100_tx_t;
163
164 /* Receive frame descriptor. */
165 typedef struct {
166 int16_t status;
167 uint16_t command;
168 uint32_t link; /* struct RxFD * */
169 uint32_t rx_buf_addr; /* void * */
170 uint16_t count;
171 uint16_t size;
172 char packet[MAX_ETH_FRAME_SIZE + 4];
173 } eepro100_rx_t;
174
175 typedef enum {
176 COMMAND_EL = BIT(15),
177 COMMAND_S = BIT(14),
178 COMMAND_I = BIT(13),
179 COMMAND_NC = BIT(4),
180 COMMAND_SF = BIT(3),
181 COMMAND_CMD = BITS(2, 0),
182 } scb_command_bit;
183
184 typedef enum {
185 STATUS_C = BIT(15),
186 STATUS_OK = BIT(13),
187 } scb_status_bit;
188
189 typedef struct {
190 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
191 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
192 tx_multiple_collisions, tx_total_collisions;
193 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
194 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
195 rx_short_frame_errors;
196 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
197 uint16_t xmt_tco_frames, rcv_tco_frames;
198 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
199 uint32_t reserved[4];
200 } eepro100_stats_t;
201
202 typedef enum {
203 cu_idle = 0,
204 cu_suspended = 1,
205 cu_active = 2,
206 cu_lpq_active = 2,
207 cu_hqp_active = 3
208 } cu_state_t;
209
210 typedef enum {
211 ru_idle = 0,
212 ru_suspended = 1,
213 ru_no_resources = 2,
214 ru_ready = 4
215 } ru_state_t;
216
217 typedef struct {
218 PCIDevice dev;
219 uint8_t mult[8]; /* multicast mask array */
220 int mmio_index;
221 NICState *nic;
222 NICConf conf;
223 uint8_t scb_stat; /* SCB stat/ack byte */
224 uint8_t int_stat; /* PCI interrupt status */
225 /* region must not be saved by nic_save. */
226 uint32_t region[3]; /* PCI region addresses */
227 uint16_t mdimem[32];
228 eeprom_t *eeprom;
229 uint32_t device; /* device variant */
230 uint32_t pointer;
231 /* (cu_base + cu_offset) address the next command block in the command block list. */
232 uint32_t cu_base; /* CU base address */
233 uint32_t cu_offset; /* CU address offset */
234 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
235 uint32_t ru_base; /* RU base address */
236 uint32_t ru_offset; /* RU address offset */
237 uint32_t statsaddr; /* pointer to eepro100_stats_t */
238
239 /* Temporary status information (no need to save these values),
240 * used while processing CU commands. */
241 eepro100_tx_t tx; /* transmit buffer descriptor */
242 uint32_t cb_address; /* = cu_base + cu_offset */
243
244 /* Statistical counters. Also used for wake-up packet (i82559). */
245 eepro100_stats_t statistics;
246
247 #if 0
248 uint16_t status;
249 #endif
250
251 /* Configuration bytes. */
252 uint8_t configuration[22];
253
254 /* Data in mem is always in the byte order of the controller (le). */
255 uint8_t mem[PCI_MEM_SIZE];
256 /* vmstate for each particular nic */
257 VMStateDescription *vmstate;
258
259 /* Quasi static device properties (no need to save them). */
260 uint16_t stats_size;
261 bool has_extended_tcb_support;
262 } EEPRO100State;
263
264 /* Word indices in EEPROM. */
265 typedef enum {
266 EEPROM_CNFG_MDIX = 0x03,
267 EEPROM_ID = 0x05,
268 EEPROM_PHY_ID = 0x06,
269 EEPROM_VENDOR_ID = 0x0c,
270 EEPROM_CONFIG_ASF = 0x0d,
271 EEPROM_DEVICE_ID = 0x23,
272 EEPROM_SMBUS_ADDR = 0x90,
273 } EEPROMOffset;
274
275 /* Bit values for EEPROM ID word. */
276 typedef enum {
277 EEPROM_ID_MDM = BIT(0), /* Modem */
278 EEPROM_ID_STB = BIT(1), /* Standby Enable */
279 EEPROM_ID_WMR = BIT(2), /* ??? */
280 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
281 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
282 EEPROM_ID_ALT = BIT(7), /* */
283 /* BITS(10, 8) device revision */
284 EEPROM_ID_BD = BIT(11), /* boot disable */
285 EEPROM_ID_ID = BIT(13), /* id bit */
286 /* BITS(15, 14) signature */
287 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
288 } eeprom_id_bit;
289
290 /* Default values for MDI (PHY) registers */
291 static const uint16_t eepro100_mdi_default[] = {
292 /* MDI Registers 0 - 6, 7 */
293 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
294 /* MDI Registers 8 - 15 */
295 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
296 /* MDI Registers 16 - 31 */
297 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
298 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
299 };
300
301 /* Readonly mask for MDI (PHY) registers */
302 static const uint16_t eepro100_mdi_mask[] = {
303 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
304 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
305 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
306 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
307 };
308
309 /* XXX: optimize */
310 static void stl_le_phys(target_phys_addr_t addr, uint32_t val)
311 {
312 val = cpu_to_le32(val);
313 cpu_physical_memory_write(addr, (const uint8_t *)&val, sizeof(val));
314 }
315
316 #define POLYNOMIAL 0x04c11db6
317
318 /* From FreeBSD */
319 /* XXX: optimize */
320 static unsigned compute_mcast_idx(const uint8_t * ep)
321 {
322 uint32_t crc;
323 int carry, i, j;
324 uint8_t b;
325
326 crc = 0xffffffff;
327 for (i = 0; i < 6; i++) {
328 b = *ep++;
329 for (j = 0; j < 8; j++) {
330 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
331 crc <<= 1;
332 b >>= 1;
333 if (carry) {
334 crc = ((crc ^ POLYNOMIAL) | carry);
335 }
336 }
337 }
338 return (crc & BITS(7, 2)) >> 2;
339 }
340
341 #if defined(DEBUG_EEPRO100)
342 static const char *nic_dump(const uint8_t * buf, unsigned size)
343 {
344 static char dump[3 * 16 + 1];
345 char *p = &dump[0];
346 if (size > 16) {
347 size = 16;
348 }
349 while (size-- > 0) {
350 p += sprintf(p, " %02x", *buf++);
351 }
352 return dump;
353 }
354 #endif /* DEBUG_EEPRO100 */
355
356 enum scb_stat_ack {
357 stat_ack_not_ours = 0x00,
358 stat_ack_sw_gen = 0x04,
359 stat_ack_rnr = 0x10,
360 stat_ack_cu_idle = 0x20,
361 stat_ack_frame_rx = 0x40,
362 stat_ack_cu_cmd_done = 0x80,
363 stat_ack_not_present = 0xFF,
364 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
365 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
366 };
367
368 static void disable_interrupt(EEPRO100State * s)
369 {
370 if (s->int_stat) {
371 TRACE(INT, logout("interrupt disabled\n"));
372 qemu_irq_lower(s->dev.irq[0]);
373 s->int_stat = 0;
374 }
375 }
376
377 static void enable_interrupt(EEPRO100State * s)
378 {
379 if (!s->int_stat) {
380 TRACE(INT, logout("interrupt enabled\n"));
381 qemu_irq_raise(s->dev.irq[0]);
382 s->int_stat = 1;
383 }
384 }
385
386 static void eepro100_acknowledge(EEPRO100State * s)
387 {
388 s->scb_stat &= ~s->mem[SCBAck];
389 s->mem[SCBAck] = s->scb_stat;
390 if (s->scb_stat == 0) {
391 disable_interrupt(s);
392 }
393 }
394
395 static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
396 {
397 uint8_t mask = ~s->mem[SCBIntmask];
398 s->mem[SCBAck] |= stat;
399 stat = s->scb_stat = s->mem[SCBAck];
400 stat &= (mask | 0x0f);
401 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
402 if (stat && (mask & 0x01)) {
403 /* SCB mask and SCB Bit M do not disable interrupt. */
404 enable_interrupt(s);
405 } else if (s->int_stat) {
406 disable_interrupt(s);
407 }
408 }
409
410 static void eepro100_cx_interrupt(EEPRO100State * s)
411 {
412 /* CU completed action command. */
413 /* Transmit not ok (82557 only, not in emulation). */
414 eepro100_interrupt(s, 0x80);
415 }
416
417 static void eepro100_cna_interrupt(EEPRO100State * s)
418 {
419 /* CU left the active state. */
420 eepro100_interrupt(s, 0x20);
421 }
422
423 static void eepro100_fr_interrupt(EEPRO100State * s)
424 {
425 /* RU received a complete frame. */
426 eepro100_interrupt(s, 0x40);
427 }
428
429 #if 0
430 static void eepro100_rnr_interrupt(EEPRO100State * s)
431 {
432 /* RU is not ready. */
433 eepro100_interrupt(s, 0x10);
434 }
435 #endif
436
437 static void eepro100_mdi_interrupt(EEPRO100State * s)
438 {
439 /* MDI completed read or write cycle. */
440 eepro100_interrupt(s, 0x08);
441 }
442
443 static void eepro100_swi_interrupt(EEPRO100State * s)
444 {
445 /* Software has requested an interrupt. */
446 eepro100_interrupt(s, 0x04);
447 }
448
449 #if 0
450 static void eepro100_fcp_interrupt(EEPRO100State * s)
451 {
452 /* Flow control pause interrupt (82558 and later). */
453 eepro100_interrupt(s, 0x01);
454 }
455 #endif
456
457 static void pci_reset(EEPRO100State * s)
458 {
459 uint32_t device = s->device;
460 uint8_t *pci_conf = s->dev.config;
461 bool power_management = 1;
462
463 TRACE(OTHER, logout("%p\n", s));
464
465 /* PCI Vendor ID */
466 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
467 /* PCI Device ID depends on device and is set below. */
468 /* PCI Command */
469 /* TODO: this is the default, do not override. */
470 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
471 /* PCI Status */
472 /* TODO: Value at RST# should be 0. */
473 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
474 /* PCI Revision ID */
475 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
476 /* TODO: this is the default, do not override. */
477 /* PCI Class Code */
478 PCI_CONFIG_8(PCI_CLASS_PROG, 0x00);
479 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
480 /* PCI Cache Line Size */
481 /* check cache line size!!! */
482 //~ PCI_CONFIG_8(0x0c, 0x00);
483 /* PCI Latency Timer */
484 PCI_CONFIG_8(PCI_LATENCY_TIMER, 0x20); // latency timer = 32 clocks
485 /* PCI Header Type */
486 /* BIST (built-in self test) */
487 /* Expansion ROM Base Address (depends on boot disable!!!) */
488 /* TODO: not needed, set when BAR is registered */
489 PCI_CONFIG_32(PCI_ROM_ADDRESS, PCI_BASE_ADDRESS_SPACE_MEMORY);
490 /* Capability Pointer */
491 /* TODO: revisions with power_management 1 use this but
492 * do not set new capability list bit in status register. */
493 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0xdc);
494 /* Interrupt Line */
495 /* Interrupt Pin */
496 /* TODO: RST# value should be 0 */
497 PCI_CONFIG_8(PCI_INTERRUPT_PIN, 1); // interrupt pin 0
498 /* Minimum Grant */
499 PCI_CONFIG_8(PCI_MIN_GNT, 0x08);
500 /* Maximum Latency */
501 PCI_CONFIG_8(PCI_MAX_LAT, 0x18);
502
503 switch (device) {
504 case i82550:
505 // TODO: check device id.
506 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
507 /* Revision ID: 0x0c, 0x0d, 0x0e. */
508 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
509 // TODO: check size of statistical counters.
510 s->stats_size = 80;
511 // TODO: check extended tcb support.
512 s->has_extended_tcb_support = 1;
513 break;
514 case i82551:
515 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
516 /* Revision ID: 0x0f, 0x10. */
517 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
518 // TODO: check size of statistical counters.
519 s->stats_size = 80;
520 s->has_extended_tcb_support = 1;
521 break;
522 case i82557A:
523 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
524 PCI_CONFIG_8(PCI_REVISION_ID, 0x01);
525 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
526 power_management = 0;
527 break;
528 case i82557B:
529 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
530 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
531 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
532 power_management = 0;
533 break;
534 case i82557C:
535 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
536 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
537 PCI_CONFIG_8(PCI_CAPABILITY_LIST, 0x00);
538 power_management = 0;
539 break;
540 case i82558A:
541 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
542 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
543 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
544 PCI_CONFIG_8(PCI_REVISION_ID, 0x04);
545 s->stats_size = 76;
546 s->has_extended_tcb_support = 1;
547 break;
548 case i82558B:
549 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
550 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
551 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
552 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
553 s->stats_size = 76;
554 s->has_extended_tcb_support = 1;
555 break;
556 case i82559A:
557 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
558 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
559 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
560 PCI_CONFIG_8(PCI_REVISION_ID, 0x06);
561 s->stats_size = 80;
562 s->has_extended_tcb_support = 1;
563 break;
564 case i82559B:
565 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
566 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
567 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
568 PCI_CONFIG_8(PCI_REVISION_ID, 0x07);
569 s->stats_size = 80;
570 s->has_extended_tcb_support = 1;
571 break;
572 case i82559C:
573 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82557);
574 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
575 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
576 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
577 // TODO: Windows wants revision id 0x0c.
578 PCI_CONFIG_8(PCI_REVISION_ID, 0x0c);
579 #if EEPROM_SIZE > 0
580 PCI_CONFIG_16(PCI_SUBSYSTEM_VENDOR_ID, 0x8086);
581 PCI_CONFIG_16(PCI_SUBSYSTEM_ID, 0x0040);
582 #endif
583 s->stats_size = 80;
584 s->has_extended_tcb_support = 1;
585 break;
586 case i82559ER:
587 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
588 PCI_CONFIG_16(PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
589 PCI_STATUS_FAST_BACK | PCI_STATUS_CAP_LIST);
590 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
591 s->stats_size = 80;
592 s->has_extended_tcb_support = 1;
593 break;
594 case i82562:
595 // TODO: check device id.
596 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82551IT);
597 /* TODO: wrong revision id. */
598 PCI_CONFIG_8(PCI_REVISION_ID, 0x0e);
599 s->stats_size = 80;
600 s->has_extended_tcb_support = 1;
601 break;
602 default:
603 logout("Device %X is undefined!\n", device);
604 }
605
606 s->configuration[6] |= BIT(5);
607
608 if (s->stats_size == 80) {
609 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
610 if (s->configuration[6] & BIT(2)) {
611 /* TCO statistical counters. */
612 assert(s->configuration[6] & BIT(5));
613 } else {
614 if (s->configuration[6] & BIT(5)) {
615 /* No extended statistical counters, i82557 compatible. */
616 s->stats_size = 64;
617 } else {
618 /* i82558 compatible. */
619 s->stats_size = 76;
620 }
621 }
622 } else {
623 if (s->configuration[6] & BIT(5)) {
624 /* No extended statistical counters. */
625 s->stats_size = 64;
626 }
627 }
628 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
629
630 if (power_management) {
631 /* Power Management Capabilities */
632 PCI_CONFIG_8(0xdc, 0x01);
633 /* Next Item Pointer */
634 /* Capability ID */
635 PCI_CONFIG_16(0xde, 0x7e21);
636 /* TODO: Power Management Control / Status. */
637 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
638 }
639
640 #if EEPROM_SIZE > 0
641 if (device == i82557C || device == i82558B || device == i82559C) {
642 // TODO: get vendor id from EEPROM for i82557C or later.
643 // TODO: get device id from EEPROM for i82557C or later.
644 // TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
645 // TODO: header type is determined by EEPROM for i82559.
646 // TODO: get subsystem id from EEPROM for i82557C or later.
647 // TODO: get subsystem vendor id from EEPROM for i82557C or later.
648 // TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
649 // TODO: capability pointer depends on EEPROM for i82558.
650 logout("Get device id and revision from EEPROM!!!\n");
651 }
652 #endif /* EEPROM_SIZE > 0 */
653 }
654
655 static void nic_selective_reset(EEPRO100State * s)
656 {
657 size_t i;
658 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
659 //~ eeprom93xx_reset(s->eeprom);
660 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
661 eeprom_contents[EEPROM_ID] = EEPROM_ID_VALID;
662 if (s->device == i82557B || s->device == i82557C)
663 eeprom_contents[5] = 0x0100;
664 eeprom_contents[EEPROM_PHY_ID] = 1;
665 uint16_t sum = 0;
666 for (i = 0; i < EEPROM_SIZE - 1; i++) {
667 sum += eeprom_contents[i];
668 }
669 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
670 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
671
672 memset(s->mem, 0, sizeof(s->mem));
673 uint32_t val = BIT(21);
674 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
675
676 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
677 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
678 }
679
680 static void nic_reset(void *opaque)
681 {
682 EEPRO100State *s = opaque;
683 TRACE(OTHER, logout("%p\n", s));
684 /* TODO: Clearing of multicast table for selective reset, too? */
685 memset(&s->mult[0], 0, sizeof(s->mult));
686 nic_selective_reset(s);
687 }
688
689 #if defined(DEBUG_EEPRO100)
690 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
691 "Command/Status",
692 "General Pointer",
693 "Port",
694 "EEPROM/Flash Control",
695 "MDI Control",
696 "Receive DMA Byte Count",
697 "Flow Control",
698 "General Status/Control"
699 };
700
701 static char *regname(uint32_t addr)
702 {
703 static char buf[32];
704 if (addr < PCI_IO_SIZE) {
705 const char *r = e100_reg[addr / 4];
706 if (r != 0) {
707 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
708 } else {
709 snprintf(buf, sizeof(buf), "0x%02x", addr);
710 }
711 } else {
712 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
713 }
714 return buf;
715 }
716 #endif /* DEBUG_EEPRO100 */
717
718 #if 0
719 static uint16_t eepro100_read_status(EEPRO100State * s)
720 {
721 uint16_t val = s->status;
722 TRACE(OTHER, logout("val=0x%04x\n", val));
723 return val;
724 }
725
726 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
727 {
728 TRACE(OTHER, logout("val=0x%04x\n", val));
729 s->status = val;
730 }
731 #endif
732
733 /*****************************************************************************
734 *
735 * Command emulation.
736 *
737 ****************************************************************************/
738
739 #if 0
740 static uint16_t eepro100_read_command(EEPRO100State * s)
741 {
742 uint16_t val = 0xffff;
743 //~ TRACE(OTHER, logout("val=0x%04x\n", val));
744 return val;
745 }
746 #endif
747
748 /* Commands that can be put in a command list entry. */
749 enum commands {
750 CmdNOp = 0,
751 CmdIASetup = 1,
752 CmdConfigure = 2,
753 CmdMulticastList = 3,
754 CmdTx = 4,
755 CmdTDR = 5, /* load microcode */
756 CmdDump = 6,
757 CmdDiagnose = 7,
758
759 /* And some extra flags: */
760 CmdSuspend = 0x4000, /* Suspend after completion. */
761 CmdIntr = 0x2000, /* Interrupt after completion. */
762 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
763 };
764
765 static cu_state_t get_cu_state(EEPRO100State * s)
766 {
767 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
768 }
769
770 static void set_cu_state(EEPRO100State * s, cu_state_t state)
771 {
772 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
773 }
774
775 static ru_state_t get_ru_state(EEPRO100State * s)
776 {
777 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
778 }
779
780 static void set_ru_state(EEPRO100State * s, ru_state_t state)
781 {
782 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
783 }
784
785 static void dump_statistics(EEPRO100State * s)
786 {
787 /* Dump statistical data. Most data is never changed by the emulation
788 * and always 0, so we first just copy the whole block and then those
789 * values which really matter.
790 * Number of data should check configuration!!!
791 */
792 cpu_physical_memory_write(s->statsaddr,
793 (uint8_t *) & s->statistics, s->stats_size);
794 stl_le_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
795 stl_le_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
796 stl_le_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
797 stl_le_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
798 //~ stw_le_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
799 //~ stw_le_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
800 //~ missing("CU dump statistical counters");
801 }
802
803 static void tx_command(EEPRO100State *s)
804 {
805 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
806 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
807 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
808 uint8_t buf[2600];
809 uint16_t size = 0;
810 uint32_t tbd_address = s->cb_address + 0x10;
811 TRACE(RXTX, logout
812 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
813 tbd_array, tcb_bytes, s->tx.tbd_count));
814
815 if (tcb_bytes > 2600) {
816 logout("TCB byte count too large, using 2600\n");
817 tcb_bytes = 2600;
818 }
819 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
820 logout
821 ("illegal values of TBD array address and TCB byte count!\n");
822 }
823 assert(tcb_bytes <= sizeof(buf));
824 while (size < tcb_bytes) {
825 uint32_t tx_buffer_address = ldl_phys(tbd_address);
826 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
827 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
828 tbd_address += 8;
829 TRACE(RXTX, logout
830 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
831 tx_buffer_address, tx_buffer_size));
832 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
833 cpu_physical_memory_read(tx_buffer_address, &buf[size],
834 tx_buffer_size);
835 size += tx_buffer_size;
836 }
837 if (tbd_array == 0xffffffff) {
838 /* Simplified mode. Was already handled by code above. */
839 } else {
840 /* Flexible mode. */
841 uint8_t tbd_count = 0;
842 if (s->has_extended_tcb_support && !(s->configuration[6] & BIT(4))) {
843 /* Extended Flexible TCB. */
844 for (; tbd_count < 2; tbd_count++) {
845 uint32_t tx_buffer_address = ldl_phys(tbd_address);
846 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
847 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
848 tbd_address += 8;
849 TRACE(RXTX, logout
850 ("TBD (extended flexible mode): buffer address 0x%08x, size 0x%04x\n",
851 tx_buffer_address, tx_buffer_size));
852 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
853 cpu_physical_memory_read(tx_buffer_address, &buf[size],
854 tx_buffer_size);
855 size += tx_buffer_size;
856 if (tx_buffer_el & 1) {
857 break;
858 }
859 }
860 }
861 tbd_address = tbd_array;
862 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
863 uint32_t tx_buffer_address = ldl_phys(tbd_address);
864 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
865 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
866 tbd_address += 8;
867 TRACE(RXTX, logout
868 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
869 tx_buffer_address, tx_buffer_size));
870 tx_buffer_size = MIN(tx_buffer_size, sizeof(buf) - size);
871 cpu_physical_memory_read(tx_buffer_address, &buf[size],
872 tx_buffer_size);
873 size += tx_buffer_size;
874 if (tx_buffer_el & 1) {
875 break;
876 }
877 }
878 }
879 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
880 qemu_send_packet(&s->nic->nc, buf, size);
881 s->statistics.tx_good_frames++;
882 /* Transmit with bad status would raise an CX/TNO interrupt.
883 * (82557 only). Emulation never has bad status. */
884 //~ eepro100_cx_interrupt(s);
885 }
886
887 static void set_multicast_list(EEPRO100State *s)
888 {
889 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
890 uint16_t i;
891 memset(&s->mult[0], 0, sizeof(s->mult));
892 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
893 for (i = 0; i < multicast_count; i += 6) {
894 uint8_t multicast_addr[6];
895 cpu_physical_memory_read(s->cb_address + 10 + i, multicast_addr, 6);
896 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
897 unsigned mcast_idx = compute_mcast_idx(multicast_addr);
898 assert(mcast_idx < 64);
899 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
900 }
901 }
902
903 static void action_command(EEPRO100State *s)
904 {
905 for (;;) {
906 s->cb_address = s->cu_base + s->cu_offset;
907 cpu_physical_memory_read(s->cb_address, (uint8_t *)&s->tx, sizeof(s->tx));
908 uint16_t status = le16_to_cpu(s->tx.status);
909 uint16_t command = le16_to_cpu(s->tx.command);
910 logout("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
911 status, command, s->tx.link);
912 bool bit_el = ((command & COMMAND_EL) != 0);
913 bool bit_s = ((command & COMMAND_S) != 0);
914 bool bit_i = ((command & COMMAND_I) != 0);
915 bool bit_nc = ((command & COMMAND_NC) != 0);
916 bool success = true;
917 //~ bool bit_sf = ((command & COMMAND_SF) != 0);
918 uint16_t cmd = command & COMMAND_CMD;
919 s->cu_offset = le32_to_cpu(s->tx.link);
920 switch (cmd) {
921 case CmdNOp:
922 /* Do nothing. */
923 break;
924 case CmdIASetup:
925 cpu_physical_memory_read(s->cb_address + 8, &s->conf.macaddr.a[0], 6);
926 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
927 break;
928 case CmdConfigure:
929 cpu_physical_memory_read(s->cb_address + 8, &s->configuration[0],
930 sizeof(s->configuration));
931 TRACE(OTHER, logout("configuration: %s\n", nic_dump(&s->configuration[0], 16)));
932 break;
933 case CmdMulticastList:
934 set_multicast_list(s);
935 break;
936 case CmdTx:
937 if (bit_nc) {
938 missing("CmdTx: NC = 0");
939 success = false;
940 break;
941 }
942 tx_command(s);
943 break;
944 case CmdTDR:
945 TRACE(OTHER, logout("load microcode\n"));
946 /* Starting with offset 8, the command contains
947 * 64 dwords microcode which we just ignore here. */
948 break;
949 default:
950 missing("undefined command");
951 success = false;
952 break;
953 }
954 /* Write new status. */
955 stw_phys(s->cb_address, status | STATUS_C | (success ? STATUS_OK : 0));
956 if (bit_i) {
957 /* CU completed action. */
958 eepro100_cx_interrupt(s);
959 }
960 if (bit_el) {
961 /* CU becomes idle. Terminate command loop. */
962 set_cu_state(s, cu_idle);
963 eepro100_cna_interrupt(s);
964 break;
965 } else if (bit_s) {
966 /* CU becomes suspended. Terminate command loop. */
967 set_cu_state(s, cu_suspended);
968 eepro100_cna_interrupt(s);
969 break;
970 } else {
971 /* More entries in list. */
972 TRACE(OTHER, logout("CU list with at least one more entry\n"));
973 }
974 }
975 TRACE(OTHER, logout("CU list empty\n"));
976 /* List is empty. Now CU is idle or suspended. */
977 }
978
979 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
980 {
981 switch (val) {
982 case CU_NOP:
983 /* No operation. */
984 break;
985 case CU_START:
986 if (get_cu_state(s) != cu_idle) {
987 /* Intel documentation says that CU must be idle for the CU
988 * start command. Intel driver for Linux also starts the CU
989 * from suspended state. */
990 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
991 //~ assert(!"wrong CU state");
992 }
993 set_cu_state(s, cu_active);
994 s->cu_offset = s->pointer;
995 action_command(s);
996 break;
997 case CU_RESUME:
998 if (get_cu_state(s) != cu_suspended) {
999 logout("bad CU resume from CU state %u\n", get_cu_state(s));
1000 /* Workaround for bad Linux eepro100 driver which resumes
1001 * from idle state. */
1002 //~ missing("cu resume");
1003 set_cu_state(s, cu_suspended);
1004 }
1005 if (get_cu_state(s) == cu_suspended) {
1006 TRACE(OTHER, logout("CU resuming\n"));
1007 set_cu_state(s, cu_active);
1008 action_command(s);
1009 }
1010 break;
1011 case CU_STATSADDR:
1012 /* Load dump counters address. */
1013 s->statsaddr = s->pointer;
1014 TRACE(OTHER, logout("val=0x%02x (status address)\n", val));
1015 break;
1016 case CU_SHOWSTATS:
1017 /* Dump statistical counters. */
1018 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1019 dump_statistics(s);
1020 stl_le_phys(s->statsaddr + s->stats_size, 0xa005);
1021 break;
1022 case CU_CMD_BASE:
1023 /* Load CU base. */
1024 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1025 s->cu_base = s->pointer;
1026 break;
1027 case CU_DUMPSTATS:
1028 /* Dump and reset statistical counters. */
1029 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1030 dump_statistics(s);
1031 stl_le_phys(s->statsaddr + s->stats_size, 0xa007);
1032 memset(&s->statistics, 0, sizeof(s->statistics));
1033 break;
1034 case CU_SRESUME:
1035 /* CU static resume. */
1036 missing("CU static resume");
1037 break;
1038 default:
1039 missing("Undefined CU command");
1040 }
1041 }
1042
1043 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1044 {
1045 switch (val) {
1046 case RU_NOP:
1047 /* No operation. */
1048 break;
1049 case RX_START:
1050 /* RU start. */
1051 if (get_ru_state(s) != ru_idle) {
1052 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1053 //~ assert(!"wrong RU state");
1054 }
1055 set_ru_state(s, ru_ready);
1056 s->ru_offset = s->pointer;
1057 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1058 break;
1059 case RX_RESUME:
1060 /* Restart RU. */
1061 if (get_ru_state(s) != ru_suspended) {
1062 logout("RU state is %u, should be %u\n", get_ru_state(s),
1063 ru_suspended);
1064 //~ assert(!"wrong RU state");
1065 }
1066 set_ru_state(s, ru_ready);
1067 break;
1068 case RX_ADDR_LOAD:
1069 /* Load RU base. */
1070 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1071 s->ru_base = s->pointer;
1072 break;
1073 default:
1074 logout("val=0x%02x (undefined RU command)\n", val);
1075 missing("Undefined SU command");
1076 }
1077 }
1078
1079 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1080 {
1081 eepro100_ru_command(s, val & 0x0f);
1082 eepro100_cu_command(s, val & 0xf0);
1083 if ((val) == 0) {
1084 TRACE(OTHER, logout("val=0x%02x\n", val));
1085 }
1086 /* Clear command byte after command was accepted. */
1087 s->mem[SCBCmd] = 0;
1088 }
1089
1090 /*****************************************************************************
1091 *
1092 * EEPROM emulation.
1093 *
1094 ****************************************************************************/
1095
1096 #define EEPROM_CS 0x02
1097 #define EEPROM_SK 0x01
1098 #define EEPROM_DI 0x04
1099 #define EEPROM_DO 0x08
1100
1101 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1102 {
1103 uint16_t val;
1104 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
1105 if (eeprom93xx_read(s->eeprom)) {
1106 val |= EEPROM_DO;
1107 } else {
1108 val &= ~EEPROM_DO;
1109 }
1110 TRACE(EEPROM, logout("val=0x%04x\n", val));
1111 return val;
1112 }
1113
1114 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1115 {
1116 TRACE(EEPROM, logout("val=0x%02x\n", val));
1117
1118 /* mask unwriteable bits */
1119 //~ val = SET_MASKED(val, 0x31, eeprom->value);
1120
1121 int eecs = ((val & EEPROM_CS) != 0);
1122 int eesk = ((val & EEPROM_SK) != 0);
1123 int eedi = ((val & EEPROM_DI) != 0);
1124 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1125 }
1126
1127 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
1128 {
1129 s->pointer = le32_to_cpu(val);
1130 TRACE(OTHER, logout("val=0x%08x\n", val));
1131 }
1132
1133 /*****************************************************************************
1134 *
1135 * MDI emulation.
1136 *
1137 ****************************************************************************/
1138
1139 #if defined(DEBUG_EEPRO100)
1140 static const char * const mdi_op_name[] = {
1141 "opcode 0",
1142 "write",
1143 "read",
1144 "opcode 3"
1145 };
1146
1147 static const char * const mdi_reg_name[] = {
1148 "Control",
1149 "Status",
1150 "PHY Identification (Word 1)",
1151 "PHY Identification (Word 2)",
1152 "Auto-Negotiation Advertisement",
1153 "Auto-Negotiation Link Partner Ability",
1154 "Auto-Negotiation Expansion"
1155 };
1156
1157 static const char *reg2name(uint8_t reg)
1158 {
1159 static char buffer[10];
1160 const char *p = buffer;
1161 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1162 p = mdi_reg_name[reg];
1163 } else {
1164 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1165 }
1166 return p;
1167 }
1168 #endif /* DEBUG_EEPRO100 */
1169
1170 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1171 {
1172 uint32_t val;
1173 memcpy(&val, &s->mem[0x10], sizeof(val));
1174
1175 #ifdef DEBUG_EEPRO100
1176 uint8_t raiseint = (val & BIT(29)) >> 29;
1177 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1178 uint8_t phy = (val & BITS(25, 21)) >> 21;
1179 uint8_t reg = (val & BITS(20, 16)) >> 16;
1180 uint16_t data = (val & BITS(15, 0));
1181 #endif
1182 /* Emulation takes no time to finish MDI transaction. */
1183 val |= BIT(28);
1184 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1185 val, raiseint, mdi_op_name[opcode], phy,
1186 reg2name(reg), data));
1187 return val;
1188 }
1189
1190 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
1191 {
1192 uint8_t raiseint = (val & BIT(29)) >> 29;
1193 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1194 uint8_t phy = (val & BITS(25, 21)) >> 21;
1195 uint8_t reg = (val & BITS(20, 16)) >> 16;
1196 uint16_t data = (val & BITS(15, 0));
1197 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1198 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1199 if (phy != 1) {
1200 /* Unsupported PHY address. */
1201 //~ logout("phy must be 1 but is %u\n", phy);
1202 data = 0;
1203 } else if (opcode != 1 && opcode != 2) {
1204 /* Unsupported opcode. */
1205 logout("opcode must be 1 or 2 but is %u\n", opcode);
1206 data = 0;
1207 } else if (reg > 6) {
1208 /* Unsupported register. */
1209 logout("register must be 0...6 but is %u\n", reg);
1210 data = 0;
1211 } else {
1212 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1213 val, raiseint, mdi_op_name[opcode], phy,
1214 reg2name(reg), data));
1215 if (opcode == 1) {
1216 /* MDI write */
1217 switch (reg) {
1218 case 0: /* Control Register */
1219 if (data & 0x8000) {
1220 /* Reset status and control registers to default. */
1221 s->mdimem[0] = eepro100_mdi_default[0];
1222 s->mdimem[1] = eepro100_mdi_default[1];
1223 data = s->mdimem[reg];
1224 } else {
1225 /* Restart Auto Configuration = Normal Operation */
1226 data &= ~0x0200;
1227 }
1228 break;
1229 case 1: /* Status Register */
1230 missing("not writable");
1231 data = s->mdimem[reg];
1232 break;
1233 case 2: /* PHY Identification Register (Word 1) */
1234 case 3: /* PHY Identification Register (Word 2) */
1235 missing("not implemented");
1236 break;
1237 case 4: /* Auto-Negotiation Advertisement Register */
1238 case 5: /* Auto-Negotiation Link Partner Ability Register */
1239 break;
1240 case 6: /* Auto-Negotiation Expansion Register */
1241 default:
1242 missing("not implemented");
1243 }
1244 s->mdimem[reg] = data;
1245 } else if (opcode == 2) {
1246 /* MDI read */
1247 switch (reg) {
1248 case 0: /* Control Register */
1249 if (data & 0x8000) {
1250 /* Reset status and control registers to default. */
1251 s->mdimem[0] = eepro100_mdi_default[0];
1252 s->mdimem[1] = eepro100_mdi_default[1];
1253 }
1254 break;
1255 case 1: /* Status Register */
1256 s->mdimem[reg] |= 0x0020;
1257 break;
1258 case 2: /* PHY Identification Register (Word 1) */
1259 case 3: /* PHY Identification Register (Word 2) */
1260 case 4: /* Auto-Negotiation Advertisement Register */
1261 break;
1262 case 5: /* Auto-Negotiation Link Partner Ability Register */
1263 s->mdimem[reg] = 0x41fe;
1264 break;
1265 case 6: /* Auto-Negotiation Expansion Register */
1266 s->mdimem[reg] = 0x0001;
1267 break;
1268 }
1269 data = s->mdimem[reg];
1270 }
1271 /* Emulation takes no time to finish MDI transaction.
1272 * Set MDI bit in SCB status register. */
1273 s->mem[SCBAck] |= 0x08;
1274 val |= BIT(28);
1275 if (raiseint) {
1276 eepro100_mdi_interrupt(s);
1277 }
1278 }
1279 val = (val & 0xffff0000) + data;
1280 memcpy(&s->mem[0x10], &val, sizeof(val));
1281 }
1282
1283 /*****************************************************************************
1284 *
1285 * Port emulation.
1286 *
1287 ****************************************************************************/
1288
1289 #define PORT_SOFTWARE_RESET 0
1290 #define PORT_SELFTEST 1
1291 #define PORT_SELECTIVE_RESET 2
1292 #define PORT_DUMP 3
1293 #define PORT_SELECTION_MASK 3
1294
1295 typedef struct {
1296 uint32_t st_sign; /* Self Test Signature */
1297 uint32_t st_result; /* Self Test Results */
1298 } eepro100_selftest_t;
1299
1300 static uint32_t eepro100_read_port(EEPRO100State * s)
1301 {
1302 return 0;
1303 }
1304
1305 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1306 {
1307 val = le32_to_cpu(val);
1308 uint32_t address = (val & ~PORT_SELECTION_MASK);
1309 uint8_t selection = (val & PORT_SELECTION_MASK);
1310 switch (selection) {
1311 case PORT_SOFTWARE_RESET:
1312 nic_reset(s);
1313 break;
1314 case PORT_SELFTEST:
1315 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1316 eepro100_selftest_t data;
1317 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1318 data.st_sign = 0xffffffff;
1319 data.st_result = 0;
1320 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1321 break;
1322 case PORT_SELECTIVE_RESET:
1323 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1324 nic_selective_reset(s);
1325 break;
1326 default:
1327 logout("val=0x%08x\n", val);
1328 missing("unknown port selection");
1329 }
1330 }
1331
1332 /*****************************************************************************
1333 *
1334 * General hardware emulation.
1335 *
1336 ****************************************************************************/
1337
1338 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1339 {
1340 uint8_t val;
1341 if (addr <= sizeof(s->mem) - sizeof(val)) {
1342 memcpy(&val, &s->mem[addr], sizeof(val));
1343 }
1344
1345 switch (addr) {
1346 case SCBStatus:
1347 //~ val = eepro100_read_status(s);
1348 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1349 break;
1350 case SCBAck:
1351 //~ val = eepro100_read_status(s);
1352 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1353 break;
1354 case SCBCmd:
1355 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1356 //~ val = eepro100_read_command(s);
1357 break;
1358 case SCBIntmask:
1359 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1360 break;
1361 case SCBPort + 3:
1362 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1363 break;
1364 case SCBeeprom:
1365 val = eepro100_read_eeprom(s);
1366 break;
1367 case SCBpmdr: /* Power Management Driver Register */
1368 val = 0;
1369 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1370 break;
1371 case SCBgstat: /* General Status Register */
1372 /* 100 Mbps full duplex, valid link */
1373 val = 0x07;
1374 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1375 break;
1376 default:
1377 logout("addr=%s val=0x%02x\n", regname(addr), val);
1378 missing("unknown byte read");
1379 }
1380 return val;
1381 }
1382
1383 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1384 {
1385 uint16_t val;
1386 if (addr <= sizeof(s->mem) - sizeof(val)) {
1387 memcpy(&val, &s->mem[addr], sizeof(val));
1388 }
1389
1390 switch (addr) {
1391 case SCBStatus:
1392 //~ val = eepro100_read_status(s);
1393 case SCBCmd:
1394 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1395 break;
1396 case SCBeeprom:
1397 val = eepro100_read_eeprom(s);
1398 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1399 break;
1400 default:
1401 logout("addr=%s val=0x%04x\n", regname(addr), val);
1402 missing("unknown word read");
1403 }
1404 return val;
1405 }
1406
1407 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1408 {
1409 uint32_t val;
1410 if (addr <= sizeof(s->mem) - sizeof(val)) {
1411 memcpy(&val, &s->mem[addr], sizeof(val));
1412 }
1413
1414 switch (addr) {
1415 case SCBStatus:
1416 //~ val = eepro100_read_status(s);
1417 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1418 break;
1419 case SCBPointer:
1420 //~ val = eepro100_read_pointer(s);
1421 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1422 break;
1423 case SCBPort:
1424 val = eepro100_read_port(s);
1425 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1426 break;
1427 case SCBCtrlMDI:
1428 val = eepro100_read_mdi(s);
1429 break;
1430 default:
1431 logout("addr=%s val=0x%08x\n", regname(addr), val);
1432 missing("unknown longword read");
1433 }
1434 return val;
1435 }
1436
1437 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1438 {
1439 if (addr <= sizeof(s->mem) - sizeof(val)) {
1440 memcpy(&s->mem[addr], &val, sizeof(val));
1441 }
1442
1443 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1444
1445 switch (addr) {
1446 case SCBStatus:
1447 //~ eepro100_write_status(s, val);
1448 break;
1449 case SCBAck:
1450 eepro100_acknowledge(s);
1451 break;
1452 case SCBCmd:
1453 eepro100_write_command(s, val);
1454 break;
1455 case SCBIntmask:
1456 if (val & BIT(1)) {
1457 eepro100_swi_interrupt(s);
1458 }
1459 eepro100_interrupt(s, 0);
1460 break;
1461 case SCBPort + 3:
1462 case SCBFlow: /* does not exist on 82557 */
1463 case SCBFlow + 1:
1464 case SCBFlow + 2:
1465 case SCBpmdr: /* does not exist on 82557 */
1466 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1467 break;
1468 case SCBeeprom:
1469 eepro100_write_eeprom(s->eeprom, val);
1470 break;
1471 default:
1472 logout("addr=%s val=0x%02x\n", regname(addr), val);
1473 missing("unknown byte write");
1474 }
1475 }
1476
1477 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1478 {
1479 if (addr <= sizeof(s->mem) - sizeof(val)) {
1480 memcpy(&s->mem[addr], &val, sizeof(val));
1481 }
1482
1483 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1484
1485 switch (addr) {
1486 case SCBStatus:
1487 //~ eepro100_write_status(s, val);
1488 eepro100_acknowledge(s);
1489 break;
1490 case SCBCmd:
1491 eepro100_write_command(s, val);
1492 eepro100_write1(s, SCBIntmask, val >> 8);
1493 break;
1494 case SCBeeprom:
1495 eepro100_write_eeprom(s->eeprom, val);
1496 break;
1497 default:
1498 logout("addr=%s val=0x%04x\n", regname(addr), val);
1499 missing("unknown word write");
1500 }
1501 }
1502
1503 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1504 {
1505 if (addr <= sizeof(s->mem) - sizeof(val)) {
1506 memcpy(&s->mem[addr], &val, sizeof(val));
1507 }
1508
1509 switch (addr) {
1510 case SCBPointer:
1511 eepro100_write_pointer(s, val);
1512 break;
1513 case SCBPort:
1514 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1515 eepro100_write_port(s, val);
1516 break;
1517 case SCBCtrlMDI:
1518 eepro100_write_mdi(s, val);
1519 break;
1520 default:
1521 logout("addr=%s val=0x%08x\n", regname(addr), val);
1522 missing("unknown longword write");
1523 }
1524 }
1525
1526 /*****************************************************************************
1527 *
1528 * Port mapped I/O.
1529 *
1530 ****************************************************************************/
1531
1532 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1533 {
1534 EEPRO100State *s = opaque;
1535 //~ logout("addr=%s\n", regname(addr));
1536 return eepro100_read1(s, addr - s->region[1]);
1537 }
1538
1539 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1540 {
1541 EEPRO100State *s = opaque;
1542 return eepro100_read2(s, addr - s->region[1]);
1543 }
1544
1545 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1546 {
1547 EEPRO100State *s = opaque;
1548 return eepro100_read4(s, addr - s->region[1]);
1549 }
1550
1551 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1552 {
1553 EEPRO100State *s = opaque;
1554 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1555 eepro100_write1(s, addr - s->region[1], val);
1556 }
1557
1558 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1559 {
1560 EEPRO100State *s = opaque;
1561 eepro100_write2(s, addr - s->region[1], val);
1562 }
1563
1564 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1565 {
1566 EEPRO100State *s = opaque;
1567 eepro100_write4(s, addr - s->region[1], val);
1568 }
1569
1570 /***********************************************************/
1571 /* PCI EEPRO100 definitions */
1572
1573 static void pci_map(PCIDevice * pci_dev, int region_num,
1574 pcibus_t addr, pcibus_t size, int type)
1575 {
1576 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1577
1578 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1579 "size=0x%08"FMT_PCIBUS", type=%d\n",
1580 region_num, addr, size, type));
1581
1582 assert(region_num == 1);
1583 register_ioport_write(addr, size, 1, ioport_write1, s);
1584 register_ioport_read(addr, size, 1, ioport_read1, s);
1585 register_ioport_write(addr, size, 2, ioport_write2, s);
1586 register_ioport_read(addr, size, 2, ioport_read2, s);
1587 register_ioport_write(addr, size, 4, ioport_write4, s);
1588 register_ioport_read(addr, size, 4, ioport_read4, s);
1589
1590 s->region[region_num] = addr;
1591 }
1592
1593 /*****************************************************************************
1594 *
1595 * Memory mapped I/O.
1596 *
1597 ****************************************************************************/
1598
1599 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1600 {
1601 EEPRO100State *s = opaque;
1602 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1603 eepro100_write1(s, addr, val);
1604 }
1605
1606 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1607 {
1608 EEPRO100State *s = opaque;
1609 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1610 eepro100_write2(s, addr, val);
1611 }
1612
1613 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1614 {
1615 EEPRO100State *s = opaque;
1616 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1617 eepro100_write4(s, addr, val);
1618 }
1619
1620 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1621 {
1622 EEPRO100State *s = opaque;
1623 //~ logout("addr=%s\n", regname(addr));
1624 return eepro100_read1(s, addr);
1625 }
1626
1627 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1628 {
1629 EEPRO100State *s = opaque;
1630 //~ logout("addr=%s\n", regname(addr));
1631 return eepro100_read2(s, addr);
1632 }
1633
1634 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1635 {
1636 EEPRO100State *s = opaque;
1637 //~ logout("addr=%s\n", regname(addr));
1638 return eepro100_read4(s, addr);
1639 }
1640
1641 static CPUWriteMemoryFunc * const pci_mmio_write[] = {
1642 pci_mmio_writeb,
1643 pci_mmio_writew,
1644 pci_mmio_writel
1645 };
1646
1647 static CPUReadMemoryFunc * const pci_mmio_read[] = {
1648 pci_mmio_readb,
1649 pci_mmio_readw,
1650 pci_mmio_readl
1651 };
1652
1653 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1654 pcibus_t addr, pcibus_t size, int type)
1655 {
1656 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1657
1658 TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
1659 "size=0x%08"FMT_PCIBUS", type=%d\n",
1660 region_num, addr, size, type));
1661
1662 if (region_num == 0) {
1663 /* Map control / status registers. */
1664 cpu_register_physical_memory(addr, size, s->mmio_index);
1665 s->region[region_num] = addr;
1666 }
1667 }
1668
1669 static int nic_can_receive(VLANClientState *nc)
1670 {
1671 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1672 TRACE(RXTX, logout("%p\n", s));
1673 return get_ru_state(s) == ru_ready;
1674 //~ return !eepro100_buffer_full(s);
1675 }
1676
1677 static ssize_t nic_receive(VLANClientState *nc, const uint8_t * buf, size_t size)
1678 {
1679 /* TODO:
1680 * - Magic packets should set bit 30 in power management driver register.
1681 * - Interesting packets should set bit 29 in power management driver register.
1682 */
1683 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1684 uint16_t rfd_status = 0xa000;
1685 static const uint8_t broadcast_macaddr[6] =
1686 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1687
1688 /* TODO: check multiple IA bit. */
1689 if (s->configuration[20] & BIT(6)) {
1690 missing("Multiple IA bit");
1691 return -1;
1692 }
1693
1694 if (s->configuration[8] & 0x80) {
1695 /* CSMA is disabled. */
1696 logout("%p received while CSMA is disabled\n", s);
1697 return -1;
1698 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1699 /* Short frame and configuration byte 7/0 (discard short receive) set:
1700 * Short frame is discarded */
1701 logout("%p received short frame (%zu byte)\n", s, size);
1702 s->statistics.rx_short_frame_errors++;
1703 //~ return -1;
1704 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1705 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1706 * Long frames are discarded. */
1707 logout("%p received long frame (%zu byte), ignored\n", s, size);
1708 return -1;
1709 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { // !!!
1710 /* Frame matches individual address. */
1711 /* TODO: check configuration byte 15/4 (ignore U/L). */
1712 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1713 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1714 /* Broadcast frame. */
1715 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1716 rfd_status |= 0x0002;
1717 } else if (buf[0] & 0x01) {
1718 /* Multicast frame. */
1719 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1720 if (s->configuration[21] & BIT(3)) {
1721 /* Multicast all bit is set, receive all multicast frames. */
1722 } else {
1723 unsigned mcast_idx = compute_mcast_idx(buf);
1724 assert(mcast_idx < 64);
1725 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1726 /* Multicast frame is allowed in hash table. */
1727 } else if (s->configuration[15] & BIT(0)) {
1728 /* Promiscuous: receive all. */
1729 rfd_status |= 0x0004;
1730 } else {
1731 TRACE(RXTX, logout("%p multicast ignored\n", s));
1732 return -1;
1733 }
1734 }
1735 /* TODO: Next not for promiscuous mode? */
1736 rfd_status |= 0x0002;
1737 } else if (s->configuration[15] & BIT(0)) {
1738 /* Promiscuous: receive all. */
1739 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1740 rfd_status |= 0x0004;
1741 } else {
1742 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1743 nic_dump(buf, size)));
1744 return size;
1745 }
1746
1747 if (get_ru_state(s) != ru_ready) {
1748 /* No resources available. */
1749 logout("no resources, state=%u\n", get_ru_state(s));
1750 s->statistics.rx_resource_errors++;
1751 //~ assert(!"no resources");
1752 return -1;
1753 }
1754 //~ !!!
1755 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1756 eepro100_rx_t rx;
1757 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1758 offsetof(eepro100_rx_t, packet));
1759 uint16_t rfd_command = le16_to_cpu(rx.command);
1760 uint16_t rfd_size = le16_to_cpu(rx.size);
1761
1762 if (size > rfd_size) {
1763 logout("Receive buffer (%" PRId16 " bytes) too small for data "
1764 "(%zu bytes); data truncated\n", rfd_size, size);
1765 size = rfd_size;
1766 }
1767 if (size < 64) {
1768 rfd_status |= 0x0080;
1769 }
1770 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1771 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1772 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1773 rfd_status);
1774 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1775 /* Early receive interrupt not supported. */
1776 //~ eepro100_er_interrupt(s);
1777 /* Receive CRC Transfer not supported. */
1778 if (s->configuration[18] & BIT(2)) {
1779 missing("Receive CRC Transfer");
1780 return -1;
1781 }
1782 /* TODO: check stripping enable bit. */
1783 //~ assert(!(s->configuration[17] & BIT(0)));
1784 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1785 offsetof(eepro100_rx_t, packet), buf, size);
1786 s->statistics.rx_good_frames++;
1787 eepro100_fr_interrupt(s);
1788 s->ru_offset = le32_to_cpu(rx.link);
1789 if (rfd_command & COMMAND_EL) {
1790 /* EL bit is set, so this was the last frame. */
1791 logout("receive: Running out of frames\n");
1792 set_ru_state(s, ru_suspended);
1793 }
1794 if (rfd_command & COMMAND_S) {
1795 /* S bit is set. */
1796 set_ru_state(s, ru_suspended);
1797 }
1798 return size;
1799 }
1800
1801 static const VMStateDescription vmstate_eepro100 = {
1802 .version_id = 3,
1803 .minimum_version_id = 2,
1804 .minimum_version_id_old = 2,
1805 .fields = (VMStateField []) {
1806 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1807 VMSTATE_UNUSED(32),
1808 VMSTATE_BUFFER(mult, EEPRO100State),
1809 VMSTATE_BUFFER(mem, EEPRO100State),
1810 /* Save all members of struct between scb_stat and mem. */
1811 VMSTATE_UINT8(scb_stat, EEPRO100State),
1812 VMSTATE_UINT8(int_stat, EEPRO100State),
1813 VMSTATE_UNUSED(3*4),
1814 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1815 VMSTATE_UNUSED(19*4),
1816 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1817 /* The eeprom should be saved and restored by its own routines. */
1818 VMSTATE_UINT32(device, EEPRO100State),
1819 /* TODO check device. */
1820 VMSTATE_UINT32(pointer, EEPRO100State),
1821 VMSTATE_UINT32(cu_base, EEPRO100State),
1822 VMSTATE_UINT32(cu_offset, EEPRO100State),
1823 VMSTATE_UINT32(ru_base, EEPRO100State),
1824 VMSTATE_UINT32(ru_offset, EEPRO100State),
1825 VMSTATE_UINT32(statsaddr, EEPRO100State),
1826 /* Save eepro100_stats_t statistics. */
1827 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1828 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1829 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1830 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1831 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1832 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1833 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1834 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1835 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1836 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1837 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1838 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1839 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1840 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1841 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1842 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1843 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1844 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1845 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1846 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1847 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1848 #if 0
1849 VMSTATE_UINT16(status, EEPRO100State),
1850 #endif
1851 /* Configuration bytes. */
1852 VMSTATE_BUFFER(configuration, EEPRO100State),
1853 VMSTATE_END_OF_LIST()
1854 }
1855 };
1856
1857 static void nic_cleanup(VLANClientState *nc)
1858 {
1859 EEPRO100State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1860
1861 s->nic = NULL;
1862 }
1863
1864 static int pci_nic_uninit(PCIDevice *pci_dev)
1865 {
1866 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1867
1868 cpu_unregister_io_memory(s->mmio_index);
1869 vmstate_unregister(s->vmstate, s);
1870 eeprom93xx_free(s->eeprom);
1871 qemu_del_vlan_client(&s->nic->nc);
1872 return 0;
1873 }
1874
1875 static NetClientInfo net_eepro100_info = {
1876 .type = NET_CLIENT_TYPE_NIC,
1877 .size = sizeof(NICState),
1878 .can_receive = nic_can_receive,
1879 .receive = nic_receive,
1880 .cleanup = nic_cleanup,
1881 };
1882
1883 static int nic_init(PCIDevice *pci_dev, uint32_t device)
1884 {
1885 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1886
1887 TRACE(OTHER, logout("\n"));
1888
1889 s->device = device;
1890
1891 pci_reset(s);
1892
1893 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1894 * i82559 and later support 64 or 256 word EEPROM. */
1895 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1896
1897 /* Handler for memory-mapped I/O */
1898 s->mmio_index =
1899 cpu_register_io_memory(pci_mmio_read, pci_mmio_write, s);
1900
1901 pci_register_bar(&s->dev, 0, PCI_MEM_SIZE,
1902 PCI_BASE_ADDRESS_SPACE_MEMORY |
1903 PCI_BASE_ADDRESS_MEM_PREFETCH, pci_mmio_map);
1904 pci_register_bar(&s->dev, 1, PCI_IO_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
1905 pci_map);
1906 pci_register_bar(&s->dev, 2, PCI_FLASH_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
1907 pci_mmio_map);
1908
1909 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1910 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1911 assert(s->region[1] == 0);
1912
1913 nic_reset(s);
1914
1915 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1916 pci_dev->qdev.info->name, pci_dev->qdev.id, s);
1917
1918 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1919 TRACE(OTHER, logout("%s\n", s->nic->nc.info_str));
1920
1921 qemu_register_reset(nic_reset, s);
1922
1923 s->vmstate = qemu_malloc(sizeof(vmstate_eepro100));
1924 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1925 s->vmstate->name = s->nic->nc.model;
1926 vmstate_register(-1, s->vmstate, s);
1927
1928 return 0;
1929 }
1930
1931 static int pci_i82550_init(PCIDevice *pci_dev)
1932 {
1933 return nic_init(pci_dev, i82550);
1934 }
1935
1936 static int pci_i82551_init(PCIDevice *pci_dev)
1937 {
1938 return nic_init(pci_dev, i82551);
1939 }
1940
1941 static int pci_i82557a_init(PCIDevice *pci_dev)
1942 {
1943 return nic_init(pci_dev, i82557A);
1944 }
1945
1946 static int pci_i82557b_init(PCIDevice *pci_dev)
1947 {
1948 return nic_init(pci_dev, i82557B);
1949 }
1950
1951 static int pci_i82557c_init(PCIDevice *pci_dev)
1952 {
1953 return nic_init(pci_dev, i82557C);
1954 }
1955
1956 static int pci_i82558a_init(PCIDevice *pci_dev)
1957 {
1958 return nic_init(pci_dev, i82558A);
1959 }
1960
1961 static int pci_i82558b_init(PCIDevice *pci_dev)
1962 {
1963 return nic_init(pci_dev, i82558B);
1964 }
1965
1966 static int pci_i82559a_init(PCIDevice *pci_dev)
1967 {
1968 return nic_init(pci_dev, i82559A);
1969 }
1970
1971 static int pci_i82559b_init(PCIDevice *pci_dev)
1972 {
1973 return nic_init(pci_dev, i82559B);
1974 }
1975
1976 static int pci_i82559c_init(PCIDevice *pci_dev)
1977 {
1978 return nic_init(pci_dev, i82559C);
1979 }
1980
1981 static int pci_i82559er_init(PCIDevice *pci_dev)
1982 {
1983 return nic_init(pci_dev, i82559ER);
1984 }
1985
1986 static int pci_i82562_init(PCIDevice *pci_dev)
1987 {
1988 return nic_init(pci_dev, i82562);
1989 }
1990
1991 static PCIDeviceInfo eepro100_info[] = {
1992 {
1993 .qdev.name = "i82550",
1994 .qdev.desc = "Intel i82550 Ethernet",
1995 .qdev.size = sizeof(EEPRO100State),
1996 .init = pci_i82550_init,
1997 .exit = pci_nic_uninit,
1998 .romfile = "gpxe-eepro100-80861209.rom",
1999 .qdev.props = (Property[]) {
2000 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2001 DEFINE_PROP_END_OF_LIST(),
2002 },
2003 },{
2004 .qdev.name = "i82551",
2005 .qdev.desc = "Intel i82551 Ethernet",
2006 .qdev.size = sizeof(EEPRO100State),
2007 .init = pci_i82551_init,
2008 .exit = pci_nic_uninit,
2009 .romfile = "gpxe-eepro100-80861209.rom",
2010 .qdev.props = (Property[]) {
2011 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2012 DEFINE_PROP_END_OF_LIST(),
2013 },
2014 },{
2015 .qdev.name = "i82557a",
2016 .qdev.desc = "Intel i82557A Ethernet",
2017 .qdev.size = sizeof(EEPRO100State),
2018 .init = pci_i82557a_init,
2019 .exit = pci_nic_uninit,
2020 .romfile = "gpxe-eepro100-80861229.rom",
2021 .qdev.props = (Property[]) {
2022 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2023 DEFINE_PROP_END_OF_LIST(),
2024 },
2025 },{
2026 .qdev.name = "i82557b",
2027 .qdev.desc = "Intel i82557B Ethernet",
2028 .qdev.size = sizeof(EEPRO100State),
2029 .init = pci_i82557b_init,
2030 .exit = pci_nic_uninit,
2031 .romfile = "gpxe-eepro100-80861229.rom",
2032 .qdev.props = (Property[]) {
2033 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2034 DEFINE_PROP_END_OF_LIST(),
2035 },
2036 },{
2037 .qdev.name = "i82557c",
2038 .qdev.desc = "Intel i82557C Ethernet",
2039 .qdev.size = sizeof(EEPRO100State),
2040 .init = pci_i82557c_init,
2041 .exit = pci_nic_uninit,
2042 .romfile = "gpxe-eepro100-80861229.rom",
2043 .qdev.props = (Property[]) {
2044 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2045 DEFINE_PROP_END_OF_LIST(),
2046 },
2047 },{
2048 .qdev.name = "i82558a",
2049 .qdev.desc = "Intel i82558A Ethernet",
2050 .qdev.size = sizeof(EEPRO100State),
2051 .init = pci_i82558a_init,
2052 .exit = pci_nic_uninit,
2053 .romfile = "gpxe-eepro100-80861229.rom",
2054 .qdev.props = (Property[]) {
2055 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2056 DEFINE_PROP_END_OF_LIST(),
2057 },
2058 },{
2059 .qdev.name = "i82558b",
2060 .qdev.desc = "Intel i82558B Ethernet",
2061 .qdev.size = sizeof(EEPRO100State),
2062 .init = pci_i82558b_init,
2063 .exit = pci_nic_uninit,
2064 .romfile = "gpxe-eepro100-80861229.rom",
2065 .qdev.props = (Property[]) {
2066 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2067 DEFINE_PROP_END_OF_LIST(),
2068 },
2069 },{
2070 .qdev.name = "i82559a",
2071 .qdev.desc = "Intel i82559A Ethernet",
2072 .qdev.size = sizeof(EEPRO100State),
2073 .init = pci_i82559a_init,
2074 .exit = pci_nic_uninit,
2075 .romfile = "gpxe-eepro100-80861229.rom",
2076 .qdev.props = (Property[]) {
2077 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2078 DEFINE_PROP_END_OF_LIST(),
2079 },
2080 },{
2081 .qdev.name = "i82559b",
2082 .qdev.desc = "Intel i82559B Ethernet",
2083 .qdev.size = sizeof(EEPRO100State),
2084 .init = pci_i82559b_init,
2085 .exit = pci_nic_uninit,
2086 .romfile = "gpxe-eepro100-80861229.rom",
2087 .qdev.props = (Property[]) {
2088 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2089 DEFINE_PROP_END_OF_LIST(),
2090 },
2091 },{
2092 .qdev.name = "i82559c",
2093 .qdev.desc = "Intel i82559C Ethernet",
2094 .qdev.size = sizeof(EEPRO100State),
2095 .init = pci_i82559c_init,
2096 .exit = pci_nic_uninit,
2097 .romfile = "gpxe-eepro100-80861229.rom",
2098 .qdev.props = (Property[]) {
2099 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2100 DEFINE_PROP_END_OF_LIST(),
2101 },
2102 },{
2103 .qdev.name = "i82559er",
2104 .qdev.desc = "Intel i82559ER Ethernet",
2105 .qdev.size = sizeof(EEPRO100State),
2106 .init = pci_i82559er_init,
2107 .exit = pci_nic_uninit,
2108 .romfile = "gpxe-eepro100-80861209.rom",
2109 .qdev.props = (Property[]) {
2110 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2111 DEFINE_PROP_END_OF_LIST(),
2112 },
2113 },{
2114 .qdev.name = "i82562",
2115 .qdev.desc = "Intel i82562 Ethernet",
2116 .qdev.size = sizeof(EEPRO100State),
2117 .init = pci_i82562_init,
2118 .exit = pci_nic_uninit,
2119 .romfile = "gpxe-eepro100-80861209.rom",
2120 .qdev.props = (Property[]) {
2121 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2122 DEFINE_PROP_END_OF_LIST(),
2123 },
2124 },{
2125 /* end of list */
2126 }
2127 };
2128
2129 static void eepro100_register_devices(void)
2130 {
2131 pci_qdev_register_many(eepro100_info);
2132 }
2133
2134 device_init(eepro100_register_devices)
QEmu