target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20
  21 #include "cpu.h"
  22 #include "sysemu/kvm.h"
  23 #include "exec/exec-all.h"
  24 #include "exec/cpu_ldst.h"
  25 #include "exec/log.h"
  26
  27 enum {
  28     TLBRET_XI = -6,
  29     TLBRET_RI = -5,
  30     TLBRET_DIRTY = -4,
  31     TLBRET_INVALID = -3,
  32     TLBRET_NOMATCH = -2,
  33     TLBRET_BADADDR = -1,
  34     TLBRET_MATCH = 0
  35 };
  36
  37 #if !defined(CONFIG_USER_ONLY)
  38
  39 /* no MMU emulation */
  40 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  41                         target_ulong address, int rw, int access_type)
  42 {
  43     *physical = address;
  44     *prot = PAGE_READ | PAGE_WRITE;
  45     return TLBRET_MATCH;
  46 }
  47
  48 /* fixed mapping MMU emulation */
  49 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  50                            target_ulong address, int rw, int access_type)
  51 {
  52     if (address <= (int32_t)0x7FFFFFFFUL) {
  53         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  54             *physical = address + 0x40000000UL;
  55         else
  56             *physical = address;
  57     } else if (address <= (int32_t)0xBFFFFFFFUL)
  58         *physical = address & 0x1FFFFFFF;
  59     else
  60         *physical = address;
  61
  62     *prot = PAGE_READ | PAGE_WRITE;
  63     return TLBRET_MATCH;
  64 }
  65
  66 /* MIPS32/MIPS64 R4000-style MMU emulation */
  67 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  68                      target_ulong address, int rw, int access_type)
  69 {
  70     uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
  71     int i;
  72
  73     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  74         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  75         /* 1k pages are not supported. */
  76         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  77         target_ulong tag = address & ~mask;
  78         target_ulong VPN = tlb->VPN & ~mask;
  79 #if defined(TARGET_MIPS64)
  80         tag &= env->SEGMask;
  81 #endif
  82
  83         /* Check ASID, virtual page number & size */
  84         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
  85             /* TLB match */
  86             int n = !!(address & mask & ~(mask >> 1));
  87             /* Check access rights */
  88             if (!(n ? tlb->V1 : tlb->V0)) {
  89                 return TLBRET_INVALID;
  90             }
  91             if (rw == MMU_INST_FETCH && (n ? tlb->XI1 : tlb->XI0)) {
  92                 return TLBRET_XI;
  93             }
  94             if (rw == MMU_DATA_LOAD && (n ? tlb->RI1 : tlb->RI0)) {
  95                 return TLBRET_RI;
  96             }
  97             if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
  98                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  99                 *prot = PAGE_READ;
 100                 if (n ? tlb->D1 : tlb->D0)
 101                     *prot |= PAGE_WRITE;
 102                 return TLBRET_MATCH;
 103             }
 104             return TLBRET_DIRTY;
 105         }
 106     }
 107     return TLBRET_NOMATCH;
 108 }
 109
 110 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 111                                 int *prot, target_ulong real_address,
 112                                 int rw, int access_type)
 113 {
 114     /* User mode can only access useg/xuseg */
 115     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 116     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 117     int kernel_mode = !user_mode && !supervisor_mode;
 118 #if defined(TARGET_MIPS64)
 119     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 120     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 121     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 122 #endif
 123     int ret = TLBRET_MATCH;
 124     /* effective address (modified for KVM T&E kernel segments) */
 125     target_ulong address = real_address;
 126
 127 #define USEG_LIMIT      0x7FFFFFFFUL
 128 #define KSEG0_BASE      0x80000000UL
 129 #define KSEG1_BASE      0xA0000000UL
 130 #define KSEG2_BASE      0xC0000000UL
 131 #define KSEG3_BASE      0xE0000000UL
 132
 133 #define KVM_KSEG0_BASE  0x40000000UL
 134 #define KVM_KSEG2_BASE  0x60000000UL
 135
 136     if (kvm_enabled()) {
 137         /* KVM T&E adds guest kernel segments in useg */
 138         if (real_address >= KVM_KSEG0_BASE) {
 139             if (real_address < KVM_KSEG2_BASE) {
 140                 /* kseg0 */
 141                 address += KSEG0_BASE - KVM_KSEG0_BASE;
 142             } else if (real_address <= USEG_LIMIT) {
 143                 /* kseg2/3 */
 144                 address += KSEG2_BASE - KVM_KSEG2_BASE;
 145             }
 146         }
 147     }
 148
 149     if (address <= USEG_LIMIT) {
 150         /* useg */
 151         if (env->CP0_Status & (1 << CP0St_ERL)) {
 152             *physical = address & 0xFFFFFFFF;
 153             *prot = PAGE_READ | PAGE_WRITE;
 154         } else {
 155             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 156         }
 157 #if defined(TARGET_MIPS64)
 158     } else if (address < 0x4000000000000000ULL) {
 159         /* xuseg */
 160         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 161             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 162         } else {
 163             ret = TLBRET_BADADDR;
 164         }
 165     } else if (address < 0x8000000000000000ULL) {
 166         /* xsseg */
 167         if ((supervisor_mode || kernel_mode) &&
 168             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 169             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 170         } else {
 171             ret = TLBRET_BADADDR;
 172         }
 173     } else if (address < 0xC000000000000000ULL) {
 174         /* xkphys */
 175         if (kernel_mode && KX &&
 176             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 177             *physical = address & env->PAMask;
 178             *prot = PAGE_READ | PAGE_WRITE;
 179         } else {
 180             ret = TLBRET_BADADDR;
 181         }
 182     } else if (address < 0xFFFFFFFF80000000ULL) {
 183         /* xkseg */
 184         if (kernel_mode && KX &&
 185             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 186             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 187         } else {
 188             ret = TLBRET_BADADDR;
 189         }
 190 #endif
 191     } else if (address < (int32_t)KSEG1_BASE) {
 192         /* kseg0 */
 193         if (kernel_mode) {
 194             *physical = address - (int32_t)KSEG0_BASE;
 195             *prot = PAGE_READ | PAGE_WRITE;
 196         } else {
 197             ret = TLBRET_BADADDR;
 198         }
 199     } else if (address < (int32_t)KSEG2_BASE) {
 200         /* kseg1 */
 201         if (kernel_mode) {
 202             *physical = address - (int32_t)KSEG1_BASE;
 203             *prot = PAGE_READ | PAGE_WRITE;
 204         } else {
 205             ret = TLBRET_BADADDR;
 206         }
 207     } else if (address < (int32_t)KSEG3_BASE) {
 208         /* sseg (kseg2) */
 209         if (supervisor_mode || kernel_mode) {
 210             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 211         } else {
 212             ret = TLBRET_BADADDR;
 213         }
 214     } else {
 215         /* kseg3 */
 216         /* XXX: debug segment is not emulated */
 217         if (kernel_mode) {
 218             ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
 219         } else {
 220             ret = TLBRET_BADADDR;
 221         }
 222     }
 223     return ret;
 224 }
 225
 226 void cpu_mips_tlb_flush(CPUMIPSState *env, int flush_global)
 227 {
 228     MIPSCPU *cpu = mips_env_get_cpu(env);
 229
 230     /* Flush qemu's TLB and discard all shadowed entries.  */
 231     tlb_flush(CPU(cpu), flush_global);
 232     env->tlb->tlb_in_use = env->tlb->nb_tlb;
 233 }
 234
 235 /* Called for updates to CP0_Status.  */
 236 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 237 {
 238     int32_t tcstatus, *tcst;
 239     uint32_t v = cpu->CP0_Status;
 240     uint32_t cu, mx, asid, ksu;
 241     uint32_t mask = ((1 << CP0TCSt_TCU3)
 242                        | (1 << CP0TCSt_TCU2)
 243                        | (1 << CP0TCSt_TCU1)
 244                        | (1 << CP0TCSt_TCU0)
 245                        | (1 << CP0TCSt_TMX)
 246                        | (3 << CP0TCSt_TKSU)
 247                        | (0xff << CP0TCSt_TASID));
 248
 249     cu = (v >> CP0St_CU0) & 0xf;
 250     mx = (v >> CP0St_MX) & 0x1;
 251     ksu = (v >> CP0St_KSU) & 0x3;
 252     asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
 253
 254     tcstatus = cu << CP0TCSt_TCU0;
 255     tcstatus |= mx << CP0TCSt_TMX;
 256     tcstatus |= ksu << CP0TCSt_TKSU;
 257     tcstatus |= asid;
 258
 259     if (tc == cpu->current_tc) {
 260         tcst = &cpu->active_tc.CP0_TCStatus;
 261     } else {
 262         tcst = &cpu->tcs[tc].CP0_TCStatus;
 263     }
 264
 265     *tcst &= ~mask;
 266     *tcst |= tcstatus;
 267     compute_hflags(cpu);
 268 }
 269
 270 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val)
 271 {
 272     uint32_t mask = env->CP0_Status_rw_bitmask;
 273     target_ulong old = env->CP0_Status;
 274
 275     if (env->insn_flags & ISA_MIPS32R6) {
 276         bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
 277 #if defined(TARGET_MIPS64)
 278         uint32_t ksux = (1 << CP0St_KX) & val;
 279         ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
 280         ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
 281         val = (val & ~(7 << CP0St_UX)) | ksux;
 282 #endif
 283         if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
 284             mask &= ~(3 << CP0St_KSU);
 285         }
 286         mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
 287     }
 288
 289     env->CP0_Status = (old & ~mask) | (val & mask);
 290 #if defined(TARGET_MIPS64)
 291     if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) {
 292         /* Access to at least one of the 64-bit segments has been disabled */
 293         cpu_mips_tlb_flush(env, 1);
 294     }
 295 #endif
 296     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
 297         sync_c0_status(env, env, env->current_tc);
 298     } else {
 299         compute_hflags(env);
 300     }
 301 }
 302
 303 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val)
 304 {
 305     uint32_t mask = 0x00C00300;
 306     uint32_t old = env->CP0_Cause;
 307     int i;
 308
 309     if (env->insn_flags & ISA_MIPS32R2) {
 310         mask |= 1 << CP0Ca_DC;
 311     }
 312     if (env->insn_flags & ISA_MIPS32R6) {
 313         mask &= ~((1 << CP0Ca_WP) & val);
 314     }
 315
 316     env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask);
 317
 318     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
 319         if (env->CP0_Cause & (1 << CP0Ca_DC)) {
 320             cpu_mips_stop_count(env);
 321         } else {
 322             cpu_mips_start_count(env);
 323         }
 324     }
 325
 326     /* Set/reset software interrupts */
 327     for (i = 0 ; i < 2 ; i++) {
 328         if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
 329             cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i)));
 330         }
 331     }
 332 }
 333 #endif
 334
 335 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 336                                 int rw, int tlb_error)
 337 {
 338     CPUState *cs = CPU(mips_env_get_cpu(env));
 339     int exception = 0, error_code = 0;
 340
 341     if (rw == MMU_INST_FETCH) {
 342         error_code |= EXCP_INST_NOTAVAIL;
 343     }
 344
 345     switch (tlb_error) {
 346     default:
 347     case TLBRET_BADADDR:
 348         /* Reference to kernel address from user mode or supervisor mode */
 349         /* Reference to supervisor address from user mode */
 350         if (rw == MMU_DATA_STORE) {
 351             exception = EXCP_AdES;
 352         } else {
 353             exception = EXCP_AdEL;
 354         }
 355         break;
 356     case TLBRET_NOMATCH:
 357         /* No TLB match for a mapped address */
 358         if (rw == MMU_DATA_STORE) {
 359             exception = EXCP_TLBS;
 360         } else {
 361             exception = EXCP_TLBL;
 362         }
 363         error_code |= EXCP_TLB_NOMATCH;
 364         break;
 365     case TLBRET_INVALID:
 366         /* TLB match with no valid bit */
 367         if (rw == MMU_DATA_STORE) {
 368             exception = EXCP_TLBS;
 369         } else {
 370             exception = EXCP_TLBL;
 371         }
 372         break;
 373     case TLBRET_DIRTY:
 374         /* TLB match but 'D' bit is cleared */
 375         exception = EXCP_LTLBL;
 376         break;
 377     case TLBRET_XI:
 378         /* Execute-Inhibit Exception */
 379         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 380             exception = EXCP_TLBXI;
 381         } else {
 382             exception = EXCP_TLBL;
 383         }
 384         break;
 385     case TLBRET_RI:
 386         /* Read-Inhibit Exception */
 387         if (env->CP0_PageGrain & (1 << CP0PG_IEC)) {
 388             exception = EXCP_TLBRI;
 389         } else {
 390             exception = EXCP_TLBL;
 391         }
 392         break;
 393     }
 394     /* Raise exception */
 395     env->CP0_BadVAddr = address;
 396     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 397                        ((address >> 9) & 0x007ffff0);
 398     env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
 399                        (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
 400                        (address & (TARGET_PAGE_MASK << 1));
 401 #if defined(TARGET_MIPS64)
 402     env->CP0_EntryHi &= env->SEGMask;
 403     env->CP0_XContext =
 404         /* PTEBase */   (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 405         /* R */         (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
 406         /* BadVPN2 */   (extract64(address, 13, env->SEGBITS - 13) << 4);
 407 #endif
 408     cs->exception_index = exception;
 409     env->error_code = error_code;
 410 }
 411
 412 #if !defined(CONFIG_USER_ONLY)
 413 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 414 {
 415     MIPSCPU *cpu = MIPS_CPU(cs);
 416     hwaddr phys_addr;
 417     int prot;
 418
 419     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 420                              ACCESS_INT) != 0) {
 421         return -1;
 422     }
 423     return phys_addr;
 424 }
 425 #endif
 426
 427 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 428                               int mmu_idx)
 429 {
 430     MIPSCPU *cpu = MIPS_CPU(cs);
 431     CPUMIPSState *env = &cpu->env;
 432 #if !defined(CONFIG_USER_ONLY)
 433     hwaddr physical;
 434     int prot;
 435     int access_type;
 436 #endif
 437     int ret = 0;
 438
 439 #if 0
 440     log_cpu_state(cs, 0);
 441 #endif
 442     qemu_log_mask(CPU_LOG_MMU,
 443               "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 444               __func__, env->active_tc.PC, address, rw, mmu_idx);
 445
 446     /* data access */
 447 #if !defined(CONFIG_USER_ONLY)
 448     /* XXX: put correct access by using cpu_restore_state()
 449        correctly */
 450     access_type = ACCESS_INT;
 451     ret = get_physical_address(env, &physical, &prot,
 452                                address, rw, access_type);
 453     qemu_log_mask(CPU_LOG_MMU,
 454              "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 455              " prot %d\n",
 456              __func__, address, ret, physical, prot);
 457     if (ret == TLBRET_MATCH) {
 458         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 459                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 460                      mmu_idx, TARGET_PAGE_SIZE);
 461         ret = 0;
 462     } else if (ret < 0)
 463 #endif
 464     {
 465         raise_mmu_exception(env, address, rw, ret);
 466         ret = 1;
 467     }
 468
 469     return ret;
 470 }
 471
 472 #if !defined(CONFIG_USER_ONLY)
 473 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 474 {
 475     hwaddr physical;
 476     int prot;
 477     int access_type;
 478     int ret = 0;
 479
 480     /* data access */
 481     access_type = ACCESS_INT;
 482     ret = get_physical_address(env, &physical, &prot,
 483                                address, rw, access_type);
 484     if (ret != TLBRET_MATCH) {
 485         raise_mmu_exception(env, address, rw, ret);
 486         return -1LL;
 487     } else {
 488         return physical;
 489     }
 490 }
 491
 492 static const char * const excp_names[EXCP_LAST + 1] = {
 493     [EXCP_RESET] = "reset",
 494     [EXCP_SRESET] = "soft reset",
 495     [EXCP_DSS] = "debug single step",
 496     [EXCP_DINT] = "debug interrupt",
 497     [EXCP_NMI] = "non-maskable interrupt",
 498     [EXCP_MCHECK] = "machine check",
 499     [EXCP_EXT_INTERRUPT] = "interrupt",
 500     [EXCP_DFWATCH] = "deferred watchpoint",
 501     [EXCP_DIB] = "debug instruction breakpoint",
 502     [EXCP_IWATCH] = "instruction fetch watchpoint",
 503     [EXCP_AdEL] = "address error load",
 504     [EXCP_AdES] = "address error store",
 505     [EXCP_TLBF] = "TLB refill",
 506     [EXCP_IBE] = "instruction bus error",
 507     [EXCP_DBp] = "debug breakpoint",
 508     [EXCP_SYSCALL] = "syscall",
 509     [EXCP_BREAK] = "break",
 510     [EXCP_CpU] = "coprocessor unusable",
 511     [EXCP_RI] = "reserved instruction",
 512     [EXCP_OVERFLOW] = "arithmetic overflow",
 513     [EXCP_TRAP] = "trap",
 514     [EXCP_FPE] = "floating point",
 515     [EXCP_DDBS] = "debug data break store",
 516     [EXCP_DWATCH] = "data watchpoint",
 517     [EXCP_LTLBL] = "TLB modify",
 518     [EXCP_TLBL] = "TLB load",
 519     [EXCP_TLBS] = "TLB store",
 520     [EXCP_DBE] = "data bus error",
 521     [EXCP_DDBL] = "debug data break load",
 522     [EXCP_THREAD] = "thread",
 523     [EXCP_MDMX] = "MDMX",
 524     [EXCP_C2E] = "precise coprocessor 2",
 525     [EXCP_CACHE] = "cache error",
 526     [EXCP_TLBXI] = "TLB execute-inhibit",
 527     [EXCP_TLBRI] = "TLB read-inhibit",
 528     [EXCP_MSADIS] = "MSA disabled",
 529     [EXCP_MSAFPE] = "MSA floating point",
 530 };
 531 #endif
 532
 533 target_ulong exception_resume_pc (CPUMIPSState *env)
 534 {
 535     target_ulong bad_pc;
 536     target_ulong isa_mode;
 537
 538     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 539     bad_pc = env->active_tc.PC | isa_mode;
 540     if (env->hflags & MIPS_HFLAG_BMASK) {
 541         /* If the exception was raised from a delay slot, come back to
 542            the jump.  */
 543         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 544     }
 545
 546     return bad_pc;
 547 }
 548
 549 #if !defined(CONFIG_USER_ONLY)
 550 static void set_hflags_for_handler (CPUMIPSState *env)
 551 {
 552     /* Exception handlers are entered in 32-bit mode.  */
 553     env->hflags &= ~(MIPS_HFLAG_M16);
 554     /* ...except that microMIPS lets you choose.  */
 555     if (env->insn_flags & ASE_MICROMIPS) {
 556         env->hflags |= (!!(env->CP0_Config3
 557                            & (1 << CP0C3_ISA_ON_EXC))
 558                         << MIPS_HFLAG_M16_SHIFT);
 559     }
 560 }
 561
 562 static inline void set_badinstr_registers(CPUMIPSState *env)
 563 {
 564     if (env->hflags & MIPS_HFLAG_M16) {
 565         /* TODO: add BadInstr support for microMIPS */
 566         return;
 567     }
 568     if (env->CP0_Config3 & (1 << CP0C3_BI)) {
 569         env->CP0_BadInstr = cpu_ldl_code(env, env->active_tc.PC);
 570     }
 571     if ((env->CP0_Config3 & (1 << CP0C3_BP)) &&
 572         (env->hflags & MIPS_HFLAG_BMASK)) {
 573         env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
 574     }
 575 }
 576 #endif
 577
 578 void mips_cpu_do_interrupt(CPUState *cs)
 579 {
 580 #if !defined(CONFIG_USER_ONLY)
 581     MIPSCPU *cpu = MIPS_CPU(cs);
 582     CPUMIPSState *env = &cpu->env;
 583     bool update_badinstr = 0;
 584     target_ulong offset;
 585     int cause = -1;
 586     const char *name;
 587
 588     if (qemu_loglevel_mask(CPU_LOG_INT)
 589         && cs->exception_index != EXCP_EXT_INTERRUPT) {
 590         if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
 591             name = "unknown";
 592         } else {
 593             name = excp_names[cs->exception_index];
 594         }
 595
 596         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx
 597                  " %s exception\n",
 598                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 599     }
 600     if (cs->exception_index == EXCP_EXT_INTERRUPT &&
 601         (env->hflags & MIPS_HFLAG_DM)) {
 602         cs->exception_index = EXCP_DINT;
 603     }
 604     offset = 0x180;
 605     switch (cs->exception_index) {
 606     case EXCP_DSS:
 607         env->CP0_Debug |= 1 << CP0DB_DSS;
 608         /* Debug single step cannot be raised inside a delay slot and
 609            resume will always occur on the next instruction
 610            (but we assume the pc has always been updated during
 611            code translation). */
 612         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 613         goto enter_debug_mode;
 614     case EXCP_DINT:
 615         env->CP0_Debug |= 1 << CP0DB_DINT;
 616         goto set_DEPC;
 617     case EXCP_DIB:
 618         env->CP0_Debug |= 1 << CP0DB_DIB;
 619         goto set_DEPC;
 620     case EXCP_DBp:
 621         env->CP0_Debug |= 1 << CP0DB_DBp;
 622         goto set_DEPC;
 623     case EXCP_DDBS:
 624         env->CP0_Debug |= 1 << CP0DB_DDBS;
 625         goto set_DEPC;
 626     case EXCP_DDBL:
 627         env->CP0_Debug |= 1 << CP0DB_DDBL;
 628     set_DEPC:
 629         env->CP0_DEPC = exception_resume_pc(env);
 630         env->hflags &= ~MIPS_HFLAG_BMASK;
 631  enter_debug_mode:
 632         if (env->insn_flags & ISA_MIPS3) {
 633             env->hflags |= MIPS_HFLAG_64;
 634             if (!(env->insn_flags & ISA_MIPS64R6) ||
 635                 env->CP0_Status & (1 << CP0St_KX)) {
 636                 env->hflags &= ~MIPS_HFLAG_AWRAP;
 637             }
 638         }
 639         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
 640         env->hflags &= ~(MIPS_HFLAG_KSU);
 641         /* EJTAG probe trap enable is not implemented... */
 642         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 643             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 644         env->active_tc.PC = env->exception_base + 0x480;
 645         set_hflags_for_handler(env);
 646         break;
 647     case EXCP_RESET:
 648         cpu_reset(CPU(cpu));
 649         break;
 650     case EXCP_SRESET:
 651         env->CP0_Status |= (1 << CP0St_SR);
 652         memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
 653         goto set_error_EPC;
 654     case EXCP_NMI:
 655         env->CP0_Status |= (1 << CP0St_NMI);
 656  set_error_EPC:
 657         env->CP0_ErrorEPC = exception_resume_pc(env);
 658         env->hflags &= ~MIPS_HFLAG_BMASK;
 659         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 660         if (env->insn_flags & ISA_MIPS3) {
 661             env->hflags |= MIPS_HFLAG_64;
 662             if (!(env->insn_flags & ISA_MIPS64R6) ||
 663                 env->CP0_Status & (1 << CP0St_KX)) {
 664                 env->hflags &= ~MIPS_HFLAG_AWRAP;
 665             }
 666         }
 667         env->hflags |= MIPS_HFLAG_CP0;
 668         env->hflags &= ~(MIPS_HFLAG_KSU);
 669         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 670             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 671         env->active_tc.PC = env->exception_base;
 672         set_hflags_for_handler(env);
 673         break;
 674     case EXCP_EXT_INTERRUPT:
 675         cause = 0;
 676         if (env->CP0_Cause & (1 << CP0Ca_IV)) {
 677             uint32_t spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & 0x1f;
 678
 679             if ((env->CP0_Status & (1 << CP0St_BEV)) || spacing == 0) {
 680                 offset = 0x200;
 681             } else {
 682                 uint32_t vector = 0;
 683                 uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
 684
 685                 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
 686                     /* For VEIC mode, the external interrupt controller feeds
 687                      * the vector through the CP0Cause IP lines.  */
 688                     vector = pending;
 689                 } else {
 690                     /* Vectored Interrupts
 691                      * Mask with Status.IM7-IM0 to get enabled interrupts. */
 692                     pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
 693                     /* Find the highest-priority interrupt. */
 694                     while (pending >>= 1) {
 695                         vector++;
 696                     }
 697                 }
 698                 offset = 0x200 + (vector * (spacing << 5));
 699             }
 700         }
 701         goto set_EPC;
 702     case EXCP_LTLBL:
 703         cause = 1;
 704         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 705         goto set_EPC;
 706     case EXCP_TLBL:
 707         cause = 2;
 708         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 709         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 710             !(env->CP0_Status & (1 << CP0St_EXL))) {
 711 #if defined(TARGET_MIPS64)
 712             int R = env->CP0_BadVAddr >> 62;
 713             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 714             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 715             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 716
 717             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 718                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 719                 offset = 0x080;
 720             else
 721 #endif
 722                 offset = 0x000;
 723         }
 724         goto set_EPC;
 725     case EXCP_TLBS:
 726         cause = 3;
 727         update_badinstr = 1;
 728         if ((env->error_code & EXCP_TLB_NOMATCH) &&
 729             !(env->CP0_Status & (1 << CP0St_EXL))) {
 730 #if defined(TARGET_MIPS64)
 731             int R = env->CP0_BadVAddr >> 62;
 732             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 733             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 734             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 735
 736             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 737                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 738                 offset = 0x080;
 739             else
 740 #endif
 741                 offset = 0x000;
 742         }
 743         goto set_EPC;
 744     case EXCP_AdEL:
 745         cause = 4;
 746         update_badinstr = !(env->error_code & EXCP_INST_NOTAVAIL);
 747         goto set_EPC;
 748     case EXCP_AdES:
 749         cause = 5;
 750         update_badinstr = 1;
 751         goto set_EPC;
 752     case EXCP_IBE:
 753         cause = 6;
 754         goto set_EPC;
 755     case EXCP_DBE:
 756         cause = 7;
 757         goto set_EPC;
 758     case EXCP_SYSCALL:
 759         cause = 8;
 760         update_badinstr = 1;
 761         goto set_EPC;
 762     case EXCP_BREAK:
 763         cause = 9;
 764         update_badinstr = 1;
 765         goto set_EPC;
 766     case EXCP_RI:
 767         cause = 10;
 768         update_badinstr = 1;
 769         goto set_EPC;
 770     case EXCP_CpU:
 771         cause = 11;
 772         update_badinstr = 1;
 773         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 774                          (env->error_code << CP0Ca_CE);
 775         goto set_EPC;
 776     case EXCP_OVERFLOW:
 777         cause = 12;
 778         update_badinstr = 1;
 779         goto set_EPC;
 780     case EXCP_TRAP:
 781         cause = 13;
 782         update_badinstr = 1;
 783         goto set_EPC;
 784     case EXCP_MSAFPE:
 785         cause = 14;
 786         update_badinstr = 1;
 787         goto set_EPC;
 788     case EXCP_FPE:
 789         cause = 15;
 790         update_badinstr = 1;
 791         goto set_EPC;
 792     case EXCP_C2E:
 793         cause = 18;
 794         goto set_EPC;
 795     case EXCP_TLBRI:
 796         cause = 19;
 797         update_badinstr = 1;
 798         goto set_EPC;
 799     case EXCP_TLBXI:
 800         cause = 20;
 801         goto set_EPC;
 802     case EXCP_MSADIS:
 803         cause = 21;
 804         update_badinstr = 1;
 805         goto set_EPC;
 806     case EXCP_MDMX:
 807         cause = 22;
 808         goto set_EPC;
 809     case EXCP_DWATCH:
 810         cause = 23;
 811         /* XXX: TODO: manage deferred watch exceptions */
 812         goto set_EPC;
 813     case EXCP_MCHECK:
 814         cause = 24;
 815         goto set_EPC;
 816     case EXCP_THREAD:
 817         cause = 25;
 818         goto set_EPC;
 819     case EXCP_DSPDIS:
 820         cause = 26;
 821         goto set_EPC;
 822     case EXCP_CACHE:
 823         cause = 30;
 824         if (env->CP0_Status & (1 << CP0St_BEV)) {
 825             offset = 0x100;
 826         } else {
 827             offset = 0x20000100;
 828         }
 829  set_EPC:
 830         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 831             env->CP0_EPC = exception_resume_pc(env);
 832             if (update_badinstr) {
 833                 set_badinstr_registers(env);
 834             }
 835             if (env->hflags & MIPS_HFLAG_BMASK) {
 836                 env->CP0_Cause |= (1U << CP0Ca_BD);
 837             } else {
 838                 env->CP0_Cause &= ~(1U << CP0Ca_BD);
 839             }
 840             env->CP0_Status |= (1 << CP0St_EXL);
 841             if (env->insn_flags & ISA_MIPS3) {
 842                 env->hflags |= MIPS_HFLAG_64;
 843                 if (!(env->insn_flags & ISA_MIPS64R6) ||
 844                     env->CP0_Status & (1 << CP0St_KX)) {
 845                     env->hflags &= ~MIPS_HFLAG_AWRAP;
 846                 }
 847             }
 848             env->hflags |= MIPS_HFLAG_CP0;
 849             env->hflags &= ~(MIPS_HFLAG_KSU);
 850         }
 851         env->hflags &= ~MIPS_HFLAG_BMASK;
 852         if (env->CP0_Status & (1 << CP0St_BEV)) {
 853             env->active_tc.PC = env->exception_base + 0x200;
 854         } else {
 855             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 856         }
 857         env->active_tc.PC += offset;
 858         set_hflags_for_handler(env);
 859         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 860         break;
 861     default:
 862         abort();
 863     }
 864     if (qemu_loglevel_mask(CPU_LOG_INT)
 865         && cs->exception_index != EXCP_EXT_INTERRUPT) {
 866         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 867                  "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 868                  __func__, env->active_tc.PC, env->CP0_EPC, cause,
 869                  env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 870                  env->CP0_DEPC);
 871     }
 872 #endif
 873     cs->exception_index = EXCP_NONE;
 874 }
 875
 876 bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 877 {
 878     if (interrupt_request & CPU_INTERRUPT_HARD) {
 879         MIPSCPU *cpu = MIPS_CPU(cs);
 880         CPUMIPSState *env = &cpu->env;
 881
 882         if (cpu_mips_hw_interrupts_enabled(env) &&
 883             cpu_mips_hw_interrupts_pending(env)) {
 884             /* Raise it */
 885             cs->exception_index = EXCP_EXT_INTERRUPT;
 886             env->error_code = 0;
 887             mips_cpu_do_interrupt(cs);
 888             return true;
 889         }
 890     }
 891     return false;
 892 }
 893
 894 #if !defined(CONFIG_USER_ONLY)
 895 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 896 {
 897     MIPSCPU *cpu = mips_env_get_cpu(env);
 898     CPUState *cs;
 899     r4k_tlb_t *tlb;
 900     target_ulong addr;
 901     target_ulong end;
 902     uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
 903     target_ulong mask;
 904
 905     tlb = &env->tlb->mmu.r4k.tlb[idx];
 906     /* The qemu TLB is flushed when the ASID changes, so no need to
 907        flush these entries again.  */
 908     if (tlb->G == 0 && tlb->ASID != ASID) {
 909         return;
 910     }
 911
 912     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 913         /* For tlbwr, we can shadow the discarded entry into
 914            a new (fake) TLB entry, as long as the guest can not
 915            tell that it's there.  */
 916         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 917         env->tlb->tlb_in_use++;
 918         return;
 919     }
 920
 921     /* 1k pages are not supported. */
 922     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 923     if (tlb->V0) {
 924         cs = CPU(cpu);
 925         addr = tlb->VPN & ~mask;
 926 #if defined(TARGET_MIPS64)
 927         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 928             addr |= 0x3FFFFF0000000000ULL;
 929         }
 930 #endif
 931         end = addr | (mask >> 1);
 932         while (addr < end) {
 933             tlb_flush_page(cs, addr);
 934             addr += TARGET_PAGE_SIZE;
 935         }
 936     }
 937     if (tlb->V1) {
 938         cs = CPU(cpu);
 939         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 940 #if defined(TARGET_MIPS64)
 941         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 942             addr |= 0x3FFFFF0000000000ULL;
 943         }
 944 #endif
 945         end = addr | mask;
 946         while (addr - 1 < end) {
 947             tlb_flush_page(cs, addr);
 948             addr += TARGET_PAGE_SIZE;
 949         }
 950     }
 951 }
 952 #endif
 953
 954 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
 955                                           uint32_t exception,
 956                                           int error_code,
 957                                           uintptr_t pc)
 958 {
 959     CPUState *cs = CPU(mips_env_get_cpu(env));
 960
 961     if (exception < EXCP_SC) {
 962         qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n",
 963                       __func__, exception, error_code);
 964     }
 965     cs->exception_index = exception;
 966     env->error_code = error_code;
 967
 968     cpu_loop_exit_restore(cs, pc);
 969 }