tcg/tci/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2009, 2011 Stefan Weil
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "tcg-be-null.h"
  26
  27 /* TODO list:
  28  * - See TODO comments in code.
  29  */
  30
  31 /* Marker for missing code. */
  32 #define TODO() \
  33     do { \
  34         fprintf(stderr, "TODO %s:%u: %s()\n", \
  35                 __FILE__, __LINE__, __func__); \
  36         tcg_abort(); \
  37     } while (0)
  38
  39 /* Bitfield n...m (in 32 bit value). */
  40 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
  41
  42 /* Macros used in tcg_target_op_defs. */
  43 #define R       "r"
  44 #define RI      "ri"
  45 #if TCG_TARGET_REG_BITS == 32
  46 # define R64    "r", "r"
  47 #else
  48 # define R64    "r"
  49 #endif
  50 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  51 # define L      "L", "L"
  52 # define S      "S", "S"
  53 #else
  54 # define L      "L"
  55 # define S      "S"
  56 #endif
  57
  58 /* TODO: documentation. */
  59 static const TCGTargetOpDef tcg_target_op_defs[] = {
  60     { INDEX_op_exit_tb, { NULL } },
  61     { INDEX_op_goto_tb, { NULL } },
  62     { INDEX_op_br, { NULL } },
  63
  64     { INDEX_op_ld8u_i32, { R, R } },
  65     { INDEX_op_ld8s_i32, { R, R } },
  66     { INDEX_op_ld16u_i32, { R, R } },
  67     { INDEX_op_ld16s_i32, { R, R } },
  68     { INDEX_op_ld_i32, { R, R } },
  69     { INDEX_op_st8_i32, { R, R } },
  70     { INDEX_op_st16_i32, { R, R } },
  71     { INDEX_op_st_i32, { R, R } },
  72
  73     { INDEX_op_add_i32, { R, RI, RI } },
  74     { INDEX_op_sub_i32, { R, RI, RI } },
  75     { INDEX_op_mul_i32, { R, RI, RI } },
  76 #if TCG_TARGET_HAS_div_i32
  77     { INDEX_op_div_i32, { R, R, R } },
  78     { INDEX_op_divu_i32, { R, R, R } },
  79     { INDEX_op_rem_i32, { R, R, R } },
  80     { INDEX_op_remu_i32, { R, R, R } },
  81 #elif TCG_TARGET_HAS_div2_i32
  82     { INDEX_op_div2_i32, { R, R, "0", "1", R } },
  83     { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
  84 #endif
  85     /* TODO: Does R, RI, RI result in faster code than R, R, RI?
  86        If both operands are constants, we can optimize. */
  87     { INDEX_op_and_i32, { R, RI, RI } },
  88 #if TCG_TARGET_HAS_andc_i32
  89     { INDEX_op_andc_i32, { R, RI, RI } },
  90 #endif
  91 #if TCG_TARGET_HAS_eqv_i32
  92     { INDEX_op_eqv_i32, { R, RI, RI } },
  93 #endif
  94 #if TCG_TARGET_HAS_nand_i32
  95     { INDEX_op_nand_i32, { R, RI, RI } },
  96 #endif
  97 #if TCG_TARGET_HAS_nor_i32
  98     { INDEX_op_nor_i32, { R, RI, RI } },
  99 #endif
 100     { INDEX_op_or_i32, { R, RI, RI } },
 101 #if TCG_TARGET_HAS_orc_i32
 102     { INDEX_op_orc_i32, { R, RI, RI } },
 103 #endif
 104     { INDEX_op_xor_i32, { R, RI, RI } },
 105     { INDEX_op_shl_i32, { R, RI, RI } },
 106     { INDEX_op_shr_i32, { R, RI, RI } },
 107     { INDEX_op_sar_i32, { R, RI, RI } },
 108 #if TCG_TARGET_HAS_rot_i32
 109     { INDEX_op_rotl_i32, { R, RI, RI } },
 110     { INDEX_op_rotr_i32, { R, RI, RI } },
 111 #endif
 112 #if TCG_TARGET_HAS_deposit_i32
 113     { INDEX_op_deposit_i32, { R, "0", R } },
 114 #endif
 115
 116     { INDEX_op_brcond_i32, { R, RI } },
 117
 118     { INDEX_op_setcond_i32, { R, R, RI } },
 119 #if TCG_TARGET_REG_BITS == 64
 120     { INDEX_op_setcond_i64, { R, R, RI } },
 121 #endif /* TCG_TARGET_REG_BITS == 64 */
 122
 123 #if TCG_TARGET_REG_BITS == 32
 124     /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
 125     { INDEX_op_add2_i32, { R, R, R, R, R, R } },
 126     { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
 127     { INDEX_op_brcond2_i32, { R, R, RI, RI } },
 128     { INDEX_op_mulu2_i32, { R, R, R, R } },
 129     { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
 130 #endif
 131
 132 #if TCG_TARGET_HAS_not_i32
 133     { INDEX_op_not_i32, { R, R } },
 134 #endif
 135 #if TCG_TARGET_HAS_neg_i32
 136     { INDEX_op_neg_i32, { R, R } },
 137 #endif
 138
 139 #if TCG_TARGET_REG_BITS == 64
 140     { INDEX_op_ld8u_i64, { R, R } },
 141     { INDEX_op_ld8s_i64, { R, R } },
 142     { INDEX_op_ld16u_i64, { R, R } },
 143     { INDEX_op_ld16s_i64, { R, R } },
 144     { INDEX_op_ld32u_i64, { R, R } },
 145     { INDEX_op_ld32s_i64, { R, R } },
 146     { INDEX_op_ld_i64, { R, R } },
 147
 148     { INDEX_op_st8_i64, { R, R } },
 149     { INDEX_op_st16_i64, { R, R } },
 150     { INDEX_op_st32_i64, { R, R } },
 151     { INDEX_op_st_i64, { R, R } },
 152
 153     { INDEX_op_add_i64, { R, RI, RI } },
 154     { INDEX_op_sub_i64, { R, RI, RI } },
 155     { INDEX_op_mul_i64, { R, RI, RI } },
 156 #if TCG_TARGET_HAS_div_i64
 157     { INDEX_op_div_i64, { R, R, R } },
 158     { INDEX_op_divu_i64, { R, R, R } },
 159     { INDEX_op_rem_i64, { R, R, R } },
 160     { INDEX_op_remu_i64, { R, R, R } },
 161 #elif TCG_TARGET_HAS_div2_i64
 162     { INDEX_op_div2_i64, { R, R, "0", "1", R } },
 163     { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
 164 #endif
 165     { INDEX_op_and_i64, { R, RI, RI } },
 166 #if TCG_TARGET_HAS_andc_i64
 167     { INDEX_op_andc_i64, { R, RI, RI } },
 168 #endif
 169 #if TCG_TARGET_HAS_eqv_i64
 170     { INDEX_op_eqv_i64, { R, RI, RI } },
 171 #endif
 172 #if TCG_TARGET_HAS_nand_i64
 173     { INDEX_op_nand_i64, { R, RI, RI } },
 174 #endif
 175 #if TCG_TARGET_HAS_nor_i64
 176     { INDEX_op_nor_i64, { R, RI, RI } },
 177 #endif
 178     { INDEX_op_or_i64, { R, RI, RI } },
 179 #if TCG_TARGET_HAS_orc_i64
 180     { INDEX_op_orc_i64, { R, RI, RI } },
 181 #endif
 182     { INDEX_op_xor_i64, { R, RI, RI } },
 183     { INDEX_op_shl_i64, { R, RI, RI } },
 184     { INDEX_op_shr_i64, { R, RI, RI } },
 185     { INDEX_op_sar_i64, { R, RI, RI } },
 186 #if TCG_TARGET_HAS_rot_i64
 187     { INDEX_op_rotl_i64, { R, RI, RI } },
 188     { INDEX_op_rotr_i64, { R, RI, RI } },
 189 #endif
 190 #if TCG_TARGET_HAS_deposit_i64
 191     { INDEX_op_deposit_i64, { R, "0", R } },
 192 #endif
 193     { INDEX_op_brcond_i64, { R, RI } },
 194
 195 #if TCG_TARGET_HAS_ext8s_i64
 196     { INDEX_op_ext8s_i64, { R, R } },
 197 #endif
 198 #if TCG_TARGET_HAS_ext16s_i64
 199     { INDEX_op_ext16s_i64, { R, R } },
 200 #endif
 201 #if TCG_TARGET_HAS_ext32s_i64
 202     { INDEX_op_ext32s_i64, { R, R } },
 203 #endif
 204 #if TCG_TARGET_HAS_ext8u_i64
 205     { INDEX_op_ext8u_i64, { R, R } },
 206 #endif
 207 #if TCG_TARGET_HAS_ext16u_i64
 208     { INDEX_op_ext16u_i64, { R, R } },
 209 #endif
 210 #if TCG_TARGET_HAS_ext32u_i64
 211     { INDEX_op_ext32u_i64, { R, R } },
 212 #endif
 213 #if TCG_TARGET_HAS_bswap16_i64
 214     { INDEX_op_bswap16_i64, { R, R } },
 215 #endif
 216 #if TCG_TARGET_HAS_bswap32_i64
 217     { INDEX_op_bswap32_i64, { R, R } },
 218 #endif
 219 #if TCG_TARGET_HAS_bswap64_i64
 220     { INDEX_op_bswap64_i64, { R, R } },
 221 #endif
 222 #if TCG_TARGET_HAS_not_i64
 223     { INDEX_op_not_i64, { R, R } },
 224 #endif
 225 #if TCG_TARGET_HAS_neg_i64
 226     { INDEX_op_neg_i64, { R, R } },
 227 #endif
 228 #endif /* TCG_TARGET_REG_BITS == 64 */
 229
 230     { INDEX_op_qemu_ld_i32, { R, L } },
 231     { INDEX_op_qemu_ld_i64, { R64, L } },
 232
 233     { INDEX_op_qemu_st_i32, { R, S } },
 234     { INDEX_op_qemu_st_i64, { R64, S } },
 235
 236 #if TCG_TARGET_HAS_ext8s_i32
 237     { INDEX_op_ext8s_i32, { R, R } },
 238 #endif
 239 #if TCG_TARGET_HAS_ext16s_i32
 240     { INDEX_op_ext16s_i32, { R, R } },
 241 #endif
 242 #if TCG_TARGET_HAS_ext8u_i32
 243     { INDEX_op_ext8u_i32, { R, R } },
 244 #endif
 245 #if TCG_TARGET_HAS_ext16u_i32
 246     { INDEX_op_ext16u_i32, { R, R } },
 247 #endif
 248
 249 #if TCG_TARGET_HAS_bswap16_i32
 250     { INDEX_op_bswap16_i32, { R, R } },
 251 #endif
 252 #if TCG_TARGET_HAS_bswap32_i32
 253     { INDEX_op_bswap32_i32, { R, R } },
 254 #endif
 255
 256     { -1 },
 257 };
 258
 259 static const int tcg_target_reg_alloc_order[] = {
 260     TCG_REG_R0,
 261     TCG_REG_R1,
 262     TCG_REG_R2,
 263     TCG_REG_R3,
 264 #if 0 /* used for TCG_REG_CALL_STACK */
 265     TCG_REG_R4,
 266 #endif
 267     TCG_REG_R5,
 268     TCG_REG_R6,
 269     TCG_REG_R7,
 270 #if TCG_TARGET_NB_REGS >= 16
 271     TCG_REG_R8,
 272     TCG_REG_R9,
 273     TCG_REG_R10,
 274     TCG_REG_R11,
 275     TCG_REG_R12,
 276     TCG_REG_R13,
 277     TCG_REG_R14,
 278     TCG_REG_R15,
 279 #endif
 280 };
 281
 282 #if MAX_OPC_PARAM_IARGS != 5
 283 # error Fix needed, number of supported input arguments changed!
 284 #endif
 285
 286 static const int tcg_target_call_iarg_regs[] = {
 287     TCG_REG_R0,
 288     TCG_REG_R1,
 289     TCG_REG_R2,
 290     TCG_REG_R3,
 291 #if 0 /* used for TCG_REG_CALL_STACK */
 292     TCG_REG_R4,
 293 #endif
 294     TCG_REG_R5,
 295 #if TCG_TARGET_REG_BITS == 32
 296     /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
 297     TCG_REG_R6,
 298     TCG_REG_R7,
 299 #if TCG_TARGET_NB_REGS >= 16
 300     TCG_REG_R8,
 301     TCG_REG_R9,
 302     TCG_REG_R10,
 303 #else
 304 # error Too few input registers available
 305 #endif
 306 #endif
 307 };
 308
 309 static const int tcg_target_call_oarg_regs[] = {
 310     TCG_REG_R0,
 311 #if TCG_TARGET_REG_BITS == 32
 312     TCG_REG_R1
 313 #endif
 314 };
 315
 316 #ifndef NDEBUG
 317 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 318     "r00",
 319     "r01",
 320     "r02",
 321     "r03",
 322     "r04",
 323     "r05",
 324     "r06",
 325     "r07",
 326 #if TCG_TARGET_NB_REGS >= 16
 327     "r08",
 328     "r09",
 329     "r10",
 330     "r11",
 331     "r12",
 332     "r13",
 333     "r14",
 334     "r15",
 335 #if TCG_TARGET_NB_REGS >= 32
 336     "r16",
 337     "r17",
 338     "r18",
 339     "r19",
 340     "r20",
 341     "r21",
 342     "r22",
 343     "r23",
 344     "r24",
 345     "r25",
 346     "r26",
 347     "r27",
 348     "r28",
 349     "r29",
 350     "r30",
 351     "r31"
 352 #endif
 353 #endif
 354 };
 355 #endif
 356
 357 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
 358                         intptr_t value, intptr_t addend)
 359 {
 360     /* tcg_out_reloc always uses the same type, addend. */
 361     assert(type == sizeof(tcg_target_long));
 362     assert(addend == 0);
 363     assert(value != 0);
 364     if (TCG_TARGET_REG_BITS == 32) {
 365         tcg_patch32(code_ptr, value);
 366     } else {
 367         tcg_patch64(code_ptr, value);
 368     }
 369 }
 370
 371 /* Parse target specific constraints. */
 372 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 373 {
 374     const char *ct_str = *pct_str;
 375     switch (ct_str[0]) {
 376     case 'r':
 377     case 'L':                   /* qemu_ld constraint */
 378     case 'S':                   /* qemu_st constraint */
 379         ct->ct |= TCG_CT_REG;
 380         tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1);
 381         break;
 382     default:
 383         return -1;
 384     }
 385     ct_str++;
 386     *pct_str = ct_str;
 387     return 0;
 388 }
 389
 390 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 391 /* Show current bytecode. Used by tcg interpreter. */
 392 void tci_disas(uint8_t opc)
 393 {
 394     const TCGOpDef *def = &tcg_op_defs[opc];
 395     fprintf(stderr, "TCG %s %u, %u, %u\n",
 396             def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs);
 397 }
 398 #endif
 399
 400 /* Write value (native size). */
 401 static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
 402 {
 403     if (TCG_TARGET_REG_BITS == 32) {
 404         tcg_out32(s, v);
 405     } else {
 406         tcg_out64(s, v);
 407     }
 408 }
 409
 410 /* Write opcode. */
 411 static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
 412 {
 413     tcg_out8(s, op);
 414     tcg_out8(s, 0);
 415 }
 416
 417 /* Write register. */
 418 static void tcg_out_r(TCGContext *s, TCGArg t0)
 419 {
 420     assert(t0 < TCG_TARGET_NB_REGS);
 421     tcg_out8(s, t0);
 422 }
 423
 424 /* Write register or constant (native size). */
 425 static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
 426 {
 427     if (const_arg) {
 428         assert(const_arg == 1);
 429         tcg_out8(s, TCG_CONST);
 430         tcg_out_i(s, arg);
 431     } else {
 432         tcg_out_r(s, arg);
 433     }
 434 }
 435
 436 /* Write register or constant (32 bit). */
 437 static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
 438 {
 439     if (const_arg) {
 440         assert(const_arg == 1);
 441         tcg_out8(s, TCG_CONST);
 442         tcg_out32(s, arg);
 443     } else {
 444         tcg_out_r(s, arg);
 445     }
 446 }
 447
 448 #if TCG_TARGET_REG_BITS == 64
 449 /* Write register or constant (64 bit). */
 450 static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
 451 {
 452     if (const_arg) {
 453         assert(const_arg == 1);
 454         tcg_out8(s, TCG_CONST);
 455         tcg_out64(s, arg);
 456     } else {
 457         tcg_out_r(s, arg);
 458     }
 459 }
 460 #endif
 461
 462 /* Write label. */
 463 static void tci_out_label(TCGContext *s, TCGArg arg)
 464 {
 465     TCGLabel *label = &s->labels[arg];
 466     if (label->has_value) {
 467         tcg_out_i(s, label->u.value);
 468         assert(label->u.value);
 469     } else {
 470         tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), arg, 0);
 471         s->code_ptr += sizeof(tcg_target_ulong);
 472     }
 473 }
 474
 475 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
 476                        intptr_t arg2)
 477 {
 478     uint8_t *old_code_ptr = s->code_ptr;
 479     if (type == TCG_TYPE_I32) {
 480         tcg_out_op_t(s, INDEX_op_ld_i32);
 481         tcg_out_r(s, ret);
 482         tcg_out_r(s, arg1);
 483         tcg_out32(s, arg2);
 484     } else {
 485         assert(type == TCG_TYPE_I64);
 486 #if TCG_TARGET_REG_BITS == 64
 487         tcg_out_op_t(s, INDEX_op_ld_i64);
 488         tcg_out_r(s, ret);
 489         tcg_out_r(s, arg1);
 490         assert(arg2 == (int32_t)arg2);
 491         tcg_out32(s, arg2);
 492 #else
 493         TODO();
 494 #endif
 495     }
 496     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 497 }
 498
 499 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
 500 {
 501     uint8_t *old_code_ptr = s->code_ptr;
 502     assert(ret != arg);
 503 #if TCG_TARGET_REG_BITS == 32
 504     tcg_out_op_t(s, INDEX_op_mov_i32);
 505 #else
 506     tcg_out_op_t(s, INDEX_op_mov_i64);
 507 #endif
 508     tcg_out_r(s, ret);
 509     tcg_out_r(s, arg);
 510     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 511 }
 512
 513 static void tcg_out_movi(TCGContext *s, TCGType type,
 514                          TCGReg t0, tcg_target_long arg)
 515 {
 516     uint8_t *old_code_ptr = s->code_ptr;
 517     uint32_t arg32 = arg;
 518     if (type == TCG_TYPE_I32 || arg == arg32) {
 519         tcg_out_op_t(s, INDEX_op_movi_i32);
 520         tcg_out_r(s, t0);
 521         tcg_out32(s, arg32);
 522     } else {
 523         assert(type == TCG_TYPE_I64);
 524 #if TCG_TARGET_REG_BITS == 64
 525         tcg_out_op_t(s, INDEX_op_movi_i64);
 526         tcg_out_r(s, t0);
 527         tcg_out64(s, arg);
 528 #else
 529         TODO();
 530 #endif
 531     }
 532     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 533 }
 534
 535 static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
 536 {
 537     uint8_t *old_code_ptr = s->code_ptr;
 538     tcg_out_op_t(s, INDEX_op_call);
 539     tcg_out_ri(s, 1, (uintptr_t)arg);
 540     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 541 }
 542
 543 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
 544                        const int *const_args)
 545 {
 546     uint8_t *old_code_ptr = s->code_ptr;
 547
 548     tcg_out_op_t(s, opc);
 549
 550     switch (opc) {
 551     case INDEX_op_exit_tb:
 552         tcg_out64(s, args[0]);
 553         break;
 554     case INDEX_op_goto_tb:
 555         if (s->tb_jmp_offset) {
 556             /* Direct jump method. */
 557             assert(args[0] < ARRAY_SIZE(s->tb_jmp_offset));
 558             s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
 559             tcg_out32(s, 0);
 560         } else {
 561             /* Indirect jump method. */
 562             TODO();
 563         }
 564         assert(args[0] < ARRAY_SIZE(s->tb_next_offset));
 565         s->tb_next_offset[args[0]] = tcg_current_code_size(s);
 566         break;
 567     case INDEX_op_br:
 568         tci_out_label(s, args[0]);
 569         break;
 570     case INDEX_op_setcond_i32:
 571         tcg_out_r(s, args[0]);
 572         tcg_out_r(s, args[1]);
 573         tcg_out_ri32(s, const_args[2], args[2]);
 574         tcg_out8(s, args[3]);   /* condition */
 575         break;
 576 #if TCG_TARGET_REG_BITS == 32
 577     case INDEX_op_setcond2_i32:
 578         /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
 579         tcg_out_r(s, args[0]);
 580         tcg_out_r(s, args[1]);
 581         tcg_out_r(s, args[2]);
 582         tcg_out_ri32(s, const_args[3], args[3]);
 583         tcg_out_ri32(s, const_args[4], args[4]);
 584         tcg_out8(s, args[5]);   /* condition */
 585         break;
 586 #elif TCG_TARGET_REG_BITS == 64
 587     case INDEX_op_setcond_i64:
 588         tcg_out_r(s, args[0]);
 589         tcg_out_r(s, args[1]);
 590         tcg_out_ri64(s, const_args[2], args[2]);
 591         tcg_out8(s, args[3]);   /* condition */
 592         break;
 593 #endif
 594     case INDEX_op_ld8u_i32:
 595     case INDEX_op_ld8s_i32:
 596     case INDEX_op_ld16u_i32:
 597     case INDEX_op_ld16s_i32:
 598     case INDEX_op_ld_i32:
 599     case INDEX_op_st8_i32:
 600     case INDEX_op_st16_i32:
 601     case INDEX_op_st_i32:
 602     case INDEX_op_ld8u_i64:
 603     case INDEX_op_ld8s_i64:
 604     case INDEX_op_ld16u_i64:
 605     case INDEX_op_ld16s_i64:
 606     case INDEX_op_ld32u_i64:
 607     case INDEX_op_ld32s_i64:
 608     case INDEX_op_ld_i64:
 609     case INDEX_op_st8_i64:
 610     case INDEX_op_st16_i64:
 611     case INDEX_op_st32_i64:
 612     case INDEX_op_st_i64:
 613         tcg_out_r(s, args[0]);
 614         tcg_out_r(s, args[1]);
 615         assert(args[2] == (int32_t)args[2]);
 616         tcg_out32(s, args[2]);
 617         break;
 618     case INDEX_op_add_i32:
 619     case INDEX_op_sub_i32:
 620     case INDEX_op_mul_i32:
 621     case INDEX_op_and_i32:
 622     case INDEX_op_andc_i32:     /* Optional (TCG_TARGET_HAS_andc_i32). */
 623     case INDEX_op_eqv_i32:      /* Optional (TCG_TARGET_HAS_eqv_i32). */
 624     case INDEX_op_nand_i32:     /* Optional (TCG_TARGET_HAS_nand_i32). */
 625     case INDEX_op_nor_i32:      /* Optional (TCG_TARGET_HAS_nor_i32). */
 626     case INDEX_op_or_i32:
 627     case INDEX_op_orc_i32:      /* Optional (TCG_TARGET_HAS_orc_i32). */
 628     case INDEX_op_xor_i32:
 629     case INDEX_op_shl_i32:
 630     case INDEX_op_shr_i32:
 631     case INDEX_op_sar_i32:
 632     case INDEX_op_rotl_i32:     /* Optional (TCG_TARGET_HAS_rot_i32). */
 633     case INDEX_op_rotr_i32:     /* Optional (TCG_TARGET_HAS_rot_i32). */
 634         tcg_out_r(s, args[0]);
 635         tcg_out_ri32(s, const_args[1], args[1]);
 636         tcg_out_ri32(s, const_args[2], args[2]);
 637         break;
 638     case INDEX_op_deposit_i32:  /* Optional (TCG_TARGET_HAS_deposit_i32). */
 639         tcg_out_r(s, args[0]);
 640         tcg_out_r(s, args[1]);
 641         tcg_out_r(s, args[2]);
 642         assert(args[3] <= UINT8_MAX);
 643         tcg_out8(s, args[3]);
 644         assert(args[4] <= UINT8_MAX);
 645         tcg_out8(s, args[4]);
 646         break;
 647
 648 #if TCG_TARGET_REG_BITS == 64
 649     case INDEX_op_add_i64:
 650     case INDEX_op_sub_i64:
 651     case INDEX_op_mul_i64:
 652     case INDEX_op_and_i64:
 653     case INDEX_op_andc_i64:     /* Optional (TCG_TARGET_HAS_andc_i64). */
 654     case INDEX_op_eqv_i64:      /* Optional (TCG_TARGET_HAS_eqv_i64). */
 655     case INDEX_op_nand_i64:     /* Optional (TCG_TARGET_HAS_nand_i64). */
 656     case INDEX_op_nor_i64:      /* Optional (TCG_TARGET_HAS_nor_i64). */
 657     case INDEX_op_or_i64:
 658     case INDEX_op_orc_i64:      /* Optional (TCG_TARGET_HAS_orc_i64). */
 659     case INDEX_op_xor_i64:
 660     case INDEX_op_shl_i64:
 661     case INDEX_op_shr_i64:
 662     case INDEX_op_sar_i64:
 663     case INDEX_op_rotl_i64:     /* Optional (TCG_TARGET_HAS_rot_i64). */
 664     case INDEX_op_rotr_i64:     /* Optional (TCG_TARGET_HAS_rot_i64). */
 665         tcg_out_r(s, args[0]);
 666         tcg_out_ri64(s, const_args[1], args[1]);
 667         tcg_out_ri64(s, const_args[2], args[2]);
 668         break;
 669     case INDEX_op_deposit_i64:  /* Optional (TCG_TARGET_HAS_deposit_i64). */
 670         tcg_out_r(s, args[0]);
 671         tcg_out_r(s, args[1]);
 672         tcg_out_r(s, args[2]);
 673         assert(args[3] <= UINT8_MAX);
 674         tcg_out8(s, args[3]);
 675         assert(args[4] <= UINT8_MAX);
 676         tcg_out8(s, args[4]);
 677         break;
 678     case INDEX_op_div_i64:      /* Optional (TCG_TARGET_HAS_div_i64). */
 679     case INDEX_op_divu_i64:     /* Optional (TCG_TARGET_HAS_div_i64). */
 680     case INDEX_op_rem_i64:      /* Optional (TCG_TARGET_HAS_div_i64). */
 681     case INDEX_op_remu_i64:     /* Optional (TCG_TARGET_HAS_div_i64). */
 682         TODO();
 683         break;
 684     case INDEX_op_div2_i64:     /* Optional (TCG_TARGET_HAS_div2_i64). */
 685     case INDEX_op_divu2_i64:    /* Optional (TCG_TARGET_HAS_div2_i64). */
 686         TODO();
 687         break;
 688     case INDEX_op_brcond_i64:
 689         tcg_out_r(s, args[0]);
 690         tcg_out_ri64(s, const_args[1], args[1]);
 691         tcg_out8(s, args[2]);           /* condition */
 692         tci_out_label(s, args[3]);
 693         break;
 694     case INDEX_op_bswap16_i64:  /* Optional (TCG_TARGET_HAS_bswap16_i64). */
 695     case INDEX_op_bswap32_i64:  /* Optional (TCG_TARGET_HAS_bswap32_i64). */
 696     case INDEX_op_bswap64_i64:  /* Optional (TCG_TARGET_HAS_bswap64_i64). */
 697     case INDEX_op_not_i64:      /* Optional (TCG_TARGET_HAS_not_i64). */
 698     case INDEX_op_neg_i64:      /* Optional (TCG_TARGET_HAS_neg_i64). */
 699     case INDEX_op_ext8s_i64:    /* Optional (TCG_TARGET_HAS_ext8s_i64). */
 700     case INDEX_op_ext8u_i64:    /* Optional (TCG_TARGET_HAS_ext8u_i64). */
 701     case INDEX_op_ext16s_i64:   /* Optional (TCG_TARGET_HAS_ext16s_i64). */
 702     case INDEX_op_ext16u_i64:   /* Optional (TCG_TARGET_HAS_ext16u_i64). */
 703     case INDEX_op_ext32s_i64:   /* Optional (TCG_TARGET_HAS_ext32s_i64). */
 704     case INDEX_op_ext32u_i64:   /* Optional (TCG_TARGET_HAS_ext32u_i64). */
 705 #endif /* TCG_TARGET_REG_BITS == 64 */
 706     case INDEX_op_neg_i32:      /* Optional (TCG_TARGET_HAS_neg_i32). */
 707     case INDEX_op_not_i32:      /* Optional (TCG_TARGET_HAS_not_i32). */
 708     case INDEX_op_ext8s_i32:    /* Optional (TCG_TARGET_HAS_ext8s_i32). */
 709     case INDEX_op_ext16s_i32:   /* Optional (TCG_TARGET_HAS_ext16s_i32). */
 710     case INDEX_op_ext8u_i32:    /* Optional (TCG_TARGET_HAS_ext8u_i32). */
 711     case INDEX_op_ext16u_i32:   /* Optional (TCG_TARGET_HAS_ext16u_i32). */
 712     case INDEX_op_bswap16_i32:  /* Optional (TCG_TARGET_HAS_bswap16_i32). */
 713     case INDEX_op_bswap32_i32:  /* Optional (TCG_TARGET_HAS_bswap32_i32). */
 714         tcg_out_r(s, args[0]);
 715         tcg_out_r(s, args[1]);
 716         break;
 717     case INDEX_op_div_i32:      /* Optional (TCG_TARGET_HAS_div_i32). */
 718     case INDEX_op_divu_i32:     /* Optional (TCG_TARGET_HAS_div_i32). */
 719     case INDEX_op_rem_i32:      /* Optional (TCG_TARGET_HAS_div_i32). */
 720     case INDEX_op_remu_i32:     /* Optional (TCG_TARGET_HAS_div_i32). */
 721         tcg_out_r(s, args[0]);
 722         tcg_out_ri32(s, const_args[1], args[1]);
 723         tcg_out_ri32(s, const_args[2], args[2]);
 724         break;
 725     case INDEX_op_div2_i32:     /* Optional (TCG_TARGET_HAS_div2_i32). */
 726     case INDEX_op_divu2_i32:    /* Optional (TCG_TARGET_HAS_div2_i32). */
 727         TODO();
 728         break;
 729 #if TCG_TARGET_REG_BITS == 32
 730     case INDEX_op_add2_i32:
 731     case INDEX_op_sub2_i32:
 732         tcg_out_r(s, args[0]);
 733         tcg_out_r(s, args[1]);
 734         tcg_out_r(s, args[2]);
 735         tcg_out_r(s, args[3]);
 736         tcg_out_r(s, args[4]);
 737         tcg_out_r(s, args[5]);
 738         break;
 739     case INDEX_op_brcond2_i32:
 740         tcg_out_r(s, args[0]);
 741         tcg_out_r(s, args[1]);
 742         tcg_out_ri32(s, const_args[2], args[2]);
 743         tcg_out_ri32(s, const_args[3], args[3]);
 744         tcg_out8(s, args[4]);           /* condition */
 745         tci_out_label(s, args[5]);
 746         break;
 747     case INDEX_op_mulu2_i32:
 748         tcg_out_r(s, args[0]);
 749         tcg_out_r(s, args[1]);
 750         tcg_out_r(s, args[2]);
 751         tcg_out_r(s, args[3]);
 752         break;
 753 #endif
 754     case INDEX_op_brcond_i32:
 755         tcg_out_r(s, args[0]);
 756         tcg_out_ri32(s, const_args[1], args[1]);
 757         tcg_out8(s, args[2]);           /* condition */
 758         tci_out_label(s, args[3]);
 759         break;
 760     case INDEX_op_qemu_ld_i32:
 761         tcg_out_r(s, *args++);
 762         tcg_out_r(s, *args++);
 763         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 764             tcg_out_r(s, *args++);
 765         }
 766         tcg_out_i(s, *args++);
 767 #ifdef CONFIG_SOFTMMU
 768         tcg_out_i(s, *args);
 769 #endif
 770         break;
 771     case INDEX_op_qemu_ld_i64:
 772         tcg_out_r(s, *args++);
 773         if (TCG_TARGET_REG_BITS == 32) {
 774             tcg_out_r(s, *args++);
 775         }
 776         tcg_out_r(s, *args++);
 777         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 778             tcg_out_r(s, *args++);
 779         }
 780         tcg_out_i(s, *args++);
 781 #ifdef CONFIG_SOFTMMU
 782         tcg_out_i(s, *args);
 783 #endif
 784         break;
 785     case INDEX_op_qemu_st_i32:
 786         tcg_out_r(s, *args++);
 787         tcg_out_r(s, *args++);
 788         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 789             tcg_out_r(s, *args++);
 790         }
 791         tcg_out_i(s, *args++);
 792 #ifdef CONFIG_SOFTMMU
 793         tcg_out_i(s, *args);
 794 #endif
 795         break;
 796     case INDEX_op_qemu_st_i64:
 797         tcg_out_r(s, *args++);
 798         if (TCG_TARGET_REG_BITS == 32) {
 799             tcg_out_r(s, *args++);
 800         }
 801         tcg_out_r(s, *args++);
 802         if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
 803             tcg_out_r(s, *args++);
 804         }
 805         tcg_out_i(s, *args++);
 806 #ifdef CONFIG_SOFTMMU
 807         tcg_out_i(s, *args);
 808 #endif
 809         break;
 810     case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
 811     case INDEX_op_mov_i64:
 812     case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi.  */
 813     case INDEX_op_movi_i64:
 814     case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
 815     default:
 816         tcg_abort();
 817     }
 818     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 819 }
 820
 821 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
 822                        intptr_t arg2)
 823 {
 824     uint8_t *old_code_ptr = s->code_ptr;
 825     if (type == TCG_TYPE_I32) {
 826         tcg_out_op_t(s, INDEX_op_st_i32);
 827         tcg_out_r(s, arg);
 828         tcg_out_r(s, arg1);
 829         tcg_out32(s, arg2);
 830     } else {
 831         assert(type == TCG_TYPE_I64);
 832 #if TCG_TARGET_REG_BITS == 64
 833         tcg_out_op_t(s, INDEX_op_st_i64);
 834         tcg_out_r(s, arg);
 835         tcg_out_r(s, arg1);
 836         tcg_out32(s, arg2);
 837 #else
 838         TODO();
 839 #endif
 840     }
 841     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 842 }
 843
 844 /* Test if a constant matches the constraint. */
 845 static int tcg_target_const_match(tcg_target_long val, TCGType type,
 846                                   const TCGArgConstraint *arg_ct)
 847 {
 848     /* No need to return 0 or 1, 0 or != 0 is good enough. */
 849     return arg_ct->ct & TCG_CT_CONST;
 850 }
 851
 852 static void tcg_target_init(TCGContext *s)
 853 {
 854 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
 855     const char *envval = getenv("DEBUG_TCG");
 856     if (envval) {
 857         qemu_set_log(strtol(envval, NULL, 0));
 858     }
 859 #endif
 860
 861     /* The current code uses uint8_t for tcg operations. */
 862     assert(ARRAY_SIZE(tcg_op_defs) <= UINT8_MAX);
 863
 864     /* Registers available for 32 bit operations. */
 865     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
 866                      BIT(TCG_TARGET_NB_REGS) - 1);
 867     /* Registers available for 64 bit operations. */
 868     tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,
 869                      BIT(TCG_TARGET_NB_REGS) - 1);
 870     /* TODO: Which registers should be set here? */
 871     tcg_regset_set32(tcg_target_call_clobber_regs, 0,
 872                      BIT(TCG_TARGET_NB_REGS) - 1);
 873
 874     tcg_regset_clear(s->reserved_regs);
 875     tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
 876     tcg_add_target_add_op_defs(tcg_target_op_defs);
 877
 878     /* We use negative offsets from "sp" so that we can distinguish
 879        stores that might pretend to be call arguments.  */
 880     tcg_set_frame(s, TCG_REG_CALL_STACK,
 881                   -CPU_TEMP_BUF_NLONGS * sizeof(long),
 882                   CPU_TEMP_BUF_NLONGS * sizeof(long));
 883 }
 884
 885 /* Generate global QEMU prologue and epilogue code. */
 886 static inline void tcg_target_qemu_prologue(TCGContext *s)
 887 {
 888 }