target-m68k/cpu.h

   1 /*
   2  * m68k virtual CPU header
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery
   5  *  Written by Paul Brook
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #ifndef CPU_M68K_H
  21 #define CPU_M68K_H
  22
  23 #define TARGET_LONG_BITS 32
  24
  25 #define CPUArchState struct CPUM68KState
  26
  27 #include "qemu-common.h"
  28 #include "exec/cpu-defs.h"
  29 #include "cpu-qom.h"
  30 #include "fpu/softfloat.h"
  31
  32 #define MAX_QREGS 32
  33
  34 #define EXCP_ACCESS         2   /* Access (MMU) error.  */
  35 #define EXCP_ADDRESS        3   /* Address error.  */
  36 #define EXCP_ILLEGAL        4   /* Illegal instruction.  */
  37 #define EXCP_DIV0           5   /* Divide by zero */
  38 #define EXCP_PRIVILEGE      8   /* Privilege violation.  */
  39 #define EXCP_TRACE          9
  40 #define EXCP_LINEA          10  /* Unimplemented line-A (MAC) opcode.  */
  41 #define EXCP_LINEF          11  /* Unimplemented line-F (FPU) opcode.  */
  42 #define EXCP_DEBUGNBP       12  /* Non-breakpoint debug interrupt.  */
  43 #define EXCP_DEBEGBP        13  /* Breakpoint debug interrupt.  */
  44 #define EXCP_FORMAT         14  /* RTE format error.  */
  45 #define EXCP_UNINITIALIZED  15
  46 #define EXCP_TRAP0          32   /* User trap #0.  */
  47 #define EXCP_TRAP15         47   /* User trap #15.  */
  48 #define EXCP_UNSUPPORTED    61
  49 #define EXCP_ICE            13
  50
  51 #define EXCP_RTE            0x100
  52 #define EXCP_HALT_INSN      0x101
  53
  54 #define NB_MMU_MODES 2
  55
  56 typedef struct CPUM68KState {
  57     uint32_t dregs[8];
  58     uint32_t aregs[8];
  59     uint32_t pc;
  60     uint32_t sr;
  61
  62     /* SSP and USP.  The current_sp is stored in aregs[7], the other here.  */
  63     int current_sp;
  64     uint32_t sp[2];
  65
  66     /* Condition flags.  */
  67     uint32_t cc_op;
  68     uint32_t cc_dest;
  69     uint32_t cc_src;
  70     uint32_t cc_x;
  71
  72     float64 fregs[8];
  73     float64 fp_result;
  74     uint32_t fpcr;
  75     uint32_t fpsr;
  76     float_status fp_status;
  77
  78     uint64_t mactmp;
  79     /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
  80        two 8-bit parts.  We store a single 64-bit value and
  81        rearrange/extend this when changing modes.  */
  82     uint64_t macc[4];
  83     uint32_t macsr;
  84     uint32_t mac_mask;
  85
  86     /* Temporary storage for DIV helpers.  */
  87     uint32_t div1;
  88     uint32_t div2;
  89
  90     /* MMU status.  */
  91     struct {
  92         uint32_t ar;
  93     } mmu;
  94
  95     /* Control registers.  */
  96     uint32_t vbr;
  97     uint32_t mbar;
  98     uint32_t rambar0;
  99     uint32_t cacr;
 100
 101     int pending_vector;
 102     int pending_level;
 103
 104     uint32_t qregs[MAX_QREGS];
 105
 106     CPU_COMMON
 107
 108     /* Fields from here on are preserved across CPU reset. */
 109     uint32_t features;
 110 } CPUM68KState;
 111
 112 /**
 113  * M68kCPU:
 114  * @env: #CPUM68KState
 115  *
 116  * A Motorola 68k CPU.
 117  */
 118 struct M68kCPU {
 119     /*< private >*/
 120     CPUState parent_obj;
 121     /*< public >*/
 122
 123     CPUM68KState env;
 124 };
 125
 126 static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env)
 127 {
 128     return container_of(env, M68kCPU, env);
 129 }
 130
 131 #define ENV_GET_CPU(e) CPU(m68k_env_get_cpu(e))
 132
 133 #define ENV_OFFSET offsetof(M68kCPU, env)
 134
 135 void m68k_cpu_do_interrupt(CPUState *cpu);
 136 bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
 137 void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 138                          int flags);
 139 hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 140 int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 141 int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 142
 143 void m68k_cpu_exec_enter(CPUState *cs);
 144 void m68k_cpu_exec_exit(CPUState *cs);
 145
 146 void m68k_tcg_init(void);
 147 void m68k_cpu_init_gdb(M68kCPU *cpu);
 148 M68kCPU *cpu_m68k_init(const char *cpu_model);
 149 /* you can call this signal handler from your SIGBUS and SIGSEGV
 150    signal handlers to inform the virtual CPU of exceptions. non zero
 151    is returned if the signal was handled by the virtual CPU.  */
 152 int cpu_m68k_signal_handler(int host_signum, void *pinfo,
 153                            void *puc);
 154 void cpu_m68k_flush_flags(CPUM68KState *, int);
 155
 156 enum {
 157     CC_OP_DYNAMIC, /* Use env->cc_op  */
 158     CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
 159     CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
 160     CC_OP_ADD,   /* CC_DEST = result, CC_SRC = source */
 161     CC_OP_SUB,   /* CC_DEST = result, CC_SRC = source */
 162     CC_OP_CMPB,  /* CC_DEST = result, CC_SRC = source */
 163     CC_OP_CMPW,  /* CC_DEST = result, CC_SRC = source */
 164     CC_OP_ADDX,  /* CC_DEST = result, CC_SRC = source */
 165     CC_OP_SUBX,  /* CC_DEST = result, CC_SRC = source */
 166     CC_OP_SHIFT, /* CC_DEST = result, CC_SRC = carry */
 167 };
 168
 169 #define CCF_C 0x01
 170 #define CCF_V 0x02
 171 #define CCF_Z 0x04
 172 #define CCF_N 0x08
 173 #define CCF_X 0x10
 174
 175 #define SR_I_SHIFT 8
 176 #define SR_I  0x0700
 177 #define SR_M  0x1000
 178 #define SR_S  0x2000
 179 #define SR_T  0x8000
 180
 181 #define M68K_SSP    0
 182 #define M68K_USP    1
 183
 184 /* CACR fields are implementation defined, but some bits are common.  */
 185 #define M68K_CACR_EUSP  0x10
 186
 187 #define MACSR_PAV0  0x100
 188 #define MACSR_OMC   0x080
 189 #define MACSR_SU    0x040
 190 #define MACSR_FI    0x020
 191 #define MACSR_RT    0x010
 192 #define MACSR_N     0x008
 193 #define MACSR_Z     0x004
 194 #define MACSR_V     0x002
 195 #define MACSR_EV    0x001
 196
 197 void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector);
 198 void m68k_set_macsr(CPUM68KState *env, uint32_t val);
 199 void m68k_switch_sp(CPUM68KState *env);
 200
 201 #define M68K_FPCR_PREC (1 << 6)
 202
 203 void do_m68k_semihosting(CPUM68KState *env, int nr);
 204
 205 /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
 206    Each feature covers the subset of instructions common to the
 207    ISA revisions mentioned.  */
 208
 209 enum m68k_features {
 210     M68K_FEATURE_CF_ISA_A,
 211     M68K_FEATURE_CF_ISA_B, /* (ISA B or C).  */
 212     M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C).  */
 213     M68K_FEATURE_BRAL, /* Long unconditional branch.  (ISA A+ or B).  */
 214     M68K_FEATURE_CF_FPU,
 215     M68K_FEATURE_CF_MAC,
 216     M68K_FEATURE_CF_EMAC,
 217     M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate).  */
 218     M68K_FEATURE_USP, /* User Stack Pointer.  (ISA A+, B or C).  */
 219     M68K_FEATURE_EXT_FULL, /* 68020+ full extension word.  */
 220     M68K_FEATURE_WORD_INDEX /* word sized address index registers.  */
 221 };
 222
 223 static inline int m68k_feature(CPUM68KState *env, int feature)
 224 {
 225     return (env->features & (1u << feature)) != 0;
 226 }
 227
 228 void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 229
 230 void register_m68k_insns (CPUM68KState *env);
 231
 232 #ifdef CONFIG_USER_ONLY
 233 /* Linux uses 8k pages.  */
 234 #define TARGET_PAGE_BITS 13
 235 #else
 236 /* Smallest TLB entry size is 1k.  */
 237 #define TARGET_PAGE_BITS 10
 238 #endif
 239
 240 #define TARGET_PHYS_ADDR_SPACE_BITS 32
 241 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 242
 243 #define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
 244
 245 #define cpu_signal_handler cpu_m68k_signal_handler
 246 #define cpu_list m68k_cpu_list
 247
 248 /* MMU modes definitions */
 249 #define MMU_MODE0_SUFFIX _kernel
 250 #define MMU_MODE1_SUFFIX _user
 251 #define MMU_USER_IDX 1
 252 static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
 253 {
 254     return (env->sr & SR_S) == 0 ? 1 : 0;
 255 }
 256
 257 int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 258                               int mmu_idx);
 259
 260 #include "exec/cpu-all.h"
 261
 262 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
 263                                         target_ulong *cs_base, uint32_t *flags)
 264 {
 265     *pc = env->pc;
 266     *cs_base = 0;
 267     *flags = (env->fpcr & M68K_FPCR_PREC)       /* Bit  6 */
 268             | (env->sr & SR_S)                  /* Bit  13 */
 269             | ((env->macsr >> 4) & 0xf);        /* Bits 0-3 */
 270 }
 271
 272 #endif