hw/ne2000.c

   1 /*
   2  * QEMU NE2000 emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include <stdlib.h>
  25 #include <stdio.h>
  26 #include <stdarg.h>
  27 #include <string.h>
  28 #include <getopt.h>
  29 #include <inttypes.h>
  30 #include <unistd.h>
  31 #include <sys/mman.h>
  32 #include <fcntl.h>
  33 #include <signal.h>
  34 #include <time.h>
  35 #include <sys/time.h>
  36 #include <malloc.h>
  37 #include <termios.h>
  38 #include <sys/poll.h>
  39 #include <errno.h>
  40 #include <sys/wait.h>
  41 #include <netinet/in.h>
  42
  43 #include "cpu.h"
  44 #include "vl.h"
  45
  46 /* debug NE2000 card */
  47 //#define DEBUG_NE2000
  48
  49 #define MAX_ETH_FRAME_SIZE 1514
  50
  51 #define E8390_CMD       0x00  /* The command register (for all pages) */
  52 /* Page 0 register offsets. */
  53 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  54 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  55 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  56 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  57 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  58 #define EN0_TSR         0x04    /* Transmit status reg RD */
  59 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  60 #define EN0_NCR         0x05    /* Number of collision reg RD */
  61 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  62 #define EN0_FIFO        0x06    /* FIFO RD */
  63 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  64 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  65 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  66 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  67 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  68 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  69 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  70 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  71 #define EN0_RSR         0x0c    /* rx status reg RD */
  72 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  73 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  74 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  75 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  76 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
  77 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
  78 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
  79
  80 #define EN1_PHYS        0x11
  81 #define EN1_CURPAG      0x17
  82 #define EN1_MULT        0x18
  83
  84 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  85 #define E8390_STOP      0x01    /* Stop and reset the chip */
  86 #define E8390_START     0x02    /* Start the chip, clear reset */
  87 #define E8390_TRANS     0x04    /* Transmit a frame */
  88 #define E8390_RREAD     0x08    /* Remote read */
  89 #define E8390_RWRITE    0x10    /* Remote write  */
  90 #define E8390_NODMA     0x20    /* Remote DMA */
  91 #define E8390_PAGE0     0x00    /* Select page chip registers */
  92 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  93 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  94
  95 /* Bits in EN0_ISR - Interrupt status register */
  96 #define ENISR_RX        0x01    /* Receiver, no error */
  97 #define ENISR_TX        0x02    /* Transmitter, no error */
  98 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
  99 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
 100 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
 101 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
 102 #define ENISR_RDC       0x40    /* remote dma complete */
 103 #define ENISR_RESET     0x80    /* Reset completed */
 104 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
 105
 106 /* Bits in received packet status byte and EN0_RSR*/
 107 #define ENRSR_RXOK      0x01    /* Received a good packet */
 108 #define ENRSR_CRC       0x02    /* CRC error */
 109 #define ENRSR_FAE       0x04    /* frame alignment error */
 110 #define ENRSR_FO        0x08    /* FIFO overrun */
 111 #define ENRSR_MPA       0x10    /* missed pkt */
 112 #define ENRSR_PHY       0x20    /* physical/multicast address */
 113 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 114 #define ENRSR_DEF       0x80    /* deferring */
 115
 116 /* Transmitted packet status, EN0_TSR. */
 117 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 118 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 119 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 120 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 121 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 122 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 123 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 124 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 125
 126 #define NE2000_MEM_SIZE 32768
 127
 128 typedef struct NE2000State {
 129     uint8_t cmd;
 130     uint32_t start;
 131     uint32_t stop;
 132     uint8_t boundary;
 133     uint8_t tsr;
 134     uint8_t tpsr;
 135     uint16_t tcnt;
 136     uint16_t rcnt;
 137     uint32_t rsar;
 138     uint8_t isr;
 139     uint8_t dcfg;
 140     uint8_t imr;
 141     uint8_t phys[6]; /* mac address */
 142     uint8_t curpag;
 143     uint8_t mult[8]; /* multicast mask array */
 144     int irq;
 145     NetDriverState *nd;
 146     uint8_t mem[NE2000_MEM_SIZE];
 147 } NE2000State;
 148
 149 static void ne2000_reset(NE2000State *s)
 150 {
 151     int i;
 152
 153     s->isr = ENISR_RESET;
 154     memcpy(s->mem, s->nd->macaddr, 6);
 155     s->mem[14] = 0x57;
 156     s->mem[15] = 0x57;
 157
 158     /* duplicate prom data */
 159     for(i = 15;i >= 0; i--) {
 160         s->mem[2 * i] = s->mem[i];
 161         s->mem[2 * i + 1] = s->mem[i];
 162     }
 163 }
 164
 165 static void ne2000_update_irq(NE2000State *s)
 166 {
 167     int isr;
 168     isr = s->isr & s->imr;
 169     if (isr)
 170         pic_set_irq(s->irq, 1);
 171     else
 172         pic_set_irq(s->irq, 0);
 173 }
 174
 175 /* return the max buffer size if the NE2000 can receive more data */
 176 static int ne2000_can_receive(void *opaque)
 177 {
 178     NE2000State *s = opaque;
 179     int avail, index, boundary;
 180
 181     if (s->cmd & E8390_STOP)
 182         return 0;
 183     index = s->curpag << 8;
 184     boundary = s->boundary << 8;
 185     if (index < boundary)
 186         avail = boundary - index;
 187     else
 188         avail = (s->stop - s->start) - (index - boundary);
 189     if (avail < (MAX_ETH_FRAME_SIZE + 4))
 190         return 0;
 191     return MAX_ETH_FRAME_SIZE;
 192 }
 193
 194 #define MIN_BUF_SIZE 60
 195
 196 static void ne2000_receive(void *opaque, const uint8_t *buf, int size)
 197 {
 198     NE2000State *s = opaque;
 199     uint8_t *p;
 200     int total_len, next, avail, len, index;
 201     uint8_t buf1[60];
 202
 203 #if defined(DEBUG_NE2000)
 204     printf("NE2000: received len=%d\n", size);
 205 #endif
 206
 207     /* if too small buffer, then expand it */
 208     if (size < MIN_BUF_SIZE) {
 209         memcpy(buf1, buf, size);
 210         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
 211         buf = buf1;
 212         size = MIN_BUF_SIZE;
 213     }
 214
 215     index = s->curpag << 8;
 216     /* 4 bytes for header */
 217     total_len = size + 4;
 218     /* address for next packet (4 bytes for CRC) */
 219     next = index + ((total_len + 4 + 255) & ~0xff);
 220     if (next >= s->stop)
 221         next -= (s->stop - s->start);
 222     /* prepare packet header */
 223     p = s->mem + index;
 224     p[0] = ENRSR_RXOK; /* receive status */
 225     p[1] = next >> 8;
 226     p[2] = total_len;
 227     p[3] = total_len >> 8;
 228     index += 4;
 229
 230     /* write packet data */
 231     while (size > 0) {
 232         avail = s->stop - index;
 233         len = size;
 234         if (len > avail)
 235             len = avail;
 236         memcpy(s->mem + index, buf, len);
 237         buf += len;
 238         index += len;
 239         if (index == s->stop)
 240             index = s->start;
 241         size -= len;
 242     }
 243     s->curpag = next >> 8;
 244
 245     /* now we can signal we have receive something */
 246     s->isr |= ENISR_RX;
 247     ne2000_update_irq(s);
 248 }
 249
 250 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 251 {
 252     NE2000State *s = opaque;
 253     int offset, page;
 254
 255     addr &= 0xf;
 256 #ifdef DEBUG_NE2000
 257     printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
 258 #endif
 259     if (addr == E8390_CMD) {
 260         /* control register */
 261         s->cmd = val;
 262         if (val & E8390_START) {
 263             /* test specific case: zero length transfert */
 264             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
 265                 s->rcnt == 0) {
 266                 s->isr |= ENISR_RDC;
 267                 ne2000_update_irq(s);
 268             }
 269             if (val & E8390_TRANS) {
 270                 net_send_packet(s->nd, s->mem + (s->tpsr << 8), s->tcnt);
 271                 /* signal end of transfert */
 272                 s->tsr = ENTSR_PTX;
 273                 s->isr |= ENISR_TX;
 274                 ne2000_update_irq(s);
 275             }
 276         }
 277     } else {
 278         page = s->cmd >> 6;
 279         offset = addr | (page << 4);
 280         switch(offset) {
 281         case EN0_STARTPG:
 282             s->start = val << 8;
 283             break;
 284         case EN0_STOPPG:
 285             s->stop = val << 8;
 286             break;
 287         case EN0_BOUNDARY:
 288             s->boundary = val;
 289             break;
 290         case EN0_IMR:
 291             s->imr = val;
 292             ne2000_update_irq(s);
 293             break;
 294         case EN0_TPSR:
 295             s->tpsr = val;
 296             break;
 297         case EN0_TCNTLO:
 298             s->tcnt = (s->tcnt & 0xff00) | val;
 299             break;
 300         case EN0_TCNTHI:
 301             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
 302             break;
 303         case EN0_RSARLO:
 304             s->rsar = (s->rsar & 0xff00) | val;
 305             break;
 306         case EN0_RSARHI:
 307             s->rsar = (s->rsar & 0x00ff) | (val << 8);
 308             break;
 309         case EN0_RCNTLO:
 310             s->rcnt = (s->rcnt & 0xff00) | val;
 311             break;
 312         case EN0_RCNTHI:
 313             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
 314             break;
 315         case EN0_DCFG:
 316             s->dcfg = val;
 317             break;
 318         case EN0_ISR:
 319             s->isr &= ~val;
 320             ne2000_update_irq(s);
 321             break;
 322         case EN1_PHYS ... EN1_PHYS + 5:
 323             s->phys[offset - EN1_PHYS] = val;
 324             break;
 325         case EN1_CURPAG:
 326             s->curpag = val;
 327             break;
 328         case EN1_MULT ... EN1_MULT + 7:
 329             s->mult[offset - EN1_MULT] = val;
 330             break;
 331         }
 332     }
 333 }
 334
 335 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 336 {
 337     NE2000State *s = opaque;
 338     int offset, page, ret;
 339
 340     addr &= 0xf;
 341     if (addr == E8390_CMD) {
 342         ret = s->cmd;
 343     } else {
 344         page = s->cmd >> 6;
 345         offset = addr | (page << 4);
 346         switch(offset) {
 347         case EN0_TSR:
 348             ret = s->tsr;
 349             break;
 350         case EN0_BOUNDARY:
 351             ret = s->boundary;
 352             break;
 353         case EN0_ISR:
 354             ret = s->isr;
 355             break;
 356         case EN1_PHYS ... EN1_PHYS + 5:
 357             ret = s->phys[offset - EN1_PHYS];
 358             break;
 359         case EN1_CURPAG:
 360             ret = s->curpag;
 361             break;
 362         case EN1_MULT ... EN1_MULT + 7:
 363             ret = s->mult[offset - EN1_MULT];
 364             break;
 365         default:
 366             ret = 0x00;
 367             break;
 368         }
 369     }
 370 #ifdef DEBUG_NE2000
 371     printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
 372 #endif
 373     return ret;
 374 }
 375
 376 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 377 {
 378     NE2000State *s = opaque;
 379     uint8_t *p;
 380
 381 #ifdef DEBUG_NE2000
 382     printf("NE2000: asic write val=0x%04x\n", val);
 383 #endif
 384     p = s->mem + s->rsar;
 385     if (s->dcfg & 0x01) {
 386         /* 16 bit access */
 387         p[0] = val;
 388         p[1] = val >> 8;
 389         s->rsar += 2;
 390         s->rcnt -= 2;
 391     } else {
 392         /* 8 bit access */
 393         p[0] = val;
 394         s->rsar++;
 395         s->rcnt--;
 396     }
 397     /* wrap */
 398     if (s->rsar == s->stop)
 399         s->rsar = s->start;
 400     if (s->rcnt == 0) {
 401         /* signal end of transfert */
 402         s->isr |= ENISR_RDC;
 403         ne2000_update_irq(s);
 404     }
 405 }
 406
 407 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 408 {
 409     NE2000State *s = opaque;
 410     uint8_t *p;
 411     int ret;
 412
 413     p = s->mem + s->rsar;
 414     if (s->dcfg & 0x01) {
 415         /* 16 bit access */
 416         ret = p[0] | (p[1] << 8);
 417         s->rsar += 2;
 418         s->rcnt -= 2;
 419     } else {
 420         /* 8 bit access */
 421         ret = p[0];
 422         s->rsar++;
 423         s->rcnt--;
 424     }
 425     /* wrap */
 426     if (s->rsar == s->stop)
 427         s->rsar = s->start;
 428     if (s->rcnt == 0) {
 429         /* signal end of transfert */
 430         s->isr |= ENISR_RDC;
 431         ne2000_update_irq(s);
 432     }
 433 #ifdef DEBUG_NE2000
 434     printf("NE2000: asic read val=0x%04x\n", ret);
 435 #endif
 436     return ret;
 437 }
 438
 439 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 440 {
 441     /* nothing to do (end of reset pulse) */
 442 }
 443
 444 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 445 {
 446     NE2000State *s = opaque;
 447     ne2000_reset(s);
 448     return 0;
 449 }
 450
 451 void ne2000_init(int base, int irq, NetDriverState *nd)
 452 {
 453     NE2000State *s;
 454
 455     s = qemu_mallocz(sizeof(NE2000State));
 456     if (!s)
 457         return;
 458
 459     register_ioport_write(base, 16, 1, ne2000_ioport_write, s);
 460     register_ioport_read(base, 16, 1, ne2000_ioport_read, s);
 461
 462     register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s);
 463     register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s);
 464     register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s);
 465     register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s);
 466
 467     register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
 468     register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
 469     s->irq = irq;
 470     s->nd = nd;
 471
 472     ne2000_reset(s);
 473
 474     qemu_add_fd_read_handler(nd->fd, ne2000_can_receive, ne2000_receive, s);
 475 }