4 * Copyright (c) 2008 OKL
5 * Originally Written by Hans Jiang
6 * Copyright (c) 2011 NICTA Pty Ltd.
8 * This work is licensed under the terms of the GNU GPL, version 2 or later.
9 * See the COPYING file in the top-level directory.
11 * This is a `bare-bones' implementation of the IMX series serial ports.
13 * -- implement FIFOs. The real hardware has 32 word transmit
14 * and receive FIFOs; we currently use a 1-char buffer
16 * -- implement BAUD-rate and modem lines, for when the backend
17 * is a real serial device.
21 #include "hw/sysbus.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/char.h"
24 #include "hw/arm/imx.h"
26 //#define DEBUG_SERIAL 1
28 #define DPRINTF(fmt, args...) \
29 do { printf("imx_serial: " fmt , ##args); } while (0)
31 #define DPRINTF(fmt, args...) do {} while (0)
35 * Define to 1 for messages about attempts to
36 * access unimplemented registers or similar.
38 //#define DEBUG_IMPLEMENTATION 1
39 #ifdef DEBUG_IMPLEMENTATION
40 # define IPRINTF(fmt, args...) \
41 do { fprintf(stderr, "imx_serial: " fmt, ##args); } while (0)
43 # define IPRINTF(fmt, args...) do {} while (0)
46 #define TYPE_IMX_SERIAL "imx-serial"
47 #define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL)
49 typedef struct IMXSerialState
{
50 SysBusDevice parent_obj
;
62 * The registers below are implemented just so that the
63 * guest OS sees what it has written
75 static const VMStateDescription vmstate_imx_serial
= {
78 .minimum_version_id
= 1,
79 .minimum_version_id_old
= 1,
80 .fields
= (VMStateField
[]) {
81 VMSTATE_INT32(readbuff
, IMXSerialState
),
82 VMSTATE_UINT32(usr1
, IMXSerialState
),
83 VMSTATE_UINT32(usr2
, IMXSerialState
),
84 VMSTATE_UINT32(ucr1
, IMXSerialState
),
85 VMSTATE_UINT32(uts1
, IMXSerialState
),
86 VMSTATE_UINT32(onems
, IMXSerialState
),
87 VMSTATE_UINT32(ufcr
, IMXSerialState
),
88 VMSTATE_UINT32(ubmr
, IMXSerialState
),
89 VMSTATE_UINT32(ubrc
, IMXSerialState
),
90 VMSTATE_UINT32(ucr3
, IMXSerialState
),
96 #define URXD_CHARRDY (1<<15) /* character read is valid */
97 #define URXD_ERR (1<<14) /* Character has error */
98 #define URXD_BRK (1<<11) /* Break received */
100 #define USR1_PARTYER (1<<15) /* Parity Error */
101 #define USR1_RTSS (1<<14) /* RTS pin status */
102 #define USR1_TRDY (1<<13) /* Tx ready */
103 #define USR1_RTSD (1<<12) /* RTS delta: pin changed state */
104 #define USR1_ESCF (1<<11) /* Escape sequence interrupt */
105 #define USR1_FRAMERR (1<<10) /* Framing error */
106 #define USR1_RRDY (1<<9) /* receiver ready */
107 #define USR1_AGTIM (1<<8) /* Aging timer interrupt */
108 #define USR1_DTRD (1<<7) /* DTR changed */
109 #define USR1_RXDS (1<<6) /* Receiver is idle */
110 #define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */
111 #define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */
113 #define USR2_ADET (1<<15) /* Autobaud complete */
114 #define USR2_TXFE (1<<14) /* Transmit FIFO empty */
115 #define USR2_DTRF (1<<13) /* DTR/DSR transition */
116 #define USR2_IDLE (1<<12) /* UART has been idle for too long */
117 #define USR2_ACST (1<<11) /* Autobaud counter stopped */
118 #define USR2_RIDELT (1<<10) /* Ring Indicator delta */
119 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
120 #define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */
121 #define USR2_WAKE (1<<7) /* Start bit detected */
122 #define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */
123 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
124 #define USR2_RTSF (1<<4) /* RTS transition */
125 #define USR2_TXDC (1<<3) /* Transmission complete */
126 #define USR2_BRCD (1<<2) /* Break condition detected */
127 #define USR2_ORE (1<<1) /* Overrun error */
128 #define USR2_RDR (1<<0) /* Receive data ready */
130 #define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */
131 #define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */
132 #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */
133 #define UCR1_UARTEN (1<<0) /* UART Enable */
135 #define UCR2_TXEN (1<<2) /* Transmitter enable */
136 #define UCR2_RXEN (1<<1) /* Receiver enable */
137 #define UCR2_SRST (1<<0) /* Reset complete */
139 #define UTS1_TXEMPTY (1<<6)
140 #define UTS1_RXEMPTY (1<<5)
141 #define UTS1_TXFULL (1<<4)
142 #define UTS1_RXFULL (1<<3)
144 static void imx_update(IMXSerialState
*s
)
148 flags
= (s
->usr1
& s
->ucr1
) & (USR1_TRDY
|USR1_RRDY
);
149 if (!(s
->ucr1
& UCR1_TXMPTYEN
)) {
153 qemu_set_irq(s
->irq
, !!flags
);
156 static void imx_serial_reset(IMXSerialState
*s
)
159 s
->usr1
= USR1_TRDY
| USR1_RXDS
;
161 * Fake attachment of a terminal: assert RTS.
163 s
->usr1
|= USR1_RTSS
;
164 s
->usr2
= USR2_TXFE
| USR2_TXDC
| USR2_DCDIN
;
165 s
->uts1
= UTS1_RXEMPTY
| UTS1_TXEMPTY
;
171 s
->readbuff
= URXD_ERR
;
174 static void imx_serial_reset_at_boot(DeviceState
*dev
)
176 IMXSerialState
*s
= IMX_SERIAL(dev
);
181 * enable the uart on boot, so messages from the linux decompresser
182 * are visible. On real hardware this is done by the boot rom
183 * before anything else is loaded.
185 s
->ucr1
= UCR1_UARTEN
;
190 static uint64_t imx_serial_read(void *opaque
, hwaddr offset
,
193 IMXSerialState
*s
= (IMXSerialState
*)opaque
;
196 DPRINTF("read(offset=%x)\n", offset
>> 2);
197 switch (offset
>> 2) {
200 if (!(s
->uts1
& UTS1_RXEMPTY
)) {
201 /* Character is valid */
203 s
->usr1
&= ~USR1_RRDY
;
204 s
->usr2
&= ~USR2_RDR
;
205 s
->uts1
|= UTS1_RXEMPTY
;
207 qemu_chr_accept_input(s
->chr
);
211 case 0x20: /* UCR1 */
214 case 0x21: /* UCR2 */
217 case 0x25: /* USR1 */
220 case 0x26: /* USR2 */
223 case 0x2A: /* BRM Modulator */
226 case 0x2B: /* Baud Rate Count */
229 case 0x2d: /* Test register */
232 case 0x24: /* UFCR */
238 case 0x22: /* UCR3 */
241 case 0x23: /* UCR4 */
242 case 0x29: /* BRM Incremental */
243 return 0x0; /* TODO */
246 IPRINTF("imx_serial_read: bad offset: 0x%x\n", (int)offset
);
251 static void imx_serial_write(void *opaque
, hwaddr offset
,
252 uint64_t value
, unsigned size
)
254 IMXSerialState
*s
= (IMXSerialState
*)opaque
;
257 DPRINTF("write(offset=%x, value = %x) to %s\n",
259 (unsigned int)value
, s
->chr
? s
->chr
->label
: "NODEV");
261 switch (offset
>> 2) {
262 case 0x10: /* UTXD */
264 if (s
->ucr2
& UCR2_TXEN
) {
266 qemu_chr_fe_write(s
->chr
, &ch
, 1);
268 s
->usr1
&= ~USR1_TRDY
;
270 s
->usr1
|= USR1_TRDY
;
275 case 0x20: /* UCR1 */
276 s
->ucr1
= value
& 0xffff;
277 DPRINTF("write(ucr1=%x)\n", (unsigned int)value
);
281 case 0x21: /* UCR2 */
283 * Only a few bits in control register 2 are implemented as yet.
284 * If it's intended to use a real serial device as a back-end, this
285 * register will have to be implemented more fully.
287 if (!(value
& UCR2_SRST
)) {
292 if (value
& UCR2_RXEN
) {
293 if (!(s
->ucr2
& UCR2_RXEN
)) {
294 qemu_chr_accept_input(s
->chr
);
297 s
->ucr2
= value
& 0xffff;
300 case 0x25: /* USR1 */
301 value
&= USR1_AWAKE
| USR1_AIRINT
| USR1_DTRD
| USR1_AGTIM
|
302 USR1_FRAMERR
| USR1_ESCF
| USR1_RTSD
| USR1_PARTYER
;
306 case 0x26: /* USR2 */
308 * Writing 1 to some bits clears them; all other
311 value
&= USR2_ADET
| USR2_DTRF
| USR2_IDLE
| USR2_ACST
|
312 USR2_RIDELT
| USR2_IRINT
| USR2_WAKE
|
313 USR2_DCDDELT
| USR2_RTSF
| USR2_BRCD
| USR2_ORE
;
318 * Linux expects to see what it writes to these registers
319 * We don't currently alter the baud rate
321 case 0x29: /* UBIR */
322 s
->ubrc
= value
& 0xffff;
325 case 0x2a: /* UBMR */
326 s
->ubmr
= value
& 0xffff;
329 case 0x2c: /* One ms reg */
330 s
->onems
= value
& 0xffff;
333 case 0x24: /* FIFO control register */
334 s
->ufcr
= value
& 0xffff;
337 case 0x22: /* UCR3 */
338 s
->ucr3
= value
& 0xffff;
341 case 0x2d: /* UTS1 */
342 case 0x23: /* UCR4 */
343 IPRINTF("Unimplemented Register %x written to\n", offset
>> 2);
348 IPRINTF("imx_serial_write: Bad offset 0x%x\n", (int)offset
);
352 static int imx_can_receive(void *opaque
)
354 IMXSerialState
*s
= (IMXSerialState
*)opaque
;
355 return !(s
->usr1
& USR1_RRDY
);
358 static void imx_put_data(void *opaque
, uint32_t value
)
360 IMXSerialState
*s
= (IMXSerialState
*)opaque
;
361 DPRINTF("received char\n");
362 s
->usr1
|= USR1_RRDY
;
364 s
->uts1
&= ~UTS1_RXEMPTY
;
369 static void imx_receive(void *opaque
, const uint8_t *buf
, int size
)
371 imx_put_data(opaque
, *buf
);
374 static void imx_event(void *opaque
, int event
)
376 if (event
== CHR_EVENT_BREAK
) {
377 imx_put_data(opaque
, URXD_BRK
);
382 static const struct MemoryRegionOps imx_serial_ops
= {
383 .read
= imx_serial_read
,
384 .write
= imx_serial_write
,
385 .endianness
= DEVICE_NATIVE_ENDIAN
,
388 static int imx_serial_init(SysBusDevice
*dev
)
390 IMXSerialState
*s
= IMX_SERIAL(dev
);
393 memory_region_init_io(&s
->iomem
, OBJECT(s
), &imx_serial_ops
, s
,
394 "imx-serial", 0x1000);
395 sysbus_init_mmio(dev
, &s
->iomem
);
396 sysbus_init_irq(dev
, &s
->irq
);
399 qemu_chr_add_handlers(s
->chr
, imx_can_receive
, imx_receive
,
402 DPRINTF("No char dev for uart at 0x%lx\n",
403 (unsigned long)s
->iomem
.ram_addr
);
409 void imx_serial_create(int uart
, const hwaddr addr
, qemu_irq irq
)
413 CharDriverState
*chr
;
414 const char chr_name
[] = "serial";
415 char label
[ARRAY_SIZE(chr_name
) + 1];
417 dev
= qdev_create(NULL
, TYPE_IMX_SERIAL
);
419 if (uart
>= MAX_SERIAL_PORTS
) {
420 hw_error("Cannot assign uart %d: QEMU supports only %d ports\n",
421 uart
, MAX_SERIAL_PORTS
);
423 chr
= serial_hds
[uart
];
425 snprintf(label
, ARRAY_SIZE(label
), "%s%d", chr_name
, uart
);
426 chr
= qemu_chr_new(label
, "null", NULL
);
428 hw_error("Can't assign serial port to imx-uart%d.\n", uart
);
432 qdev_prop_set_chr(dev
, "chardev", chr
);
433 bus
= SYS_BUS_DEVICE(dev
);
434 qdev_init_nofail(dev
);
435 if (addr
!= (hwaddr
)-1) {
436 sysbus_mmio_map(bus
, 0, addr
);
438 sysbus_connect_irq(bus
, 0, irq
);
443 static Property imx32_serial_properties
[] = {
444 DEFINE_PROP_CHR("chardev", IMXSerialState
, chr
),
445 DEFINE_PROP_END_OF_LIST(),
448 static void imx_serial_class_init(ObjectClass
*klass
, void *data
)
450 DeviceClass
*dc
= DEVICE_CLASS(klass
);
451 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
453 k
->init
= imx_serial_init
;
454 dc
->vmsd
= &vmstate_imx_serial
;
455 dc
->reset
= imx_serial_reset_at_boot
;
456 set_bit(DEVICE_CATEGORY_INPUT
, dc
->categories
);
457 dc
->desc
= "i.MX series UART";
458 dc
->props
= imx32_serial_properties
;
461 static const TypeInfo imx_serial_info
= {
462 .name
= TYPE_IMX_SERIAL
,
463 .parent
= TYPE_SYS_BUS_DEVICE
,
464 .instance_size
= sizeof(IMXSerialState
),
465 .class_init
= imx_serial_class_init
,
468 static void imx_serial_register_types(void)
470 type_register_static(&imx_serial_info
);
473 type_init(imx_serial_register_types
)