hw/ppc/prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/timer/m48t59.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/char/serial.h"
  28 #include "hw/block/fdc.h"
  29 #include "net/net.h"
  30 #include "sysemu/sysemu.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/pci/pci.h"
  33 #include "hw/pci/pci_host.h"
  34 #include "hw/ppc/ppc.h"
  35 #include "hw/boards.h"
  36 #include "qemu/log.h"
  37 #include "hw/ide.h"
  38 #include "hw/loader.h"
  39 #include "hw/timer/mc146818rtc.h"
  40 #include "hw/isa/pc87312.h"
  41 #include "sysemu/blockdev.h"
  42 #include "sysemu/arch_init.h"
  43 #include "sysemu/qtest.h"
  44 #include "exec/address-spaces.h"
  45 #include "elf.h"
  46
  47 //#define HARD_DEBUG_PPC_IO
  48 //#define DEBUG_PPC_IO
  49
  50 /* SMP is not enabled, for now */
  51 #define MAX_CPUS 1
  52
  53 #define MAX_IDE_BUS 2
  54
  55 #define BIOS_SIZE (1024 * 1024)
  56 #define BIOS_FILENAME "ppc_rom.bin"
  57 #define KERNEL_LOAD_ADDR 0x01000000
  58 #define INITRD_LOAD_ADDR 0x01800000
  59
  60 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  61 #define DEBUG_PPC_IO
  62 #endif
  63
  64 #if defined (HARD_DEBUG_PPC_IO)
  65 #define PPC_IO_DPRINTF(fmt, ...)                         \
  66 do {                                                     \
  67     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  68         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  69     } else {                                             \
  70         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  71     }                                                    \
  72 } while (0)
  73 #elif defined (DEBUG_PPC_IO)
  74 #define PPC_IO_DPRINTF(fmt, ...) \
  75 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  76 #else
  77 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  78 #endif
  79
  80 /* Constants for devices init */
  81 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  82 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  83 static const int ide_irq[2] = { 13, 13 };
  84
  85 #define NE2000_NB_MAX 6
  86
  87 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  88 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  89
  90 /* ISA IO ports bridge */
  91 #define PPC_IO_BASE 0x80000000
  92
  93 /* PowerPC control and status registers */
  94 #if 0 // Not used
  95 static struct {
  96     /* IDs */
  97     uint32_t veni_devi;
  98     uint32_t revi;
  99     /* Control and status */
 100     uint32_t gcsr;
 101     uint32_t xcfr;
 102     uint32_t ct32;
 103     uint32_t mcsr;
 104     /* General purpose registers */
 105     uint32_t gprg[6];
 106     /* Exceptions */
 107     uint32_t feen;
 108     uint32_t fest;
 109     uint32_t fema;
 110     uint32_t fecl;
 111     uint32_t eeen;
 112     uint32_t eest;
 113     uint32_t eecl;
 114     uint32_t eeint;
 115     uint32_t eemck0;
 116     uint32_t eemck1;
 117     /* Error diagnostic */
 118 } XCSR;
 119
 120 static void PPC_XCSR_writeb (void *opaque,
 121                              hwaddr addr, uint32_t value)
 122 {
 123     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 124            value);
 125 }
 126
 127 static void PPC_XCSR_writew (void *opaque,
 128                              hwaddr addr, uint32_t value)
 129 {
 130     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 131            value);
 132 }
 133
 134 static void PPC_XCSR_writel (void *opaque,
 135                              hwaddr addr, uint32_t value)
 136 {
 137     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 138            value);
 139 }
 140
 141 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
 142 {
 143     uint32_t retval = 0;
 144
 145     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 146            retval);
 147
 148     return retval;
 149 }
 150
 151 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
 152 {
 153     uint32_t retval = 0;
 154
 155     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 156            retval);
 157
 158     return retval;
 159 }
 160
 161 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
 162 {
 163     uint32_t retval = 0;
 164
 165     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 166            retval);
 167
 168     return retval;
 169 }
 170
 171 static const MemoryRegionOps PPC_XCSR_ops = {
 172     .old_mmio = {
 173         .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
 174         .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
 175     },
 176     .endianness = DEVICE_LITTLE_ENDIAN,
 177 };
 178
 179 #endif
 180
 181 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 182 typedef struct sysctrl_t {
 183     qemu_irq reset_irq;
 184     M48t59State *nvram;
 185     uint8_t state;
 186     uint8_t syscontrol;
 187     int contiguous_map;
 188     qemu_irq contiguous_map_irq;
 189     int endian;
 190 } sysctrl_t;
 191
 192 enum {
 193     STATE_HARDFILE = 0x01,
 194 };
 195
 196 static sysctrl_t *sysctrl;
 197
 198 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 199 {
 200     sysctrl_t *sysctrl = opaque;
 201
 202     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 203                    addr - PPC_IO_BASE, val);
 204     switch (addr) {
 205     case 0x0092:
 206         /* Special port 92 */
 207         /* Check soft reset asked */
 208         if (val & 0x01) {
 209             qemu_irq_raise(sysctrl->reset_irq);
 210         } else {
 211             qemu_irq_lower(sysctrl->reset_irq);
 212         }
 213         /* Check LE mode */
 214         if (val & 0x02) {
 215             sysctrl->endian = 1;
 216         } else {
 217             sysctrl->endian = 0;
 218         }
 219         break;
 220     case 0x0800:
 221         /* Motorola CPU configuration register : read-only */
 222         break;
 223     case 0x0802:
 224         /* Motorola base module feature register : read-only */
 225         break;
 226     case 0x0803:
 227         /* Motorola base module status register : read-only */
 228         break;
 229     case 0x0808:
 230         /* Hardfile light register */
 231         if (val & 1)
 232             sysctrl->state |= STATE_HARDFILE;
 233         else
 234             sysctrl->state &= ~STATE_HARDFILE;
 235         break;
 236     case 0x0810:
 237         /* Password protect 1 register */
 238         if (sysctrl->nvram != NULL)
 239             m48t59_toggle_lock(sysctrl->nvram, 1);
 240         break;
 241     case 0x0812:
 242         /* Password protect 2 register */
 243         if (sysctrl->nvram != NULL)
 244             m48t59_toggle_lock(sysctrl->nvram, 2);
 245         break;
 246     case 0x0814:
 247         /* L2 invalidate register */
 248         //        tlb_flush(first_cpu, 1);
 249         break;
 250     case 0x081C:
 251         /* system control register */
 252         sysctrl->syscontrol = val & 0x0F;
 253         break;
 254     case 0x0850:
 255         /* I/O map type register */
 256         sysctrl->contiguous_map = val & 0x01;
 257         qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
 258         break;
 259     default:
 260         printf("ERROR: unaffected IO port write: %04" PRIx32
 261                " => %02" PRIx32"\n", addr, val);
 262         break;
 263     }
 264 }
 265
 266 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 267 {
 268     sysctrl_t *sysctrl = opaque;
 269     uint32_t retval = 0xFF;
 270
 271     switch (addr) {
 272     case 0x0092:
 273         /* Special port 92 */
 274         retval = sysctrl->endian << 1;
 275         break;
 276     case 0x0800:
 277         /* Motorola CPU configuration register */
 278         retval = 0xEF; /* MPC750 */
 279         break;
 280     case 0x0802:
 281         /* Motorola Base module feature register */
 282         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 283         break;
 284     case 0x0803:
 285         /* Motorola base module status register */
 286         retval = 0xE0; /* Standard MPC750 */
 287         break;
 288     case 0x080C:
 289         /* Equipment present register:
 290          *  no L2 cache
 291          *  no upgrade processor
 292          *  no cards in PCI slots
 293          *  SCSI fuse is bad
 294          */
 295         retval = 0x3C;
 296         break;
 297     case 0x0810:
 298         /* Motorola base module extended feature register */
 299         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 300         break;
 301     case 0x0814:
 302         /* L2 invalidate: don't care */
 303         break;
 304     case 0x0818:
 305         /* Keylock */
 306         retval = 0x00;
 307         break;
 308     case 0x081C:
 309         /* system control register
 310          * 7 - 6 / 1 - 0: L2 cache enable
 311          */
 312         retval = sysctrl->syscontrol;
 313         break;
 314     case 0x0823:
 315         /* */
 316         retval = 0x03; /* no L2 cache */
 317         break;
 318     case 0x0850:
 319         /* I/O map type register */
 320         retval = sysctrl->contiguous_map;
 321         break;
 322     default:
 323         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 324         break;
 325     }
 326     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 327                    addr - PPC_IO_BASE, retval);
 328
 329     return retval;
 330 }
 331
 332
 333 #define NVRAM_SIZE        0x2000
 334
 335 static void cpu_request_exit(void *opaque, int irq, int level)
 336 {
 337     CPUState *cpu = current_cpu;
 338
 339     if (cpu && level) {
 340         cpu_exit(cpu);
 341     }
 342 }
 343
 344 static void ppc_prep_reset(void *opaque)
 345 {
 346     PowerPCCPU *cpu = opaque;
 347
 348     cpu_reset(CPU(cpu));
 349 }
 350
 351 static const MemoryRegionPortio prep_portio_list[] = {
 352     /* System control ports */
 353     { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
 354     { 0x0800, 0x52, 1,
 355       .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
 356     /* Special port to get debug messages from Open-Firmware */
 357     { 0x0F00, 4, 1, .write = PPC_debug_write, },
 358     PORTIO_END_OF_LIST(),
 359 };
 360
 361 static PortioList prep_port_list;
 362
 363 /* PowerPC PREP hardware initialisation */
 364 static void ppc_prep_init(MachineState *machine)
 365 {
 366     ram_addr_t ram_size = machine->ram_size;
 367     const char *cpu_model = machine->cpu_model;
 368     const char *kernel_filename = machine->kernel_filename;
 369     const char *kernel_cmdline = machine->kernel_cmdline;
 370     const char *initrd_filename = machine->initrd_filename;
 371     const char *boot_device = machine->boot_order;
 372     MemoryRegion *sysmem = get_system_memory();
 373     PowerPCCPU *cpu = NULL;
 374     CPUPPCState *env = NULL;
 375     nvram_t nvram;
 376     M48t59State *m48t59;
 377 #if 0
 378     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 379 #endif
 380     int linux_boot, i, nb_nics1;
 381     MemoryRegion *ram = g_new(MemoryRegion, 1);
 382     uint32_t kernel_base, initrd_base;
 383     long kernel_size, initrd_size;
 384     DeviceState *dev;
 385     PCIHostState *pcihost;
 386     PCIBus *pci_bus;
 387     PCIDevice *pci;
 388     ISABus *isa_bus;
 389     ISADevice *isa;
 390     qemu_irq *cpu_exit_irq;
 391     int ppc_boot_device;
 392     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 393
 394     sysctrl = g_malloc0(sizeof(sysctrl_t));
 395
 396     linux_boot = (kernel_filename != NULL);
 397
 398     /* init CPUs */
 399     if (cpu_model == NULL)
 400         cpu_model = "602";
 401     for (i = 0; i < smp_cpus; i++) {
 402         cpu = cpu_ppc_init(cpu_model);
 403         if (cpu == NULL) {
 404             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 405             exit(1);
 406         }
 407         env = &cpu->env;
 408
 409         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 410             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 411             cpu_ppc_tb_init(env, 7812500UL);
 412         } else {
 413             /* Set time-base frequency to 100 Mhz */
 414             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 415         }
 416         qemu_register_reset(ppc_prep_reset, cpu);
 417     }
 418
 419     /* allocate RAM */
 420     memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
 421     memory_region_add_subregion(sysmem, 0, ram);
 422
 423     if (linux_boot) {
 424         kernel_base = KERNEL_LOAD_ADDR;
 425         /* now we can load the kernel */
 426         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 427                                           ram_size - kernel_base);
 428         if (kernel_size < 0) {
 429             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 430             exit(1);
 431         }
 432         /* load initrd */
 433         if (initrd_filename) {
 434             initrd_base = INITRD_LOAD_ADDR;
 435             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 436                                               ram_size - initrd_base);
 437             if (initrd_size < 0) {
 438                 hw_error("qemu: could not load initial ram disk '%s'\n",
 439                           initrd_filename);
 440             }
 441         } else {
 442             initrd_base = 0;
 443             initrd_size = 0;
 444         }
 445         ppc_boot_device = 'm';
 446     } else {
 447         kernel_base = 0;
 448         kernel_size = 0;
 449         initrd_base = 0;
 450         initrd_size = 0;
 451         ppc_boot_device = '\0';
 452         /* For now, OHW cannot boot from the network. */
 453         for (i = 0; boot_device[i] != '\0'; i++) {
 454             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 455                 ppc_boot_device = boot_device[i];
 456                 break;
 457             }
 458         }
 459         if (ppc_boot_device == '\0') {
 460             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 461             exit(1);
 462         }
 463     }
 464
 465     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 466         hw_error("Only 6xx bus is supported on PREP machine\n");
 467     }
 468
 469     dev = qdev_create(NULL, "raven-pcihost");
 470     if (bios_name == NULL) {
 471         bios_name = BIOS_FILENAME;
 472     }
 473     qdev_prop_set_string(dev, "bios-name", bios_name);
 474     qdev_prop_set_uint32(dev, "elf-machine", ELF_MACHINE);
 475     pcihost = PCI_HOST_BRIDGE(dev);
 476     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 477     qdev_init_nofail(dev);
 478     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 479     if (pci_bus == NULL) {
 480         fprintf(stderr, "Couldn't create PCI host controller.\n");
 481         exit(1);
 482     }
 483     sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
 484
 485     /* PCI -> ISA bridge */
 486     pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
 487     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 488     cpu = POWERPC_CPU(first_cpu);
 489     qdev_connect_gpio_out(&pci->qdev, 0,
 490                           cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
 491     qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
 492     sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
 493     sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
 494     sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
 495     sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
 496     isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
 497
 498     /* Super I/O (parallel + serial ports) */
 499     isa = isa_create(isa_bus, TYPE_PC87312);
 500     dev = DEVICE(isa);
 501     qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
 502     qdev_init_nofail(dev);
 503
 504     /* init basic PC hardware */
 505     pci_vga_init(pci_bus);
 506
 507     nb_nics1 = nb_nics;
 508     if (nb_nics1 > NE2000_NB_MAX)
 509         nb_nics1 = NE2000_NB_MAX;
 510     for(i = 0; i < nb_nics1; i++) {
 511         if (nd_table[i].model == NULL) {
 512             nd_table[i].model = g_strdup("ne2k_isa");
 513         }
 514         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 515             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 516                             &nd_table[i]);
 517         } else {
 518             pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
 519         }
 520     }
 521
 522     ide_drive_get(hd, ARRAY_SIZE(hd));
 523     for(i = 0; i < MAX_IDE_BUS; i++) {
 524         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 525                      hd[2 * i],
 526                      hd[2 * i + 1]);
 527     }
 528     isa_create_simple(isa_bus, "i8042");
 529
 530     cpu = POWERPC_CPU(first_cpu);
 531     sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
 532
 533     portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
 534     portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
 535
 536     /* PowerPC control and status register group */
 537 #if 0
 538     memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
 539     memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
 540 #endif
 541
 542     if (usb_enabled(false)) {
 543         pci_create_simple(pci_bus, -1, "pci-ohci");
 544     }
 545
 546     m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
 547     if (m48t59 == NULL)
 548         return;
 549     sysctrl->nvram = m48t59;
 550
 551     /* Initialise NVRAM */
 552     nvram.opaque = m48t59;
 553     nvram.read_fn = &m48t59_read;
 554     nvram.write_fn = &m48t59_write;
 555     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 556                          kernel_base, kernel_size,
 557                          kernel_cmdline,
 558                          initrd_base, initrd_size,
 559                          /* XXX: need an option to load a NVRAM image */
 560                          0,
 561                          graphic_width, graphic_height, graphic_depth);
 562 }
 563
 564 static QEMUMachine prep_machine = {
 565     .name = "prep",
 566     .desc = "PowerPC PREP platform",
 567     .init = ppc_prep_init,
 568     .max_cpus = MAX_CPUS,
 569     .default_boot_order = "cad",
 570 };
 571
 572 static void prep_machine_init(void)
 573 {
 574     qemu_register_machine(&prep_machine);
 575 }
 576
 577 machine_init(prep_machine_init);