hw/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw.h"
  24 #include "pc.h"
  25 #include "apic.h"
  26 #include "qemu-timer.h"
  27 #include "host-utils.h"
  28 #include "sysbus.h"
  29
  30 //#define DEBUG_IOAPIC
  31
  32 #ifdef DEBUG_IOAPIC
  33 #define DPRINTF(fmt, ...)                                       \
  34     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define DPRINTF(fmt, ...)
  37 #endif
  38
  39 #define IOAPIC_LVT_MASKED               (1<<16)
  40
  41 #define IOAPIC_TRIGGER_EDGE             0
  42 #define IOAPIC_TRIGGER_LEVEL            1
  43
  44 /*io{apic,sapic} delivery mode*/
  45 #define IOAPIC_DM_FIXED                 0x0
  46 #define IOAPIC_DM_LOWEST_PRIORITY       0x1
  47 #define IOAPIC_DM_PMI                   0x2
  48 #define IOAPIC_DM_NMI                   0x4
  49 #define IOAPIC_DM_INIT                  0x5
  50 #define IOAPIC_DM_SIPI                  0x5
  51 #define IOAPIC_DM_EXTINT                0x7
  52
  53 typedef struct IOAPICState IOAPICState;
  54
  55 struct IOAPICState {
  56     SysBusDevice busdev;
  57     uint8_t id;
  58     uint8_t ioregsel;
  59
  60     uint32_t irr;
  61     uint64_t ioredtbl[IOAPIC_NUM_PINS];
  62 };
  63
  64 static void ioapic_service(IOAPICState *s)
  65 {
  66     uint8_t i;
  67     uint8_t trig_mode;
  68     uint8_t vector;
  69     uint8_t delivery_mode;
  70     uint32_t mask;
  71     uint64_t entry;
  72     uint8_t dest;
  73     uint8_t dest_mode;
  74     uint8_t polarity;
  75
  76     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  77         mask = 1 << i;
  78         if (s->irr & mask) {
  79             entry = s->ioredtbl[i];
  80             if (!(entry & IOAPIC_LVT_MASKED)) {
  81                 trig_mode = ((entry >> 15) & 1);
  82                 dest = entry >> 56;
  83                 dest_mode = (entry >> 11) & 1;
  84                 delivery_mode = (entry >> 8) & 7;
  85                 polarity = (entry >> 13) & 1;
  86                 if (trig_mode == IOAPIC_TRIGGER_EDGE)
  87                     s->irr &= ~mask;
  88                 if (delivery_mode == IOAPIC_DM_EXTINT)
  89                     vector = pic_read_irq(isa_pic);
  90                 else
  91                     vector = entry & 0xff;
  92
  93                 apic_deliver_irq(dest, dest_mode, delivery_mode,
  94                                  vector, polarity, trig_mode);
  95             }
  96         }
  97     }
  98 }
  99
 100 static void ioapic_set_irq(void *opaque, int vector, int level)
 101 {
 102     IOAPICState *s = opaque;
 103
 104     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 105      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 106      * the cleanest way of doing it but it should work. */
 107
 108     DPRINTF("%s: %s vec %x\n", __func__, level? "raise" : "lower", vector);
 109     if (vector == 0)
 110         vector = 2;
 111
 112     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 113         uint32_t mask = 1 << vector;
 114         uint64_t entry = s->ioredtbl[vector];
 115
 116         if ((entry >> 15) & 1) {
 117             /* level triggered */
 118             if (level) {
 119                 s->irr |= mask;
 120                 ioapic_service(s);
 121             } else {
 122                 s->irr &= ~mask;
 123             }
 124         } else {
 125             /* edge triggered */
 126             if (level) {
 127                 s->irr |= mask;
 128                 ioapic_service(s);
 129             }
 130         }
 131     }
 132 }
 133
 134 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
 135 {
 136     IOAPICState *s = opaque;
 137     int index;
 138     uint32_t val = 0;
 139
 140     addr &= 0xff;
 141     if (addr == 0x00) {
 142         val = s->ioregsel;
 143     } else if (addr == 0x10) {
 144         switch (s->ioregsel) {
 145             case 0x00:
 146                 val = s->id << 24;
 147                 break;
 148             case 0x01:
 149                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
 150                 break;
 151             case 0x02:
 152                 val = 0;
 153                 break;
 154             default:
 155                 index = (s->ioregsel - 0x10) >> 1;
 156                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 157                     if (s->ioregsel & 1)
 158                         val = s->ioredtbl[index] >> 32;
 159                     else
 160                         val = s->ioredtbl[index] & 0xffffffff;
 161                 }
 162         }
 163         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 164     }
 165     return val;
 166 }
 167
 168 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 169 {
 170     IOAPICState *s = opaque;
 171     int index;
 172
 173     addr &= 0xff;
 174     if (addr == 0x00)  {
 175         s->ioregsel = val;
 176         return;
 177     } else if (addr == 0x10) {
 178         DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
 179         switch (s->ioregsel) {
 180             case 0x00:
 181                 s->id = (val >> 24) & 0xff;
 182                 return;
 183             case 0x01:
 184             case 0x02:
 185                 return;
 186             default:
 187                 index = (s->ioregsel - 0x10) >> 1;
 188                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 189                     if (s->ioregsel & 1) {
 190                         s->ioredtbl[index] &= 0xffffffff;
 191                         s->ioredtbl[index] |= (uint64_t)val << 32;
 192                     } else {
 193                         s->ioredtbl[index] &= ~0xffffffffULL;
 194                         s->ioredtbl[index] |= val;
 195                     }
 196                     ioapic_service(s);
 197                 }
 198         }
 199     }
 200 }
 201
 202 static const VMStateDescription vmstate_ioapic = {
 203     .name = "ioapic",
 204     .version_id = 1,
 205     .minimum_version_id = 1,
 206     .minimum_version_id_old = 1,
 207     .fields      = (VMStateField []) {
 208         VMSTATE_UINT8(id, IOAPICState),
 209         VMSTATE_UINT8(ioregsel, IOAPICState),
 210         VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
 211         VMSTATE_END_OF_LIST()
 212     }
 213 };
 214
 215 static void ioapic_reset(DeviceState *d)
 216 {
 217     IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
 218     int i;
 219
 220     s->id = 0;
 221     s->ioregsel = 0;
 222     s->irr = 0;
 223     for(i = 0; i < IOAPIC_NUM_PINS; i++)
 224         s->ioredtbl[i] = 1 << 16; /* mask LVT */
 225 }
 226
 227 static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
 228     ioapic_mem_readl,
 229     ioapic_mem_readl,
 230     ioapic_mem_readl,
 231 };
 232
 233 static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
 234     ioapic_mem_writel,
 235     ioapic_mem_writel,
 236     ioapic_mem_writel,
 237 };
 238
 239 static int ioapic_init1(SysBusDevice *dev)
 240 {
 241     IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
 242     int io_memory;
 243
 244     io_memory = cpu_register_io_memory(ioapic_mem_read,
 245                                        ioapic_mem_write, s,
 246                                        DEVICE_NATIVE_ENDIAN);
 247     sysbus_init_mmio(dev, 0x1000, io_memory);
 248
 249     qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
 250
 251     return 0;
 252 }
 253
 254 static SysBusDeviceInfo ioapic_info = {
 255     .init = ioapic_init1,
 256     .qdev.name = "ioapic",
 257     .qdev.size = sizeof(IOAPICState),
 258     .qdev.vmsd = &vmstate_ioapic,
 259     .qdev.reset = ioapic_reset,
 260     .qdev.no_user = 1,
 261 };
 262
 263 static void ioapic_register_devices(void)
 264 {
 265     sysbus_register_withprop(&ioapic_info);
 266 }
 267
 268 device_init(ioapic_register_devices)