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target/ppc: Convert debug to trace events (decrementer and IRQ)
[qemu.git] / hw / ppc / ppc.c
blobb813ef732ec186e32167dd6684a9f1a35242821b
1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/irq.h"
27 #include "hw/ppc/ppc.h"
28 #include "hw/ppc/ppc_e500.h"
29 #include "qemu/timer.h"
30 #include "sysemu/cpus.h"
31 #include "qemu/log.h"
32 #include "qemu/main-loop.h"
33 #include "qemu/error-report.h"
34 #include "sysemu/kvm.h"
35 #include "sysemu/runstate.h"
36 #include "kvm_ppc.h"
37 #include "migration/vmstate.h"
38 #include "trace.h"
39
40 static void cpu_ppc_tb_stop (CPUPPCState *env);
41 static void cpu_ppc_tb_start (CPUPPCState *env);
42
43 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
44 {
45 CPUState *cs = CPU(cpu);
46 CPUPPCState *env = &cpu->env;
47 unsigned int old_pending;
48 bool locked = false;
49
50 /* We may already have the BQL if coming from the reset path */
51 if (!qemu_mutex_iothread_locked()) {
52 locked = true;
53 qemu_mutex_lock_iothread();
54 }
55
56 old_pending = env->pending_interrupts;
57
58 if (level) {
59 env->pending_interrupts |= 1 << n_IRQ;
60 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
61 } else {
62 env->pending_interrupts &= ~(1 << n_IRQ);
63 if (env->pending_interrupts == 0) {
64 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
65 }
66 }
67
68 if (old_pending != env->pending_interrupts) {
69 kvmppc_set_interrupt(cpu, n_IRQ, level);
70 }
71
72
73 trace_ppc_irq_set_exit(env, n_IRQ, level, env->pending_interrupts,
74 CPU(cpu)->interrupt_request);
75
76 if (locked) {
77 qemu_mutex_unlock_iothread();
78 }
79 }
80
81 /* PowerPC 6xx / 7xx internal IRQ controller */
82 static void ppc6xx_set_irq(void *opaque, int pin, int level)
83 {
84 PowerPCCPU *cpu = opaque;
85 CPUPPCState *env = &cpu->env;
86 int cur_level;
87
88 trace_ppc_irq_set(env, pin, level);
89
90 cur_level = (env->irq_input_state >> pin) & 1;
91 /* Don't generate spurious events */
92 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
93 CPUState *cs = CPU(cpu);
94
95 switch (pin) {
96 case PPC6xx_INPUT_TBEN:
97 /* Level sensitive - active high */
98 trace_ppc_irq_set_state("time base", level);
99 if (level) {
100 cpu_ppc_tb_start(env);
101 } else {
102 cpu_ppc_tb_stop(env);
103 }
104 break;
105 case PPC6xx_INPUT_INT:
106 /* Level sensitive - active high */
107 trace_ppc_irq_set_state("external IRQ", level);
108 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
109 break;
110 case PPC6xx_INPUT_SMI:
111 /* Level sensitive - active high */
112 trace_ppc_irq_set_state("SMI IRQ", level);
113 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
114 break;
115 case PPC6xx_INPUT_MCP:
116 /* Negative edge sensitive */
117 /* XXX: TODO: actual reaction may depends on HID0 status
118 * 603/604/740/750: check HID0[EMCP]
119 */
120 if (cur_level == 1 && level == 0) {
121 trace_ppc_irq_set_state("machine check", 1);
122 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
123 }
124 break;
125 case PPC6xx_INPUT_CKSTP_IN:
126 /* Level sensitive - active low */
127 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
128 /* XXX: Note that the only way to restart the CPU is to reset it */
129 if (level) {
130 trace_ppc_irq_cpu("stop");
131 cs->halted = 1;
132 }
133 break;
134 case PPC6xx_INPUT_HRESET:
135 /* Level sensitive - active low */
136 if (level) {
137 trace_ppc_irq_reset("CPU");
138 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
139 }
140 break;
141 case PPC6xx_INPUT_SRESET:
142 trace_ppc_irq_set_state("RESET IRQ", level);
143 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
144 break;
145 default:
146 g_assert_not_reached();
147 }
148 if (level)
149 env->irq_input_state |= 1 << pin;
150 else
151 env->irq_input_state &= ~(1 << pin);
152 }
153 }
154
155 void ppc6xx_irq_init(PowerPCCPU *cpu)
156 {
157 CPUPPCState *env = &cpu->env;
158
159 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
160 PPC6xx_INPUT_NB);
161 }
162
163 #if defined(TARGET_PPC64)
164 /* PowerPC 970 internal IRQ controller */
165 static void ppc970_set_irq(void *opaque, int pin, int level)
166 {
167 PowerPCCPU *cpu = opaque;
168 CPUPPCState *env = &cpu->env;
169 int cur_level;
170
171 trace_ppc_irq_set(env, pin, level);
172
173 cur_level = (env->irq_input_state >> pin) & 1;
174 /* Don't generate spurious events */
175 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
176 CPUState *cs = CPU(cpu);
177
178 switch (pin) {
179 case PPC970_INPUT_INT:
180 /* Level sensitive - active high */
181 trace_ppc_irq_set_state("external IRQ", level);
182 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
183 break;
184 case PPC970_INPUT_THINT:
185 /* Level sensitive - active high */
186 trace_ppc_irq_set_state("SMI IRQ", level);
187 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
188 break;
189 case PPC970_INPUT_MCP:
190 /* Negative edge sensitive */
191 /* XXX: TODO: actual reaction may depends on HID0 status
192 * 603/604/740/750: check HID0[EMCP]
193 */
194 if (cur_level == 1 && level == 0) {
195 trace_ppc_irq_set_state("machine check", 1);
196 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
197 }
198 break;
199 case PPC970_INPUT_CKSTP:
200 /* Level sensitive - active low */
201 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
202 if (level) {
203 trace_ppc_irq_cpu("stop");
204 cs->halted = 1;
205 } else {
206 trace_ppc_irq_cpu("restart");
207 cs->halted = 0;
208 qemu_cpu_kick(cs);
209 }
210 break;
211 case PPC970_INPUT_HRESET:
212 /* Level sensitive - active low */
213 if (level) {
214 cpu_interrupt(cs, CPU_INTERRUPT_RESET);
215 }
216 break;
217 case PPC970_INPUT_SRESET:
218 trace_ppc_irq_set_state("RESET IRQ", level);
219 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
220 break;
221 case PPC970_INPUT_TBEN:
222 trace_ppc_irq_set_state("TBEN IRQ", level);
223 /* XXX: TODO */
224 break;
225 default:
226 g_assert_not_reached();
227 }
228 if (level)
229 env->irq_input_state |= 1 << pin;
230 else
231 env->irq_input_state &= ~(1 << pin);
232 }
233 }
234
235 void ppc970_irq_init(PowerPCCPU *cpu)
236 {
237 CPUPPCState *env = &cpu->env;
238
239 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu,
240 PPC970_INPUT_NB);
241 }
242
243 /* POWER7 internal IRQ controller */
244 static void power7_set_irq(void *opaque, int pin, int level)
245 {
246 PowerPCCPU *cpu = opaque;
247
248 trace_ppc_irq_set(&cpu->env, pin, level);
249
250 switch (pin) {
251 case POWER7_INPUT_INT:
252 /* Level sensitive - active high */
253 trace_ppc_irq_set_state("external IRQ", level);
254 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
255 break;
256 default:
257 g_assert_not_reached();
258 }
259 }
260
261 void ppcPOWER7_irq_init(PowerPCCPU *cpu)
262 {
263 CPUPPCState *env = &cpu->env;
264
265 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
266 POWER7_INPUT_NB);
267 }
268
269 /* POWER9 internal IRQ controller */
270 static void power9_set_irq(void *opaque, int pin, int level)
271 {
272 PowerPCCPU *cpu = opaque;
273
274 trace_ppc_irq_set(&cpu->env, pin, level);
275
276 switch (pin) {
277 case POWER9_INPUT_INT:
278 /* Level sensitive - active high */
279 trace_ppc_irq_set_state("external IRQ", level);
280 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
281 break;
282 case POWER9_INPUT_HINT:
283 /* Level sensitive - active high */
284 trace_ppc_irq_set_state("HV external IRQ", level);
285 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level);
286 break;
287 default:
288 g_assert_not_reached();
289 return;
290 }
291 }
292
293 void ppcPOWER9_irq_init(PowerPCCPU *cpu)
294 {
295 CPUPPCState *env = &cpu->env;
296
297 env->irq_inputs = (void **)qemu_allocate_irqs(&power9_set_irq, cpu,
298 POWER9_INPUT_NB);
299 }
300 #endif /* defined(TARGET_PPC64) */
301
302 void ppc40x_core_reset(PowerPCCPU *cpu)
303 {
304 CPUPPCState *env = &cpu->env;
305 target_ulong dbsr;
306
307 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n");
308 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
309 dbsr = env->spr[SPR_40x_DBSR];
310 dbsr &= ~0x00000300;
311 dbsr |= 0x00000100;
312 env->spr[SPR_40x_DBSR] = dbsr;
313 }
314
315 void ppc40x_chip_reset(PowerPCCPU *cpu)
316 {
317 CPUPPCState *env = &cpu->env;
318 target_ulong dbsr;
319
320 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n");
321 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
322 /* XXX: TODO reset all internal peripherals */
323 dbsr = env->spr[SPR_40x_DBSR];
324 dbsr &= ~0x00000300;
325 dbsr |= 0x00000200;
326 env->spr[SPR_40x_DBSR] = dbsr;
327 }
328
329 void ppc40x_system_reset(PowerPCCPU *cpu)
330 {
331 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n");
332 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
333 }
334
335 void store_40x_dbcr0(CPUPPCState *env, uint32_t val)
336 {
337 PowerPCCPU *cpu = env_archcpu(env);
338
339 switch ((val >> 28) & 0x3) {
340 case 0x0:
341 /* No action */
342 break;
343 case 0x1:
344 /* Core reset */
345 ppc40x_core_reset(cpu);
346 break;
347 case 0x2:
348 /* Chip reset */
349 ppc40x_chip_reset(cpu);
350 break;
351 case 0x3:
352 /* System reset */
353 ppc40x_system_reset(cpu);
354 break;
355 }
356 }
357
358 /* PowerPC 40x internal IRQ controller */
359 static void ppc40x_set_irq(void *opaque, int pin, int level)
360 {
361 PowerPCCPU *cpu = opaque;
362 CPUPPCState *env = &cpu->env;
363 int cur_level;
364
365 trace_ppc_irq_set(env, pin, level);
366
367 cur_level = (env->irq_input_state >> pin) & 1;
368 /* Don't generate spurious events */
369 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
370 CPUState *cs = CPU(cpu);
371
372 switch (pin) {
373 case PPC40x_INPUT_RESET_SYS:
374 if (level) {
375 trace_ppc_irq_reset("system");
376 ppc40x_system_reset(cpu);
377 }
378 break;
379 case PPC40x_INPUT_RESET_CHIP:
380 if (level) {
381 trace_ppc_irq_reset("chip");
382 ppc40x_chip_reset(cpu);
383 }
384 break;
385 case PPC40x_INPUT_RESET_CORE:
386 /* XXX: TODO: update DBSR[MRR] */
387 if (level) {
388 trace_ppc_irq_reset("core");
389 ppc40x_core_reset(cpu);
390 }
391 break;
392 case PPC40x_INPUT_CINT:
393 /* Level sensitive - active high */
394 trace_ppc_irq_set_state("critical IRQ", level);
395 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
396 break;
397 case PPC40x_INPUT_INT:
398 /* Level sensitive - active high */
399 trace_ppc_irq_set_state("external IRQ", level);
400 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
401 break;
402 case PPC40x_INPUT_HALT:
403 /* Level sensitive - active low */
404 if (level) {
405 trace_ppc_irq_cpu("stop");
406 cs->halted = 1;
407 } else {
408 trace_ppc_irq_cpu("restart");
409 cs->halted = 0;
410 qemu_cpu_kick(cs);
411 }
412 break;
413 case PPC40x_INPUT_DEBUG:
414 /* Level sensitive - active high */
415 trace_ppc_irq_set_state("debug pin", level);
416 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
417 break;
418 default:
419 g_assert_not_reached();
420 }
421 if (level)
422 env->irq_input_state |= 1 << pin;
423 else
424 env->irq_input_state &= ~(1 << pin);
425 }
426 }
427
428 void ppc40x_irq_init(PowerPCCPU *cpu)
429 {
430 CPUPPCState *env = &cpu->env;
431
432 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
433 cpu, PPC40x_INPUT_NB);
434 }
435
436 /* PowerPC E500 internal IRQ controller */
437 static void ppce500_set_irq(void *opaque, int pin, int level)
438 {
439 PowerPCCPU *cpu = opaque;
440 CPUPPCState *env = &cpu->env;
441 int cur_level;
442
443 trace_ppc_irq_set(env, pin, level);
444
445 cur_level = (env->irq_input_state >> pin) & 1;
446 /* Don't generate spurious events */
447 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
448 switch (pin) {
449 case PPCE500_INPUT_MCK:
450 if (level) {
451 trace_ppc_irq_reset("system");
452 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
453 }
454 break;
455 case PPCE500_INPUT_RESET_CORE:
456 if (level) {
457 trace_ppc_irq_reset("core");
458 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
459 }
460 break;
461 case PPCE500_INPUT_CINT:
462 /* Level sensitive - active high */
463 trace_ppc_irq_set_state("critical IRQ", level);
464 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
465 break;
466 case PPCE500_INPUT_INT:
467 /* Level sensitive - active high */
468 trace_ppc_irq_set_state("core IRQ", level);
469 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
470 break;
471 case PPCE500_INPUT_DEBUG:
472 /* Level sensitive - active high */
473 trace_ppc_irq_set_state("debug pin", level);
474 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
475 break;
476 default:
477 g_assert_not_reached();
478 }
479 if (level)
480 env->irq_input_state |= 1 << pin;
481 else
482 env->irq_input_state &= ~(1 << pin);
483 }
484 }
485
486 void ppce500_irq_init(PowerPCCPU *cpu)
487 {
488 CPUPPCState *env = &cpu->env;
489
490 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
491 cpu, PPCE500_INPUT_NB);
492 }
493
494 /* Enable or Disable the E500 EPR capability */
495 void ppce500_set_mpic_proxy(bool enabled)
496 {
497 CPUState *cs;
498
499 CPU_FOREACH(cs) {
500 PowerPCCPU *cpu = POWERPC_CPU(cs);
501
502 cpu->env.mpic_proxy = enabled;
503 if (kvm_enabled()) {
504 kvmppc_set_mpic_proxy(cpu, enabled);
505 }
506 }
507 }
508
509 /*****************************************************************************/
510 /* PowerPC time base and decrementer emulation */
511
512 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
513 {
514 /* TB time in tb periods */
515 return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset;
516 }
517
518 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
519 {
520 ppc_tb_t *tb_env = env->tb_env;
521 uint64_t tb;
522
523 if (kvm_enabled()) {
524 return env->spr[SPR_TBL];
525 }
526
527 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
528 trace_ppc_tb_load(tb);
529
530 return tb;
531 }
532
533 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
534 {
535 ppc_tb_t *tb_env = env->tb_env;
536 uint64_t tb;
537
538 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
539 trace_ppc_tb_load(tb);
540
541 return tb >> 32;
542 }
543
544 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
545 {
546 if (kvm_enabled()) {
547 return env->spr[SPR_TBU];
548 }
549
550 return _cpu_ppc_load_tbu(env);
551 }
552
553 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
554 int64_t *tb_offsetp, uint64_t value)
555 {
556 *tb_offsetp = value -
557 muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND);
558
559 trace_ppc_tb_store(value, *tb_offsetp);
560 }
561
562 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
563 {
564 ppc_tb_t *tb_env = env->tb_env;
565 uint64_t tb;
566
567 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
568 tb &= 0xFFFFFFFF00000000ULL;
569 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
570 &tb_env->tb_offset, tb | (uint64_t)value);
571 }
572
573 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
574 {
575 ppc_tb_t *tb_env = env->tb_env;
576 uint64_t tb;
577
578 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset);
579 tb &= 0x00000000FFFFFFFFULL;
580 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
581 &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
582 }
583
584 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
585 {
586 _cpu_ppc_store_tbu(env, value);
587 }
588
589 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
590 {
591 ppc_tb_t *tb_env = env->tb_env;
592 uint64_t tb;
593
594 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
595 trace_ppc_tb_load(tb);
596
597 return tb;
598 }
599
600 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
601 {
602 ppc_tb_t *tb_env = env->tb_env;
603 uint64_t tb;
604
605 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
606 trace_ppc_tb_load(tb);
607
608 return tb >> 32;
609 }
610
611 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
612 {
613 ppc_tb_t *tb_env = env->tb_env;
614 uint64_t tb;
615
616 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
617 tb &= 0xFFFFFFFF00000000ULL;
618 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
619 &tb_env->atb_offset, tb | (uint64_t)value);
620 }
621
622 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
623 {
624 ppc_tb_t *tb_env = env->tb_env;
625 uint64_t tb;
626
627 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset);
628 tb &= 0x00000000FFFFFFFFULL;
629 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
630 &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
631 }
632
633 uint64_t cpu_ppc_load_vtb(CPUPPCState *env)
634 {
635 ppc_tb_t *tb_env = env->tb_env;
636
637 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
638 tb_env->vtb_offset);
639 }
640
641 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value)
642 {
643 ppc_tb_t *tb_env = env->tb_env;
644
645 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
646 &tb_env->vtb_offset, value);
647 }
648
649 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value)
650 {
651 ppc_tb_t *tb_env = env->tb_env;
652 uint64_t tb;
653
654 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
655 tb_env->tb_offset);
656 tb &= 0xFFFFFFUL;
657 tb |= (value & ~0xFFFFFFUL);
658 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
659 &tb_env->tb_offset, tb);
660 }
661
662 static void cpu_ppc_tb_stop (CPUPPCState *env)
663 {
664 ppc_tb_t *tb_env = env->tb_env;
665 uint64_t tb, atb, vmclk;
666
667 /* If the time base is already frozen, do nothing */
668 if (tb_env->tb_freq != 0) {
669 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
670 /* Get the time base */
671 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
672 /* Get the alternate time base */
673 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
674 /* Store the time base value (ie compute the current offset) */
675 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
676 /* Store the alternate time base value (compute the current offset) */
677 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
678 /* Set the time base frequency to zero */
679 tb_env->tb_freq = 0;
680 /* Now, the time bases are frozen to tb_offset / atb_offset value */
681 }
682 }
683
684 static void cpu_ppc_tb_start (CPUPPCState *env)
685 {
686 ppc_tb_t *tb_env = env->tb_env;
687 uint64_t tb, atb, vmclk;
688
689 /* If the time base is not frozen, do nothing */
690 if (tb_env->tb_freq == 0) {
691 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
692 /* Get the time base from tb_offset */
693 tb = tb_env->tb_offset;
694 /* Get the alternate time base from atb_offset */
695 atb = tb_env->atb_offset;
696 /* Restore the tb frequency from the decrementer frequency */
697 tb_env->tb_freq = tb_env->decr_freq;
698 /* Store the time base value */
699 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
700 /* Store the alternate time base value */
701 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
702 }
703 }
704
705 bool ppc_decr_clear_on_delivery(CPUPPCState *env)
706 {
707 ppc_tb_t *tb_env = env->tb_env;
708 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL;
709 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED);
710 }
711
712 static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
713 {
714 ppc_tb_t *tb_env = env->tb_env;
715 int64_t decr, diff;
716
717 diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
718 if (diff >= 0) {
719 decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
720 } else if (tb_env->flags & PPC_TIMER_BOOKE) {
721 decr = 0;
722 } else {
723 decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND);
724 }
725 trace_ppc_decr_load(decr);
726
727 return decr;
728 }
729
730 target_ulong cpu_ppc_load_decr(CPUPPCState *env)
731 {
732 ppc_tb_t *tb_env = env->tb_env;
733 uint64_t decr;
734
735 if (kvm_enabled()) {
736 return env->spr[SPR_DECR];
737 }
738
739 decr = _cpu_ppc_load_decr(env, tb_env->decr_next);
740
741 /*
742 * If large decrementer is enabled then the decrementer is signed extened
743 * to 64 bits, otherwise it is a 32 bit value.
744 */
745 if (env->spr[SPR_LPCR] & LPCR_LD) {
746 return decr;
747 }
748 return (uint32_t) decr;
749 }
750
751 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env)
752 {
753 PowerPCCPU *cpu = env_archcpu(env);
754 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
755 ppc_tb_t *tb_env = env->tb_env;
756 uint64_t hdecr;
757
758 hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next);
759
760 /*
761 * If we have a large decrementer (POWER9 or later) then hdecr is sign
762 * extended to 64 bits, otherwise it is 32 bits.
763 */
764 if (pcc->lrg_decr_bits > 32) {
765 return hdecr;
766 }
767 return (uint32_t) hdecr;
768 }
769
770 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
771 {
772 ppc_tb_t *tb_env = env->tb_env;
773
774 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
775 tb_env->purr_offset);
776 }
777
778 /* When decrementer expires,
779 * all we need to do is generate or queue a CPU exception
780 */
781 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
782 {
783 /* Raise it */
784 trace_ppc_decr_excp("raise");
785 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
786 }
787
788 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu)
789 {
790 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0);
791 }
792
793 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
794 {
795 CPUPPCState *env = &cpu->env;
796
797 /* Raise it */
798 trace_ppc_decr_excp("raise HV");
799
800 /* The architecture specifies that we don't deliver HDEC
801 * interrupts in a PM state. Not only they don't cause a
802 * wakeup but they also get effectively discarded.
803 */
804 if (!env->resume_as_sreset) {
805 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
806 }
807 }
808
809 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu)
810 {
811 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0);
812 }
813
814 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
815 QEMUTimer *timer,
816 void (*raise_excp)(void *),
817 void (*lower_excp)(PowerPCCPU *),
818 target_ulong decr, target_ulong value,
819 int nr_bits)
820 {
821 CPUPPCState *env = &cpu->env;
822 ppc_tb_t *tb_env = env->tb_env;
823 uint64_t now, next;
824 bool negative;
825
826 /* Truncate value to decr_width and sign extend for simplicity */
827 value &= ((1ULL << nr_bits) - 1);
828 negative = !!(value & (1ULL << (nr_bits - 1)));
829 if (negative) {
830 value |= (0xFFFFFFFFULL << nr_bits);
831 }
832
833 trace_ppc_decr_store(nr_bits, decr, value);
834
835 if (kvm_enabled()) {
836 /* KVM handles decrementer exceptions, we don't need our own timer */
837 return;
838 }
839
840 /*
841 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC
842 * interrupt.
843 *
844 * If we get a really small DEC value, we can assume that by the time we
845 * handled it we should inject an interrupt already.
846 *
847 * On MSB level based DEC implementations the MSB always means the interrupt
848 * is pending, so raise it on those.
849 *
850 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers
851 * an edge interrupt, so raise it here too.
852 */
853 if ((value < 3) ||
854 ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && negative) ||
855 ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && negative
856 && !(decr & (1ULL << (nr_bits - 1))))) {
857 (*raise_excp)(cpu);
858 return;
859 }
860
861 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */
862 if (!negative && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) {
863 (*lower_excp)(cpu);
864 }
865
866 /* Calculate the next timer event */
867 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
868 next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq);
869 *nextp = next;
870
871 /* Adjust timer */
872 timer_mod(timer, next);
873 }
874
875 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr,
876 target_ulong value, int nr_bits)
877 {
878 ppc_tb_t *tb_env = cpu->env.tb_env;
879
880 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer,
881 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr,
882 value, nr_bits);
883 }
884
885 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value)
886 {
887 PowerPCCPU *cpu = env_archcpu(env);
888 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
889 int nr_bits = 32;
890
891 if (env->spr[SPR_LPCR] & LPCR_LD) {
892 nr_bits = pcc->lrg_decr_bits;
893 }
894
895 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits);
896 }
897
898 static void cpu_ppc_decr_cb(void *opaque)
899 {
900 PowerPCCPU *cpu = opaque;
901
902 cpu_ppc_decr_excp(cpu);
903 }
904
905 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr,
906 target_ulong value, int nr_bits)
907 {
908 ppc_tb_t *tb_env = cpu->env.tb_env;
909
910 if (tb_env->hdecr_timer != NULL) {
911 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer,
912 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower,
913 hdecr, value, nr_bits);
914 }
915 }
916
917 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value)
918 {
919 PowerPCCPU *cpu = env_archcpu(env);
920 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
921
922 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value,
923 pcc->lrg_decr_bits);
924 }
925
926 static void cpu_ppc_hdecr_cb(void *opaque)
927 {
928 PowerPCCPU *cpu = opaque;
929
930 cpu_ppc_hdecr_excp(cpu);
931 }
932
933 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value)
934 {
935 ppc_tb_t *tb_env = env->tb_env;
936
937 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
938 &tb_env->purr_offset, value);
939 }
940
941 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
942 {
943 CPUPPCState *env = opaque;
944 PowerPCCPU *cpu = env_archcpu(env);
945 ppc_tb_t *tb_env = env->tb_env;
946
947 tb_env->tb_freq = freq;
948 tb_env->decr_freq = freq;
949 /* There is a bug in Linux 2.4 kernels:
950 * if a decrementer exception is pending when it enables msr_ee at startup,
951 * it's not ready to handle it...
952 */
953 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32);
954 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32);
955 cpu_ppc_store_purr(env, 0x0000000000000000ULL);
956 }
957
958 static void timebase_save(PPCTimebase *tb)
959 {
960 uint64_t ticks = cpu_get_host_ticks();
961 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
962
963 if (!first_ppc_cpu->env.tb_env) {
964 error_report("No timebase object");
965 return;
966 }
967
968 /* not used anymore, we keep it for compatibility */
969 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST);
970 /*
971 * tb_offset is only expected to be changed by QEMU so
972 * there is no need to update it from KVM here
973 */
974 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset;
975
976 tb->runstate_paused =
977 runstate_check(RUN_STATE_PAUSED) || runstate_check(RUN_STATE_SAVE_VM);
978 }
979
980 static void timebase_load(PPCTimebase *tb)
981 {
982 CPUState *cpu;
983 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
984 int64_t tb_off_adj, tb_off;
985 unsigned long freq;
986
987 if (!first_ppc_cpu->env.tb_env) {
988 error_report("No timebase object");
989 return;
990 }
991
992 freq = first_ppc_cpu->env.tb_env->tb_freq;
993
994 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks();
995
996 tb_off = first_ppc_cpu->env.tb_env->tb_offset;
997 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off,
998 (tb_off_adj - tb_off) / freq);
999
1000 /* Set new offset to all CPUs */
1001 CPU_FOREACH(cpu) {
1002 PowerPCCPU *pcpu = POWERPC_CPU(cpu);
1003 pcpu->env.tb_env->tb_offset = tb_off_adj;
1004 kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset);
1005 }
1006 }
1007
1008 void cpu_ppc_clock_vm_state_change(void *opaque, bool running,
1009 RunState state)
1010 {
1011 PPCTimebase *tb = opaque;
1012
1013 if (running) {
1014 timebase_load(tb);
1015 } else {
1016 timebase_save(tb);
1017 }
1018 }
1019
1020 /*
1021 * When migrating a running guest, read the clock just
1022 * before migration, so that the guest clock counts
1023 * during the events between:
1024 *
1025 * * vm_stop()
1026 * *
1027 * * pre_save()
1028 *
1029 * This reduces clock difference on migration from 5s
1030 * to 0.1s (when max_downtime == 5s), because sending the
1031 * final pages of memory (which happens between vm_stop()
1032 * and pre_save()) takes max_downtime.
1033 */
1034 static int timebase_pre_save(void *opaque)
1035 {
1036 PPCTimebase *tb = opaque;
1037
1038 /* guest_timebase won't be overridden in case of paused guest or savevm */
1039 if (!tb->runstate_paused) {
1040 timebase_save(tb);
1041 }
1042
1043 return 0;
1044 }
1045
1046 const VMStateDescription vmstate_ppc_timebase = {
1047 .name = "timebase",
1048 .version_id = 1,
1049 .minimum_version_id = 1,
1050 .minimum_version_id_old = 1,
1051 .pre_save = timebase_pre_save,
1052 .fields = (VMStateField []) {
1053 VMSTATE_UINT64(guest_timebase, PPCTimebase),
1054 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase),
1055 VMSTATE_END_OF_LIST()
1056 },
1057 };
1058
1059 /* Set up (once) timebase frequency (in Hz) */
1060 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
1061 {
1062 PowerPCCPU *cpu = env_archcpu(env);
1063 ppc_tb_t *tb_env;
1064
1065 tb_env = g_malloc0(sizeof(ppc_tb_t));
1066 env->tb_env = tb_env;
1067 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1068 if (is_book3s_arch2x(env)) {
1069 /* All Book3S 64bit CPUs implement level based DEC logic */
1070 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL;
1071 }
1072 /* Create new timer */
1073 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu);
1074 if (env->has_hv_mode) {
1075 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb,
1076 cpu);
1077 } else {
1078 tb_env->hdecr_timer = NULL;
1079 }
1080 cpu_ppc_set_tb_clk(env, freq);
1081
1082 return &cpu_ppc_set_tb_clk;
1083 }
1084
1085 /* Specific helpers for POWER & PowerPC 601 RTC */
1086 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)
1087 {
1088 _cpu_ppc_store_tbu(env, value);
1089 }
1090
1091 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)
1092 {
1093 return _cpu_ppc_load_tbu(env);
1094 }
1095
1096 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)
1097 {
1098 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
1099 }
1100
1101 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)
1102 {
1103 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
1104 }
1105
1106 /*****************************************************************************/
1107 /* PowerPC 40x timers */
1108
1109 /* PIT, FIT & WDT */
1110 typedef struct ppc40x_timer_t ppc40x_timer_t;
1111 struct ppc40x_timer_t {
1112 uint64_t pit_reload; /* PIT auto-reload value */
1113 uint64_t fit_next; /* Tick for next FIT interrupt */
1114 QEMUTimer *fit_timer;
1115 uint64_t wdt_next; /* Tick for next WDT interrupt */
1116 QEMUTimer *wdt_timer;
1117
1118 /* 405 have the PIT, 440 have a DECR. */
1119 unsigned int decr_excp;
1120 };
1121
1122 /* Fixed interval timer */
1123 static void cpu_4xx_fit_cb (void *opaque)
1124 {
1125 PowerPCCPU *cpu;
1126 CPUPPCState *env;
1127 ppc_tb_t *tb_env;
1128 ppc40x_timer_t *ppc40x_timer;
1129 uint64_t now, next;
1130
1131 env = opaque;
1132 cpu = env_archcpu(env);
1133 tb_env = env->tb_env;
1134 ppc40x_timer = tb_env->opaque;
1135 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1136 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
1137 case 0:
1138 next = 1 << 9;
1139 break;
1140 case 1:
1141 next = 1 << 13;
1142 break;
1143 case 2:
1144 next = 1 << 17;
1145 break;
1146 case 3:
1147 next = 1 << 21;
1148 break;
1149 default:
1150 /* Cannot occur, but makes gcc happy */
1151 return;
1152 }
1153 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq);
1154 if (next == now)
1155 next++;
1156 timer_mod(ppc40x_timer->fit_timer, next);
1157 env->spr[SPR_40x_TSR] |= 1 << 26;
1158 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
1159 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
1160 }
1161 trace_ppc4xx_fit((int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
1162 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1163 }
1164
1165 /* Programmable interval timer */
1166 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
1167 {
1168 ppc40x_timer_t *ppc40x_timer;
1169 uint64_t now, next;
1170
1171 ppc40x_timer = tb_env->opaque;
1172 if (ppc40x_timer->pit_reload <= 1 ||
1173 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
1174 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
1175 /* Stop PIT */
1176 trace_ppc4xx_pit_stop();
1177 timer_del(tb_env->decr_timer);
1178 } else {
1179 trace_ppc4xx_pit_start(ppc40x_timer->pit_reload);
1180 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1181 next = now + muldiv64(ppc40x_timer->pit_reload,
1182 NANOSECONDS_PER_SECOND, tb_env->decr_freq);
1183 if (is_excp)
1184 next += tb_env->decr_next - now;
1185 if (next == now)
1186 next++;
1187 timer_mod(tb_env->decr_timer, next);
1188 tb_env->decr_next = next;
1189 }
1190 }
1191
1192 static void cpu_4xx_pit_cb (void *opaque)
1193 {
1194 PowerPCCPU *cpu;
1195 CPUPPCState *env;
1196 ppc_tb_t *tb_env;
1197 ppc40x_timer_t *ppc40x_timer;
1198
1199 env = opaque;
1200 cpu = env_archcpu(env);
1201 tb_env = env->tb_env;
1202 ppc40x_timer = tb_env->opaque;
1203 env->spr[SPR_40x_TSR] |= 1 << 27;
1204 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
1205 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
1206 }
1207 start_stop_pit(env, tb_env, 1);
1208 trace_ppc4xx_pit((int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
1209 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
1210 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
1211 ppc40x_timer->pit_reload);
1212 }
1213
1214 /* Watchdog timer */
1215 static void cpu_4xx_wdt_cb (void *opaque)
1216 {
1217 PowerPCCPU *cpu;
1218 CPUPPCState *env;
1219 ppc_tb_t *tb_env;
1220 ppc40x_timer_t *ppc40x_timer;
1221 uint64_t now, next;
1222
1223 env = opaque;
1224 cpu = env_archcpu(env);
1225 tb_env = env->tb_env;
1226 ppc40x_timer = tb_env->opaque;
1227 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1228 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
1229 case 0:
1230 next = 1 << 17;
1231 break;
1232 case 1:
1233 next = 1 << 21;
1234 break;
1235 case 2:
1236 next = 1 << 25;
1237 break;
1238 case 3:
1239 next = 1 << 29;
1240 break;
1241 default:
1242 /* Cannot occur, but makes gcc happy */
1243 return;
1244 }
1245 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq);
1246 if (next == now)
1247 next++;
1248 trace_ppc4xx_wdt(env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
1249 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
1250 case 0x0:
1251 case 0x1:
1252 timer_mod(ppc40x_timer->wdt_timer, next);
1253 ppc40x_timer->wdt_next = next;
1254 env->spr[SPR_40x_TSR] |= 1U << 31;
1255 break;
1256 case 0x2:
1257 timer_mod(ppc40x_timer->wdt_timer, next);
1258 ppc40x_timer->wdt_next = next;
1259 env->spr[SPR_40x_TSR] |= 1 << 30;
1260 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
1261 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
1262 }
1263 break;
1264 case 0x3:
1265 env->spr[SPR_40x_TSR] &= ~0x30000000;
1266 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
1267 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
1268 case 0x0:
1269 /* No reset */
1270 break;
1271 case 0x1: /* Core reset */
1272 ppc40x_core_reset(cpu);
1273 break;
1274 case 0x2: /* Chip reset */
1275 ppc40x_chip_reset(cpu);
1276 break;
1277 case 0x3: /* System reset */
1278 ppc40x_system_reset(cpu);
1279 break;
1280 }
1281 }
1282 }
1283
1284 void store_40x_pit (CPUPPCState *env, target_ulong val)
1285 {
1286 ppc_tb_t *tb_env;
1287 ppc40x_timer_t *ppc40x_timer;
1288
1289 tb_env = env->tb_env;
1290 ppc40x_timer = tb_env->opaque;
1291 trace_ppc40x_store_pit(val);
1292 ppc40x_timer->pit_reload = val;
1293 start_stop_pit(env, tb_env, 0);
1294 }
1295
1296 target_ulong load_40x_pit (CPUPPCState *env)
1297 {
1298 return cpu_ppc_load_decr(env);
1299 }
1300
1301 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1302 {
1303 CPUPPCState *env = opaque;
1304 ppc_tb_t *tb_env = env->tb_env;
1305
1306 trace_ppc40x_set_tb_clk(freq);
1307 tb_env->tb_freq = freq;
1308 tb_env->decr_freq = freq;
1309 /* XXX: we should also update all timers */
1310 }
1311
1312 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1313 unsigned int decr_excp)
1314 {
1315 ppc_tb_t *tb_env;
1316 ppc40x_timer_t *ppc40x_timer;
1317
1318 tb_env = g_malloc0(sizeof(ppc_tb_t));
1319 env->tb_env = tb_env;
1320 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1321 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
1322 tb_env->tb_freq = freq;
1323 tb_env->decr_freq = freq;
1324 tb_env->opaque = ppc40x_timer;
1325 trace_ppc40x_timers_init(freq);
1326 if (ppc40x_timer != NULL) {
1327 /* We use decr timer for PIT */
1328 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env);
1329 ppc40x_timer->fit_timer =
1330 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env);
1331 ppc40x_timer->wdt_timer =
1332 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env);
1333 ppc40x_timer->decr_excp = decr_excp;
1334 }
1335
1336 return &ppc_40x_set_tb_clk;
1337 }
1338
1339 /*****************************************************************************/
1340 /* Embedded PowerPC Device Control Registers */
1341 typedef struct ppc_dcrn_t ppc_dcrn_t;
1342 struct ppc_dcrn_t {
1343 dcr_read_cb dcr_read;
1344 dcr_write_cb dcr_write;
1345 void *opaque;
1346 };
1347
1348 /* XXX: on 460, DCR addresses are 32 bits wide,
1349 * using DCRIPR to get the 22 upper bits of the DCR address
1350 */
1351 #define DCRN_NB 1024
1352 struct ppc_dcr_t {
1353 ppc_dcrn_t dcrn[DCRN_NB];
1354 int (*read_error)(int dcrn);
1355 int (*write_error)(int dcrn);
1356 };
1357
1358 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1359 {
1360 ppc_dcrn_t *dcr;
1361
1362 if (dcrn < 0 || dcrn >= DCRN_NB)
1363 goto error;
1364 dcr = &dcr_env->dcrn[dcrn];
1365 if (dcr->dcr_read == NULL)
1366 goto error;
1367 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1368
1369 return 0;
1370
1371 error:
1372 if (dcr_env->read_error != NULL)
1373 return (*dcr_env->read_error)(dcrn);
1374
1375 return -1;
1376 }
1377
1378 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1379 {
1380 ppc_dcrn_t *dcr;
1381
1382 if (dcrn < 0 || dcrn >= DCRN_NB)
1383 goto error;
1384 dcr = &dcr_env->dcrn[dcrn];
1385 if (dcr->dcr_write == NULL)
1386 goto error;
1387 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1388
1389 return 0;
1390
1391 error:
1392 if (dcr_env->write_error != NULL)
1393 return (*dcr_env->write_error)(dcrn);
1394
1395 return -1;
1396 }
1397
1398 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1399 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1400 {
1401 ppc_dcr_t *dcr_env;
1402 ppc_dcrn_t *dcr;
1403
1404 dcr_env = env->dcr_env;
1405 if (dcr_env == NULL)
1406 return -1;
1407 if (dcrn < 0 || dcrn >= DCRN_NB)
1408 return -1;
1409 dcr = &dcr_env->dcrn[dcrn];
1410 if (dcr->opaque != NULL ||
1411 dcr->dcr_read != NULL ||
1412 dcr->dcr_write != NULL)
1413 return -1;
1414 dcr->opaque = opaque;
1415 dcr->dcr_read = dcr_read;
1416 dcr->dcr_write = dcr_write;
1417
1418 return 0;
1419 }
1420
1421 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1422 int (*write_error)(int dcrn))
1423 {
1424 ppc_dcr_t *dcr_env;
1425
1426 dcr_env = g_malloc0(sizeof(ppc_dcr_t));
1427 dcr_env->read_error = read_error;
1428 dcr_env->write_error = write_error;
1429 env->dcr_env = dcr_env;
1430
1431 return 0;
1432 }
1433
1434 /*****************************************************************************/
1435
1436 int ppc_cpu_pir(PowerPCCPU *cpu)
1437 {
1438 CPUPPCState *env = &cpu->env;
1439 return env->spr_cb[SPR_PIR].default_value;
1440 }
1441
1442 PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
1443 {
1444 CPUState *cs;
1445
1446 CPU_FOREACH(cs) {
1447 PowerPCCPU *cpu = POWERPC_CPU(cs);
1448
1449 if (ppc_cpu_pir(cpu) == pir) {
1450 return cpu;
1451 }
1452 }
1453
1454 return NULL;
1455 }
1456
1457 void ppc_irq_reset(PowerPCCPU *cpu)
1458 {
1459 CPUPPCState *env = &cpu->env;
1460
1461 env->irq_input_state = 0;
1462 kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0);
1463 }
QEmu