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block: m25p80: Dummy cycles for N25Q256/512
[qemu.git] / target-mips / op_helper.c
blob8ec1bef7d034769c5181a3f5161bcf36bcc23bd1
1 /*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/cpu_ldst.h"
24 #include "sysemu/kvm.h"
25
26 /*****************************************************************************/
27 /* Exceptions processing helpers */
28
29 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
30 int error_code)
31 {
32 do_raise_exception_err(env, exception, error_code, 0);
33 }
34
35 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
36 {
37 do_raise_exception(env, exception, GETPC());
38 }
39
40 void helper_raise_exception_debug(CPUMIPSState *env)
41 {
42 do_raise_exception(env, EXCP_DEBUG, 0);
43 }
44
45 static void raise_exception(CPUMIPSState *env, uint32_t exception)
46 {
47 do_raise_exception(env, exception, 0);
48 }
49
50 #if defined(CONFIG_USER_ONLY)
51 #define HELPER_LD(name, insn, type) \
52 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
53 int mem_idx, uintptr_t retaddr) \
54 { \
55 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
56 }
57 #else
58 #define HELPER_LD(name, insn, type) \
59 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
60 int mem_idx, uintptr_t retaddr) \
61 { \
62 switch (mem_idx) \
63 { \
64 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
65 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
66 default: \
67 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
68 } \
69 }
70 #endif
71 HELPER_LD(lw, ldl, int32_t)
72 #if defined(TARGET_MIPS64)
73 HELPER_LD(ld, ldq, int64_t)
74 #endif
75 #undef HELPER_LD
76
77 #if defined(CONFIG_USER_ONLY)
78 #define HELPER_ST(name, insn, type) \
79 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
80 type val, int mem_idx, uintptr_t retaddr) \
81 { \
82 cpu_##insn##_data_ra(env, addr, val, retaddr); \
83 }
84 #else
85 #define HELPER_ST(name, insn, type) \
86 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
87 type val, int mem_idx, uintptr_t retaddr) \
88 { \
89 switch (mem_idx) \
90 { \
91 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
92 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
93 default: \
94 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
95 } \
96 }
97 #endif
98 HELPER_ST(sb, stb, uint8_t)
99 HELPER_ST(sw, stl, uint32_t)
100 #if defined(TARGET_MIPS64)
101 HELPER_ST(sd, stq, uint64_t)
102 #endif
103 #undef HELPER_ST
104
105 target_ulong helper_clo (target_ulong arg1)
106 {
107 return clo32(arg1);
108 }
109
110 target_ulong helper_clz (target_ulong arg1)
111 {
112 return clz32(arg1);
113 }
114
115 #if defined(TARGET_MIPS64)
116 target_ulong helper_dclo (target_ulong arg1)
117 {
118 return clo64(arg1);
119 }
120
121 target_ulong helper_dclz (target_ulong arg1)
122 {
123 return clz64(arg1);
124 }
125 #endif /* TARGET_MIPS64 */
126
127 /* 64 bits arithmetic for 32 bits hosts */
128 static inline uint64_t get_HILO(CPUMIPSState *env)
129 {
130 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
131 }
132
133 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
134 {
135 target_ulong tmp;
136 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
137 tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
138 return tmp;
139 }
140
141 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
142 {
143 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
144 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
145 return tmp;
146 }
147
148 /* Multiplication variants of the vr54xx. */
149 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
150 target_ulong arg2)
151 {
152 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
153 (int64_t)(int32_t)arg2));
154 }
155
156 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
157 target_ulong arg2)
158 {
159 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
160 (uint64_t)(uint32_t)arg2);
161 }
162
163 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
164 target_ulong arg2)
165 {
166 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
167 (int64_t)(int32_t)arg2);
168 }
169
170 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
171 target_ulong arg2)
172 {
173 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
174 (int64_t)(int32_t)arg2);
175 }
176
177 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
178 target_ulong arg2)
179 {
180 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
181 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
182 }
183
184 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
185 target_ulong arg2)
186 {
187 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
188 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
189 }
190
191 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
192 target_ulong arg2)
193 {
194 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
195 (int64_t)(int32_t)arg2);
196 }
197
198 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
199 target_ulong arg2)
200 {
201 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
202 (int64_t)(int32_t)arg2);
203 }
204
205 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
206 target_ulong arg2)
207 {
208 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
209 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
210 }
211
212 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
213 target_ulong arg2)
214 {
215 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
216 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
217 }
218
219 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
220 target_ulong arg2)
221 {
222 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
223 }
224
225 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
226 target_ulong arg2)
227 {
228 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
229 (uint64_t)(uint32_t)arg2);
230 }
231
232 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
233 target_ulong arg2)
234 {
235 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
236 (int64_t)(int32_t)arg2);
237 }
238
239 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
240 target_ulong arg2)
241 {
242 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
243 (uint64_t)(uint32_t)arg2);
244 }
245
246 static inline target_ulong bitswap(target_ulong v)
247 {
248 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
249 ((v & (target_ulong)0x5555555555555555ULL) << 1);
250 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
251 ((v & (target_ulong)0x3333333333333333ULL) << 2);
252 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
253 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
254 return v;
255 }
256
257 #ifdef TARGET_MIPS64
258 target_ulong helper_dbitswap(target_ulong rt)
259 {
260 return bitswap(rt);
261 }
262 #endif
263
264 target_ulong helper_bitswap(target_ulong rt)
265 {
266 return (int32_t)bitswap(rt);
267 }
268
269 #ifndef CONFIG_USER_ONLY
270
271 static inline hwaddr do_translate_address(CPUMIPSState *env,
272 target_ulong address,
273 int rw, uintptr_t retaddr)
274 {
275 hwaddr lladdr;
276 CPUState *cs = CPU(mips_env_get_cpu(env));
277
278 lladdr = cpu_mips_translate_address(env, address, rw);
279
280 if (lladdr == -1LL) {
281 cpu_loop_exit_restore(cs, retaddr);
282 } else {
283 return lladdr;
284 }
285 }
286
287 #define HELPER_LD_ATOMIC(name, insn, almask) \
288 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
289 { \
290 if (arg & almask) { \
291 env->CP0_BadVAddr = arg; \
292 do_raise_exception(env, EXCP_AdEL, GETPC()); \
293 } \
294 env->lladdr = do_translate_address(env, arg, 0, GETPC()); \
295 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
296 return env->llval; \
297 }
298 HELPER_LD_ATOMIC(ll, lw, 0x3)
299 #ifdef TARGET_MIPS64
300 HELPER_LD_ATOMIC(lld, ld, 0x7)
301 #endif
302 #undef HELPER_LD_ATOMIC
303
304 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
305 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
306 target_ulong arg2, int mem_idx) \
307 { \
308 target_long tmp; \
309 \
310 if (arg2 & almask) { \
311 env->CP0_BadVAddr = arg2; \
312 do_raise_exception(env, EXCP_AdES, GETPC()); \
313 } \
314 if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \
315 tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \
316 if (tmp == env->llval) { \
317 do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \
318 return 1; \
319 } \
320 } \
321 return 0; \
322 }
323 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
324 #ifdef TARGET_MIPS64
325 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
326 #endif
327 #undef HELPER_ST_ATOMIC
328 #endif
329
330 #ifdef TARGET_WORDS_BIGENDIAN
331 #define GET_LMASK(v) ((v) & 3)
332 #define GET_OFFSET(addr, offset) (addr + (offset))
333 #else
334 #define GET_LMASK(v) (((v) & 3) ^ 3)
335 #define GET_OFFSET(addr, offset) (addr - (offset))
336 #endif
337
338 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
339 int mem_idx)
340 {
341 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
342
343 if (GET_LMASK(arg2) <= 2) {
344 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
345 GETPC());
346 }
347
348 if (GET_LMASK(arg2) <= 1) {
349 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
350 GETPC());
351 }
352
353 if (GET_LMASK(arg2) == 0) {
354 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
355 GETPC());
356 }
357 }
358
359 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
360 int mem_idx)
361 {
362 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
363
364 if (GET_LMASK(arg2) >= 1) {
365 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
366 GETPC());
367 }
368
369 if (GET_LMASK(arg2) >= 2) {
370 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
371 GETPC());
372 }
373
374 if (GET_LMASK(arg2) == 3) {
375 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
376 GETPC());
377 }
378 }
379
380 #if defined(TARGET_MIPS64)
381 /* "half" load and stores. We must do the memory access inline,
382 or fault handling won't work. */
383
384 #ifdef TARGET_WORDS_BIGENDIAN
385 #define GET_LMASK64(v) ((v) & 7)
386 #else
387 #define GET_LMASK64(v) (((v) & 7) ^ 7)
388 #endif
389
390 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
391 int mem_idx)
392 {
393 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
394
395 if (GET_LMASK64(arg2) <= 6) {
396 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
397 GETPC());
398 }
399
400 if (GET_LMASK64(arg2) <= 5) {
401 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
402 GETPC());
403 }
404
405 if (GET_LMASK64(arg2) <= 4) {
406 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
407 GETPC());
408 }
409
410 if (GET_LMASK64(arg2) <= 3) {
411 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
412 GETPC());
413 }
414
415 if (GET_LMASK64(arg2) <= 2) {
416 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
417 GETPC());
418 }
419
420 if (GET_LMASK64(arg2) <= 1) {
421 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
422 GETPC());
423 }
424
425 if (GET_LMASK64(arg2) <= 0) {
426 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
427 GETPC());
428 }
429 }
430
431 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
432 int mem_idx)
433 {
434 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
435
436 if (GET_LMASK64(arg2) >= 1) {
437 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
438 GETPC());
439 }
440
441 if (GET_LMASK64(arg2) >= 2) {
442 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
443 GETPC());
444 }
445
446 if (GET_LMASK64(arg2) >= 3) {
447 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
448 GETPC());
449 }
450
451 if (GET_LMASK64(arg2) >= 4) {
452 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
453 GETPC());
454 }
455
456 if (GET_LMASK64(arg2) >= 5) {
457 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
458 GETPC());
459 }
460
461 if (GET_LMASK64(arg2) >= 6) {
462 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
463 GETPC());
464 }
465
466 if (GET_LMASK64(arg2) == 7) {
467 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
468 GETPC());
469 }
470 }
471 #endif /* TARGET_MIPS64 */
472
473 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
474
475 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
476 uint32_t mem_idx)
477 {
478 target_ulong base_reglist = reglist & 0xf;
479 target_ulong do_r31 = reglist & 0x10;
480
481 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
482 target_ulong i;
483
484 for (i = 0; i < base_reglist; i++) {
485 env->active_tc.gpr[multiple_regs[i]] =
486 (target_long)do_lw(env, addr, mem_idx, GETPC());
487 addr += 4;
488 }
489 }
490
491 if (do_r31) {
492 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
493 GETPC());
494 }
495 }
496
497 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
498 uint32_t mem_idx)
499 {
500 target_ulong base_reglist = reglist & 0xf;
501 target_ulong do_r31 = reglist & 0x10;
502
503 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
504 target_ulong i;
505
506 for (i = 0; i < base_reglist; i++) {
507 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
508 GETPC());
509 addr += 4;
510 }
511 }
512
513 if (do_r31) {
514 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
515 }
516 }
517
518 #if defined(TARGET_MIPS64)
519 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
520 uint32_t mem_idx)
521 {
522 target_ulong base_reglist = reglist & 0xf;
523 target_ulong do_r31 = reglist & 0x10;
524
525 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
526 target_ulong i;
527
528 for (i = 0; i < base_reglist; i++) {
529 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
530 GETPC());
531 addr += 8;
532 }
533 }
534
535 if (do_r31) {
536 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
537 }
538 }
539
540 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
541 uint32_t mem_idx)
542 {
543 target_ulong base_reglist = reglist & 0xf;
544 target_ulong do_r31 = reglist & 0x10;
545
546 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
547 target_ulong i;
548
549 for (i = 0; i < base_reglist; i++) {
550 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
551 GETPC());
552 addr += 8;
553 }
554 }
555
556 if (do_r31) {
557 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
558 }
559 }
560 #endif
561
562 #ifndef CONFIG_USER_ONLY
563 /* SMP helpers. */
564 static bool mips_vpe_is_wfi(MIPSCPU *c)
565 {
566 CPUState *cpu = CPU(c);
567 CPUMIPSState *env = &c->env;
568
569 /* If the VPE is halted but otherwise active, it means it's waiting for
570 an interrupt. */
571 return cpu->halted && mips_vpe_active(env);
572 }
573
574 static bool mips_vp_is_wfi(MIPSCPU *c)
575 {
576 CPUState *cpu = CPU(c);
577 CPUMIPSState *env = &c->env;
578
579 return cpu->halted && mips_vp_active(env);
580 }
581
582 static inline void mips_vpe_wake(MIPSCPU *c)
583 {
584 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
585 because there might be other conditions that state that c should
586 be sleeping. */
587 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
588 }
589
590 static inline void mips_vpe_sleep(MIPSCPU *cpu)
591 {
592 CPUState *cs = CPU(cpu);
593
594 /* The VPE was shut off, really go to bed.
595 Reset any old _WAKE requests. */
596 cs->halted = 1;
597 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
598 }
599
600 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
601 {
602 CPUMIPSState *c = &cpu->env;
603
604 /* FIXME: TC reschedule. */
605 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
606 mips_vpe_wake(cpu);
607 }
608 }
609
610 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
611 {
612 CPUMIPSState *c = &cpu->env;
613
614 /* FIXME: TC reschedule. */
615 if (!mips_vpe_active(c)) {
616 mips_vpe_sleep(cpu);
617 }
618 }
619
620 /**
621 * mips_cpu_map_tc:
622 * @env: CPU from which mapping is performed.
623 * @tc: Should point to an int with the value of the global TC index.
624 *
625 * This function will transform @tc into a local index within the
626 * returned #CPUMIPSState.
627 */
628 /* FIXME: This code assumes that all VPEs have the same number of TCs,
629 which depends on runtime setup. Can probably be fixed by
630 walking the list of CPUMIPSStates. */
631 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
632 {
633 MIPSCPU *cpu;
634 CPUState *cs;
635 CPUState *other_cs;
636 int vpe_idx;
637 int tc_idx = *tc;
638
639 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
640 /* Not allowed to address other CPUs. */
641 *tc = env->current_tc;
642 return env;
643 }
644
645 cs = CPU(mips_env_get_cpu(env));
646 vpe_idx = tc_idx / cs->nr_threads;
647 *tc = tc_idx % cs->nr_threads;
648 other_cs = qemu_get_cpu(vpe_idx);
649 if (other_cs == NULL) {
650 return env;
651 }
652 cpu = MIPS_CPU(other_cs);
653 return &cpu->env;
654 }
655
656 /* The per VPE CP0_Status register shares some fields with the per TC
657 CP0_TCStatus registers. These fields are wired to the same registers,
658 so changes to either of them should be reflected on both registers.
659
660 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
661
662 These helper call synchronizes the regs for a given cpu. */
663
664 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
665 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
666 int tc); */
667
668 /* Called for updates to CP0_TCStatus. */
669 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
670 target_ulong v)
671 {
672 uint32_t status;
673 uint32_t tcu, tmx, tasid, tksu;
674 uint32_t mask = ((1U << CP0St_CU3)
675 | (1 << CP0St_CU2)
676 | (1 << CP0St_CU1)
677 | (1 << CP0St_CU0)
678 | (1 << CP0St_MX)
679 | (3 << CP0St_KSU));
680
681 tcu = (v >> CP0TCSt_TCU0) & 0xf;
682 tmx = (v >> CP0TCSt_TMX) & 0x1;
683 tasid = v & 0xff;
684 tksu = (v >> CP0TCSt_TKSU) & 0x3;
685
686 status = tcu << CP0St_CU0;
687 status |= tmx << CP0St_MX;
688 status |= tksu << CP0St_KSU;
689
690 cpu->CP0_Status &= ~mask;
691 cpu->CP0_Status |= status;
692
693 /* Sync the TASID with EntryHi. */
694 cpu->CP0_EntryHi &= ~0xff;
695 cpu->CP0_EntryHi |= tasid;
696
697 compute_hflags(cpu);
698 }
699
700 /* Called for updates to CP0_EntryHi. */
701 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
702 {
703 int32_t *tcst;
704 uint32_t asid, v = cpu->CP0_EntryHi;
705
706 asid = v & 0xff;
707
708 if (tc == cpu->current_tc) {
709 tcst = &cpu->active_tc.CP0_TCStatus;
710 } else {
711 tcst = &cpu->tcs[tc].CP0_TCStatus;
712 }
713
714 *tcst &= ~0xff;
715 *tcst |= asid;
716 }
717
718 /* CP0 helpers */
719 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
720 {
721 return env->mvp->CP0_MVPControl;
722 }
723
724 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
725 {
726 return env->mvp->CP0_MVPConf0;
727 }
728
729 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
730 {
731 return env->mvp->CP0_MVPConf1;
732 }
733
734 target_ulong helper_mfc0_random(CPUMIPSState *env)
735 {
736 return (int32_t)cpu_mips_get_random(env);
737 }
738
739 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
740 {
741 return env->active_tc.CP0_TCStatus;
742 }
743
744 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
745 {
746 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
747 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
748
749 if (other_tc == other->current_tc)
750 return other->active_tc.CP0_TCStatus;
751 else
752 return other->tcs[other_tc].CP0_TCStatus;
753 }
754
755 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
756 {
757 return env->active_tc.CP0_TCBind;
758 }
759
760 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
761 {
762 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
763 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
764
765 if (other_tc == other->current_tc)
766 return other->active_tc.CP0_TCBind;
767 else
768 return other->tcs[other_tc].CP0_TCBind;
769 }
770
771 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
772 {
773 return env->active_tc.PC;
774 }
775
776 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
777 {
778 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
779 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
780
781 if (other_tc == other->current_tc)
782 return other->active_tc.PC;
783 else
784 return other->tcs[other_tc].PC;
785 }
786
787 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
788 {
789 return env->active_tc.CP0_TCHalt;
790 }
791
792 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
793 {
794 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
795 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
796
797 if (other_tc == other->current_tc)
798 return other->active_tc.CP0_TCHalt;
799 else
800 return other->tcs[other_tc].CP0_TCHalt;
801 }
802
803 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
804 {
805 return env->active_tc.CP0_TCContext;
806 }
807
808 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
809 {
810 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
811 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
812
813 if (other_tc == other->current_tc)
814 return other->active_tc.CP0_TCContext;
815 else
816 return other->tcs[other_tc].CP0_TCContext;
817 }
818
819 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
820 {
821 return env->active_tc.CP0_TCSchedule;
822 }
823
824 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
825 {
826 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
827 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
828
829 if (other_tc == other->current_tc)
830 return other->active_tc.CP0_TCSchedule;
831 else
832 return other->tcs[other_tc].CP0_TCSchedule;
833 }
834
835 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
836 {
837 return env->active_tc.CP0_TCScheFBack;
838 }
839
840 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
841 {
842 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
843 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
844
845 if (other_tc == other->current_tc)
846 return other->active_tc.CP0_TCScheFBack;
847 else
848 return other->tcs[other_tc].CP0_TCScheFBack;
849 }
850
851 target_ulong helper_mfc0_count(CPUMIPSState *env)
852 {
853 return (int32_t)cpu_mips_get_count(env);
854 }
855
856 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
857 {
858 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
859 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
860
861 return other->CP0_EntryHi;
862 }
863
864 target_ulong helper_mftc0_cause(CPUMIPSState *env)
865 {
866 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
867 int32_t tccause;
868 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
869
870 if (other_tc == other->current_tc) {
871 tccause = other->CP0_Cause;
872 } else {
873 tccause = other->CP0_Cause;
874 }
875
876 return tccause;
877 }
878
879 target_ulong helper_mftc0_status(CPUMIPSState *env)
880 {
881 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
882 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
883
884 return other->CP0_Status;
885 }
886
887 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
888 {
889 return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
890 }
891
892 target_ulong helper_mfc0_maar(CPUMIPSState *env)
893 {
894 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
895 }
896
897 target_ulong helper_mfhc0_maar(CPUMIPSState *env)
898 {
899 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
900 }
901
902 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
903 {
904 return (int32_t)env->CP0_WatchLo[sel];
905 }
906
907 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
908 {
909 return env->CP0_WatchHi[sel];
910 }
911
912 target_ulong helper_mfc0_debug(CPUMIPSState *env)
913 {
914 target_ulong t0 = env->CP0_Debug;
915 if (env->hflags & MIPS_HFLAG_DM)
916 t0 |= 1 << CP0DB_DM;
917
918 return t0;
919 }
920
921 target_ulong helper_mftc0_debug(CPUMIPSState *env)
922 {
923 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
924 int32_t tcstatus;
925 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
926
927 if (other_tc == other->current_tc)
928 tcstatus = other->active_tc.CP0_Debug_tcstatus;
929 else
930 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
931
932 /* XXX: Might be wrong, check with EJTAG spec. */
933 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
934 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
935 }
936
937 #if defined(TARGET_MIPS64)
938 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
939 {
940 return env->active_tc.PC;
941 }
942
943 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
944 {
945 return env->active_tc.CP0_TCHalt;
946 }
947
948 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
949 {
950 return env->active_tc.CP0_TCContext;
951 }
952
953 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
954 {
955 return env->active_tc.CP0_TCSchedule;
956 }
957
958 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
959 {
960 return env->active_tc.CP0_TCScheFBack;
961 }
962
963 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
964 {
965 return env->lladdr >> env->CP0_LLAddr_shift;
966 }
967
968 target_ulong helper_dmfc0_maar(CPUMIPSState *env)
969 {
970 return env->CP0_MAAR[env->CP0_MAARI];
971 }
972
973 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
974 {
975 return env->CP0_WatchLo[sel];
976 }
977 #endif /* TARGET_MIPS64 */
978
979 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
980 {
981 uint32_t index_p = env->CP0_Index & 0x80000000;
982 uint32_t tlb_index = arg1 & 0x7fffffff;
983 if (tlb_index < env->tlb->nb_tlb) {
984 if (env->insn_flags & ISA_MIPS32R6) {
985 index_p |= arg1 & 0x80000000;
986 }
987 env->CP0_Index = index_p | tlb_index;
988 }
989 }
990
991 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
992 {
993 uint32_t mask = 0;
994 uint32_t newval;
995
996 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
997 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
998 (1 << CP0MVPCo_EVP);
999 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1000 mask |= (1 << CP0MVPCo_STLB);
1001 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1002
1003 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1004
1005 env->mvp->CP0_MVPControl = newval;
1006 }
1007
1008 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1009 {
1010 uint32_t mask;
1011 uint32_t newval;
1012
1013 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1014 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1015 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1016
1017 /* Yield scheduler intercept not implemented. */
1018 /* Gating storage scheduler intercept not implemented. */
1019
1020 // TODO: Enable/disable TCs.
1021
1022 env->CP0_VPEControl = newval;
1023 }
1024
1025 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1026 {
1027 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1028 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1029 uint32_t mask;
1030 uint32_t newval;
1031
1032 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1033 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1034 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1035
1036 /* TODO: Enable/disable TCs. */
1037
1038 other->CP0_VPEControl = newval;
1039 }
1040
1041 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1042 {
1043 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1044 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1045 /* FIXME: Mask away return zero on read bits. */
1046 return other->CP0_VPEControl;
1047 }
1048
1049 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1050 {
1051 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1052 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1053
1054 return other->CP0_VPEConf0;
1055 }
1056
1057 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1058 {
1059 uint32_t mask = 0;
1060 uint32_t newval;
1061
1062 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1063 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1064 mask |= (0xff << CP0VPEC0_XTC);
1065 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1066 }
1067 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1068
1069 // TODO: TC exclusive handling due to ERL/EXL.
1070
1071 env->CP0_VPEConf0 = newval;
1072 }
1073
1074 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1075 {
1076 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1077 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1078 uint32_t mask = 0;
1079 uint32_t newval;
1080
1081 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1082 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1083
1084 /* TODO: TC exclusive handling due to ERL/EXL. */
1085 other->CP0_VPEConf0 = newval;
1086 }
1087
1088 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1089 {
1090 uint32_t mask = 0;
1091 uint32_t newval;
1092
1093 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1094 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1095 (0xff << CP0VPEC1_NCP1);
1096 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1097
1098 /* UDI not implemented. */
1099 /* CP2 not implemented. */
1100
1101 // TODO: Handle FPU (CP1) binding.
1102
1103 env->CP0_VPEConf1 = newval;
1104 }
1105
1106 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1107 {
1108 /* Yield qualifier inputs not implemented. */
1109 env->CP0_YQMask = 0x00000000;
1110 }
1111
1112 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1113 {
1114 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1115 }
1116
1117 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1118
1119 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1120 {
1121 /* 1k pages not implemented */
1122 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1123 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1124 | (rxi << (CP0EnLo_XI - 30));
1125 }
1126
1127 #if defined(TARGET_MIPS64)
1128 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1129
1130 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1131 {
1132 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1133 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1134 }
1135 #endif
1136
1137 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1138 {
1139 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1140 uint32_t newval;
1141
1142 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1143
1144 env->active_tc.CP0_TCStatus = newval;
1145 sync_c0_tcstatus(env, env->current_tc, newval);
1146 }
1147
1148 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1149 {
1150 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1151 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1152
1153 if (other_tc == other->current_tc)
1154 other->active_tc.CP0_TCStatus = arg1;
1155 else
1156 other->tcs[other_tc].CP0_TCStatus = arg1;
1157 sync_c0_tcstatus(other, other_tc, arg1);
1158 }
1159
1160 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1161 {
1162 uint32_t mask = (1 << CP0TCBd_TBE);
1163 uint32_t newval;
1164
1165 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1166 mask |= (1 << CP0TCBd_CurVPE);
1167 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1168 env->active_tc.CP0_TCBind = newval;
1169 }
1170
1171 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1172 {
1173 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1174 uint32_t mask = (1 << CP0TCBd_TBE);
1175 uint32_t newval;
1176 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1177
1178 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1179 mask |= (1 << CP0TCBd_CurVPE);
1180 if (other_tc == other->current_tc) {
1181 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1182 other->active_tc.CP0_TCBind = newval;
1183 } else {
1184 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1185 other->tcs[other_tc].CP0_TCBind = newval;
1186 }
1187 }
1188
1189 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1190 {
1191 env->active_tc.PC = arg1;
1192 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1193 env->lladdr = 0ULL;
1194 /* MIPS16 not implemented. */
1195 }
1196
1197 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1198 {
1199 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1200 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1201
1202 if (other_tc == other->current_tc) {
1203 other->active_tc.PC = arg1;
1204 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1205 other->lladdr = 0ULL;
1206 /* MIPS16 not implemented. */
1207 } else {
1208 other->tcs[other_tc].PC = arg1;
1209 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1210 other->lladdr = 0ULL;
1211 /* MIPS16 not implemented. */
1212 }
1213 }
1214
1215 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1216 {
1217 MIPSCPU *cpu = mips_env_get_cpu(env);
1218
1219 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1220
1221 // TODO: Halt TC / Restart (if allocated+active) TC.
1222 if (env->active_tc.CP0_TCHalt & 1) {
1223 mips_tc_sleep(cpu, env->current_tc);
1224 } else {
1225 mips_tc_wake(cpu, env->current_tc);
1226 }
1227 }
1228
1229 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1230 {
1231 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1232 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1233 MIPSCPU *other_cpu = mips_env_get_cpu(other);
1234
1235 // TODO: Halt TC / Restart (if allocated+active) TC.
1236
1237 if (other_tc == other->current_tc)
1238 other->active_tc.CP0_TCHalt = arg1;
1239 else
1240 other->tcs[other_tc].CP0_TCHalt = arg1;
1241
1242 if (arg1 & 1) {
1243 mips_tc_sleep(other_cpu, other_tc);
1244 } else {
1245 mips_tc_wake(other_cpu, other_tc);
1246 }
1247 }
1248
1249 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1250 {
1251 env->active_tc.CP0_TCContext = arg1;
1252 }
1253
1254 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1255 {
1256 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1257 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1258
1259 if (other_tc == other->current_tc)
1260 other->active_tc.CP0_TCContext = arg1;
1261 else
1262 other->tcs[other_tc].CP0_TCContext = arg1;
1263 }
1264
1265 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1266 {
1267 env->active_tc.CP0_TCSchedule = arg1;
1268 }
1269
1270 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1271 {
1272 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1273 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1274
1275 if (other_tc == other->current_tc)
1276 other->active_tc.CP0_TCSchedule = arg1;
1277 else
1278 other->tcs[other_tc].CP0_TCSchedule = arg1;
1279 }
1280
1281 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1282 {
1283 env->active_tc.CP0_TCScheFBack = arg1;
1284 }
1285
1286 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1287 {
1288 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1289 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1290
1291 if (other_tc == other->current_tc)
1292 other->active_tc.CP0_TCScheFBack = arg1;
1293 else
1294 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1295 }
1296
1297 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1298 {
1299 /* 1k pages not implemented */
1300 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1301 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1302 | (rxi << (CP0EnLo_XI - 30));
1303 }
1304
1305 #if defined(TARGET_MIPS64)
1306 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1307 {
1308 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1309 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1310 }
1311 #endif
1312
1313 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1314 {
1315 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1316 }
1317
1318 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1319 {
1320 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1321 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1322 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1323 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1324 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1325 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1326 }
1327 }
1328
1329 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1330 {
1331 /* SmartMIPS not implemented */
1332 /* 1k pages not implemented */
1333 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1334 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1335 compute_hflags(env);
1336 restore_pamask(env);
1337 }
1338
1339 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1340 {
1341 if (env->insn_flags & ISA_MIPS32R6) {
1342 if (arg1 < env->tlb->nb_tlb) {
1343 env->CP0_Wired = arg1;
1344 }
1345 } else {
1346 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1347 }
1348 }
1349
1350 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1351 {
1352 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1353 }
1354
1355 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1356 {
1357 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1358 }
1359
1360 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1361 {
1362 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1363 }
1364
1365 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1366 {
1367 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1368 }
1369
1370 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1371 {
1372 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1373 }
1374
1375 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1376 {
1377 uint32_t mask = 0x0000000F;
1378
1379 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1380 (env->insn_flags & ISA_MIPS32R6)) {
1381 mask |= (1 << 4);
1382 }
1383 if (env->insn_flags & ISA_MIPS32R6) {
1384 mask |= (1 << 5);
1385 }
1386 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1387 mask |= (1 << 29);
1388
1389 if (arg1 & (1 << 29)) {
1390 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1391 } else {
1392 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1393 }
1394 }
1395
1396 env->CP0_HWREna = arg1 & mask;
1397 }
1398
1399 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1400 {
1401 cpu_mips_store_count(env, arg1);
1402 }
1403
1404 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1405 {
1406 target_ulong old, val, mask;
1407 mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1408 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1409 mask |= 1 << CP0EnHi_EHINV;
1410 }
1411
1412 /* 1k pages not implemented */
1413 #if defined(TARGET_MIPS64)
1414 if (env->insn_flags & ISA_MIPS32R6) {
1415 int entryhi_r = extract64(arg1, 62, 2);
1416 int config0_at = extract32(env->CP0_Config0, 13, 2);
1417 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1418 if ((entryhi_r == 2) ||
1419 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1420 /* skip EntryHi.R field if new value is reserved */
1421 mask &= ~(0x3ull << 62);
1422 }
1423 }
1424 mask &= env->SEGMask;
1425 #endif
1426 old = env->CP0_EntryHi;
1427 val = (arg1 & mask) | (old & ~mask);
1428 env->CP0_EntryHi = val;
1429 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1430 sync_c0_entryhi(env, env->current_tc);
1431 }
1432 /* If the ASID changes, flush qemu's TLB. */
1433 if ((old & 0xFF) != (val & 0xFF))
1434 cpu_mips_tlb_flush(env, 1);
1435 }
1436
1437 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1438 {
1439 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1440 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1441
1442 other->CP0_EntryHi = arg1;
1443 sync_c0_entryhi(other, other_tc);
1444 }
1445
1446 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1447 {
1448 cpu_mips_store_compare(env, arg1);
1449 }
1450
1451 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1452 {
1453 MIPSCPU *cpu = mips_env_get_cpu(env);
1454 uint32_t val, old;
1455
1456 old = env->CP0_Status;
1457 cpu_mips_store_status(env, arg1);
1458 val = env->CP0_Status;
1459
1460 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1461 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1462 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1463 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1464 env->CP0_Cause);
1465 switch (env->hflags & MIPS_HFLAG_KSU) {
1466 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1467 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1468 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1469 default:
1470 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1471 break;
1472 }
1473 }
1474 }
1475
1476 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1477 {
1478 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1479 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1480 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1481
1482 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1483 sync_c0_status(env, other, other_tc);
1484 }
1485
1486 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1487 {
1488 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1489 }
1490
1491 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1492 {
1493 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1494 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1495 }
1496
1497 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1498 {
1499 cpu_mips_store_cause(env, arg1);
1500 }
1501
1502 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1503 {
1504 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1505 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1506
1507 cpu_mips_store_cause(other, arg1);
1508 }
1509
1510 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1511 {
1512 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1513 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1514
1515 return other->CP0_EPC;
1516 }
1517
1518 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1519 {
1520 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1521 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1522
1523 return other->CP0_EBase;
1524 }
1525
1526 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1527 {
1528 env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1529 }
1530
1531 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1532 {
1533 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1534 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1535 other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1536 }
1537
1538 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1539 {
1540 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1541 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1542
1543 switch (idx) {
1544 case 0: return other->CP0_Config0;
1545 case 1: return other->CP0_Config1;
1546 case 2: return other->CP0_Config2;
1547 case 3: return other->CP0_Config3;
1548 /* 4 and 5 are reserved. */
1549 case 6: return other->CP0_Config6;
1550 case 7: return other->CP0_Config7;
1551 default:
1552 break;
1553 }
1554 return 0;
1555 }
1556
1557 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1558 {
1559 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1560 }
1561
1562 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1563 {
1564 /* tertiary/secondary caches not implemented */
1565 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1566 }
1567
1568 void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1569 {
1570 if (env->insn_flags & ASE_MICROMIPS) {
1571 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1572 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1573 }
1574 }
1575
1576 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1577 {
1578 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1579 (arg1 & env->CP0_Config4_rw_bitmask);
1580 }
1581
1582 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1583 {
1584 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1585 (arg1 & env->CP0_Config5_rw_bitmask);
1586 compute_hflags(env);
1587 }
1588
1589 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1590 {
1591 target_long mask = env->CP0_LLAddr_rw_bitmask;
1592 arg1 = arg1 << env->CP0_LLAddr_shift;
1593 env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1594 }
1595
1596 #define MTC0_MAAR_MASK(env) \
1597 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1598
1599 void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1600 {
1601 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1602 }
1603
1604 void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1605 {
1606 env->CP0_MAAR[env->CP0_MAARI] =
1607 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1608 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1609 }
1610
1611 void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1612 {
1613 int index = arg1 & 0x3f;
1614 if (index == 0x3f) {
1615 /* Software may write all ones to INDEX to determine the
1616 maximum value supported. */
1617 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1618 } else if (index < MIPS_MAAR_MAX) {
1619 env->CP0_MAARI = index;
1620 }
1621 /* Other than the all ones, if the
1622 value written is not supported, then INDEX is unchanged
1623 from its previous value. */
1624 }
1625
1626 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1627 {
1628 /* Watch exceptions for instructions, data loads, data stores
1629 not implemented. */
1630 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1631 }
1632
1633 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1634 {
1635 env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1636 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1637 }
1638
1639 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1640 {
1641 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1642 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1643 }
1644
1645 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1646 {
1647 env->CP0_Framemask = arg1; /* XXX */
1648 }
1649
1650 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1651 {
1652 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1653 if (arg1 & (1 << CP0DB_DM))
1654 env->hflags |= MIPS_HFLAG_DM;
1655 else
1656 env->hflags &= ~MIPS_HFLAG_DM;
1657 }
1658
1659 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1660 {
1661 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1662 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1663 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1664
1665 /* XXX: Might be wrong, check with EJTAG spec. */
1666 if (other_tc == other->current_tc)
1667 other->active_tc.CP0_Debug_tcstatus = val;
1668 else
1669 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1670 other->CP0_Debug = (other->CP0_Debug &
1671 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1672 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1673 }
1674
1675 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1676 {
1677 env->CP0_Performance0 = arg1 & 0x000007ff;
1678 }
1679
1680 void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1681 {
1682 int32_t wst = arg1 & (1 << CP0EC_WST);
1683 int32_t spr = arg1 & (1 << CP0EC_SPR);
1684 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1685
1686 env->CP0_ErrCtl = wst | spr | itc;
1687
1688 if (itc && !wst && !spr) {
1689 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1690 } else {
1691 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1692 }
1693 }
1694
1695 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1696 {
1697 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1698 /* If CACHE instruction is configured for ITC tags then make all
1699 CP0.TagLo bits writable. The actual write to ITC Configuration
1700 Tag will take care of the read-only bits. */
1701 env->CP0_TagLo = arg1;
1702 } else {
1703 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1704 }
1705 }
1706
1707 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1708 {
1709 env->CP0_DataLo = arg1; /* XXX */
1710 }
1711
1712 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1713 {
1714 env->CP0_TagHi = arg1; /* XXX */
1715 }
1716
1717 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1718 {
1719 env->CP0_DataHi = arg1; /* XXX */
1720 }
1721
1722 /* MIPS MT functions */
1723 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1724 {
1725 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1726 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1727
1728 if (other_tc == other->current_tc)
1729 return other->active_tc.gpr[sel];
1730 else
1731 return other->tcs[other_tc].gpr[sel];
1732 }
1733
1734 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1735 {
1736 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1737 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1738
1739 if (other_tc == other->current_tc)
1740 return other->active_tc.LO[sel];
1741 else
1742 return other->tcs[other_tc].LO[sel];
1743 }
1744
1745 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1746 {
1747 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1748 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1749
1750 if (other_tc == other->current_tc)
1751 return other->active_tc.HI[sel];
1752 else
1753 return other->tcs[other_tc].HI[sel];
1754 }
1755
1756 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1757 {
1758 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1759 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1760
1761 if (other_tc == other->current_tc)
1762 return other->active_tc.ACX[sel];
1763 else
1764 return other->tcs[other_tc].ACX[sel];
1765 }
1766
1767 target_ulong helper_mftdsp(CPUMIPSState *env)
1768 {
1769 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1770 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1771
1772 if (other_tc == other->current_tc)
1773 return other->active_tc.DSPControl;
1774 else
1775 return other->tcs[other_tc].DSPControl;
1776 }
1777
1778 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1779 {
1780 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1781 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1782
1783 if (other_tc == other->current_tc)
1784 other->active_tc.gpr[sel] = arg1;
1785 else
1786 other->tcs[other_tc].gpr[sel] = arg1;
1787 }
1788
1789 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1790 {
1791 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1792 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1793
1794 if (other_tc == other->current_tc)
1795 other->active_tc.LO[sel] = arg1;
1796 else
1797 other->tcs[other_tc].LO[sel] = arg1;
1798 }
1799
1800 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1801 {
1802 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1803 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1804
1805 if (other_tc == other->current_tc)
1806 other->active_tc.HI[sel] = arg1;
1807 else
1808 other->tcs[other_tc].HI[sel] = arg1;
1809 }
1810
1811 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1812 {
1813 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1814 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1815
1816 if (other_tc == other->current_tc)
1817 other->active_tc.ACX[sel] = arg1;
1818 else
1819 other->tcs[other_tc].ACX[sel] = arg1;
1820 }
1821
1822 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1823 {
1824 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1825 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1826
1827 if (other_tc == other->current_tc)
1828 other->active_tc.DSPControl = arg1;
1829 else
1830 other->tcs[other_tc].DSPControl = arg1;
1831 }
1832
1833 /* MIPS MT functions */
1834 target_ulong helper_dmt(void)
1835 {
1836 // TODO
1837 return 0;
1838 }
1839
1840 target_ulong helper_emt(void)
1841 {
1842 // TODO
1843 return 0;
1844 }
1845
1846 target_ulong helper_dvpe(CPUMIPSState *env)
1847 {
1848 CPUState *other_cs = first_cpu;
1849 target_ulong prev = env->mvp->CP0_MVPControl;
1850
1851 CPU_FOREACH(other_cs) {
1852 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1853 /* Turn off all VPEs except the one executing the dvpe. */
1854 if (&other_cpu->env != env) {
1855 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1856 mips_vpe_sleep(other_cpu);
1857 }
1858 }
1859 return prev;
1860 }
1861
1862 target_ulong helper_evpe(CPUMIPSState *env)
1863 {
1864 CPUState *other_cs = first_cpu;
1865 target_ulong prev = env->mvp->CP0_MVPControl;
1866
1867 CPU_FOREACH(other_cs) {
1868 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1869
1870 if (&other_cpu->env != env
1871 /* If the VPE is WFI, don't disturb its sleep. */
1872 && !mips_vpe_is_wfi(other_cpu)) {
1873 /* Enable the VPE. */
1874 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1875 mips_vpe_wake(other_cpu); /* And wake it up. */
1876 }
1877 }
1878 return prev;
1879 }
1880 #endif /* !CONFIG_USER_ONLY */
1881
1882 void helper_fork(target_ulong arg1, target_ulong arg2)
1883 {
1884 // arg1 = rt, arg2 = rs
1885 // TODO: store to TC register
1886 }
1887
1888 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1889 {
1890 target_long arg1 = arg;
1891
1892 if (arg1 < 0) {
1893 /* No scheduling policy implemented. */
1894 if (arg1 != -2) {
1895 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1896 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1897 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1898 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1899 do_raise_exception(env, EXCP_THREAD, GETPC());
1900 }
1901 }
1902 } else if (arg1 == 0) {
1903 if (0 /* TODO: TC underflow */) {
1904 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1905 do_raise_exception(env, EXCP_THREAD, GETPC());
1906 } else {
1907 // TODO: Deallocate TC
1908 }
1909 } else if (arg1 > 0) {
1910 /* Yield qualifier inputs not implemented. */
1911 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1912 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1913 do_raise_exception(env, EXCP_THREAD, GETPC());
1914 }
1915 return env->CP0_YQMask;
1916 }
1917
1918 /* R6 Multi-threading */
1919 #ifndef CONFIG_USER_ONLY
1920 target_ulong helper_dvp(CPUMIPSState *env)
1921 {
1922 CPUState *other_cs = first_cpu;
1923 target_ulong prev = env->CP0_VPControl;
1924
1925 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
1926 CPU_FOREACH(other_cs) {
1927 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1928 /* Turn off all VPs except the one executing the dvp. */
1929 if (&other_cpu->env != env) {
1930 mips_vpe_sleep(other_cpu);
1931 }
1932 }
1933 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
1934 }
1935 return prev;
1936 }
1937
1938 target_ulong helper_evp(CPUMIPSState *env)
1939 {
1940 CPUState *other_cs = first_cpu;
1941 target_ulong prev = env->CP0_VPControl;
1942
1943 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
1944 CPU_FOREACH(other_cs) {
1945 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1946 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
1947 /* If the VP is WFI, don't disturb its sleep.
1948 * Otherwise, wake it up. */
1949 mips_vpe_wake(other_cpu);
1950 }
1951 }
1952 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
1953 }
1954 return prev;
1955 }
1956 #endif /* !CONFIG_USER_ONLY */
1957
1958 #ifndef CONFIG_USER_ONLY
1959 /* TLB management */
1960 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1961 {
1962 /* Discard entries from env->tlb[first] onwards. */
1963 while (env->tlb->tlb_in_use > first) {
1964 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1965 }
1966 }
1967
1968 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
1969 {
1970 #if defined(TARGET_MIPS64)
1971 return extract64(entrylo, 6, 54);
1972 #else
1973 return extract64(entrylo, 6, 24) | /* PFN */
1974 (extract64(entrylo, 32, 32) << 24); /* PFNX */
1975 #endif
1976 }
1977
1978 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1979 {
1980 r4k_tlb_t *tlb;
1981
1982 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1983 tlb = &env->tlb->mmu.r4k.tlb[idx];
1984 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1985 tlb->EHINV = 1;
1986 return;
1987 }
1988 tlb->EHINV = 0;
1989 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1990 #if defined(TARGET_MIPS64)
1991 tlb->VPN &= env->SEGMask;
1992 #endif
1993 tlb->ASID = env->CP0_EntryHi & 0xFF;
1994 tlb->PageMask = env->CP0_PageMask;
1995 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1996 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1997 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1998 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1999 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2000 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2001 tlb->PFN[0] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) << 12;
2002 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2003 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2004 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2005 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2006 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2007 tlb->PFN[1] = get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) << 12;
2008 }
2009
2010 void r4k_helper_tlbinv(CPUMIPSState *env)
2011 {
2012 int idx;
2013 r4k_tlb_t *tlb;
2014 uint8_t ASID = env->CP0_EntryHi & 0xFF;
2015
2016 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2017 tlb = &env->tlb->mmu.r4k.tlb[idx];
2018 if (!tlb->G && tlb->ASID == ASID) {
2019 tlb->EHINV = 1;
2020 }
2021 }
2022 cpu_mips_tlb_flush(env, 1);
2023 }
2024
2025 void r4k_helper_tlbinvf(CPUMIPSState *env)
2026 {
2027 int idx;
2028
2029 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2030 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2031 }
2032 cpu_mips_tlb_flush(env, 1);
2033 }
2034
2035 void r4k_helper_tlbwi(CPUMIPSState *env)
2036 {
2037 r4k_tlb_t *tlb;
2038 int idx;
2039 target_ulong VPN;
2040 uint8_t ASID;
2041 bool G, V0, D0, V1, D1;
2042
2043 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2044 tlb = &env->tlb->mmu.r4k.tlb[idx];
2045 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2046 #if defined(TARGET_MIPS64)
2047 VPN &= env->SEGMask;
2048 #endif
2049 ASID = env->CP0_EntryHi & 0xff;
2050 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2051 V0 = (env->CP0_EntryLo0 & 2) != 0;
2052 D0 = (env->CP0_EntryLo0 & 4) != 0;
2053 V1 = (env->CP0_EntryLo1 & 2) != 0;
2054 D1 = (env->CP0_EntryLo1 & 4) != 0;
2055
2056 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2057 permissions on the current entry. */
2058 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2059 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2060 (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
2061 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2062 }
2063
2064 r4k_invalidate_tlb(env, idx, 0);
2065 r4k_fill_tlb(env, idx);
2066 }
2067
2068 void r4k_helper_tlbwr(CPUMIPSState *env)
2069 {
2070 int r = cpu_mips_get_random(env);
2071
2072 r4k_invalidate_tlb(env, r, 1);
2073 r4k_fill_tlb(env, r);
2074 }
2075
2076 void r4k_helper_tlbp(CPUMIPSState *env)
2077 {
2078 r4k_tlb_t *tlb;
2079 target_ulong mask;
2080 target_ulong tag;
2081 target_ulong VPN;
2082 uint8_t ASID;
2083 int i;
2084
2085 ASID = env->CP0_EntryHi & 0xFF;
2086 for (i = 0; i < env->tlb->nb_tlb; i++) {
2087 tlb = &env->tlb->mmu.r4k.tlb[i];
2088 /* 1k pages are not supported. */
2089 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2090 tag = env->CP0_EntryHi & ~mask;
2091 VPN = tlb->VPN & ~mask;
2092 #if defined(TARGET_MIPS64)
2093 tag &= env->SEGMask;
2094 #endif
2095 /* Check ASID, virtual page number & size */
2096 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2097 /* TLB match */
2098 env->CP0_Index = i;
2099 break;
2100 }
2101 }
2102 if (i == env->tlb->nb_tlb) {
2103 /* No match. Discard any shadow entries, if any of them match. */
2104 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2105 tlb = &env->tlb->mmu.r4k.tlb[i];
2106 /* 1k pages are not supported. */
2107 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2108 tag = env->CP0_EntryHi & ~mask;
2109 VPN = tlb->VPN & ~mask;
2110 #if defined(TARGET_MIPS64)
2111 tag &= env->SEGMask;
2112 #endif
2113 /* Check ASID, virtual page number & size */
2114 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2115 r4k_mips_tlb_flush_extra (env, i);
2116 break;
2117 }
2118 }
2119
2120 env->CP0_Index |= 0x80000000;
2121 }
2122 }
2123
2124 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2125 {
2126 #if defined(TARGET_MIPS64)
2127 return tlb_pfn << 6;
2128 #else
2129 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2130 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2131 #endif
2132 }
2133
2134 void r4k_helper_tlbr(CPUMIPSState *env)
2135 {
2136 r4k_tlb_t *tlb;
2137 uint8_t ASID;
2138 int idx;
2139
2140 ASID = env->CP0_EntryHi & 0xFF;
2141 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2142 tlb = &env->tlb->mmu.r4k.tlb[idx];
2143
2144 /* If this will change the current ASID, flush qemu's TLB. */
2145 if (ASID != tlb->ASID)
2146 cpu_mips_tlb_flush (env, 1);
2147
2148 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2149
2150 if (tlb->EHINV) {
2151 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2152 env->CP0_PageMask = 0;
2153 env->CP0_EntryLo0 = 0;
2154 env->CP0_EntryLo1 = 0;
2155 } else {
2156 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2157 env->CP0_PageMask = tlb->PageMask;
2158 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2159 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2160 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2161 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2162 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2163 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2164 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2165 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2166 }
2167 }
2168
2169 void helper_tlbwi(CPUMIPSState *env)
2170 {
2171 env->tlb->helper_tlbwi(env);
2172 }
2173
2174 void helper_tlbwr(CPUMIPSState *env)
2175 {
2176 env->tlb->helper_tlbwr(env);
2177 }
2178
2179 void helper_tlbp(CPUMIPSState *env)
2180 {
2181 env->tlb->helper_tlbp(env);
2182 }
2183
2184 void helper_tlbr(CPUMIPSState *env)
2185 {
2186 env->tlb->helper_tlbr(env);
2187 }
2188
2189 void helper_tlbinv(CPUMIPSState *env)
2190 {
2191 env->tlb->helper_tlbinv(env);
2192 }
2193
2194 void helper_tlbinvf(CPUMIPSState *env)
2195 {
2196 env->tlb->helper_tlbinvf(env);
2197 }
2198
2199 /* Specials */
2200 target_ulong helper_di(CPUMIPSState *env)
2201 {
2202 target_ulong t0 = env->CP0_Status;
2203
2204 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2205 return t0;
2206 }
2207
2208 target_ulong helper_ei(CPUMIPSState *env)
2209 {
2210 target_ulong t0 = env->CP0_Status;
2211
2212 env->CP0_Status = t0 | (1 << CP0St_IE);
2213 return t0;
2214 }
2215
2216 static void debug_pre_eret(CPUMIPSState *env)
2217 {
2218 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2219 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2220 env->active_tc.PC, env->CP0_EPC);
2221 if (env->CP0_Status & (1 << CP0St_ERL))
2222 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2223 if (env->hflags & MIPS_HFLAG_DM)
2224 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2225 qemu_log("\n");
2226 }
2227 }
2228
2229 static void debug_post_eret(CPUMIPSState *env)
2230 {
2231 MIPSCPU *cpu = mips_env_get_cpu(env);
2232
2233 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2234 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2235 env->active_tc.PC, env->CP0_EPC);
2236 if (env->CP0_Status & (1 << CP0St_ERL))
2237 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2238 if (env->hflags & MIPS_HFLAG_DM)
2239 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2240 switch (env->hflags & MIPS_HFLAG_KSU) {
2241 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2242 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2243 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2244 default:
2245 cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2246 break;
2247 }
2248 }
2249 }
2250
2251 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2252 {
2253 env->active_tc.PC = error_pc & ~(target_ulong)1;
2254 if (error_pc & 1) {
2255 env->hflags |= MIPS_HFLAG_M16;
2256 } else {
2257 env->hflags &= ~(MIPS_HFLAG_M16);
2258 }
2259 }
2260
2261 static inline void exception_return(CPUMIPSState *env)
2262 {
2263 debug_pre_eret(env);
2264 if (env->CP0_Status & (1 << CP0St_ERL)) {
2265 set_pc(env, env->CP0_ErrorEPC);
2266 env->CP0_Status &= ~(1 << CP0St_ERL);
2267 } else {
2268 set_pc(env, env->CP0_EPC);
2269 env->CP0_Status &= ~(1 << CP0St_EXL);
2270 }
2271 compute_hflags(env);
2272 debug_post_eret(env);
2273 }
2274
2275 void helper_eret(CPUMIPSState *env)
2276 {
2277 exception_return(env);
2278 env->lladdr = 1;
2279 }
2280
2281 void helper_eretnc(CPUMIPSState *env)
2282 {
2283 exception_return(env);
2284 }
2285
2286 void helper_deret(CPUMIPSState *env)
2287 {
2288 debug_pre_eret(env);
2289 set_pc(env, env->CP0_DEPC);
2290
2291 env->hflags &= ~MIPS_HFLAG_DM;
2292 compute_hflags(env);
2293 debug_post_eret(env);
2294 }
2295 #endif /* !CONFIG_USER_ONLY */
2296
2297 static inline void check_hwrena(CPUMIPSState *env, int reg)
2298 {
2299 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2300 return;
2301 }
2302 do_raise_exception(env, EXCP_RI, GETPC());
2303 }
2304
2305 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2306 {
2307 check_hwrena(env, 0);
2308 return env->CP0_EBase & 0x3ff;
2309 }
2310
2311 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2312 {
2313 check_hwrena(env, 1);
2314 return env->SYNCI_Step;
2315 }
2316
2317 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2318 {
2319 check_hwrena(env, 2);
2320 #ifdef CONFIG_USER_ONLY
2321 return env->CP0_Count;
2322 #else
2323 return (int32_t)cpu_mips_get_count(env);
2324 #endif
2325 }
2326
2327 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2328 {
2329 check_hwrena(env, 3);
2330 return env->CCRes;
2331 }
2332
2333 target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2334 {
2335 check_hwrena(env, 4);
2336 return env->CP0_Performance0;
2337 }
2338
2339 target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2340 {
2341 check_hwrena(env, 5);
2342 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2343 }
2344
2345 void helper_pmon(CPUMIPSState *env, int function)
2346 {
2347 function /= 2;
2348 switch (function) {
2349 case 2: /* TODO: char inbyte(int waitflag); */
2350 if (env->active_tc.gpr[4] == 0)
2351 env->active_tc.gpr[2] = -1;
2352 /* Fall through */
2353 case 11: /* TODO: char inbyte (void); */
2354 env->active_tc.gpr[2] = -1;
2355 break;
2356 case 3:
2357 case 12:
2358 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2359 break;
2360 case 17:
2361 break;
2362 case 158:
2363 {
2364 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2365 printf("%s", fmt);
2366 }
2367 break;
2368 }
2369 }
2370
2371 void helper_wait(CPUMIPSState *env)
2372 {
2373 CPUState *cs = CPU(mips_env_get_cpu(env));
2374
2375 cs->halted = 1;
2376 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2377 /* Last instruction in the block, PC was updated before
2378 - no need to recover PC and icount */
2379 raise_exception(env, EXCP_HLT);
2380 }
2381
2382 #if !defined(CONFIG_USER_ONLY)
2383
2384 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2385 int access_type, int is_user,
2386 uintptr_t retaddr)
2387 {
2388 MIPSCPU *cpu = MIPS_CPU(cs);
2389 CPUMIPSState *env = &cpu->env;
2390 int error_code = 0;
2391 int excp;
2392
2393 env->CP0_BadVAddr = addr;
2394
2395 if (access_type == MMU_DATA_STORE) {
2396 excp = EXCP_AdES;
2397 } else {
2398 excp = EXCP_AdEL;
2399 if (access_type == MMU_INST_FETCH) {
2400 error_code |= EXCP_INST_NOTAVAIL;
2401 }
2402 }
2403
2404 do_raise_exception_err(env, excp, error_code, retaddr);
2405 }
2406
2407 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2408 uintptr_t retaddr)
2409 {
2410 int ret;
2411
2412 ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2413 if (ret) {
2414 MIPSCPU *cpu = MIPS_CPU(cs);
2415 CPUMIPSState *env = &cpu->env;
2416
2417 do_raise_exception_err(env, cs->exception_index,
2418 env->error_code, retaddr);
2419 }
2420 }
2421
2422 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2423 bool is_write, bool is_exec, int unused,
2424 unsigned size)
2425 {
2426 MIPSCPU *cpu = MIPS_CPU(cs);
2427 CPUMIPSState *env = &cpu->env;
2428
2429 /*
2430 * Raising an exception with KVM enabled will crash because it won't be from
2431 * the main execution loop so the longjmp won't have a matching setjmp.
2432 * Until we can trigger a bus error exception through KVM lets just ignore
2433 * the access.
2434 */
2435 if (kvm_enabled()) {
2436 return;
2437 }
2438
2439 if (is_exec) {
2440 raise_exception(env, EXCP_IBE);
2441 } else {
2442 raise_exception(env, EXCP_DBE);
2443 }
2444 }
2445 #endif /* !CONFIG_USER_ONLY */
2446
2447 /* Complex FPU operations which may need stack space. */
2448
2449 #define FLOAT_TWO32 make_float32(1 << 30)
2450 #define FLOAT_TWO64 make_float64(1ULL << 62)
2451 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2452 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2453
2454 /* convert MIPS rounding mode in FCR31 to IEEE library */
2455 unsigned int ieee_rm[] = {
2456 float_round_nearest_even,
2457 float_round_to_zero,
2458 float_round_up,
2459 float_round_down
2460 };
2461
2462 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2463 {
2464 target_ulong arg1 = 0;
2465
2466 switch (reg) {
2467 case 0:
2468 arg1 = (int32_t)env->active_fpu.fcr0;
2469 break;
2470 case 1:
2471 /* UFR Support - Read Status FR */
2472 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2473 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2474 arg1 = (int32_t)
2475 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2476 } else {
2477 do_raise_exception(env, EXCP_RI, GETPC());
2478 }
2479 }
2480 break;
2481 case 5:
2482 /* FRE Support - read Config5.FRE bit */
2483 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2484 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2485 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2486 } else {
2487 helper_raise_exception(env, EXCP_RI);
2488 }
2489 }
2490 break;
2491 case 25:
2492 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2493 break;
2494 case 26:
2495 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2496 break;
2497 case 28:
2498 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2499 break;
2500 default:
2501 arg1 = (int32_t)env->active_fpu.fcr31;
2502 break;
2503 }
2504
2505 return arg1;
2506 }
2507
2508 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2509 {
2510 switch (fs) {
2511 case 1:
2512 /* UFR Alias - Reset Status FR */
2513 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2514 return;
2515 }
2516 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2517 env->CP0_Status &= ~(1 << CP0St_FR);
2518 compute_hflags(env);
2519 } else {
2520 do_raise_exception(env, EXCP_RI, GETPC());
2521 }
2522 break;
2523 case 4:
2524 /* UNFR Alias - Set Status FR */
2525 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2526 return;
2527 }
2528 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2529 env->CP0_Status |= (1 << CP0St_FR);
2530 compute_hflags(env);
2531 } else {
2532 do_raise_exception(env, EXCP_RI, GETPC());
2533 }
2534 break;
2535 case 5:
2536 /* FRE Support - clear Config5.FRE bit */
2537 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2538 return;
2539 }
2540 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2541 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2542 compute_hflags(env);
2543 } else {
2544 helper_raise_exception(env, EXCP_RI);
2545 }
2546 break;
2547 case 6:
2548 /* FRE Support - set Config5.FRE bit */
2549 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2550 return;
2551 }
2552 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2553 env->CP0_Config5 |= (1 << CP0C5_FRE);
2554 compute_hflags(env);
2555 } else {
2556 helper_raise_exception(env, EXCP_RI);
2557 }
2558 break;
2559 case 25:
2560 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2561 return;
2562 }
2563 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2564 ((arg1 & 0x1) << 23);
2565 break;
2566 case 26:
2567 if (arg1 & 0x007c0000)
2568 return;
2569 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2570 break;
2571 case 28:
2572 if (arg1 & 0x007c0000)
2573 return;
2574 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2575 ((arg1 & 0x4) << 22);
2576 break;
2577 case 31:
2578 if (env->insn_flags & ISA_MIPS32R6) {
2579 uint32_t mask = 0xfefc0000;
2580 env->active_fpu.fcr31 = (arg1 & ~mask) |
2581 (env->active_fpu.fcr31 & mask);
2582 } else if (!(arg1 & 0x007c0000)) {
2583 env->active_fpu.fcr31 = arg1;
2584 }
2585 break;
2586 default:
2587 return;
2588 }
2589 /* set rounding mode */
2590 restore_rounding_mode(env);
2591 /* set flush-to-zero mode */
2592 restore_flush_mode(env);
2593 set_float_exception_flags(0, &env->active_fpu.fp_status);
2594 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2595 do_raise_exception(env, EXCP_FPE, GETPC());
2596 }
2597
2598 int ieee_ex_to_mips(int xcpt)
2599 {
2600 int ret = 0;
2601 if (xcpt) {
2602 if (xcpt & float_flag_invalid) {
2603 ret |= FP_INVALID;
2604 }
2605 if (xcpt & float_flag_overflow) {
2606 ret |= FP_OVERFLOW;
2607 }
2608 if (xcpt & float_flag_underflow) {
2609 ret |= FP_UNDERFLOW;
2610 }
2611 if (xcpt & float_flag_divbyzero) {
2612 ret |= FP_DIV0;
2613 }
2614 if (xcpt & float_flag_inexact) {
2615 ret |= FP_INEXACT;
2616 }
2617 }
2618 return ret;
2619 }
2620
2621 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2622 {
2623 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2624
2625 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2626
2627 if (tmp) {
2628 set_float_exception_flags(0, &env->active_fpu.fp_status);
2629
2630 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2631 do_raise_exception(env, EXCP_FPE, pc);
2632 } else {
2633 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2634 }
2635 }
2636 }
2637
2638 /* Float support.
2639 Single precition routines have a "s" suffix, double precision a
2640 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2641 paired single lower "pl", paired single upper "pu". */
2642
2643 /* unary operations, modifying fp status */
2644 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2645 {
2646 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2647 update_fcr31(env, GETPC());
2648 return fdt0;
2649 }
2650
2651 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2652 {
2653 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2654 update_fcr31(env, GETPC());
2655 return fst0;
2656 }
2657
2658 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2659 {
2660 uint64_t fdt2;
2661
2662 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2663 fdt2 = float64_maybe_silence_nan(fdt2);
2664 update_fcr31(env, GETPC());
2665 return fdt2;
2666 }
2667
2668 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2669 {
2670 uint64_t fdt2;
2671
2672 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2673 update_fcr31(env, GETPC());
2674 return fdt2;
2675 }
2676
2677 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2678 {
2679 uint64_t fdt2;
2680
2681 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2682 update_fcr31(env, GETPC());
2683 return fdt2;
2684 }
2685
2686 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2687 {
2688 uint64_t dt2;
2689
2690 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2691 if (get_float_exception_flags(&env->active_fpu.fp_status)
2692 & (float_flag_invalid | float_flag_overflow)) {
2693 dt2 = FP_TO_INT64_OVERFLOW;
2694 }
2695 update_fcr31(env, GETPC());
2696 return dt2;
2697 }
2698
2699 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2700 {
2701 uint64_t dt2;
2702
2703 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2704 if (get_float_exception_flags(&env->active_fpu.fp_status)
2705 & (float_flag_invalid | float_flag_overflow)) {
2706 dt2 = FP_TO_INT64_OVERFLOW;
2707 }
2708 update_fcr31(env, GETPC());
2709 return dt2;
2710 }
2711
2712 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2713 {
2714 uint32_t fst2;
2715 uint32_t fsth2;
2716
2717 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2718 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2719 update_fcr31(env, GETPC());
2720 return ((uint64_t)fsth2 << 32) | fst2;
2721 }
2722
2723 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2724 {
2725 uint32_t wt2;
2726 uint32_t wth2;
2727 int excp, excph;
2728
2729 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2730 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2731 if (excp & (float_flag_overflow | float_flag_invalid)) {
2732 wt2 = FP_TO_INT32_OVERFLOW;
2733 }
2734
2735 set_float_exception_flags(0, &env->active_fpu.fp_status);
2736 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2737 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2738 if (excph & (float_flag_overflow | float_flag_invalid)) {
2739 wth2 = FP_TO_INT32_OVERFLOW;
2740 }
2741
2742 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2743 update_fcr31(env, GETPC());
2744
2745 return ((uint64_t)wth2 << 32) | wt2;
2746 }
2747
2748 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2749 {
2750 uint32_t fst2;
2751
2752 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2753 fst2 = float32_maybe_silence_nan(fst2);
2754 update_fcr31(env, GETPC());
2755 return fst2;
2756 }
2757
2758 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2759 {
2760 uint32_t fst2;
2761
2762 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2763 update_fcr31(env, GETPC());
2764 return fst2;
2765 }
2766
2767 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2768 {
2769 uint32_t fst2;
2770
2771 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2772 update_fcr31(env, GETPC());
2773 return fst2;
2774 }
2775
2776 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2777 {
2778 uint32_t wt2;
2779
2780 wt2 = wt0;
2781 update_fcr31(env, GETPC());
2782 return wt2;
2783 }
2784
2785 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2786 {
2787 uint32_t wt2;
2788
2789 wt2 = wth0;
2790 update_fcr31(env, GETPC());
2791 return wt2;
2792 }
2793
2794 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2795 {
2796 uint32_t wt2;
2797
2798 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2799 if (get_float_exception_flags(&env->active_fpu.fp_status)
2800 & (float_flag_invalid | float_flag_overflow)) {
2801 wt2 = FP_TO_INT32_OVERFLOW;
2802 }
2803 update_fcr31(env, GETPC());
2804 return wt2;
2805 }
2806
2807 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2808 {
2809 uint32_t wt2;
2810
2811 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2812 if (get_float_exception_flags(&env->active_fpu.fp_status)
2813 & (float_flag_invalid | float_flag_overflow)) {
2814 wt2 = FP_TO_INT32_OVERFLOW;
2815 }
2816 update_fcr31(env, GETPC());
2817 return wt2;
2818 }
2819
2820 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2821 {
2822 uint64_t dt2;
2823
2824 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2825 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2826 restore_rounding_mode(env);
2827 if (get_float_exception_flags(&env->active_fpu.fp_status)
2828 & (float_flag_invalid | float_flag_overflow)) {
2829 dt2 = FP_TO_INT64_OVERFLOW;
2830 }
2831 update_fcr31(env, GETPC());
2832 return dt2;
2833 }
2834
2835 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2836 {
2837 uint64_t dt2;
2838
2839 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2840 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2841 restore_rounding_mode(env);
2842 if (get_float_exception_flags(&env->active_fpu.fp_status)
2843 & (float_flag_invalid | float_flag_overflow)) {
2844 dt2 = FP_TO_INT64_OVERFLOW;
2845 }
2846 update_fcr31(env, GETPC());
2847 return dt2;
2848 }
2849
2850 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2851 {
2852 uint32_t wt2;
2853
2854 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2855 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2856 restore_rounding_mode(env);
2857 if (get_float_exception_flags(&env->active_fpu.fp_status)
2858 & (float_flag_invalid | float_flag_overflow)) {
2859 wt2 = FP_TO_INT32_OVERFLOW;
2860 }
2861 update_fcr31(env, GETPC());
2862 return wt2;
2863 }
2864
2865 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2866 {
2867 uint32_t wt2;
2868
2869 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2870 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2871 restore_rounding_mode(env);
2872 if (get_float_exception_flags(&env->active_fpu.fp_status)
2873 & (float_flag_invalid | float_flag_overflow)) {
2874 wt2 = FP_TO_INT32_OVERFLOW;
2875 }
2876 update_fcr31(env, GETPC());
2877 return wt2;
2878 }
2879
2880 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2881 {
2882 uint64_t dt2;
2883
2884 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2885 if (get_float_exception_flags(&env->active_fpu.fp_status)
2886 & (float_flag_invalid | float_flag_overflow)) {
2887 dt2 = FP_TO_INT64_OVERFLOW;
2888 }
2889 update_fcr31(env, GETPC());
2890 return dt2;
2891 }
2892
2893 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2894 {
2895 uint64_t dt2;
2896
2897 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2898 if (get_float_exception_flags(&env->active_fpu.fp_status)
2899 & (float_flag_invalid | float_flag_overflow)) {
2900 dt2 = FP_TO_INT64_OVERFLOW;
2901 }
2902 update_fcr31(env, GETPC());
2903 return dt2;
2904 }
2905
2906 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2907 {
2908 uint32_t wt2;
2909
2910 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2911 if (get_float_exception_flags(&env->active_fpu.fp_status)
2912 & (float_flag_invalid | float_flag_overflow)) {
2913 wt2 = FP_TO_INT32_OVERFLOW;
2914 }
2915 update_fcr31(env, GETPC());
2916 return wt2;
2917 }
2918
2919 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2920 {
2921 uint32_t wt2;
2922
2923 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2924 if (get_float_exception_flags(&env->active_fpu.fp_status)
2925 & (float_flag_invalid | float_flag_overflow)) {
2926 wt2 = FP_TO_INT32_OVERFLOW;
2927 }
2928 update_fcr31(env, GETPC());
2929 return wt2;
2930 }
2931
2932 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2933 {
2934 uint64_t dt2;
2935
2936 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2937 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2938 restore_rounding_mode(env);
2939 if (get_float_exception_flags(&env->active_fpu.fp_status)
2940 & (float_flag_invalid | float_flag_overflow)) {
2941 dt2 = FP_TO_INT64_OVERFLOW;
2942 }
2943 update_fcr31(env, GETPC());
2944 return dt2;
2945 }
2946
2947 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2948 {
2949 uint64_t dt2;
2950
2951 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2952 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2953 restore_rounding_mode(env);
2954 if (get_float_exception_flags(&env->active_fpu.fp_status)
2955 & (float_flag_invalid | float_flag_overflow)) {
2956 dt2 = FP_TO_INT64_OVERFLOW;
2957 }
2958 update_fcr31(env, GETPC());
2959 return dt2;
2960 }
2961
2962 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2963 {
2964 uint32_t wt2;
2965
2966 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2967 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2968 restore_rounding_mode(env);
2969 if (get_float_exception_flags(&env->active_fpu.fp_status)
2970 & (float_flag_invalid | float_flag_overflow)) {
2971 wt2 = FP_TO_INT32_OVERFLOW;
2972 }
2973 update_fcr31(env, GETPC());
2974 return wt2;
2975 }
2976
2977 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2978 {
2979 uint32_t wt2;
2980
2981 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2982 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2983 restore_rounding_mode(env);
2984 if (get_float_exception_flags(&env->active_fpu.fp_status)
2985 & (float_flag_invalid | float_flag_overflow)) {
2986 wt2 = FP_TO_INT32_OVERFLOW;
2987 }
2988 update_fcr31(env, GETPC());
2989 return wt2;
2990 }
2991
2992 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2993 {
2994 uint64_t dt2;
2995
2996 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2997 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2998 restore_rounding_mode(env);
2999 if (get_float_exception_flags(&env->active_fpu.fp_status)
3000 & (float_flag_invalid | float_flag_overflow)) {
3001 dt2 = FP_TO_INT64_OVERFLOW;
3002 }
3003 update_fcr31(env, GETPC());
3004 return dt2;
3005 }
3006
3007 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
3008 {
3009 uint64_t dt2;
3010
3011 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3012 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3013 restore_rounding_mode(env);
3014 if (get_float_exception_flags(&env->active_fpu.fp_status)
3015 & (float_flag_invalid | float_flag_overflow)) {
3016 dt2 = FP_TO_INT64_OVERFLOW;
3017 }
3018 update_fcr31(env, GETPC());
3019 return dt2;
3020 }
3021
3022 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
3023 {
3024 uint32_t wt2;
3025
3026 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3027 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3028 restore_rounding_mode(env);
3029 if (get_float_exception_flags(&env->active_fpu.fp_status)
3030 & (float_flag_invalid | float_flag_overflow)) {
3031 wt2 = FP_TO_INT32_OVERFLOW;
3032 }
3033 update_fcr31(env, GETPC());
3034 return wt2;
3035 }
3036
3037 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
3038 {
3039 uint32_t wt2;
3040
3041 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3042 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3043 restore_rounding_mode(env);
3044 if (get_float_exception_flags(&env->active_fpu.fp_status)
3045 & (float_flag_invalid | float_flag_overflow)) {
3046 wt2 = FP_TO_INT32_OVERFLOW;
3047 }
3048 update_fcr31(env, GETPC());
3049 return wt2;
3050 }
3051
3052 /* unary operations, not modifying fp status */
3053 #define FLOAT_UNOP(name) \
3054 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3055 { \
3056 return float64_ ## name(fdt0); \
3057 } \
3058 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3059 { \
3060 return float32_ ## name(fst0); \
3061 } \
3062 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3063 { \
3064 uint32_t wt0; \
3065 uint32_t wth0; \
3066 \
3067 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3068 wth0 = float32_ ## name(fdt0 >> 32); \
3069 return ((uint64_t)wth0 << 32) | wt0; \
3070 }
3071 FLOAT_UNOP(abs)
3072 FLOAT_UNOP(chs)
3073 #undef FLOAT_UNOP
3074
3075 /* MIPS specific unary operations */
3076 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3077 {
3078 uint64_t fdt2;
3079
3080 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3081 update_fcr31(env, GETPC());
3082 return fdt2;
3083 }
3084
3085 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3086 {
3087 uint32_t fst2;
3088
3089 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3090 update_fcr31(env, GETPC());
3091 return fst2;
3092 }
3093
3094 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3095 {
3096 uint64_t fdt2;
3097
3098 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3099 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3100 update_fcr31(env, GETPC());
3101 return fdt2;
3102 }
3103
3104 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3105 {
3106 uint32_t fst2;
3107
3108 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3109 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3110 update_fcr31(env, GETPC());
3111 return fst2;
3112 }
3113
3114 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3115 {
3116 uint64_t fdt2;
3117
3118 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3119 update_fcr31(env, GETPC());
3120 return fdt2;
3121 }
3122
3123 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3124 {
3125 uint32_t fst2;
3126
3127 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3128 update_fcr31(env, GETPC());
3129 return fst2;
3130 }
3131
3132 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3133 {
3134 uint32_t fst2;
3135 uint32_t fsth2;
3136
3137 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3138 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3139 update_fcr31(env, GETPC());
3140 return ((uint64_t)fsth2 << 32) | fst2;
3141 }
3142
3143 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3144 {
3145 uint64_t fdt2;
3146
3147 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3148 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3149 update_fcr31(env, GETPC());
3150 return fdt2;
3151 }
3152
3153 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3154 {
3155 uint32_t fst2;
3156
3157 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3158 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3159 update_fcr31(env, GETPC());
3160 return fst2;
3161 }
3162
3163 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3164 {
3165 uint32_t fst2;
3166 uint32_t fsth2;
3167
3168 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3169 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3170 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3171 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3172 update_fcr31(env, GETPC());
3173 return ((uint64_t)fsth2 << 32) | fst2;
3174 }
3175
3176 #define FLOAT_RINT(name, bits) \
3177 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3178 uint ## bits ## _t fs) \
3179 { \
3180 uint ## bits ## _t fdret; \
3181 \
3182 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3183 update_fcr31(env, GETPC()); \
3184 return fdret; \
3185 }
3186
3187 FLOAT_RINT(rint_s, 32)
3188 FLOAT_RINT(rint_d, 64)
3189 #undef FLOAT_RINT
3190
3191 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3192 #define FLOAT_CLASS_QUIET_NAN 0x002
3193 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3194 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3195 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3196 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3197 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3198 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3199 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3200 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3201
3202 #define FLOAT_CLASS(name, bits) \
3203 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
3204 { \
3205 if (float ## bits ## _is_signaling_nan(arg)) { \
3206 return FLOAT_CLASS_SIGNALING_NAN; \
3207 } else if (float ## bits ## _is_quiet_nan(arg)) { \
3208 return FLOAT_CLASS_QUIET_NAN; \
3209 } else if (float ## bits ## _is_neg(arg)) { \
3210 if (float ## bits ## _is_infinity(arg)) { \
3211 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3212 } else if (float ## bits ## _is_zero(arg)) { \
3213 return FLOAT_CLASS_NEGATIVE_ZERO; \
3214 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3215 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3216 } else { \
3217 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3218 } \
3219 } else { \
3220 if (float ## bits ## _is_infinity(arg)) { \
3221 return FLOAT_CLASS_POSITIVE_INFINITY; \
3222 } else if (float ## bits ## _is_zero(arg)) { \
3223 return FLOAT_CLASS_POSITIVE_ZERO; \
3224 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3225 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3226 } else { \
3227 return FLOAT_CLASS_POSITIVE_NORMAL; \
3228 } \
3229 } \
3230 }
3231
3232 FLOAT_CLASS(class_s, 32)
3233 FLOAT_CLASS(class_d, 64)
3234 #undef FLOAT_CLASS
3235
3236 /* binary operations */
3237 #define FLOAT_BINOP(name) \
3238 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3239 uint64_t fdt0, uint64_t fdt1) \
3240 { \
3241 uint64_t dt2; \
3242 \
3243 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3244 update_fcr31(env, GETPC()); \
3245 return dt2; \
3246 } \
3247 \
3248 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3249 uint32_t fst0, uint32_t fst1) \
3250 { \
3251 uint32_t wt2; \
3252 \
3253 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3254 update_fcr31(env, GETPC()); \
3255 return wt2; \
3256 } \
3257 \
3258 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3259 uint64_t fdt0, \
3260 uint64_t fdt1) \
3261 { \
3262 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3263 uint32_t fsth0 = fdt0 >> 32; \
3264 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3265 uint32_t fsth1 = fdt1 >> 32; \
3266 uint32_t wt2; \
3267 uint32_t wth2; \
3268 \
3269 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3270 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3271 update_fcr31(env, GETPC()); \
3272 return ((uint64_t)wth2 << 32) | wt2; \
3273 }
3274
3275 FLOAT_BINOP(add)
3276 FLOAT_BINOP(sub)
3277 FLOAT_BINOP(mul)
3278 FLOAT_BINOP(div)
3279 #undef FLOAT_BINOP
3280
3281 /* MIPS specific binary operations */
3282 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3283 {
3284 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3285 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3286 update_fcr31(env, GETPC());
3287 return fdt2;
3288 }
3289
3290 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3291 {
3292 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3293 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3294 update_fcr31(env, GETPC());
3295 return fst2;
3296 }
3297
3298 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3299 {
3300 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3301 uint32_t fsth0 = fdt0 >> 32;
3302 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3303 uint32_t fsth2 = fdt2 >> 32;
3304
3305 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3306 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3307 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3308 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3309 update_fcr31(env, GETPC());
3310 return ((uint64_t)fsth2 << 32) | fst2;
3311 }
3312
3313 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3314 {
3315 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3316 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3317 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3318 update_fcr31(env, GETPC());
3319 return fdt2;
3320 }
3321
3322 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3323 {
3324 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3325 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3326 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3327 update_fcr31(env, GETPC());
3328 return fst2;
3329 }
3330
3331 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3332 {
3333 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3334 uint32_t fsth0 = fdt0 >> 32;
3335 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3336 uint32_t fsth2 = fdt2 >> 32;
3337
3338 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3339 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3340 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3341 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3342 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3343 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3344 update_fcr31(env, GETPC());
3345 return ((uint64_t)fsth2 << 32) | fst2;
3346 }
3347
3348 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3349 {
3350 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3351 uint32_t fsth0 = fdt0 >> 32;
3352 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3353 uint32_t fsth1 = fdt1 >> 32;
3354 uint32_t fst2;
3355 uint32_t fsth2;
3356
3357 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3358 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3359 update_fcr31(env, GETPC());
3360 return ((uint64_t)fsth2 << 32) | fst2;
3361 }
3362
3363 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3364 {
3365 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3366 uint32_t fsth0 = fdt0 >> 32;
3367 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3368 uint32_t fsth1 = fdt1 >> 32;
3369 uint32_t fst2;
3370 uint32_t fsth2;
3371
3372 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3373 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3374 update_fcr31(env, GETPC());
3375 return ((uint64_t)fsth2 << 32) | fst2;
3376 }
3377
3378 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3379 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3380 uint ## bits ## _t fs, \
3381 uint ## bits ## _t ft) \
3382 { \
3383 uint ## bits ## _t fdret; \
3384 \
3385 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3386 &env->active_fpu.fp_status); \
3387 update_fcr31(env, GETPC()); \
3388 return fdret; \
3389 }
3390
3391 FLOAT_MINMAX(max_s, 32, maxnum)
3392 FLOAT_MINMAX(max_d, 64, maxnum)
3393 FLOAT_MINMAX(maxa_s, 32, maxnummag)
3394 FLOAT_MINMAX(maxa_d, 64, maxnummag)
3395
3396 FLOAT_MINMAX(min_s, 32, minnum)
3397 FLOAT_MINMAX(min_d, 64, minnum)
3398 FLOAT_MINMAX(mina_s, 32, minnummag)
3399 FLOAT_MINMAX(mina_d, 64, minnummag)
3400 #undef FLOAT_MINMAX
3401
3402 /* ternary operations */
3403 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3404 { \
3405 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3406 if ((flags) & float_muladd_negate_c) { \
3407 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3408 } else { \
3409 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3410 } \
3411 if ((flags) & float_muladd_negate_result) { \
3412 a = prefix##_chs(a); \
3413 } \
3414 }
3415
3416 /* FMA based operations */
3417 #define FLOAT_FMA(name, type) \
3418 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3419 uint64_t fdt0, uint64_t fdt1, \
3420 uint64_t fdt2) \
3421 { \
3422 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3423 update_fcr31(env, GETPC()); \
3424 return fdt0; \
3425 } \
3426 \
3427 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3428 uint32_t fst0, uint32_t fst1, \
3429 uint32_t fst2) \
3430 { \
3431 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3432 update_fcr31(env, GETPC()); \
3433 return fst0; \
3434 } \
3435 \
3436 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3437 uint64_t fdt0, uint64_t fdt1, \
3438 uint64_t fdt2) \
3439 { \
3440 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3441 uint32_t fsth0 = fdt0 >> 32; \
3442 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3443 uint32_t fsth1 = fdt1 >> 32; \
3444 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3445 uint32_t fsth2 = fdt2 >> 32; \
3446 \
3447 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3448 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3449 update_fcr31(env, GETPC()); \
3450 return ((uint64_t)fsth0 << 32) | fst0; \
3451 }
3452 FLOAT_FMA(madd, 0)
3453 FLOAT_FMA(msub, float_muladd_negate_c)
3454 FLOAT_FMA(nmadd, float_muladd_negate_result)
3455 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3456 #undef FLOAT_FMA
3457
3458 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3459 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3460 uint ## bits ## _t fs, \
3461 uint ## bits ## _t ft, \
3462 uint ## bits ## _t fd) \
3463 { \
3464 uint ## bits ## _t fdret; \
3465 \
3466 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3467 &env->active_fpu.fp_status); \
3468 update_fcr31(env, GETPC()); \
3469 return fdret; \
3470 }
3471
3472 FLOAT_FMADDSUB(maddf_s, 32, 0)
3473 FLOAT_FMADDSUB(maddf_d, 64, 0)
3474 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
3475 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
3476 #undef FLOAT_FMADDSUB
3477
3478 /* compare operations */
3479 #define FOP_COND_D(op, cond) \
3480 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3481 uint64_t fdt1, int cc) \
3482 { \
3483 int c; \
3484 c = cond; \
3485 update_fcr31(env, GETPC()); \
3486 if (c) \
3487 SET_FP_COND(cc, env->active_fpu); \
3488 else \
3489 CLEAR_FP_COND(cc, env->active_fpu); \
3490 } \
3491 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3492 uint64_t fdt1, int cc) \
3493 { \
3494 int c; \
3495 fdt0 = float64_abs(fdt0); \
3496 fdt1 = float64_abs(fdt1); \
3497 c = cond; \
3498 update_fcr31(env, GETPC()); \
3499 if (c) \
3500 SET_FP_COND(cc, env->active_fpu); \
3501 else \
3502 CLEAR_FP_COND(cc, env->active_fpu); \
3503 }
3504
3505 /* NOTE: the comma operator will make "cond" to eval to false,
3506 * but float64_unordered_quiet() is still called. */
3507 FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3508 FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3509 FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3510 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3511 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3512 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3513 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3514 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3515 /* NOTE: the comma operator will make "cond" to eval to false,
3516 * but float64_unordered() is still called. */
3517 FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3518 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3519 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3520 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3521 FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3522 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3523 FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3524 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3525
3526 #define FOP_COND_S(op, cond) \
3527 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3528 uint32_t fst1, int cc) \
3529 { \
3530 int c; \
3531 c = cond; \
3532 update_fcr31(env, GETPC()); \
3533 if (c) \
3534 SET_FP_COND(cc, env->active_fpu); \
3535 else \
3536 CLEAR_FP_COND(cc, env->active_fpu); \
3537 } \
3538 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3539 uint32_t fst1, int cc) \
3540 { \
3541 int c; \
3542 fst0 = float32_abs(fst0); \
3543 fst1 = float32_abs(fst1); \
3544 c = cond; \
3545 update_fcr31(env, GETPC()); \
3546 if (c) \
3547 SET_FP_COND(cc, env->active_fpu); \
3548 else \
3549 CLEAR_FP_COND(cc, env->active_fpu); \
3550 }
3551
3552 /* NOTE: the comma operator will make "cond" to eval to false,
3553 * but float32_unordered_quiet() is still called. */
3554 FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3555 FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3556 FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3557 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3558 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3559 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3560 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3561 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3562 /* NOTE: the comma operator will make "cond" to eval to false,
3563 * but float32_unordered() is still called. */
3564 FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3565 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3566 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3567 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3568 FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3569 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3570 FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
3571 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3572
3573 #define FOP_COND_PS(op, condl, condh) \
3574 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3575 uint64_t fdt1, int cc) \
3576 { \
3577 uint32_t fst0, fsth0, fst1, fsth1; \
3578 int ch, cl; \
3579 fst0 = fdt0 & 0XFFFFFFFF; \
3580 fsth0 = fdt0 >> 32; \
3581 fst1 = fdt1 & 0XFFFFFFFF; \
3582 fsth1 = fdt1 >> 32; \
3583 cl = condl; \
3584 ch = condh; \
3585 update_fcr31(env, GETPC()); \
3586 if (cl) \
3587 SET_FP_COND(cc, env->active_fpu); \
3588 else \
3589 CLEAR_FP_COND(cc, env->active_fpu); \
3590 if (ch) \
3591 SET_FP_COND(cc + 1, env->active_fpu); \
3592 else \
3593 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3594 } \
3595 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3596 uint64_t fdt1, int cc) \
3597 { \
3598 uint32_t fst0, fsth0, fst1, fsth1; \
3599 int ch, cl; \
3600 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3601 fsth0 = float32_abs(fdt0 >> 32); \
3602 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3603 fsth1 = float32_abs(fdt1 >> 32); \
3604 cl = condl; \
3605 ch = condh; \
3606 update_fcr31(env, GETPC()); \
3607 if (cl) \
3608 SET_FP_COND(cc, env->active_fpu); \
3609 else \
3610 CLEAR_FP_COND(cc, env->active_fpu); \
3611 if (ch) \
3612 SET_FP_COND(cc + 1, env->active_fpu); \
3613 else \
3614 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3615 }
3616
3617 /* NOTE: the comma operator will make "cond" to eval to false,
3618 * but float32_unordered_quiet() is still called. */
3619 FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3620 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3621 FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3622 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3623 FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3624 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3625 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3626 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3627 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3628 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3629 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3630 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3631 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3632 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3633 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3634 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3635 /* NOTE: the comma operator will make "cond" to eval to false,
3636 * but float32_unordered() is still called. */
3637 FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3638 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3639 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3640 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3641 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3642 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3643 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3644 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3645 FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3646 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3647 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3648 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3649 FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
3650 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3651 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3652 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3653
3654 /* R6 compare operations */
3655 #define FOP_CONDN_D(op, cond) \
3656 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
3657 uint64_t fdt1) \
3658 { \
3659 uint64_t c; \
3660 c = cond; \
3661 update_fcr31(env, GETPC()); \
3662 if (c) { \
3663 return -1; \
3664 } else { \
3665 return 0; \
3666 } \
3667 }
3668
3669 /* NOTE: the comma operator will make "cond" to eval to false,
3670 * but float64_unordered_quiet() is still called. */
3671 FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3672 FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3673 FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3674 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3675 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3676 FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3677 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3678 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3679 FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3680 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3681 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3682 /* NOTE: the comma operator will make "cond" to eval to false,
3683 * but float64_unordered() is still called. */
3684 FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3685 FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3686 FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3687 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3688 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3689 FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3690 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3691 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3692 FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3693 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3694 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3695 FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3696 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3697 FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3698 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3699 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3700 FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3701 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3702 FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3703 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3704 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3705 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3706 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3707 FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3708 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3709
3710 #define FOP_CONDN_S(op, cond) \
3711 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
3712 uint32_t fst1) \
3713 { \
3714 uint64_t c; \
3715 c = cond; \
3716 update_fcr31(env, GETPC()); \
3717 if (c) { \
3718 return -1; \
3719 } else { \
3720 return 0; \
3721 } \
3722 }
3723
3724 /* NOTE: the comma operator will make "cond" to eval to false,
3725 * but float32_unordered_quiet() is still called. */
3726 FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3727 FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3728 FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3729 FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3730 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3731 FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3732 FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3733 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3734 FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3735 FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3736 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3737 /* NOTE: the comma operator will make "cond" to eval to false,
3738 * but float32_unordered() is still called. */
3739 FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3740 FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3741 FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3742 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3743 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3744 FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3745 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3746 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3747 FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3748 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3749 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3750 FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3751 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3752 FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3753 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3754 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3755 FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3756 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3757 FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3758 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3759 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3760 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3761 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3762 FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3763 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3764
3765 /* MSA */
3766 /* Data format min and max values */
3767 #define DF_BITS(df) (1 << ((df) + 3))
3768
3769 /* Element-by-element access macros */
3770 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3771
3772 #if !defined(CONFIG_USER_ONLY)
3773 #define MEMOP_IDX(DF) \
3774 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
3775 cpu_mmu_index(env, false));
3776 #else
3777 #define MEMOP_IDX(DF)
3778 #endif
3779
3780 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
3781 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3782 target_ulong addr) \
3783 { \
3784 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3785 wr_t wx; \
3786 int i; \
3787 MEMOP_IDX(DF) \
3788 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3789 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
3790 } \
3791 memcpy(pwd, &wx, sizeof(wr_t)); \
3792 }
3793
3794 #if !defined(CONFIG_USER_ONLY)
3795 MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, oi, GETRA())
3796 MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, oi, GETRA())
3797 MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, oi, GETRA())
3798 MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, oi, GETRA())
3799 #else
3800 MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
3801 MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
3802 MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
3803 MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
3804 #endif
3805
3806 #define MSA_PAGESPAN(x) \
3807 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3808
3809 static inline void ensure_writable_pages(CPUMIPSState *env,
3810 target_ulong addr,
3811 int mmu_idx,
3812 uintptr_t retaddr)
3813 {
3814 #if !defined(CONFIG_USER_ONLY)
3815 target_ulong page_addr;
3816 if (unlikely(MSA_PAGESPAN(addr))) {
3817 /* first page */
3818 probe_write(env, addr, mmu_idx, retaddr);
3819 /* second page */
3820 page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3821 probe_write(env, page_addr, mmu_idx, retaddr);
3822 }
3823 #endif
3824 }
3825
3826 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
3827 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3828 target_ulong addr) \
3829 { \
3830 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3831 int mmu_idx = cpu_mmu_index(env, false); \
3832 int i; \
3833 MEMOP_IDX(DF) \
3834 ensure_writable_pages(env, addr, mmu_idx, GETRA()); \
3835 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3836 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
3837 } \
3838 }
3839
3840 #if !defined(CONFIG_USER_ONLY)
3841 MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, oi, GETRA())
3842 MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, oi, GETRA())
3843 MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, oi, GETRA())
3844 MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, oi, GETRA())
3845 #else
3846 MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
3847 MSA_ST_DF(DF_HALF, h, cpu_stw_data)
3848 MSA_ST_DF(DF_WORD, w, cpu_stl_data)
3849 MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
3850 #endif
3851
3852 void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
3853 {
3854 #ifndef CONFIG_USER_ONLY
3855 target_ulong index = addr & 0x1fffffff;
3856 if (op == 9) {
3857 /* Index Store Tag */
3858 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
3859 8, MEMTXATTRS_UNSPECIFIED);
3860 } else if (op == 5) {
3861 /* Index Load Tag */
3862 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
3863 8, MEMTXATTRS_UNSPECIFIED);
3864 }
3865 #endif
3866 }
QEmu