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.travis.yml: rationalise clang testing
[qemu.git] / memory.c
blob10fa2ddd31e507d803537d00489a14898b3831d2
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "qemu-common.h"
19 #include "cpu.h"
20 #include "exec/memory.h"
21 #include "exec/address-spaces.h"
22 #include "exec/ioport.h"
23 #include "qapi/visitor.h"
24 #include "qemu/bitops.h"
25 #include "qemu/error-report.h"
26 #include "qom/object.h"
27 #include "trace-root.h"
28
29 #include "exec/memory-internal.h"
30 #include "exec/ram_addr.h"
31 #include "sysemu/kvm.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/misc/mmio_interface.h"
34 #include "hw/qdev-properties.h"
35 #include "migration/vmstate.h"
36
37 //#define DEBUG_UNASSIGNED
38
39 static unsigned memory_region_transaction_depth;
40 static bool memory_region_update_pending;
41 static bool ioeventfd_update_pending;
42 static bool global_dirty_log = false;
43
44 static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
45 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
46
47 static QTAILQ_HEAD(, AddressSpace) address_spaces
48 = QTAILQ_HEAD_INITIALIZER(address_spaces);
49
50 static GHashTable *flat_views;
51
52 typedef struct AddrRange AddrRange;
53
54 /*
55 * Note that signed integers are needed for negative offsetting in aliases
56 * (large MemoryRegion::alias_offset).
57 */
58 struct AddrRange {
59 Int128 start;
60 Int128 size;
61 };
62
63 static AddrRange addrrange_make(Int128 start, Int128 size)
64 {
65 return (AddrRange) { start, size };
66 }
67
68 static bool addrrange_equal(AddrRange r1, AddrRange r2)
69 {
70 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
71 }
72
73 static Int128 addrrange_end(AddrRange r)
74 {
75 return int128_add(r.start, r.size);
76 }
77
78 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
79 {
80 int128_addto(&range.start, delta);
81 return range;
82 }
83
84 static bool addrrange_contains(AddrRange range, Int128 addr)
85 {
86 return int128_ge(addr, range.start)
87 && int128_lt(addr, addrrange_end(range));
88 }
89
90 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
91 {
92 return addrrange_contains(r1, r2.start)
93 || addrrange_contains(r2, r1.start);
94 }
95
96 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
97 {
98 Int128 start = int128_max(r1.start, r2.start);
99 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
100 return addrrange_make(start, int128_sub(end, start));
101 }
102
103 enum ListenerDirection { Forward, Reverse };
104
105 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
106 do { \
107 MemoryListener *_listener; \
108 \
109 switch (_direction) { \
110 case Forward: \
111 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
112 if (_listener->_callback) { \
113 _listener->_callback(_listener, ##_args); \
114 } \
115 } \
116 break; \
117 case Reverse: \
118 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, \
119 memory_listeners, link) { \
120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
130 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
131 do { \
132 MemoryListener *_listener; \
133 struct memory_listeners_as *list = &(_as)->listeners; \
134 \
135 switch (_direction) { \
136 case Forward: \
137 QTAILQ_FOREACH(_listener, list, link_as) { \
138 if (_listener->_callback) { \
139 _listener->_callback(_listener, _section, ##_args); \
140 } \
141 } \
142 break; \
143 case Reverse: \
144 QTAILQ_FOREACH_REVERSE(_listener, list, memory_listeners_as, \
145 link_as) { \
146 if (_listener->_callback) { \
147 _listener->_callback(_listener, _section, ##_args); \
148 } \
149 } \
150 break; \
151 default: \
152 abort(); \
153 } \
154 } while (0)
155
156 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
157 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
158 do { \
159 MemoryRegionSection mrs = section_from_flat_range(fr, \
160 address_space_to_flatview(as)); \
161 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
162 } while(0)
163
164 struct CoalescedMemoryRange {
165 AddrRange addr;
166 QTAILQ_ENTRY(CoalescedMemoryRange) link;
167 };
168
169 struct MemoryRegionIoeventfd {
170 AddrRange addr;
171 bool match_data;
172 uint64_t data;
173 EventNotifier *e;
174 };
175
176 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
177 MemoryRegionIoeventfd b)
178 {
179 if (int128_lt(a.addr.start, b.addr.start)) {
180 return true;
181 } else if (int128_gt(a.addr.start, b.addr.start)) {
182 return false;
183 } else if (int128_lt(a.addr.size, b.addr.size)) {
184 return true;
185 } else if (int128_gt(a.addr.size, b.addr.size)) {
186 return false;
187 } else if (a.match_data < b.match_data) {
188 return true;
189 } else if (a.match_data > b.match_data) {
190 return false;
191 } else if (a.match_data) {
192 if (a.data < b.data) {
193 return true;
194 } else if (a.data > b.data) {
195 return false;
196 }
197 }
198 if (a.e < b.e) {
199 return true;
200 } else if (a.e > b.e) {
201 return false;
202 }
203 return false;
204 }
205
206 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd a,
207 MemoryRegionIoeventfd b)
208 {
209 return !memory_region_ioeventfd_before(a, b)
210 && !memory_region_ioeventfd_before(b, a);
211 }
212
213 /* Range of memory in the global map. Addresses are absolute. */
214 struct FlatRange {
215 MemoryRegion *mr;
216 hwaddr offset_in_region;
217 AddrRange addr;
218 uint8_t dirty_log_mask;
219 bool romd_mode;
220 bool readonly;
221 };
222
223 typedef struct AddressSpaceOps AddressSpaceOps;
224
225 #define FOR_EACH_FLAT_RANGE(var, view) \
226 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
227
228 static inline MemoryRegionSection
229 section_from_flat_range(FlatRange *fr, FlatView *fv)
230 {
231 return (MemoryRegionSection) {
232 .mr = fr->mr,
233 .fv = fv,
234 .offset_within_region = fr->offset_in_region,
235 .size = fr->addr.size,
236 .offset_within_address_space = int128_get64(fr->addr.start),
237 .readonly = fr->readonly,
238 };
239 }
240
241 static bool flatrange_equal(FlatRange *a, FlatRange *b)
242 {
243 return a->mr == b->mr
244 && addrrange_equal(a->addr, b->addr)
245 && a->offset_in_region == b->offset_in_region
246 && a->romd_mode == b->romd_mode
247 && a->readonly == b->readonly;
248 }
249
250 static FlatView *flatview_new(MemoryRegion *mr_root)
251 {
252 FlatView *view;
253
254 view = g_new0(FlatView, 1);
255 view->ref = 1;
256 view->root = mr_root;
257 memory_region_ref(mr_root);
258 trace_flatview_new(view, mr_root);
259
260 return view;
261 }
262
263 /* Insert a range into a given position. Caller is responsible for maintaining
264 * sorting order.
265 */
266 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
267 {
268 if (view->nr == view->nr_allocated) {
269 view->nr_allocated = MAX(2 * view->nr, 10);
270 view->ranges = g_realloc(view->ranges,
271 view->nr_allocated * sizeof(*view->ranges));
272 }
273 memmove(view->ranges + pos + 1, view->ranges + pos,
274 (view->nr - pos) * sizeof(FlatRange));
275 view->ranges[pos] = *range;
276 memory_region_ref(range->mr);
277 ++view->nr;
278 }
279
280 static void flatview_destroy(FlatView *view)
281 {
282 int i;
283
284 trace_flatview_destroy(view, view->root);
285 if (view->dispatch) {
286 address_space_dispatch_free(view->dispatch);
287 }
288 for (i = 0; i < view->nr; i++) {
289 memory_region_unref(view->ranges[i].mr);
290 }
291 g_free(view->ranges);
292 memory_region_unref(view->root);
293 g_free(view);
294 }
295
296 static bool flatview_ref(FlatView *view)
297 {
298 return atomic_fetch_inc_nonzero(&view->ref) > 0;
299 }
300
301 void flatview_unref(FlatView *view)
302 {
303 if (atomic_fetch_dec(&view->ref) == 1) {
304 trace_flatview_destroy_rcu(view, view->root);
305 assert(view->root);
306 call_rcu(view, flatview_destroy, rcu);
307 }
308 }
309
310 static bool can_merge(FlatRange *r1, FlatRange *r2)
311 {
312 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
313 && r1->mr == r2->mr
314 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
315 r1->addr.size),
316 int128_make64(r2->offset_in_region))
317 && r1->dirty_log_mask == r2->dirty_log_mask
318 && r1->romd_mode == r2->romd_mode
319 && r1->readonly == r2->readonly;
320 }
321
322 /* Attempt to simplify a view by merging adjacent ranges */
323 static void flatview_simplify(FlatView *view)
324 {
325 unsigned i, j;
326
327 i = 0;
328 while (i < view->nr) {
329 j = i + 1;
330 while (j < view->nr
331 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
332 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
333 ++j;
334 }
335 ++i;
336 memmove(&view->ranges[i], &view->ranges[j],
337 (view->nr - j) * sizeof(view->ranges[j]));
338 view->nr -= j - i;
339 }
340 }
341
342 static bool memory_region_big_endian(MemoryRegion *mr)
343 {
344 #ifdef TARGET_WORDS_BIGENDIAN
345 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
346 #else
347 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
348 #endif
349 }
350
351 static bool memory_region_wrong_endianness(MemoryRegion *mr)
352 {
353 #ifdef TARGET_WORDS_BIGENDIAN
354 return mr->ops->endianness == DEVICE_LITTLE_ENDIAN;
355 #else
356 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
357 #endif
358 }
359
360 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, unsigned size)
361 {
362 if (memory_region_wrong_endianness(mr)) {
363 switch (size) {
364 case 1:
365 break;
366 case 2:
367 *data = bswap16(*data);
368 break;
369 case 4:
370 *data = bswap32(*data);
371 break;
372 case 8:
373 *data = bswap64(*data);
374 break;
375 default:
376 abort();
377 }
378 }
379 }
380
381 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
382 {
383 MemoryRegion *root;
384 hwaddr abs_addr = offset;
385
386 abs_addr += mr->addr;
387 for (root = mr; root->container; ) {
388 root = root->container;
389 abs_addr += root->addr;
390 }
391
392 return abs_addr;
393 }
394
395 static int get_cpu_index(void)
396 {
397 if (current_cpu) {
398 return current_cpu->cpu_index;
399 }
400 return -1;
401 }
402
403 static MemTxResult memory_region_oldmmio_read_accessor(MemoryRegion *mr,
404 hwaddr addr,
405 uint64_t *value,
406 unsigned size,
407 unsigned shift,
408 uint64_t mask,
409 MemTxAttrs attrs)
410 {
411 uint64_t tmp;
412
413 tmp = mr->ops->old_mmio.read[ctz32(size)](mr->opaque, addr);
414 if (mr->subpage) {
415 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
416 } else if (mr == &io_mem_notdirty) {
417 /* Accesses to code which has previously been translated into a TB show
418 * up in the MMIO path, as accesses to the io_mem_notdirty
419 * MemoryRegion. */
420 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
421 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
422 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
423 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
424 }
425 *value |= (tmp & mask) << shift;
426 return MEMTX_OK;
427 }
428
429 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
430 hwaddr addr,
431 uint64_t *value,
432 unsigned size,
433 unsigned shift,
434 uint64_t mask,
435 MemTxAttrs attrs)
436 {
437 uint64_t tmp;
438
439 tmp = mr->ops->read(mr->opaque, addr, size);
440 if (mr->subpage) {
441 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
442 } else if (mr == &io_mem_notdirty) {
443 /* Accesses to code which has previously been translated into a TB show
444 * up in the MMIO path, as accesses to the io_mem_notdirty
445 * MemoryRegion. */
446 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
447 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
448 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
449 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
450 }
451 *value |= (tmp & mask) << shift;
452 return MEMTX_OK;
453 }
454
455 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
456 hwaddr addr,
457 uint64_t *value,
458 unsigned size,
459 unsigned shift,
460 uint64_t mask,
461 MemTxAttrs attrs)
462 {
463 uint64_t tmp = 0;
464 MemTxResult r;
465
466 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
467 if (mr->subpage) {
468 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
469 } else if (mr == &io_mem_notdirty) {
470 /* Accesses to code which has previously been translated into a TB show
471 * up in the MMIO path, as accesses to the io_mem_notdirty
472 * MemoryRegion. */
473 trace_memory_region_tb_read(get_cpu_index(), addr, tmp, size);
474 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
475 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
476 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
477 }
478 *value |= (tmp & mask) << shift;
479 return r;
480 }
481
482 static MemTxResult memory_region_oldmmio_write_accessor(MemoryRegion *mr,
483 hwaddr addr,
484 uint64_t *value,
485 unsigned size,
486 unsigned shift,
487 uint64_t mask,
488 MemTxAttrs attrs)
489 {
490 uint64_t tmp;
491
492 tmp = (*value >> shift) & mask;
493 if (mr->subpage) {
494 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
495 } else if (mr == &io_mem_notdirty) {
496 /* Accesses to code which has previously been translated into a TB show
497 * up in the MMIO path, as accesses to the io_mem_notdirty
498 * MemoryRegion. */
499 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
500 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
501 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
502 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
503 }
504 mr->ops->old_mmio.write[ctz32(size)](mr->opaque, addr, tmp);
505 return MEMTX_OK;
506 }
507
508 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
509 hwaddr addr,
510 uint64_t *value,
511 unsigned size,
512 unsigned shift,
513 uint64_t mask,
514 MemTxAttrs attrs)
515 {
516 uint64_t tmp;
517
518 tmp = (*value >> shift) & mask;
519 if (mr->subpage) {
520 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
521 } else if (mr == &io_mem_notdirty) {
522 /* Accesses to code which has previously been translated into a TB show
523 * up in the MMIO path, as accesses to the io_mem_notdirty
524 * MemoryRegion. */
525 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
526 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
527 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
528 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
529 }
530 mr->ops->write(mr->opaque, addr, tmp, size);
531 return MEMTX_OK;
532 }
533
534 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
535 hwaddr addr,
536 uint64_t *value,
537 unsigned size,
538 unsigned shift,
539 uint64_t mask,
540 MemTxAttrs attrs)
541 {
542 uint64_t tmp;
543
544 tmp = (*value >> shift) & mask;
545 if (mr->subpage) {
546 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
547 } else if (mr == &io_mem_notdirty) {
548 /* Accesses to code which has previously been translated into a TB show
549 * up in the MMIO path, as accesses to the io_mem_notdirty
550 * MemoryRegion. */
551 trace_memory_region_tb_write(get_cpu_index(), addr, tmp, size);
552 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
553 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
554 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
555 }
556 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
557 }
558
559 static MemTxResult access_with_adjusted_size(hwaddr addr,
560 uint64_t *value,
561 unsigned size,
562 unsigned access_size_min,
563 unsigned access_size_max,
564 MemTxResult (*access_fn)
565 (MemoryRegion *mr,
566 hwaddr addr,
567 uint64_t *value,
568 unsigned size,
569 unsigned shift,
570 uint64_t mask,
571 MemTxAttrs attrs),
572 MemoryRegion *mr,
573 MemTxAttrs attrs)
574 {
575 uint64_t access_mask;
576 unsigned access_size;
577 unsigned i;
578 MemTxResult r = MEMTX_OK;
579
580 if (!access_size_min) {
581 access_size_min = 1;
582 }
583 if (!access_size_max) {
584 access_size_max = 4;
585 }
586
587 /* FIXME: support unaligned access? */
588 access_size = MAX(MIN(size, access_size_max), access_size_min);
589 access_mask = -1ULL >> (64 - access_size * 8);
590 if (memory_region_big_endian(mr)) {
591 for (i = 0; i < size; i += access_size) {
592 r |= access_fn(mr, addr + i, value, access_size,
593 (size - access_size - i) * 8, access_mask, attrs);
594 }
595 } else {
596 for (i = 0; i < size; i += access_size) {
597 r |= access_fn(mr, addr + i, value, access_size, i * 8,
598 access_mask, attrs);
599 }
600 }
601 return r;
602 }
603
604 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
605 {
606 AddressSpace *as;
607
608 while (mr->container) {
609 mr = mr->container;
610 }
611 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
612 if (mr == as->root) {
613 return as;
614 }
615 }
616 return NULL;
617 }
618
619 /* Render a memory region into the global view. Ranges in @view obscure
620 * ranges in @mr.
621 */
622 static void render_memory_region(FlatView *view,
623 MemoryRegion *mr,
624 Int128 base,
625 AddrRange clip,
626 bool readonly)
627 {
628 MemoryRegion *subregion;
629 unsigned i;
630 hwaddr offset_in_region;
631 Int128 remain;
632 Int128 now;
633 FlatRange fr;
634 AddrRange tmp;
635
636 if (!mr->enabled) {
637 return;
638 }
639
640 int128_addto(&base, int128_make64(mr->addr));
641 readonly |= mr->readonly;
642
643 tmp = addrrange_make(base, mr->size);
644
645 if (!addrrange_intersects(tmp, clip)) {
646 return;
647 }
648
649 clip = addrrange_intersection(tmp, clip);
650
651 if (mr->alias) {
652 int128_subfrom(&base, int128_make64(mr->alias->addr));
653 int128_subfrom(&base, int128_make64(mr->alias_offset));
654 render_memory_region(view, mr->alias, base, clip, readonly);
655 return;
656 }
657
658 /* Render subregions in priority order. */
659 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
660 render_memory_region(view, subregion, base, clip, readonly);
661 }
662
663 if (!mr->terminates) {
664 return;
665 }
666
667 offset_in_region = int128_get64(int128_sub(clip.start, base));
668 base = clip.start;
669 remain = clip.size;
670
671 fr.mr = mr;
672 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
673 fr.romd_mode = mr->romd_mode;
674 fr.readonly = readonly;
675
676 /* Render the region itself into any gaps left by the current view. */
677 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
678 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
679 continue;
680 }
681 if (int128_lt(base, view->ranges[i].addr.start)) {
682 now = int128_min(remain,
683 int128_sub(view->ranges[i].addr.start, base));
684 fr.offset_in_region = offset_in_region;
685 fr.addr = addrrange_make(base, now);
686 flatview_insert(view, i, &fr);
687 ++i;
688 int128_addto(&base, now);
689 offset_in_region += int128_get64(now);
690 int128_subfrom(&remain, now);
691 }
692 now = int128_sub(int128_min(int128_add(base, remain),
693 addrrange_end(view->ranges[i].addr)),
694 base);
695 int128_addto(&base, now);
696 offset_in_region += int128_get64(now);
697 int128_subfrom(&remain, now);
698 }
699 if (int128_nz(remain)) {
700 fr.offset_in_region = offset_in_region;
701 fr.addr = addrrange_make(base, remain);
702 flatview_insert(view, i, &fr);
703 }
704 }
705
706 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
707 {
708 while (mr->enabled) {
709 if (mr->alias) {
710 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
711 /* The alias is included in its entirety. Use it as
712 * the "real" root, so that we can share more FlatViews.
713 */
714 mr = mr->alias;
715 continue;
716 }
717 } else if (!mr->terminates) {
718 unsigned int found = 0;
719 MemoryRegion *child, *next = NULL;
720 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
721 if (child->enabled) {
722 if (++found > 1) {
723 next = NULL;
724 break;
725 }
726 if (!child->addr && int128_ge(mr->size, child->size)) {
727 /* A child is included in its entirety. If it's the only
728 * enabled one, use it in the hope of finding an alias down the
729 * way. This will also let us share FlatViews.
730 */
731 next = child;
732 }
733 }
734 }
735 if (found == 0) {
736 return NULL;
737 }
738 if (next) {
739 mr = next;
740 continue;
741 }
742 }
743
744 return mr;
745 }
746
747 return NULL;
748 }
749
750 /* Render a memory topology into a list of disjoint absolute ranges. */
751 static FlatView *generate_memory_topology(MemoryRegion *mr)
752 {
753 int i;
754 FlatView *view;
755
756 view = flatview_new(mr);
757
758 if (mr) {
759 render_memory_region(view, mr, int128_zero(),
760 addrrange_make(int128_zero(), int128_2_64()), false);
761 }
762 flatview_simplify(view);
763
764 view->dispatch = address_space_dispatch_new(view);
765 for (i = 0; i < view->nr; i++) {
766 MemoryRegionSection mrs =
767 section_from_flat_range(&view->ranges[i], view);
768 flatview_add_to_dispatch(view, &mrs);
769 }
770 address_space_dispatch_compact(view->dispatch);
771 g_hash_table_replace(flat_views, mr, view);
772
773 return view;
774 }
775
776 static void address_space_add_del_ioeventfds(AddressSpace *as,
777 MemoryRegionIoeventfd *fds_new,
778 unsigned fds_new_nb,
779 MemoryRegionIoeventfd *fds_old,
780 unsigned fds_old_nb)
781 {
782 unsigned iold, inew;
783 MemoryRegionIoeventfd *fd;
784 MemoryRegionSection section;
785
786 /* Generate a symmetric difference of the old and new fd sets, adding
787 * and deleting as necessary.
788 */
789
790 iold = inew = 0;
791 while (iold < fds_old_nb || inew < fds_new_nb) {
792 if (iold < fds_old_nb
793 && (inew == fds_new_nb
794 || memory_region_ioeventfd_before(fds_old[iold],
795 fds_new[inew]))) {
796 fd = &fds_old[iold];
797 section = (MemoryRegionSection) {
798 .fv = address_space_to_flatview(as),
799 .offset_within_address_space = int128_get64(fd->addr.start),
800 .size = fd->addr.size,
801 };
802 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
803 fd->match_data, fd->data, fd->e);
804 ++iold;
805 } else if (inew < fds_new_nb
806 && (iold == fds_old_nb
807 || memory_region_ioeventfd_before(fds_new[inew],
808 fds_old[iold]))) {
809 fd = &fds_new[inew];
810 section = (MemoryRegionSection) {
811 .fv = address_space_to_flatview(as),
812 .offset_within_address_space = int128_get64(fd->addr.start),
813 .size = fd->addr.size,
814 };
815 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
816 fd->match_data, fd->data, fd->e);
817 ++inew;
818 } else {
819 ++iold;
820 ++inew;
821 }
822 }
823 }
824
825 FlatView *address_space_get_flatview(AddressSpace *as)
826 {
827 FlatView *view;
828
829 rcu_read_lock();
830 do {
831 view = address_space_to_flatview(as);
832 /* If somebody has replaced as->current_map concurrently,
833 * flatview_ref returns false.
834 */
835 } while (!flatview_ref(view));
836 rcu_read_unlock();
837 return view;
838 }
839
840 static void address_space_update_ioeventfds(AddressSpace *as)
841 {
842 FlatView *view;
843 FlatRange *fr;
844 unsigned ioeventfd_nb = 0;
845 MemoryRegionIoeventfd *ioeventfds = NULL;
846 AddrRange tmp;
847 unsigned i;
848
849 view = address_space_get_flatview(as);
850 FOR_EACH_FLAT_RANGE(fr, view) {
851 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
852 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
853 int128_sub(fr->addr.start,
854 int128_make64(fr->offset_in_region)));
855 if (addrrange_intersects(fr->addr, tmp)) {
856 ++ioeventfd_nb;
857 ioeventfds = g_realloc(ioeventfds,
858 ioeventfd_nb * sizeof(*ioeventfds));
859 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
860 ioeventfds[ioeventfd_nb-1].addr = tmp;
861 }
862 }
863 }
864
865 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
866 as->ioeventfds, as->ioeventfd_nb);
867
868 g_free(as->ioeventfds);
869 as->ioeventfds = ioeventfds;
870 as->ioeventfd_nb = ioeventfd_nb;
871 flatview_unref(view);
872 }
873
874 static void address_space_update_topology_pass(AddressSpace *as,
875 const FlatView *old_view,
876 const FlatView *new_view,
877 bool adding)
878 {
879 unsigned iold, inew;
880 FlatRange *frold, *frnew;
881
882 /* Generate a symmetric difference of the old and new memory maps.
883 * Kill ranges in the old map, and instantiate ranges in the new map.
884 */
885 iold = inew = 0;
886 while (iold < old_view->nr || inew < new_view->nr) {
887 if (iold < old_view->nr) {
888 frold = &old_view->ranges[iold];
889 } else {
890 frold = NULL;
891 }
892 if (inew < new_view->nr) {
893 frnew = &new_view->ranges[inew];
894 } else {
895 frnew = NULL;
896 }
897
898 if (frold
899 && (!frnew
900 || int128_lt(frold->addr.start, frnew->addr.start)
901 || (int128_eq(frold->addr.start, frnew->addr.start)
902 && !flatrange_equal(frold, frnew)))) {
903 /* In old but not in new, or in both but attributes changed. */
904
905 if (!adding) {
906 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
907 }
908
909 ++iold;
910 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
911 /* In both and unchanged (except logging may have changed) */
912
913 if (adding) {
914 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
915 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
916 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
917 frold->dirty_log_mask,
918 frnew->dirty_log_mask);
919 }
920 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
921 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
922 frold->dirty_log_mask,
923 frnew->dirty_log_mask);
924 }
925 }
926
927 ++iold;
928 ++inew;
929 } else {
930 /* In new */
931
932 if (adding) {
933 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
934 }
935
936 ++inew;
937 }
938 }
939 }
940
941 static void flatviews_init(void)
942 {
943 static FlatView *empty_view;
944
945 if (flat_views) {
946 return;
947 }
948
949 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
950 (GDestroyNotify) flatview_unref);
951 if (!empty_view) {
952 empty_view = generate_memory_topology(NULL);
953 /* We keep it alive forever in the global variable. */
954 flatview_ref(empty_view);
955 } else {
956 g_hash_table_replace(flat_views, NULL, empty_view);
957 flatview_ref(empty_view);
958 }
959 }
960
961 static void flatviews_reset(void)
962 {
963 AddressSpace *as;
964
965 if (flat_views) {
966 g_hash_table_unref(flat_views);
967 flat_views = NULL;
968 }
969 flatviews_init();
970
971 /* Render unique FVs */
972 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
973 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
974
975 if (g_hash_table_lookup(flat_views, physmr)) {
976 continue;
977 }
978
979 generate_memory_topology(physmr);
980 }
981 }
982
983 static void address_space_set_flatview(AddressSpace *as)
984 {
985 FlatView *old_view = address_space_to_flatview(as);
986 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
987 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
988
989 assert(new_view);
990
991 if (old_view == new_view) {
992 return;
993 }
994
995 if (old_view) {
996 flatview_ref(old_view);
997 }
998
999 flatview_ref(new_view);
1000
1001 if (!QTAILQ_EMPTY(&as->listeners)) {
1002 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1003
1004 if (!old_view2) {
1005 old_view2 = &tmpview;
1006 }
1007 address_space_update_topology_pass(as, old_view2, new_view, false);
1008 address_space_update_topology_pass(as, old_view2, new_view, true);
1009 }
1010
1011 /* Writes are protected by the BQL. */
1012 atomic_rcu_set(&as->current_map, new_view);
1013 if (old_view) {
1014 flatview_unref(old_view);
1015 }
1016
1017 /* Note that all the old MemoryRegions are still alive up to this
1018 * point. This relieves most MemoryListeners from the need to
1019 * ref/unref the MemoryRegions they get---unless they use them
1020 * outside the iothread mutex, in which case precise reference
1021 * counting is necessary.
1022 */
1023 if (old_view) {
1024 flatview_unref(old_view);
1025 }
1026 }
1027
1028 static void address_space_update_topology(AddressSpace *as)
1029 {
1030 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1031
1032 flatviews_init();
1033 if (!g_hash_table_lookup(flat_views, physmr)) {
1034 generate_memory_topology(physmr);
1035 }
1036 address_space_set_flatview(as);
1037 }
1038
1039 void memory_region_transaction_begin(void)
1040 {
1041 qemu_flush_coalesced_mmio_buffer();
1042 ++memory_region_transaction_depth;
1043 }
1044
1045 void memory_region_transaction_commit(void)
1046 {
1047 AddressSpace *as;
1048
1049 assert(memory_region_transaction_depth);
1050 assert(qemu_mutex_iothread_locked());
1051
1052 --memory_region_transaction_depth;
1053 if (!memory_region_transaction_depth) {
1054 if (memory_region_update_pending) {
1055 flatviews_reset();
1056
1057 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1058
1059 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1060 address_space_set_flatview(as);
1061 address_space_update_ioeventfds(as);
1062 }
1063 memory_region_update_pending = false;
1064 ioeventfd_update_pending = false;
1065 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1066 } else if (ioeventfd_update_pending) {
1067 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1068 address_space_update_ioeventfds(as);
1069 }
1070 ioeventfd_update_pending = false;
1071 }
1072 }
1073 }
1074
1075 static void memory_region_destructor_none(MemoryRegion *mr)
1076 {
1077 }
1078
1079 static void memory_region_destructor_ram(MemoryRegion *mr)
1080 {
1081 qemu_ram_free(mr->ram_block);
1082 }
1083
1084 static bool memory_region_need_escape(char c)
1085 {
1086 return c == '/' || c == '[' || c == '\\' || c == ']';
1087 }
1088
1089 static char *memory_region_escape_name(const char *name)
1090 {
1091 const char *p;
1092 char *escaped, *q;
1093 uint8_t c;
1094 size_t bytes = 0;
1095
1096 for (p = name; *p; p++) {
1097 bytes += memory_region_need_escape(*p) ? 4 : 1;
1098 }
1099 if (bytes == p - name) {
1100 return g_memdup(name, bytes + 1);
1101 }
1102
1103 escaped = g_malloc(bytes + 1);
1104 for (p = name, q = escaped; *p; p++) {
1105 c = *p;
1106 if (unlikely(memory_region_need_escape(c))) {
1107 *q++ = '\\';
1108 *q++ = 'x';
1109 *q++ = "0123456789abcdef"[c >> 4];
1110 c = "0123456789abcdef"[c & 15];
1111 }
1112 *q++ = c;
1113 }
1114 *q = 0;
1115 return escaped;
1116 }
1117
1118 static void memory_region_do_init(MemoryRegion *mr,
1119 Object *owner,
1120 const char *name,
1121 uint64_t size)
1122 {
1123 mr->size = int128_make64(size);
1124 if (size == UINT64_MAX) {
1125 mr->size = int128_2_64();
1126 }
1127 mr->name = g_strdup(name);
1128 mr->owner = owner;
1129 mr->ram_block = NULL;
1130
1131 if (name) {
1132 char *escaped_name = memory_region_escape_name(name);
1133 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1134
1135 if (!owner) {
1136 owner = container_get(qdev_get_machine(), "/unattached");
1137 }
1138
1139 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1140 object_unref(OBJECT(mr));
1141 g_free(name_array);
1142 g_free(escaped_name);
1143 }
1144 }
1145
1146 void memory_region_init(MemoryRegion *mr,
1147 Object *owner,
1148 const char *name,
1149 uint64_t size)
1150 {
1151 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1152 memory_region_do_init(mr, owner, name, size);
1153 }
1154
1155 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1156 void *opaque, Error **errp)
1157 {
1158 MemoryRegion *mr = MEMORY_REGION(obj);
1159 uint64_t value = mr->addr;
1160
1161 visit_type_uint64(v, name, &value, errp);
1162 }
1163
1164 static void memory_region_get_container(Object *obj, Visitor *v,
1165 const char *name, void *opaque,
1166 Error **errp)
1167 {
1168 MemoryRegion *mr = MEMORY_REGION(obj);
1169 gchar *path = (gchar *)"";
1170
1171 if (mr->container) {
1172 path = object_get_canonical_path(OBJECT(mr->container));
1173 }
1174 visit_type_str(v, name, &path, errp);
1175 if (mr->container) {
1176 g_free(path);
1177 }
1178 }
1179
1180 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1181 const char *part)
1182 {
1183 MemoryRegion *mr = MEMORY_REGION(obj);
1184
1185 return OBJECT(mr->container);
1186 }
1187
1188 static void memory_region_get_priority(Object *obj, Visitor *v,
1189 const char *name, void *opaque,
1190 Error **errp)
1191 {
1192 MemoryRegion *mr = MEMORY_REGION(obj);
1193 int32_t value = mr->priority;
1194
1195 visit_type_int32(v, name, &value, errp);
1196 }
1197
1198 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1199 void *opaque, Error **errp)
1200 {
1201 MemoryRegion *mr = MEMORY_REGION(obj);
1202 uint64_t value = memory_region_size(mr);
1203
1204 visit_type_uint64(v, name, &value, errp);
1205 }
1206
1207 static void memory_region_initfn(Object *obj)
1208 {
1209 MemoryRegion *mr = MEMORY_REGION(obj);
1210 ObjectProperty *op;
1211
1212 mr->ops = &unassigned_mem_ops;
1213 mr->enabled = true;
1214 mr->romd_mode = true;
1215 mr->global_locking = true;
1216 mr->destructor = memory_region_destructor_none;
1217 QTAILQ_INIT(&mr->subregions);
1218 QTAILQ_INIT(&mr->coalesced);
1219
1220 op = object_property_add(OBJECT(mr), "container",
1221 "link<" TYPE_MEMORY_REGION ">",
1222 memory_region_get_container,
1223 NULL, /* memory_region_set_container */
1224 NULL, NULL, &error_abort);
1225 op->resolve = memory_region_resolve_container;
1226
1227 object_property_add(OBJECT(mr), "addr", "uint64",
1228 memory_region_get_addr,
1229 NULL, /* memory_region_set_addr */
1230 NULL, NULL, &error_abort);
1231 object_property_add(OBJECT(mr), "priority", "uint32",
1232 memory_region_get_priority,
1233 NULL, /* memory_region_set_priority */
1234 NULL, NULL, &error_abort);
1235 object_property_add(OBJECT(mr), "size", "uint64",
1236 memory_region_get_size,
1237 NULL, /* memory_region_set_size, */
1238 NULL, NULL, &error_abort);
1239 }
1240
1241 static void iommu_memory_region_initfn(Object *obj)
1242 {
1243 MemoryRegion *mr = MEMORY_REGION(obj);
1244
1245 mr->is_iommu = true;
1246 }
1247
1248 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1249 unsigned size)
1250 {
1251 #ifdef DEBUG_UNASSIGNED
1252 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1253 #endif
1254 if (current_cpu != NULL) {
1255 cpu_unassigned_access(current_cpu, addr, false, false, 0, size);
1256 }
1257 return 0;
1258 }
1259
1260 static void unassigned_mem_write(void *opaque, hwaddr addr,
1261 uint64_t val, unsigned size)
1262 {
1263 #ifdef DEBUG_UNASSIGNED
1264 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1265 #endif
1266 if (current_cpu != NULL) {
1267 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1268 }
1269 }
1270
1271 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1272 unsigned size, bool is_write,
1273 MemTxAttrs attrs)
1274 {
1275 return false;
1276 }
1277
1278 const MemoryRegionOps unassigned_mem_ops = {
1279 .valid.accepts = unassigned_mem_accepts,
1280 .endianness = DEVICE_NATIVE_ENDIAN,
1281 };
1282
1283 static uint64_t memory_region_ram_device_read(void *opaque,
1284 hwaddr addr, unsigned size)
1285 {
1286 MemoryRegion *mr = opaque;
1287 uint64_t data = (uint64_t)~0;
1288
1289 switch (size) {
1290 case 1:
1291 data = *(uint8_t *)(mr->ram_block->host + addr);
1292 break;
1293 case 2:
1294 data = *(uint16_t *)(mr->ram_block->host + addr);
1295 break;
1296 case 4:
1297 data = *(uint32_t *)(mr->ram_block->host + addr);
1298 break;
1299 case 8:
1300 data = *(uint64_t *)(mr->ram_block->host + addr);
1301 break;
1302 }
1303
1304 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1305
1306 return data;
1307 }
1308
1309 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1310 uint64_t data, unsigned size)
1311 {
1312 MemoryRegion *mr = opaque;
1313
1314 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1315
1316 switch (size) {
1317 case 1:
1318 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1319 break;
1320 case 2:
1321 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1322 break;
1323 case 4:
1324 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1325 break;
1326 case 8:
1327 *(uint64_t *)(mr->ram_block->host + addr) = data;
1328 break;
1329 }
1330 }
1331
1332 static const MemoryRegionOps ram_device_mem_ops = {
1333 .read = memory_region_ram_device_read,
1334 .write = memory_region_ram_device_write,
1335 .endianness = DEVICE_HOST_ENDIAN,
1336 .valid = {
1337 .min_access_size = 1,
1338 .max_access_size = 8,
1339 .unaligned = true,
1340 },
1341 .impl = {
1342 .min_access_size = 1,
1343 .max_access_size = 8,
1344 .unaligned = true,
1345 },
1346 };
1347
1348 bool memory_region_access_valid(MemoryRegion *mr,
1349 hwaddr addr,
1350 unsigned size,
1351 bool is_write,
1352 MemTxAttrs attrs)
1353 {
1354 int access_size_min, access_size_max;
1355 int access_size, i;
1356
1357 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1358 return false;
1359 }
1360
1361 if (!mr->ops->valid.accepts) {
1362 return true;
1363 }
1364
1365 access_size_min = mr->ops->valid.min_access_size;
1366 if (!mr->ops->valid.min_access_size) {
1367 access_size_min = 1;
1368 }
1369
1370 access_size_max = mr->ops->valid.max_access_size;
1371 if (!mr->ops->valid.max_access_size) {
1372 access_size_max = 4;
1373 }
1374
1375 access_size = MAX(MIN(size, access_size_max), access_size_min);
1376 for (i = 0; i < size; i += access_size) {
1377 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1378 is_write, attrs)) {
1379 return false;
1380 }
1381 }
1382
1383 return true;
1384 }
1385
1386 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1387 hwaddr addr,
1388 uint64_t *pval,
1389 unsigned size,
1390 MemTxAttrs attrs)
1391 {
1392 *pval = 0;
1393
1394 if (mr->ops->read) {
1395 return access_with_adjusted_size(addr, pval, size,
1396 mr->ops->impl.min_access_size,
1397 mr->ops->impl.max_access_size,
1398 memory_region_read_accessor,
1399 mr, attrs);
1400 } else if (mr->ops->read_with_attrs) {
1401 return access_with_adjusted_size(addr, pval, size,
1402 mr->ops->impl.min_access_size,
1403 mr->ops->impl.max_access_size,
1404 memory_region_read_with_attrs_accessor,
1405 mr, attrs);
1406 } else {
1407 return access_with_adjusted_size(addr, pval, size, 1, 4,
1408 memory_region_oldmmio_read_accessor,
1409 mr, attrs);
1410 }
1411 }
1412
1413 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1414 hwaddr addr,
1415 uint64_t *pval,
1416 unsigned size,
1417 MemTxAttrs attrs)
1418 {
1419 MemTxResult r;
1420
1421 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1422 *pval = unassigned_mem_read(mr, addr, size);
1423 return MEMTX_DECODE_ERROR;
1424 }
1425
1426 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1427 adjust_endianness(mr, pval, size);
1428 return r;
1429 }
1430
1431 /* Return true if an eventfd was signalled */
1432 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1433 hwaddr addr,
1434 uint64_t data,
1435 unsigned size,
1436 MemTxAttrs attrs)
1437 {
1438 MemoryRegionIoeventfd ioeventfd = {
1439 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1440 .data = data,
1441 };
1442 unsigned i;
1443
1444 for (i = 0; i < mr->ioeventfd_nb; i++) {
1445 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1446 ioeventfd.e = mr->ioeventfds[i].e;
1447
1448 if (memory_region_ioeventfd_equal(ioeventfd, mr->ioeventfds[i])) {
1449 event_notifier_set(ioeventfd.e);
1450 return true;
1451 }
1452 }
1453
1454 return false;
1455 }
1456
1457 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1458 hwaddr addr,
1459 uint64_t data,
1460 unsigned size,
1461 MemTxAttrs attrs)
1462 {
1463 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1464 unassigned_mem_write(mr, addr, data, size);
1465 return MEMTX_DECODE_ERROR;
1466 }
1467
1468 adjust_endianness(mr, &data, size);
1469
1470 if ((!kvm_eventfds_enabled()) &&
1471 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1472 return MEMTX_OK;
1473 }
1474
1475 if (mr->ops->write) {
1476 return access_with_adjusted_size(addr, &data, size,
1477 mr->ops->impl.min_access_size,
1478 mr->ops->impl.max_access_size,
1479 memory_region_write_accessor, mr,
1480 attrs);
1481 } else if (mr->ops->write_with_attrs) {
1482 return
1483 access_with_adjusted_size(addr, &data, size,
1484 mr->ops->impl.min_access_size,
1485 mr->ops->impl.max_access_size,
1486 memory_region_write_with_attrs_accessor,
1487 mr, attrs);
1488 } else {
1489 return access_with_adjusted_size(addr, &data, size, 1, 4,
1490 memory_region_oldmmio_write_accessor,
1491 mr, attrs);
1492 }
1493 }
1494
1495 void memory_region_init_io(MemoryRegion *mr,
1496 Object *owner,
1497 const MemoryRegionOps *ops,
1498 void *opaque,
1499 const char *name,
1500 uint64_t size)
1501 {
1502 memory_region_init(mr, owner, name, size);
1503 mr->ops = ops ? ops : &unassigned_mem_ops;
1504 mr->opaque = opaque;
1505 mr->terminates = true;
1506 }
1507
1508 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1509 Object *owner,
1510 const char *name,
1511 uint64_t size,
1512 Error **errp)
1513 {
1514 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1515 }
1516
1517 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1518 Object *owner,
1519 const char *name,
1520 uint64_t size,
1521 bool share,
1522 Error **errp)
1523 {
1524 memory_region_init(mr, owner, name, size);
1525 mr->ram = true;
1526 mr->terminates = true;
1527 mr->destructor = memory_region_destructor_ram;
1528 mr->ram_block = qemu_ram_alloc(size, share, mr, errp);
1529 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1530 }
1531
1532 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1533 Object *owner,
1534 const char *name,
1535 uint64_t size,
1536 uint64_t max_size,
1537 void (*resized)(const char*,
1538 uint64_t length,
1539 void *host),
1540 Error **errp)
1541 {
1542 memory_region_init(mr, owner, name, size);
1543 mr->ram = true;
1544 mr->terminates = true;
1545 mr->destructor = memory_region_destructor_ram;
1546 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1547 mr, errp);
1548 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1549 }
1550
1551 #ifdef __linux__
1552 void memory_region_init_ram_from_file(MemoryRegion *mr,
1553 struct Object *owner,
1554 const char *name,
1555 uint64_t size,
1556 uint64_t align,
1557 bool share,
1558 const char *path,
1559 Error **errp)
1560 {
1561 memory_region_init(mr, owner, name, size);
1562 mr->ram = true;
1563 mr->terminates = true;
1564 mr->destructor = memory_region_destructor_ram;
1565 mr->align = align;
1566 mr->ram_block = qemu_ram_alloc_from_file(size, mr, share, path, errp);
1567 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1568 }
1569
1570 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1571 struct Object *owner,
1572 const char *name,
1573 uint64_t size,
1574 bool share,
1575 int fd,
1576 Error **errp)
1577 {
1578 memory_region_init(mr, owner, name, size);
1579 mr->ram = true;
1580 mr->terminates = true;
1581 mr->destructor = memory_region_destructor_ram;
1582 mr->ram_block = qemu_ram_alloc_from_fd(size, mr, share, fd, errp);
1583 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1584 }
1585 #endif
1586
1587 void memory_region_init_ram_ptr(MemoryRegion *mr,
1588 Object *owner,
1589 const char *name,
1590 uint64_t size,
1591 void *ptr)
1592 {
1593 memory_region_init(mr, owner, name, size);
1594 mr->ram = true;
1595 mr->terminates = true;
1596 mr->destructor = memory_region_destructor_ram;
1597 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1598
1599 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1600 assert(ptr != NULL);
1601 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1602 }
1603
1604 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1605 Object *owner,
1606 const char *name,
1607 uint64_t size,
1608 void *ptr)
1609 {
1610 memory_region_init_ram_ptr(mr, owner, name, size, ptr);
1611 mr->ram_device = true;
1612 mr->ops = &ram_device_mem_ops;
1613 mr->opaque = mr;
1614 }
1615
1616 void memory_region_init_alias(MemoryRegion *mr,
1617 Object *owner,
1618 const char *name,
1619 MemoryRegion *orig,
1620 hwaddr offset,
1621 uint64_t size)
1622 {
1623 memory_region_init(mr, owner, name, size);
1624 mr->alias = orig;
1625 mr->alias_offset = offset;
1626 }
1627
1628 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1629 struct Object *owner,
1630 const char *name,
1631 uint64_t size,
1632 Error **errp)
1633 {
1634 memory_region_init(mr, owner, name, size);
1635 mr->ram = true;
1636 mr->readonly = true;
1637 mr->terminates = true;
1638 mr->destructor = memory_region_destructor_ram;
1639 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
1640 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1641 }
1642
1643 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1644 Object *owner,
1645 const MemoryRegionOps *ops,
1646 void *opaque,
1647 const char *name,
1648 uint64_t size,
1649 Error **errp)
1650 {
1651 assert(ops);
1652 memory_region_init(mr, owner, name, size);
1653 mr->ops = ops;
1654 mr->opaque = opaque;
1655 mr->terminates = true;
1656 mr->rom_device = true;
1657 mr->destructor = memory_region_destructor_ram;
1658 mr->ram_block = qemu_ram_alloc(size, false, mr, errp);
1659 }
1660
1661 void memory_region_init_iommu(void *_iommu_mr,
1662 size_t instance_size,
1663 const char *mrtypename,
1664 Object *owner,
1665 const char *name,
1666 uint64_t size)
1667 {
1668 struct IOMMUMemoryRegion *iommu_mr;
1669 struct MemoryRegion *mr;
1670
1671 object_initialize(_iommu_mr, instance_size, mrtypename);
1672 mr = MEMORY_REGION(_iommu_mr);
1673 memory_region_do_init(mr, owner, name, size);
1674 iommu_mr = IOMMU_MEMORY_REGION(mr);
1675 mr->terminates = true; /* then re-forwards */
1676 QLIST_INIT(&iommu_mr->iommu_notify);
1677 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1678 }
1679
1680 static void memory_region_finalize(Object *obj)
1681 {
1682 MemoryRegion *mr = MEMORY_REGION(obj);
1683
1684 assert(!mr->container);
1685
1686 /* We know the region is not visible in any address space (it
1687 * does not have a container and cannot be a root either because
1688 * it has no references, so we can blindly clear mr->enabled.
1689 * memory_region_set_enabled instead could trigger a transaction
1690 * and cause an infinite loop.
1691 */
1692 mr->enabled = false;
1693 memory_region_transaction_begin();
1694 while (!QTAILQ_EMPTY(&mr->subregions)) {
1695 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1696 memory_region_del_subregion(mr, subregion);
1697 }
1698 memory_region_transaction_commit();
1699
1700 mr->destructor(mr);
1701 memory_region_clear_coalescing(mr);
1702 g_free((char *)mr->name);
1703 g_free(mr->ioeventfds);
1704 }
1705
1706 Object *memory_region_owner(MemoryRegion *mr)
1707 {
1708 Object *obj = OBJECT(mr);
1709 return obj->parent;
1710 }
1711
1712 void memory_region_ref(MemoryRegion *mr)
1713 {
1714 /* MMIO callbacks most likely will access data that belongs
1715 * to the owner, hence the need to ref/unref the owner whenever
1716 * the memory region is in use.
1717 *
1718 * The memory region is a child of its owner. As long as the
1719 * owner doesn't call unparent itself on the memory region,
1720 * ref-ing the owner will also keep the memory region alive.
1721 * Memory regions without an owner are supposed to never go away;
1722 * we do not ref/unref them because it slows down DMA sensibly.
1723 */
1724 if (mr && mr->owner) {
1725 object_ref(mr->owner);
1726 }
1727 }
1728
1729 void memory_region_unref(MemoryRegion *mr)
1730 {
1731 if (mr && mr->owner) {
1732 object_unref(mr->owner);
1733 }
1734 }
1735
1736 uint64_t memory_region_size(MemoryRegion *mr)
1737 {
1738 if (int128_eq(mr->size, int128_2_64())) {
1739 return UINT64_MAX;
1740 }
1741 return int128_get64(mr->size);
1742 }
1743
1744 const char *memory_region_name(const MemoryRegion *mr)
1745 {
1746 if (!mr->name) {
1747 ((MemoryRegion *)mr)->name =
1748 object_get_canonical_path_component(OBJECT(mr));
1749 }
1750 return mr->name;
1751 }
1752
1753 bool memory_region_is_ram_device(MemoryRegion *mr)
1754 {
1755 return mr->ram_device;
1756 }
1757
1758 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1759 {
1760 uint8_t mask = mr->dirty_log_mask;
1761 if (global_dirty_log && mr->ram_block) {
1762 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1763 }
1764 return mask;
1765 }
1766
1767 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1768 {
1769 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1770 }
1771
1772 static void memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr)
1773 {
1774 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1775 IOMMUNotifier *iommu_notifier;
1776 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1777
1778 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1779 flags |= iommu_notifier->notifier_flags;
1780 }
1781
1782 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1783 imrc->notify_flag_changed(iommu_mr,
1784 iommu_mr->iommu_notify_flags,
1785 flags);
1786 }
1787
1788 iommu_mr->iommu_notify_flags = flags;
1789 }
1790
1791 void memory_region_register_iommu_notifier(MemoryRegion *mr,
1792 IOMMUNotifier *n)
1793 {
1794 IOMMUMemoryRegion *iommu_mr;
1795
1796 if (mr->alias) {
1797 memory_region_register_iommu_notifier(mr->alias, n);
1798 return;
1799 }
1800
1801 /* We need to register for at least one bitfield */
1802 iommu_mr = IOMMU_MEMORY_REGION(mr);
1803 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1804 assert(n->start <= n->end);
1805 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1806 memory_region_update_iommu_notify_flags(iommu_mr);
1807 }
1808
1809 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1810 {
1811 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1812
1813 if (imrc->get_min_page_size) {
1814 return imrc->get_min_page_size(iommu_mr);
1815 }
1816 return TARGET_PAGE_SIZE;
1817 }
1818
1819 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1820 {
1821 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1822 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1823 hwaddr addr, granularity;
1824 IOMMUTLBEntry iotlb;
1825
1826 /* If the IOMMU has its own replay callback, override */
1827 if (imrc->replay) {
1828 imrc->replay(iommu_mr, n);
1829 return;
1830 }
1831
1832 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1833
1834 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1835 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE);
1836 if (iotlb.perm != IOMMU_NONE) {
1837 n->notify(n, &iotlb);
1838 }
1839
1840 /* if (2^64 - MR size) < granularity, it's possible to get an
1841 * infinite loop here. This should catch such a wraparound */
1842 if ((addr + granularity) < addr) {
1843 break;
1844 }
1845 }
1846 }
1847
1848 void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr)
1849 {
1850 IOMMUNotifier *notifier;
1851
1852 IOMMU_NOTIFIER_FOREACH(notifier, iommu_mr) {
1853 memory_region_iommu_replay(iommu_mr, notifier);
1854 }
1855 }
1856
1857 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1858 IOMMUNotifier *n)
1859 {
1860 IOMMUMemoryRegion *iommu_mr;
1861
1862 if (mr->alias) {
1863 memory_region_unregister_iommu_notifier(mr->alias, n);
1864 return;
1865 }
1866 QLIST_REMOVE(n, node);
1867 iommu_mr = IOMMU_MEMORY_REGION(mr);
1868 memory_region_update_iommu_notify_flags(iommu_mr);
1869 }
1870
1871 void memory_region_notify_one(IOMMUNotifier *notifier,
1872 IOMMUTLBEntry *entry)
1873 {
1874 IOMMUNotifierFlag request_flags;
1875
1876 /*
1877 * Skip the notification if the notification does not overlap
1878 * with registered range.
1879 */
1880 if (notifier->start > entry->iova + entry->addr_mask ||
1881 notifier->end < entry->iova) {
1882 return;
1883 }
1884
1885 if (entry->perm & IOMMU_RW) {
1886 request_flags = IOMMU_NOTIFIER_MAP;
1887 } else {
1888 request_flags = IOMMU_NOTIFIER_UNMAP;
1889 }
1890
1891 if (notifier->notifier_flags & request_flags) {
1892 notifier->notify(notifier, entry);
1893 }
1894 }
1895
1896 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1897 IOMMUTLBEntry entry)
1898 {
1899 IOMMUNotifier *iommu_notifier;
1900
1901 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1902
1903 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1904 memory_region_notify_one(iommu_notifier, &entry);
1905 }
1906 }
1907
1908 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1909 enum IOMMUMemoryRegionAttr attr,
1910 void *data)
1911 {
1912 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1913
1914 if (!imrc->get_attr) {
1915 return -EINVAL;
1916 }
1917
1918 return imrc->get_attr(iommu_mr, attr, data);
1919 }
1920
1921 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
1922 {
1923 uint8_t mask = 1 << client;
1924 uint8_t old_logging;
1925
1926 assert(client == DIRTY_MEMORY_VGA);
1927 old_logging = mr->vga_logging_count;
1928 mr->vga_logging_count += log ? 1 : -1;
1929 if (!!old_logging == !!mr->vga_logging_count) {
1930 return;
1931 }
1932
1933 memory_region_transaction_begin();
1934 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
1935 memory_region_update_pending |= mr->enabled;
1936 memory_region_transaction_commit();
1937 }
1938
1939 bool memory_region_get_dirty(MemoryRegion *mr, hwaddr addr,
1940 hwaddr size, unsigned client)
1941 {
1942 assert(mr->ram_block);
1943 return cpu_physical_memory_get_dirty(memory_region_get_ram_addr(mr) + addr,
1944 size, client);
1945 }
1946
1947 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
1948 hwaddr size)
1949 {
1950 assert(mr->ram_block);
1951 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
1952 size,
1953 memory_region_get_dirty_log_mask(mr));
1954 }
1955
1956 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
1957 {
1958 MemoryListener *listener;
1959 AddressSpace *as;
1960 FlatView *view;
1961 FlatRange *fr;
1962
1963 /* If the same address space has multiple log_sync listeners, we
1964 * visit that address space's FlatView multiple times. But because
1965 * log_sync listeners are rare, it's still cheaper than walking each
1966 * address space once.
1967 */
1968 QTAILQ_FOREACH(listener, &memory_listeners, link) {
1969 if (!listener->log_sync) {
1970 continue;
1971 }
1972 as = listener->address_space;
1973 view = address_space_get_flatview(as);
1974 FOR_EACH_FLAT_RANGE(fr, view) {
1975 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
1976 MemoryRegionSection mrs = section_from_flat_range(fr, view);
1977 listener->log_sync(listener, &mrs);
1978 }
1979 }
1980 flatview_unref(view);
1981 }
1982 }
1983
1984 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
1985 hwaddr addr,
1986 hwaddr size,
1987 unsigned client)
1988 {
1989 assert(mr->ram_block);
1990 memory_region_sync_dirty_bitmap(mr);
1991 return cpu_physical_memory_snapshot_and_clear_dirty(
1992 memory_region_get_ram_addr(mr) + addr, size, client);
1993 }
1994
1995 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
1996 hwaddr addr, hwaddr size)
1997 {
1998 assert(mr->ram_block);
1999 return cpu_physical_memory_snapshot_get_dirty(snap,
2000 memory_region_get_ram_addr(mr) + addr, size);
2001 }
2002
2003 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2004 {
2005 if (mr->readonly != readonly) {
2006 memory_region_transaction_begin();
2007 mr->readonly = readonly;
2008 memory_region_update_pending |= mr->enabled;
2009 memory_region_transaction_commit();
2010 }
2011 }
2012
2013 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2014 {
2015 if (mr->romd_mode != romd_mode) {
2016 memory_region_transaction_begin();
2017 mr->romd_mode = romd_mode;
2018 memory_region_update_pending |= mr->enabled;
2019 memory_region_transaction_commit();
2020 }
2021 }
2022
2023 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2024 hwaddr size, unsigned client)
2025 {
2026 assert(mr->ram_block);
2027 cpu_physical_memory_test_and_clear_dirty(
2028 memory_region_get_ram_addr(mr) + addr, size, client);
2029 }
2030
2031 int memory_region_get_fd(MemoryRegion *mr)
2032 {
2033 int fd;
2034
2035 rcu_read_lock();
2036 while (mr->alias) {
2037 mr = mr->alias;
2038 }
2039 fd = mr->ram_block->fd;
2040 rcu_read_unlock();
2041
2042 return fd;
2043 }
2044
2045 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2046 {
2047 void *ptr;
2048 uint64_t offset = 0;
2049
2050 rcu_read_lock();
2051 while (mr->alias) {
2052 offset += mr->alias_offset;
2053 mr = mr->alias;
2054 }
2055 assert(mr->ram_block);
2056 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2057 rcu_read_unlock();
2058
2059 return ptr;
2060 }
2061
2062 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2063 {
2064 RAMBlock *block;
2065
2066 block = qemu_ram_block_from_host(ptr, false, offset);
2067 if (!block) {
2068 return NULL;
2069 }
2070
2071 return block->mr;
2072 }
2073
2074 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2075 {
2076 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2077 }
2078
2079 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2080 {
2081 assert(mr->ram_block);
2082
2083 qemu_ram_resize(mr->ram_block, newsize, errp);
2084 }
2085
2086 static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpace *as)
2087 {
2088 FlatView *view;
2089 FlatRange *fr;
2090 CoalescedMemoryRange *cmr;
2091 AddrRange tmp;
2092 MemoryRegionSection section;
2093
2094 view = address_space_get_flatview(as);
2095 FOR_EACH_FLAT_RANGE(fr, view) {
2096 if (fr->mr == mr) {
2097 section = (MemoryRegionSection) {
2098 .fv = view,
2099 .offset_within_address_space = int128_get64(fr->addr.start),
2100 .size = fr->addr.size,
2101 };
2102
2103 MEMORY_LISTENER_CALL(as, coalesced_mmio_del, Reverse, &section,
2104 int128_get64(fr->addr.start),
2105 int128_get64(fr->addr.size));
2106 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
2107 tmp = addrrange_shift(cmr->addr,
2108 int128_sub(fr->addr.start,
2109 int128_make64(fr->offset_in_region)));
2110 if (!addrrange_intersects(tmp, fr->addr)) {
2111 continue;
2112 }
2113 tmp = addrrange_intersection(tmp, fr->addr);
2114 MEMORY_LISTENER_CALL(as, coalesced_mmio_add, Forward, &section,
2115 int128_get64(tmp.start),
2116 int128_get64(tmp.size));
2117 }
2118 }
2119 }
2120 flatview_unref(view);
2121 }
2122
2123 static void memory_region_update_coalesced_range(MemoryRegion *mr)
2124 {
2125 AddressSpace *as;
2126
2127 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2128 memory_region_update_coalesced_range_as(mr, as);
2129 }
2130 }
2131
2132 void memory_region_set_coalescing(MemoryRegion *mr)
2133 {
2134 memory_region_clear_coalescing(mr);
2135 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2136 }
2137
2138 void memory_region_add_coalescing(MemoryRegion *mr,
2139 hwaddr offset,
2140 uint64_t size)
2141 {
2142 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2143
2144 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2145 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2146 memory_region_update_coalesced_range(mr);
2147 memory_region_set_flush_coalesced(mr);
2148 }
2149
2150 void memory_region_clear_coalescing(MemoryRegion *mr)
2151 {
2152 CoalescedMemoryRange *cmr;
2153 bool updated = false;
2154
2155 qemu_flush_coalesced_mmio_buffer();
2156 mr->flush_coalesced_mmio = false;
2157
2158 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2159 cmr = QTAILQ_FIRST(&mr->coalesced);
2160 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2161 g_free(cmr);
2162 updated = true;
2163 }
2164
2165 if (updated) {
2166 memory_region_update_coalesced_range(mr);
2167 }
2168 }
2169
2170 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2171 {
2172 mr->flush_coalesced_mmio = true;
2173 }
2174
2175 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2176 {
2177 qemu_flush_coalesced_mmio_buffer();
2178 if (QTAILQ_EMPTY(&mr->coalesced)) {
2179 mr->flush_coalesced_mmio = false;
2180 }
2181 }
2182
2183 void memory_region_clear_global_locking(MemoryRegion *mr)
2184 {
2185 mr->global_locking = false;
2186 }
2187
2188 static bool userspace_eventfd_warning;
2189
2190 void memory_region_add_eventfd(MemoryRegion *mr,
2191 hwaddr addr,
2192 unsigned size,
2193 bool match_data,
2194 uint64_t data,
2195 EventNotifier *e)
2196 {
2197 MemoryRegionIoeventfd mrfd = {
2198 .addr.start = int128_make64(addr),
2199 .addr.size = int128_make64(size),
2200 .match_data = match_data,
2201 .data = data,
2202 .e = e,
2203 };
2204 unsigned i;
2205
2206 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2207 userspace_eventfd_warning))) {
2208 userspace_eventfd_warning = true;
2209 error_report("Using eventfd without MMIO binding in KVM. "
2210 "Suboptimal performance expected");
2211 }
2212
2213 if (size) {
2214 adjust_endianness(mr, &mrfd.data, size);
2215 }
2216 memory_region_transaction_begin();
2217 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2218 if (memory_region_ioeventfd_before(mrfd, mr->ioeventfds[i])) {
2219 break;
2220 }
2221 }
2222 ++mr->ioeventfd_nb;
2223 mr->ioeventfds = g_realloc(mr->ioeventfds,
2224 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2225 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2226 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2227 mr->ioeventfds[i] = mrfd;
2228 ioeventfd_update_pending |= mr->enabled;
2229 memory_region_transaction_commit();
2230 }
2231
2232 void memory_region_del_eventfd(MemoryRegion *mr,
2233 hwaddr addr,
2234 unsigned size,
2235 bool match_data,
2236 uint64_t data,
2237 EventNotifier *e)
2238 {
2239 MemoryRegionIoeventfd mrfd = {
2240 .addr.start = int128_make64(addr),
2241 .addr.size = int128_make64(size),
2242 .match_data = match_data,
2243 .data = data,
2244 .e = e,
2245 };
2246 unsigned i;
2247
2248 if (size) {
2249 adjust_endianness(mr, &mrfd.data, size);
2250 }
2251 memory_region_transaction_begin();
2252 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2253 if (memory_region_ioeventfd_equal(mrfd, mr->ioeventfds[i])) {
2254 break;
2255 }
2256 }
2257 assert(i != mr->ioeventfd_nb);
2258 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2259 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2260 --mr->ioeventfd_nb;
2261 mr->ioeventfds = g_realloc(mr->ioeventfds,
2262 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2263 ioeventfd_update_pending |= mr->enabled;
2264 memory_region_transaction_commit();
2265 }
2266
2267 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2268 {
2269 MemoryRegion *mr = subregion->container;
2270 MemoryRegion *other;
2271
2272 memory_region_transaction_begin();
2273
2274 memory_region_ref(subregion);
2275 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2276 if (subregion->priority >= other->priority) {
2277 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2278 goto done;
2279 }
2280 }
2281 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2282 done:
2283 memory_region_update_pending |= mr->enabled && subregion->enabled;
2284 memory_region_transaction_commit();
2285 }
2286
2287 static void memory_region_add_subregion_common(MemoryRegion *mr,
2288 hwaddr offset,
2289 MemoryRegion *subregion)
2290 {
2291 assert(!subregion->container);
2292 subregion->container = mr;
2293 subregion->addr = offset;
2294 memory_region_update_container_subregions(subregion);
2295 }
2296
2297 void memory_region_add_subregion(MemoryRegion *mr,
2298 hwaddr offset,
2299 MemoryRegion *subregion)
2300 {
2301 subregion->priority = 0;
2302 memory_region_add_subregion_common(mr, offset, subregion);
2303 }
2304
2305 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2306 hwaddr offset,
2307 MemoryRegion *subregion,
2308 int priority)
2309 {
2310 subregion->priority = priority;
2311 memory_region_add_subregion_common(mr, offset, subregion);
2312 }
2313
2314 void memory_region_del_subregion(MemoryRegion *mr,
2315 MemoryRegion *subregion)
2316 {
2317 memory_region_transaction_begin();
2318 assert(subregion->container == mr);
2319 subregion->container = NULL;
2320 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2321 memory_region_unref(subregion);
2322 memory_region_update_pending |= mr->enabled && subregion->enabled;
2323 memory_region_transaction_commit();
2324 }
2325
2326 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2327 {
2328 if (enabled == mr->enabled) {
2329 return;
2330 }
2331 memory_region_transaction_begin();
2332 mr->enabled = enabled;
2333 memory_region_update_pending = true;
2334 memory_region_transaction_commit();
2335 }
2336
2337 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2338 {
2339 Int128 s = int128_make64(size);
2340
2341 if (size == UINT64_MAX) {
2342 s = int128_2_64();
2343 }
2344 if (int128_eq(s, mr->size)) {
2345 return;
2346 }
2347 memory_region_transaction_begin();
2348 mr->size = s;
2349 memory_region_update_pending = true;
2350 memory_region_transaction_commit();
2351 }
2352
2353 static void memory_region_readd_subregion(MemoryRegion *mr)
2354 {
2355 MemoryRegion *container = mr->container;
2356
2357 if (container) {
2358 memory_region_transaction_begin();
2359 memory_region_ref(mr);
2360 memory_region_del_subregion(container, mr);
2361 mr->container = container;
2362 memory_region_update_container_subregions(mr);
2363 memory_region_unref(mr);
2364 memory_region_transaction_commit();
2365 }
2366 }
2367
2368 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2369 {
2370 if (addr != mr->addr) {
2371 mr->addr = addr;
2372 memory_region_readd_subregion(mr);
2373 }
2374 }
2375
2376 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2377 {
2378 assert(mr->alias);
2379
2380 if (offset == mr->alias_offset) {
2381 return;
2382 }
2383
2384 memory_region_transaction_begin();
2385 mr->alias_offset = offset;
2386 memory_region_update_pending |= mr->enabled;
2387 memory_region_transaction_commit();
2388 }
2389
2390 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2391 {
2392 return mr->align;
2393 }
2394
2395 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2396 {
2397 const AddrRange *addr = addr_;
2398 const FlatRange *fr = fr_;
2399
2400 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2401 return -1;
2402 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2403 return 1;
2404 }
2405 return 0;
2406 }
2407
2408 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2409 {
2410 return bsearch(&addr, view->ranges, view->nr,
2411 sizeof(FlatRange), cmp_flatrange_addr);
2412 }
2413
2414 bool memory_region_is_mapped(MemoryRegion *mr)
2415 {
2416 return mr->container ? true : false;
2417 }
2418
2419 /* Same as memory_region_find, but it does not add a reference to the
2420 * returned region. It must be called from an RCU critical section.
2421 */
2422 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2423 hwaddr addr, uint64_t size)
2424 {
2425 MemoryRegionSection ret = { .mr = NULL };
2426 MemoryRegion *root;
2427 AddressSpace *as;
2428 AddrRange range;
2429 FlatView *view;
2430 FlatRange *fr;
2431
2432 addr += mr->addr;
2433 for (root = mr; root->container; ) {
2434 root = root->container;
2435 addr += root->addr;
2436 }
2437
2438 as = memory_region_to_address_space(root);
2439 if (!as) {
2440 return ret;
2441 }
2442 range = addrrange_make(int128_make64(addr), int128_make64(size));
2443
2444 view = address_space_to_flatview(as);
2445 fr = flatview_lookup(view, range);
2446 if (!fr) {
2447 return ret;
2448 }
2449
2450 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2451 --fr;
2452 }
2453
2454 ret.mr = fr->mr;
2455 ret.fv = view;
2456 range = addrrange_intersection(range, fr->addr);
2457 ret.offset_within_region = fr->offset_in_region;
2458 ret.offset_within_region += int128_get64(int128_sub(range.start,
2459 fr->addr.start));
2460 ret.size = range.size;
2461 ret.offset_within_address_space = int128_get64(range.start);
2462 ret.readonly = fr->readonly;
2463 return ret;
2464 }
2465
2466 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2467 hwaddr addr, uint64_t size)
2468 {
2469 MemoryRegionSection ret;
2470 rcu_read_lock();
2471 ret = memory_region_find_rcu(mr, addr, size);
2472 if (ret.mr) {
2473 memory_region_ref(ret.mr);
2474 }
2475 rcu_read_unlock();
2476 return ret;
2477 }
2478
2479 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2480 {
2481 MemoryRegion *mr;
2482
2483 rcu_read_lock();
2484 mr = memory_region_find_rcu(container, addr, 1).mr;
2485 rcu_read_unlock();
2486 return mr && mr != container;
2487 }
2488
2489 void memory_global_dirty_log_sync(void)
2490 {
2491 memory_region_sync_dirty_bitmap(NULL);
2492 }
2493
2494 static VMChangeStateEntry *vmstate_change;
2495
2496 void memory_global_dirty_log_start(void)
2497 {
2498 if (vmstate_change) {
2499 qemu_del_vm_change_state_handler(vmstate_change);
2500 vmstate_change = NULL;
2501 }
2502
2503 global_dirty_log = true;
2504
2505 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2506
2507 /* Refresh DIRTY_LOG_MIGRATION bit. */
2508 memory_region_transaction_begin();
2509 memory_region_update_pending = true;
2510 memory_region_transaction_commit();
2511 }
2512
2513 static void memory_global_dirty_log_do_stop(void)
2514 {
2515 global_dirty_log = false;
2516
2517 /* Refresh DIRTY_LOG_MIGRATION bit. */
2518 memory_region_transaction_begin();
2519 memory_region_update_pending = true;
2520 memory_region_transaction_commit();
2521
2522 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2523 }
2524
2525 static void memory_vm_change_state_handler(void *opaque, int running,
2526 RunState state)
2527 {
2528 if (running) {
2529 memory_global_dirty_log_do_stop();
2530
2531 if (vmstate_change) {
2532 qemu_del_vm_change_state_handler(vmstate_change);
2533 vmstate_change = NULL;
2534 }
2535 }
2536 }
2537
2538 void memory_global_dirty_log_stop(void)
2539 {
2540 if (!runstate_is_running()) {
2541 if (vmstate_change) {
2542 return;
2543 }
2544 vmstate_change = qemu_add_vm_change_state_handler(
2545 memory_vm_change_state_handler, NULL);
2546 return;
2547 }
2548
2549 memory_global_dirty_log_do_stop();
2550 }
2551
2552 static void listener_add_address_space(MemoryListener *listener,
2553 AddressSpace *as)
2554 {
2555 FlatView *view;
2556 FlatRange *fr;
2557
2558 if (listener->begin) {
2559 listener->begin(listener);
2560 }
2561 if (global_dirty_log) {
2562 if (listener->log_global_start) {
2563 listener->log_global_start(listener);
2564 }
2565 }
2566
2567 view = address_space_get_flatview(as);
2568 FOR_EACH_FLAT_RANGE(fr, view) {
2569 MemoryRegionSection section = section_from_flat_range(fr, view);
2570
2571 if (listener->region_add) {
2572 listener->region_add(listener, &section);
2573 }
2574 if (fr->dirty_log_mask && listener->log_start) {
2575 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2576 }
2577 }
2578 if (listener->commit) {
2579 listener->commit(listener);
2580 }
2581 flatview_unref(view);
2582 }
2583
2584 static void listener_del_address_space(MemoryListener *listener,
2585 AddressSpace *as)
2586 {
2587 FlatView *view;
2588 FlatRange *fr;
2589
2590 if (listener->begin) {
2591 listener->begin(listener);
2592 }
2593 view = address_space_get_flatview(as);
2594 FOR_EACH_FLAT_RANGE(fr, view) {
2595 MemoryRegionSection section = section_from_flat_range(fr, view);
2596
2597 if (fr->dirty_log_mask && listener->log_stop) {
2598 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2599 }
2600 if (listener->region_del) {
2601 listener->region_del(listener, &section);
2602 }
2603 }
2604 if (listener->commit) {
2605 listener->commit(listener);
2606 }
2607 flatview_unref(view);
2608 }
2609
2610 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2611 {
2612 MemoryListener *other = NULL;
2613
2614 listener->address_space = as;
2615 if (QTAILQ_EMPTY(&memory_listeners)
2616 || listener->priority >= QTAILQ_LAST(&memory_listeners,
2617 memory_listeners)->priority) {
2618 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2619 } else {
2620 QTAILQ_FOREACH(other, &memory_listeners, link) {
2621 if (listener->priority < other->priority) {
2622 break;
2623 }
2624 }
2625 QTAILQ_INSERT_BEFORE(other, listener, link);
2626 }
2627
2628 if (QTAILQ_EMPTY(&as->listeners)
2629 || listener->priority >= QTAILQ_LAST(&as->listeners,
2630 memory_listeners)->priority) {
2631 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2632 } else {
2633 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2634 if (listener->priority < other->priority) {
2635 break;
2636 }
2637 }
2638 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2639 }
2640
2641 listener_add_address_space(listener, as);
2642 }
2643
2644 void memory_listener_unregister(MemoryListener *listener)
2645 {
2646 if (!listener->address_space) {
2647 return;
2648 }
2649
2650 listener_del_address_space(listener, listener->address_space);
2651 QTAILQ_REMOVE(&memory_listeners, listener, link);
2652 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2653 listener->address_space = NULL;
2654 }
2655
2656 bool memory_region_request_mmio_ptr(MemoryRegion *mr, hwaddr addr)
2657 {
2658 void *host;
2659 unsigned size = 0;
2660 unsigned offset = 0;
2661 Object *new_interface;
2662
2663 if (!mr || !mr->ops->request_ptr) {
2664 return false;
2665 }
2666
2667 /*
2668 * Avoid an update if the request_ptr call
2669 * memory_region_invalidate_mmio_ptr which seems to be likely when we use
2670 * a cache.
2671 */
2672 memory_region_transaction_begin();
2673
2674 host = mr->ops->request_ptr(mr->opaque, addr - mr->addr, &size, &offset);
2675
2676 if (!host || !size) {
2677 memory_region_transaction_commit();
2678 return false;
2679 }
2680
2681 new_interface = object_new("mmio_interface");
2682 qdev_prop_set_uint64(DEVICE(new_interface), "start", offset);
2683 qdev_prop_set_uint64(DEVICE(new_interface), "end", offset + size - 1);
2684 qdev_prop_set_bit(DEVICE(new_interface), "ro", true);
2685 qdev_prop_set_ptr(DEVICE(new_interface), "host_ptr", host);
2686 qdev_prop_set_ptr(DEVICE(new_interface), "subregion", mr);
2687 object_property_set_bool(OBJECT(new_interface), true, "realized", NULL);
2688
2689 memory_region_transaction_commit();
2690 return true;
2691 }
2692
2693 typedef struct MMIOPtrInvalidate {
2694 MemoryRegion *mr;
2695 hwaddr offset;
2696 unsigned size;
2697 int busy;
2698 int allocated;
2699 } MMIOPtrInvalidate;
2700
2701 #define MAX_MMIO_INVALIDATE 10
2702 static MMIOPtrInvalidate mmio_ptr_invalidate_list[MAX_MMIO_INVALIDATE];
2703
2704 static void memory_region_do_invalidate_mmio_ptr(CPUState *cpu,
2705 run_on_cpu_data data)
2706 {
2707 MMIOPtrInvalidate *invalidate_data = (MMIOPtrInvalidate *)data.host_ptr;
2708 MemoryRegion *mr = invalidate_data->mr;
2709 hwaddr offset = invalidate_data->offset;
2710 unsigned size = invalidate_data->size;
2711 MemoryRegionSection section = memory_region_find(mr, offset, size);
2712
2713 qemu_mutex_lock_iothread();
2714
2715 /* Reset dirty so this doesn't happen later. */
2716 cpu_physical_memory_test_and_clear_dirty(offset, size, 1);
2717
2718 if (section.mr != mr) {
2719 /* memory_region_find add a ref on section.mr */
2720 memory_region_unref(section.mr);
2721 if (MMIO_INTERFACE(section.mr->owner)) {
2722 /* We found the interface just drop it. */
2723 object_property_set_bool(section.mr->owner, false, "realized",
2724 NULL);
2725 object_unref(section.mr->owner);
2726 object_unparent(section.mr->owner);
2727 }
2728 }
2729
2730 qemu_mutex_unlock_iothread();
2731
2732 if (invalidate_data->allocated) {
2733 g_free(invalidate_data);
2734 } else {
2735 invalidate_data->busy = 0;
2736 }
2737 }
2738
2739 void memory_region_invalidate_mmio_ptr(MemoryRegion *mr, hwaddr offset,
2740 unsigned size)
2741 {
2742 size_t i;
2743 MMIOPtrInvalidate *invalidate_data = NULL;
2744
2745 for (i = 0; i < MAX_MMIO_INVALIDATE; i++) {
2746 if (atomic_cmpxchg(&(mmio_ptr_invalidate_list[i].busy), 0, 1) == 0) {
2747 invalidate_data = &mmio_ptr_invalidate_list[i];
2748 break;
2749 }
2750 }
2751
2752 if (!invalidate_data) {
2753 invalidate_data = g_malloc0(sizeof(MMIOPtrInvalidate));
2754 invalidate_data->allocated = 1;
2755 }
2756
2757 invalidate_data->mr = mr;
2758 invalidate_data->offset = offset;
2759 invalidate_data->size = size;
2760
2761 async_safe_run_on_cpu(first_cpu, memory_region_do_invalidate_mmio_ptr,
2762 RUN_ON_CPU_HOST_PTR(invalidate_data));
2763 }
2764
2765 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2766 {
2767 memory_region_ref(root);
2768 as->root = root;
2769 as->current_map = NULL;
2770 as->ioeventfd_nb = 0;
2771 as->ioeventfds = NULL;
2772 QTAILQ_INIT(&as->listeners);
2773 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2774 as->name = g_strdup(name ? name : "anonymous");
2775 address_space_update_topology(as);
2776 address_space_update_ioeventfds(as);
2777 }
2778
2779 static void do_address_space_destroy(AddressSpace *as)
2780 {
2781 assert(QTAILQ_EMPTY(&as->listeners));
2782
2783 flatview_unref(as->current_map);
2784 g_free(as->name);
2785 g_free(as->ioeventfds);
2786 memory_region_unref(as->root);
2787 }
2788
2789 void address_space_destroy(AddressSpace *as)
2790 {
2791 MemoryRegion *root = as->root;
2792
2793 /* Flush out anything from MemoryListeners listening in on this */
2794 memory_region_transaction_begin();
2795 as->root = NULL;
2796 memory_region_transaction_commit();
2797 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2798
2799 /* At this point, as->dispatch and as->current_map are dummy
2800 * entries that the guest should never use. Wait for the old
2801 * values to expire before freeing the data.
2802 */
2803 as->root = root;
2804 call_rcu(as, do_address_space_destroy, rcu);
2805 }
2806
2807 static const char *memory_region_type(MemoryRegion *mr)
2808 {
2809 if (memory_region_is_ram_device(mr)) {
2810 return "ramd";
2811 } else if (memory_region_is_romd(mr)) {
2812 return "romd";
2813 } else if (memory_region_is_rom(mr)) {
2814 return "rom";
2815 } else if (memory_region_is_ram(mr)) {
2816 return "ram";
2817 } else {
2818 return "i/o";
2819 }
2820 }
2821
2822 typedef struct MemoryRegionList MemoryRegionList;
2823
2824 struct MemoryRegionList {
2825 const MemoryRegion *mr;
2826 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2827 };
2828
2829 typedef QTAILQ_HEAD(mrqueue, MemoryRegionList) MemoryRegionListHead;
2830
2831 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2832 int128_sub((size), int128_one())) : 0)
2833 #define MTREE_INDENT " "
2834
2835 static void mtree_print_mr(fprintf_function mon_printf, void *f,
2836 const MemoryRegion *mr, unsigned int level,
2837 hwaddr base,
2838 MemoryRegionListHead *alias_print_queue)
2839 {
2840 MemoryRegionList *new_ml, *ml, *next_ml;
2841 MemoryRegionListHead submr_print_queue;
2842 const MemoryRegion *submr;
2843 unsigned int i;
2844 hwaddr cur_start, cur_end;
2845
2846 if (!mr) {
2847 return;
2848 }
2849
2850 for (i = 0; i < level; i++) {
2851 mon_printf(f, MTREE_INDENT);
2852 }
2853
2854 cur_start = base + mr->addr;
2855 cur_end = cur_start + MR_SIZE(mr->size);
2856
2857 /*
2858 * Try to detect overflow of memory region. This should never
2859 * happen normally. When it happens, we dump something to warn the
2860 * user who is observing this.
2861 */
2862 if (cur_start < base || cur_end < cur_start) {
2863 mon_printf(f, "[DETECTED OVERFLOW!] ");
2864 }
2865
2866 if (mr->alias) {
2867 MemoryRegionList *ml;
2868 bool found = false;
2869
2870 /* check if the alias is already in the queue */
2871 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2872 if (ml->mr == mr->alias) {
2873 found = true;
2874 }
2875 }
2876
2877 if (!found) {
2878 ml = g_new(MemoryRegionList, 1);
2879 ml->mr = mr->alias;
2880 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2881 }
2882 mon_printf(f, TARGET_FMT_plx "-" TARGET_FMT_plx
2883 " (prio %d, %s): alias %s @%s " TARGET_FMT_plx
2884 "-" TARGET_FMT_plx "%s\n",
2885 cur_start, cur_end,
2886 mr->priority,
2887 memory_region_type((MemoryRegion *)mr),
2888 memory_region_name(mr),
2889 memory_region_name(mr->alias),
2890 mr->alias_offset,
2891 mr->alias_offset + MR_SIZE(mr->size),
2892 mr->enabled ? "" : " [disabled]");
2893 } else {
2894 mon_printf(f,
2895 TARGET_FMT_plx "-" TARGET_FMT_plx " (prio %d, %s): %s%s\n",
2896 cur_start, cur_end,
2897 mr->priority,
2898 memory_region_type((MemoryRegion *)mr),
2899 memory_region_name(mr),
2900 mr->enabled ? "" : " [disabled]");
2901 }
2902
2903 QTAILQ_INIT(&submr_print_queue);
2904
2905 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2906 new_ml = g_new(MemoryRegionList, 1);
2907 new_ml->mr = submr;
2908 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2909 if (new_ml->mr->addr < ml->mr->addr ||
2910 (new_ml->mr->addr == ml->mr->addr &&
2911 new_ml->mr->priority > ml->mr->priority)) {
2912 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2913 new_ml = NULL;
2914 break;
2915 }
2916 }
2917 if (new_ml) {
2918 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2919 }
2920 }
2921
2922 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2923 mtree_print_mr(mon_printf, f, ml->mr, level + 1, cur_start,
2924 alias_print_queue);
2925 }
2926
2927 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2928 g_free(ml);
2929 }
2930 }
2931
2932 struct FlatViewInfo {
2933 fprintf_function mon_printf;
2934 void *f;
2935 int counter;
2936 bool dispatch_tree;
2937 };
2938
2939 static void mtree_print_flatview(gpointer key, gpointer value,
2940 gpointer user_data)
2941 {
2942 FlatView *view = key;
2943 GArray *fv_address_spaces = value;
2944 struct FlatViewInfo *fvi = user_data;
2945 fprintf_function p = fvi->mon_printf;
2946 void *f = fvi->f;
2947 FlatRange *range = &view->ranges[0];
2948 MemoryRegion *mr;
2949 int n = view->nr;
2950 int i;
2951 AddressSpace *as;
2952
2953 p(f, "FlatView #%d\n", fvi->counter);
2954 ++fvi->counter;
2955
2956 for (i = 0; i < fv_address_spaces->len; ++i) {
2957 as = g_array_index(fv_address_spaces, AddressSpace*, i);
2958 p(f, " AS \"%s\", root: %s", as->name, memory_region_name(as->root));
2959 if (as->root->alias) {
2960 p(f, ", alias %s", memory_region_name(as->root->alias));
2961 }
2962 p(f, "\n");
2963 }
2964
2965 p(f, " Root memory region: %s\n",
2966 view->root ? memory_region_name(view->root) : "(none)");
2967
2968 if (n <= 0) {
2969 p(f, MTREE_INDENT "No rendered FlatView\n\n");
2970 return;
2971 }
2972
2973 while (n--) {
2974 mr = range->mr;
2975 if (range->offset_in_region) {
2976 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2977 TARGET_FMT_plx " (prio %d, %s): %s @" TARGET_FMT_plx "\n",
2978 int128_get64(range->addr.start),
2979 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2980 mr->priority,
2981 range->readonly ? "rom" : memory_region_type(mr),
2982 memory_region_name(mr),
2983 range->offset_in_region);
2984 } else {
2985 p(f, MTREE_INDENT TARGET_FMT_plx "-"
2986 TARGET_FMT_plx " (prio %d, %s): %s\n",
2987 int128_get64(range->addr.start),
2988 int128_get64(range->addr.start) + MR_SIZE(range->addr.size),
2989 mr->priority,
2990 range->readonly ? "rom" : memory_region_type(mr),
2991 memory_region_name(mr));
2992 }
2993 range++;
2994 }
2995
2996 #if !defined(CONFIG_USER_ONLY)
2997 if (fvi->dispatch_tree && view->root) {
2998 mtree_print_dispatch(p, f, view->dispatch, view->root);
2999 }
3000 #endif
3001
3002 p(f, "\n");
3003 }
3004
3005 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3006 gpointer user_data)
3007 {
3008 FlatView *view = key;
3009 GArray *fv_address_spaces = value;
3010
3011 g_array_unref(fv_address_spaces);
3012 flatview_unref(view);
3013
3014 return true;
3015 }
3016
3017 void mtree_info(fprintf_function mon_printf, void *f, bool flatview,
3018 bool dispatch_tree)
3019 {
3020 MemoryRegionListHead ml_head;
3021 MemoryRegionList *ml, *ml2;
3022 AddressSpace *as;
3023
3024 if (flatview) {
3025 FlatView *view;
3026 struct FlatViewInfo fvi = {
3027 .mon_printf = mon_printf,
3028 .f = f,
3029 .counter = 0,
3030 .dispatch_tree = dispatch_tree
3031 };
3032 GArray *fv_address_spaces;
3033 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3034
3035 /* Gather all FVs in one table */
3036 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3037 view = address_space_get_flatview(as);
3038
3039 fv_address_spaces = g_hash_table_lookup(views, view);
3040 if (!fv_address_spaces) {
3041 fv_address_spaces = g_array_new(false, false, sizeof(as));
3042 g_hash_table_insert(views, view, fv_address_spaces);
3043 }
3044
3045 g_array_append_val(fv_address_spaces, as);
3046 }
3047
3048 /* Print */
3049 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3050
3051 /* Free */
3052 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3053 g_hash_table_unref(views);
3054
3055 return;
3056 }
3057
3058 QTAILQ_INIT(&ml_head);
3059
3060 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3061 mon_printf(f, "address-space: %s\n", as->name);
3062 mtree_print_mr(mon_printf, f, as->root, 1, 0, &ml_head);
3063 mon_printf(f, "\n");
3064 }
3065
3066 /* print aliased regions */
3067 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3068 mon_printf(f, "memory-region: %s\n", memory_region_name(ml->mr));
3069 mtree_print_mr(mon_printf, f, ml->mr, 1, 0, &ml_head);
3070 mon_printf(f, "\n");
3071 }
3072
3073 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3074 g_free(ml);
3075 }
3076 }
3077
3078 void memory_region_init_ram(MemoryRegion *mr,
3079 struct Object *owner,
3080 const char *name,
3081 uint64_t size,
3082 Error **errp)
3083 {
3084 DeviceState *owner_dev;
3085 Error *err = NULL;
3086
3087 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3088 if (err) {
3089 error_propagate(errp, err);
3090 return;
3091 }
3092 /* This will assert if owner is neither NULL nor a DeviceState.
3093 * We only want the owner here for the purposes of defining a
3094 * unique name for migration. TODO: Ideally we should implement
3095 * a naming scheme for Objects which are not DeviceStates, in
3096 * which case we can relax this restriction.
3097 */
3098 owner_dev = DEVICE(owner);
3099 vmstate_register_ram(mr, owner_dev);
3100 }
3101
3102 void memory_region_init_rom(MemoryRegion *mr,
3103 struct Object *owner,
3104 const char *name,
3105 uint64_t size,
3106 Error **errp)
3107 {
3108 DeviceState *owner_dev;
3109 Error *err = NULL;
3110
3111 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3112 if (err) {
3113 error_propagate(errp, err);
3114 return;
3115 }
3116 /* This will assert if owner is neither NULL nor a DeviceState.
3117 * We only want the owner here for the purposes of defining a
3118 * unique name for migration. TODO: Ideally we should implement
3119 * a naming scheme for Objects which are not DeviceStates, in
3120 * which case we can relax this restriction.
3121 */
3122 owner_dev = DEVICE(owner);
3123 vmstate_register_ram(mr, owner_dev);
3124 }
3125
3126 void memory_region_init_rom_device(MemoryRegion *mr,
3127 struct Object *owner,
3128 const MemoryRegionOps *ops,
3129 void *opaque,
3130 const char *name,
3131 uint64_t size,
3132 Error **errp)
3133 {
3134 DeviceState *owner_dev;
3135 Error *err = NULL;
3136
3137 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3138 name, size, &err);
3139 if (err) {
3140 error_propagate(errp, err);
3141 return;
3142 }
3143 /* This will assert if owner is neither NULL nor a DeviceState.
3144 * We only want the owner here for the purposes of defining a
3145 * unique name for migration. TODO: Ideally we should implement
3146 * a naming scheme for Objects which are not DeviceStates, in
3147 * which case we can relax this restriction.
3148 */
3149 owner_dev = DEVICE(owner);
3150 vmstate_register_ram(mr, owner_dev);
3151 }
3152
3153 static const TypeInfo memory_region_info = {
3154 .parent = TYPE_OBJECT,
3155 .name = TYPE_MEMORY_REGION,
3156 .instance_size = sizeof(MemoryRegion),
3157 .instance_init = memory_region_initfn,
3158 .instance_finalize = memory_region_finalize,
3159 };
3160
3161 static const TypeInfo iommu_memory_region_info = {
3162 .parent = TYPE_MEMORY_REGION,
3163 .name = TYPE_IOMMU_MEMORY_REGION,
3164 .class_size = sizeof(IOMMUMemoryRegionClass),
3165 .instance_size = sizeof(IOMMUMemoryRegion),
3166 .instance_init = iommu_memory_region_initfn,
3167 .abstract = true,
3168 };
3169
3170 static void memory_register_types(void)
3171 {
3172 type_register_static(&memory_region_info);
3173 type_register_static(&iommu_memory_region_info);
3174 }
3175
3176 type_init(memory_register_types)
QEmu