hw/ide/pci.c

   1 /*
   2  * QEMU IDE Emulation: PCI Bus support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/isa/isa.h"
  29 #include "sysemu/dma.h"
  30 #include "qemu/error-report.h"
  31 #include "hw/ide/pci.h"
  32 #include "trace.h"
  33
  34 #define BMDMA_PAGE_SIZE 4096
  35
  36 #define BM_MIGRATION_COMPAT_STATUS_BITS \
  37         (IDE_RETRY_DMA | IDE_RETRY_PIO | \
  38         IDE_RETRY_READ | IDE_RETRY_FLUSH)
  39
  40 static void bmdma_start_dma(IDEDMA *dma, IDEState *s,
  41                             BlockCompletionFunc *dma_cb)
  42 {
  43     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  44
  45     bm->dma_cb = dma_cb;
  46     bm->cur_prd_last = 0;
  47     bm->cur_prd_addr = 0;
  48     bm->cur_prd_len = 0;
  49
  50     if (bm->status & BM_STATUS_DMAING) {
  51         bm->dma_cb(bmdma_active_if(bm), 0);
  52     }
  53 }
  54
  55 /**
  56  * Prepare an sglist based on available PRDs.
  57  * @limit: How many bytes to prepare total.
  58  *
  59  * Returns the number of bytes prepared, -1 on error.
  60  * IDEState.io_buffer_size will contain the number of bytes described
  61  * by the PRDs, whether or not we added them to the sglist.
  62  */
  63 static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit)
  64 {
  65     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
  66     IDEState *s = bmdma_active_if(bm);
  67     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
  68     struct {
  69         uint32_t addr;
  70         uint32_t size;
  71     } prd;
  72     int l, len;
  73
  74     pci_dma_sglist_init(&s->sg, pci_dev,
  75                         s->nsector / (BMDMA_PAGE_SIZE / 512) + 1);
  76     s->io_buffer_size = 0;
  77     for(;;) {
  78         if (bm->cur_prd_len == 0) {
  79             /* end of table (with a fail safe of one page) */
  80             if (bm->cur_prd_last ||
  81                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE) {
  82                 return s->sg.size;
  83             }
  84             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
  85             bm->cur_addr += 8;
  86             prd.addr = le32_to_cpu(prd.addr);
  87             prd.size = le32_to_cpu(prd.size);
  88             len = prd.size & 0xfffe;
  89             if (len == 0)
  90                 len = 0x10000;
  91             bm->cur_prd_len = len;
  92             bm->cur_prd_addr = prd.addr;
  93             bm->cur_prd_last = (prd.size & 0x80000000);
  94         }
  95         l = bm->cur_prd_len;
  96         if (l > 0) {
  97             uint64_t sg_len;
  98
  99             /* Don't add extra bytes to the SGList; consume any remaining
 100              * PRDs from the guest, but ignore them. */
 101             sg_len = MIN(limit - s->sg.size, bm->cur_prd_len);
 102             if (sg_len) {
 103                 qemu_sglist_add(&s->sg, bm->cur_prd_addr, sg_len);
 104             }
 105
 106             bm->cur_prd_addr += l;
 107             bm->cur_prd_len -= l;
 108             s->io_buffer_size += l;
 109         }
 110     }
 111
 112     qemu_sglist_destroy(&s->sg);
 113     s->io_buffer_size = 0;
 114     return -1;
 115 }
 116
 117 /* return 0 if buffer completed */
 118 static int bmdma_rw_buf(IDEDMA *dma, int is_write)
 119 {
 120     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 121     IDEState *s = bmdma_active_if(bm);
 122     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 123     struct {
 124         uint32_t addr;
 125         uint32_t size;
 126     } prd;
 127     int l, len;
 128
 129     for(;;) {
 130         l = s->io_buffer_size - s->io_buffer_index;
 131         if (l <= 0)
 132             break;
 133         if (bm->cur_prd_len == 0) {
 134             /* end of table (with a fail safe of one page) */
 135             if (bm->cur_prd_last ||
 136                 (bm->cur_addr - bm->addr) >= BMDMA_PAGE_SIZE)
 137                 return 0;
 138             pci_dma_read(pci_dev, bm->cur_addr, &prd, 8);
 139             bm->cur_addr += 8;
 140             prd.addr = le32_to_cpu(prd.addr);
 141             prd.size = le32_to_cpu(prd.size);
 142             len = prd.size & 0xfffe;
 143             if (len == 0)
 144                 len = 0x10000;
 145             bm->cur_prd_len = len;
 146             bm->cur_prd_addr = prd.addr;
 147             bm->cur_prd_last = (prd.size & 0x80000000);
 148         }
 149         if (l > bm->cur_prd_len)
 150             l = bm->cur_prd_len;
 151         if (l > 0) {
 152             if (is_write) {
 153                 pci_dma_write(pci_dev, bm->cur_prd_addr,
 154                               s->io_buffer + s->io_buffer_index, l);
 155             } else {
 156                 pci_dma_read(pci_dev, bm->cur_prd_addr,
 157                              s->io_buffer + s->io_buffer_index, l);
 158             }
 159             bm->cur_prd_addr += l;
 160             bm->cur_prd_len -= l;
 161             s->io_buffer_index += l;
 162         }
 163     }
 164     return 1;
 165 }
 166
 167 static void bmdma_set_inactive(IDEDMA *dma, bool more)
 168 {
 169     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 170
 171     bm->dma_cb = NULL;
 172     if (more) {
 173         bm->status |= BM_STATUS_DMAING;
 174     } else {
 175         bm->status &= ~BM_STATUS_DMAING;
 176     }
 177 }
 178
 179 static void bmdma_restart_dma(IDEDMA *dma)
 180 {
 181     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 182
 183     bm->cur_addr = bm->addr;
 184 }
 185
 186 static void bmdma_cancel(BMDMAState *bm)
 187 {
 188     if (bm->status & BM_STATUS_DMAING) {
 189         /* cancel DMA request */
 190         bmdma_set_inactive(&bm->dma, false);
 191     }
 192 }
 193
 194 static void bmdma_reset(IDEDMA *dma)
 195 {
 196     BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma);
 197
 198     trace_bmdma_reset();
 199     bmdma_cancel(bm);
 200     bm->cmd = 0;
 201     bm->status = 0;
 202     bm->addr = 0;
 203     bm->cur_addr = 0;
 204     bm->cur_prd_last = 0;
 205     bm->cur_prd_addr = 0;
 206     bm->cur_prd_len = 0;
 207 }
 208
 209 static void bmdma_irq(void *opaque, int n, int level)
 210 {
 211     BMDMAState *bm = opaque;
 212
 213     if (!level) {
 214         /* pass through lower */
 215         qemu_set_irq(bm->irq, level);
 216         return;
 217     }
 218
 219     bm->status |= BM_STATUS_INT;
 220
 221     /* trigger the real irq */
 222     qemu_set_irq(bm->irq, level);
 223 }
 224
 225 void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val)
 226 {
 227     trace_bmdma_cmd_writeb(val);
 228
 229     /* Ignore writes to SSBM if it keeps the old value */
 230     if ((val & BM_CMD_START) != (bm->cmd & BM_CMD_START)) {
 231         if (!(val & BM_CMD_START)) {
 232             ide_cancel_dma_sync(idebus_active_if(bm->bus));
 233             bm->status &= ~BM_STATUS_DMAING;
 234         } else {
 235             bm->cur_addr = bm->addr;
 236             if (!(bm->status & BM_STATUS_DMAING)) {
 237                 bm->status |= BM_STATUS_DMAING;
 238                 /* start dma transfer if possible */
 239                 if (bm->dma_cb)
 240                     bm->dma_cb(bmdma_active_if(bm), 0);
 241             }
 242         }
 243     }
 244
 245     bm->cmd = val & 0x09;
 246 }
 247
 248 static uint64_t bmdma_addr_read(void *opaque, hwaddr addr,
 249                                 unsigned width)
 250 {
 251     BMDMAState *bm = opaque;
 252     uint32_t mask = (1ULL << (width * 8)) - 1;
 253     uint64_t data;
 254
 255     data = (bm->addr >> (addr * 8)) & mask;
 256     trace_bmdma_addr_read(data);
 257     return data;
 258 }
 259
 260 static void bmdma_addr_write(void *opaque, hwaddr addr,
 261                              uint64_t data, unsigned width)
 262 {
 263     BMDMAState *bm = opaque;
 264     int shift = addr * 8;
 265     uint32_t mask = (1ULL << (width * 8)) - 1;
 266
 267     trace_bmdma_addr_write(data);
 268     bm->addr &= ~(mask << shift);
 269     bm->addr |= ((data & mask) << shift) & ~3;
 270 }
 271
 272 MemoryRegionOps bmdma_addr_ioport_ops = {
 273     .read = bmdma_addr_read,
 274     .write = bmdma_addr_write,
 275     .endianness = DEVICE_LITTLE_ENDIAN,
 276 };
 277
 278 static bool ide_bmdma_current_needed(void *opaque)
 279 {
 280     BMDMAState *bm = opaque;
 281
 282     return (bm->cur_prd_len != 0);
 283 }
 284
 285 static bool ide_bmdma_status_needed(void *opaque)
 286 {
 287     BMDMAState *bm = opaque;
 288
 289     /* Older versions abused some bits in the status register for internal
 290      * error state. If any of these bits are set, we must add a subsection to
 291      * transfer the real status register */
 292     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 293
 294     return ((bm->status & abused_bits) != 0);
 295 }
 296
 297 static int ide_bmdma_pre_save(void *opaque)
 298 {
 299     BMDMAState *bm = opaque;
 300     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 301
 302     if (!(bm->status & BM_STATUS_DMAING) && bm->dma_cb) {
 303         bm->bus->error_status =
 304             ide_dma_cmd_to_retry(bmdma_active_if(bm)->dma_cmd);
 305     }
 306     bm->migration_retry_unit = bm->bus->retry_unit;
 307     bm->migration_retry_sector_num = bm->bus->retry_sector_num;
 308     bm->migration_retry_nsector = bm->bus->retry_nsector;
 309     bm->migration_compat_status =
 310         (bm->status & ~abused_bits) | (bm->bus->error_status & abused_bits);
 311
 312     return 0;
 313 }
 314
 315 /* This function accesses bm->bus->error_status which is loaded only after
 316  * BMDMA itself. This is why the function is called from ide_pci_post_load
 317  * instead of being registered with VMState where it would run too early. */
 318 static int ide_bmdma_post_load(void *opaque, int version_id)
 319 {
 320     BMDMAState *bm = opaque;
 321     uint8_t abused_bits = BM_MIGRATION_COMPAT_STATUS_BITS;
 322
 323     if (bm->status == 0) {
 324         bm->status = bm->migration_compat_status & ~abused_bits;
 325         bm->bus->error_status |= bm->migration_compat_status & abused_bits;
 326     }
 327     if (bm->bus->error_status) {
 328         bm->bus->retry_sector_num = bm->migration_retry_sector_num;
 329         bm->bus->retry_nsector = bm->migration_retry_nsector;
 330         bm->bus->retry_unit = bm->migration_retry_unit;
 331     }
 332
 333     return 0;
 334 }
 335
 336 static const VMStateDescription vmstate_bmdma_current = {
 337     .name = "ide bmdma_current",
 338     .version_id = 1,
 339     .minimum_version_id = 1,
 340     .needed = ide_bmdma_current_needed,
 341     .fields = (VMStateField[]) {
 342         VMSTATE_UINT32(cur_addr, BMDMAState),
 343         VMSTATE_UINT32(cur_prd_last, BMDMAState),
 344         VMSTATE_UINT32(cur_prd_addr, BMDMAState),
 345         VMSTATE_UINT32(cur_prd_len, BMDMAState),
 346         VMSTATE_END_OF_LIST()
 347     }
 348 };
 349
 350 static const VMStateDescription vmstate_bmdma_status = {
 351     .name ="ide bmdma/status",
 352     .version_id = 1,
 353     .minimum_version_id = 1,
 354     .needed = ide_bmdma_status_needed,
 355     .fields = (VMStateField[]) {
 356         VMSTATE_UINT8(status, BMDMAState),
 357         VMSTATE_END_OF_LIST()
 358     }
 359 };
 360
 361 static const VMStateDescription vmstate_bmdma = {
 362     .name = "ide bmdma",
 363     .version_id = 3,
 364     .minimum_version_id = 0,
 365     .pre_save  = ide_bmdma_pre_save,
 366     .fields = (VMStateField[]) {
 367         VMSTATE_UINT8(cmd, BMDMAState),
 368         VMSTATE_UINT8(migration_compat_status, BMDMAState),
 369         VMSTATE_UINT32(addr, BMDMAState),
 370         VMSTATE_INT64(migration_retry_sector_num, BMDMAState),
 371         VMSTATE_UINT32(migration_retry_nsector, BMDMAState),
 372         VMSTATE_UINT8(migration_retry_unit, BMDMAState),
 373         VMSTATE_END_OF_LIST()
 374     },
 375     .subsections = (const VMStateDescription*[]) {
 376         &vmstate_bmdma_current,
 377         &vmstate_bmdma_status,
 378         NULL
 379     }
 380 };
 381
 382 static int ide_pci_post_load(void *opaque, int version_id)
 383 {
 384     PCIIDEState *d = opaque;
 385     int i;
 386
 387     for(i = 0; i < 2; i++) {
 388         /* current versions always store 0/1, but older version
 389            stored bigger values. We only need last bit */
 390         d->bmdma[i].migration_retry_unit &= 1;
 391         ide_bmdma_post_load(&d->bmdma[i], -1);
 392     }
 393
 394     return 0;
 395 }
 396
 397 const VMStateDescription vmstate_ide_pci = {
 398     .name = "ide",
 399     .version_id = 3,
 400     .minimum_version_id = 0,
 401     .post_load = ide_pci_post_load,
 402     .fields = (VMStateField[]) {
 403         VMSTATE_PCI_DEVICE(parent_obj, PCIIDEState),
 404         VMSTATE_STRUCT_ARRAY(bmdma, PCIIDEState, 2, 0,
 405                              vmstate_bmdma, BMDMAState),
 406         VMSTATE_IDE_BUS_ARRAY(bus, PCIIDEState, 2),
 407         VMSTATE_IDE_DRIVES(bus[0].ifs, PCIIDEState),
 408         VMSTATE_IDE_DRIVES(bus[1].ifs, PCIIDEState),
 409         VMSTATE_END_OF_LIST()
 410     }
 411 };
 412
 413 void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
 414 {
 415     PCIIDEState *d = PCI_IDE(dev);
 416     static const int bus[4]  = { 0, 0, 1, 1 };
 417     static const int unit[4] = { 0, 1, 0, 1 };
 418     int i;
 419
 420     for (i = 0; i < 4; i++) {
 421         if (hd_table[i] == NULL)
 422             continue;
 423         ide_create_drive(d->bus+bus[i], unit[i], hd_table[i]);
 424     }
 425 }
 426
 427 static const struct IDEDMAOps bmdma_ops = {
 428     .start_dma = bmdma_start_dma,
 429     .prepare_buf = bmdma_prepare_buf,
 430     .rw_buf = bmdma_rw_buf,
 431     .restart_dma = bmdma_restart_dma,
 432     .set_inactive = bmdma_set_inactive,
 433     .reset = bmdma_reset,
 434 };
 435
 436 void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d)
 437 {
 438     if (bus->dma == &bm->dma) {
 439         return;
 440     }
 441
 442     bm->dma.ops = &bmdma_ops;
 443     bus->dma = &bm->dma;
 444     bm->irq = bus->irq;
 445     bus->irq = qemu_allocate_irq(bmdma_irq, bm, 0);
 446     bm->pci_dev = d;
 447 }
 448
 449 static const TypeInfo pci_ide_type_info = {
 450     .name = TYPE_PCI_IDE,
 451     .parent = TYPE_PCI_DEVICE,
 452     .instance_size = sizeof(PCIIDEState),
 453     .abstract = true,
 454     .interfaces = (InterfaceInfo[]) {
 455         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 456         { },
 457     },
 458 };
 459
 460 static void pci_ide_register_types(void)
 461 {
 462     type_register_static(&pci_ide_type_info);
 463 }
 464
 465 type_init(pci_ide_register_types)