pc: acpi: remove NOP assignment
[qemu.git] / hw / gpio / puv3_gpio.c
blob445afccf9f57a434ae410379ba0fe7e215aea868
1 /*
2 * GPIO device simulation in PKUnity SoC
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or any later version.
9 * See the COPYING file in the top-level directory.
11 #include "qemu/osdep.h"
12 #include "hw/hw.h"
13 #include "hw/sysbus.h"
15 #undef DEBUG_PUV3
16 #include "hw/unicore32/puv3.h"
18 #define TYPE_PUV3_GPIO "puv3_gpio"
19 #define PUV3_GPIO(obj) OBJECT_CHECK(PUV3GPIOState, (obj), TYPE_PUV3_GPIO)
21 typedef struct PUV3GPIOState {
22 SysBusDevice parent_obj;
24 MemoryRegion iomem;
25 qemu_irq irq[9];
27 uint32_t reg_GPLR;
28 uint32_t reg_GPDR;
29 uint32_t reg_GPIR;
30 } PUV3GPIOState;
32 static uint64_t puv3_gpio_read(void *opaque, hwaddr offset,
33 unsigned size)
35 PUV3GPIOState *s = opaque;
36 uint32_t ret = 0;
38 switch (offset) {
39 case 0x00:
40 ret = s->reg_GPLR;
41 break;
42 case 0x04:
43 ret = s->reg_GPDR;
44 break;
45 case 0x20:
46 ret = s->reg_GPIR;
47 break;
48 default:
49 DPRINTF("Bad offset 0x%x\n", offset);
51 DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
53 return ret;
56 static void puv3_gpio_write(void *opaque, hwaddr offset,
57 uint64_t value, unsigned size)
59 PUV3GPIOState *s = opaque;
61 DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
62 switch (offset) {
63 case 0x04:
64 s->reg_GPDR = value;
65 break;
66 case 0x08:
67 if (s->reg_GPDR & value) {
68 s->reg_GPLR |= value;
69 } else {
70 DPRINTF("Write gpio input port error!");
72 break;
73 case 0x0c:
74 if (s->reg_GPDR & value) {
75 s->reg_GPLR &= ~value;
76 } else {
77 DPRINTF("Write gpio input port error!");
79 break;
80 case 0x10: /* GRER */
81 case 0x14: /* GFER */
82 case 0x18: /* GEDR */
83 break;
84 case 0x20: /* GPIR */
85 s->reg_GPIR = value;
86 break;
87 default:
88 DPRINTF("Bad offset 0x%x\n", offset);
92 static const MemoryRegionOps puv3_gpio_ops = {
93 .read = puv3_gpio_read,
94 .write = puv3_gpio_write,
95 .impl = {
96 .min_access_size = 4,
97 .max_access_size = 4,
99 .endianness = DEVICE_NATIVE_ENDIAN,
102 static int puv3_gpio_init(SysBusDevice *dev)
104 PUV3GPIOState *s = PUV3_GPIO(dev);
106 s->reg_GPLR = 0;
107 s->reg_GPDR = 0;
109 /* FIXME: these irqs not handled yet */
110 sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]);
111 sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]);
112 sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]);
113 sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]);
114 sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]);
115 sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]);
116 sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]);
117 sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]);
118 sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]);
120 memory_region_init_io(&s->iomem, OBJECT(s), &puv3_gpio_ops, s, "puv3_gpio",
121 PUV3_REGS_OFFSET);
122 sysbus_init_mmio(dev, &s->iomem);
124 return 0;
127 static void puv3_gpio_class_init(ObjectClass *klass, void *data)
129 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
131 sdc->init = puv3_gpio_init;
134 static const TypeInfo puv3_gpio_info = {
135 .name = TYPE_PUV3_GPIO,
136 .parent = TYPE_SYS_BUS_DEVICE,
137 .instance_size = sizeof(PUV3GPIOState),
138 .class_init = puv3_gpio_class_init,
141 static void puv3_gpio_register_type(void)
143 type_register_static(&puv3_gpio_info);
146 type_init(puv3_gpio_register_type)