target-ppc/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "sysemu/kvm.h"
   4 #include "helper_regs.h"
   5
   6 static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
   7 {
   8     PowerPCCPU *cpu = opaque;
   9     CPUPPCState *env = &cpu->env;
  10     unsigned int i, j;
  11     target_ulong sdr1;
  12     uint32_t fpscr;
  13     target_ulong xer;
  14
  15     for (i = 0; i < 32; i++)
  16         qemu_get_betls(f, &env->gpr[i]);
  17 #if !defined(TARGET_PPC64)
  18     for (i = 0; i < 32; i++)
  19         qemu_get_betls(f, &env->gprh[i]);
  20 #endif
  21     qemu_get_betls(f, &env->lr);
  22     qemu_get_betls(f, &env->ctr);
  23     for (i = 0; i < 8; i++)
  24         qemu_get_be32s(f, &env->crf[i]);
  25     qemu_get_betls(f, &xer);
  26     cpu_write_xer(env, xer);
  27     qemu_get_betls(f, &env->reserve_addr);
  28     qemu_get_betls(f, &env->msr);
  29     for (i = 0; i < 4; i++)
  30         qemu_get_betls(f, &env->tgpr[i]);
  31     for (i = 0; i < 32; i++) {
  32         union {
  33             float64 d;
  34             uint64_t l;
  35         } u;
  36         u.l = qemu_get_be64(f);
  37         env->fpr[i] = u.d;
  38     }
  39     qemu_get_be32s(f, &fpscr);
  40     env->fpscr = fpscr;
  41     qemu_get_sbe32s(f, &env->access_type);
  42 #if defined(TARGET_PPC64)
  43     qemu_get_betls(f, &env->spr[SPR_ASR]);
  44     qemu_get_sbe32s(f, &env->slb_nr);
  45 #endif
  46     qemu_get_betls(f, &sdr1);
  47     for (i = 0; i < 32; i++)
  48         qemu_get_betls(f, &env->sr[i]);
  49     for (i = 0; i < 2; i++)
  50         for (j = 0; j < 8; j++)
  51             qemu_get_betls(f, &env->DBAT[i][j]);
  52     for (i = 0; i < 2; i++)
  53         for (j = 0; j < 8; j++)
  54             qemu_get_betls(f, &env->IBAT[i][j]);
  55     qemu_get_sbe32s(f, &env->nb_tlb);
  56     qemu_get_sbe32s(f, &env->tlb_per_way);
  57     qemu_get_sbe32s(f, &env->nb_ways);
  58     qemu_get_sbe32s(f, &env->last_way);
  59     qemu_get_sbe32s(f, &env->id_tlbs);
  60     qemu_get_sbe32s(f, &env->nb_pids);
  61     if (env->tlb.tlb6) {
  62         // XXX assumes 6xx
  63         for (i = 0; i < env->nb_tlb; i++) {
  64             qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
  65             qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
  66             qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
  67         }
  68     }
  69     for (i = 0; i < 4; i++)
  70         qemu_get_betls(f, &env->pb[i]);
  71     for (i = 0; i < 1024; i++)
  72         qemu_get_betls(f, &env->spr[i]);
  73     if (!env->external_htab) {
  74         ppc_store_sdr1(env, sdr1);
  75     }
  76     qemu_get_be32s(f, &env->vscr);
  77     qemu_get_be64s(f, &env->spe_acc);
  78     qemu_get_be32s(f, &env->spe_fscr);
  79     qemu_get_betls(f, &env->msr_mask);
  80     qemu_get_be32s(f, &env->flags);
  81     qemu_get_sbe32s(f, &env->error_code);
  82     qemu_get_be32s(f, &env->pending_interrupts);
  83     qemu_get_be32s(f, &env->irq_input_state);
  84     for (i = 0; i < POWERPC_EXCP_NB; i++)
  85         qemu_get_betls(f, &env->excp_vectors[i]);
  86     qemu_get_betls(f, &env->excp_prefix);
  87     qemu_get_betls(f, &env->ivor_mask);
  88     qemu_get_betls(f, &env->ivpr_mask);
  89     qemu_get_betls(f, &env->hreset_vector);
  90     qemu_get_betls(f, &env->nip);
  91     qemu_get_betls(f, &env->hflags);
  92     qemu_get_betls(f, &env->hflags_nmsr);
  93     qemu_get_sbe32s(f, &env->mmu_idx);
  94     qemu_get_sbe32(f); /* Discard unused power_mode */
  95
  96     return 0;
  97 }
  98
  99 static int get_avr(QEMUFile *f, void *pv, size_t size)
 100 {
 101     ppc_avr_t *v = pv;
 102
 103     v->u64[0] = qemu_get_be64(f);
 104     v->u64[1] = qemu_get_be64(f);
 105
 106     return 0;
 107 }
 108
 109 static void put_avr(QEMUFile *f, void *pv, size_t size)
 110 {
 111     ppc_avr_t *v = pv;
 112
 113     qemu_put_be64(f, v->u64[0]);
 114     qemu_put_be64(f, v->u64[1]);
 115 }
 116
 117 static const VMStateInfo vmstate_info_avr = {
 118     .name = "avr",
 119     .get  = get_avr,
 120     .put  = put_avr,
 121 };
 122
 123 #define VMSTATE_AVR_ARRAY_V(_f, _s, _n, _v)                       \
 124     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_avr, ppc_avr_t)
 125
 126 #define VMSTATE_AVR_ARRAY(_f, _s, _n)                             \
 127     VMSTATE_AVR_ARRAY_V(_f, _s, _n, 0)
 128
 129 static void cpu_pre_save(void *opaque)
 130 {
 131     PowerPCCPU *cpu = opaque;
 132     CPUPPCState *env = &cpu->env;
 133     int i;
 134
 135     env->spr[SPR_LR] = env->lr;
 136     env->spr[SPR_CTR] = env->ctr;
 137     env->spr[SPR_XER] = env->xer;
 138 #if defined(TARGET_PPC64)
 139     env->spr[SPR_CFAR] = env->cfar;
 140 #endif
 141     env->spr[SPR_BOOKE_SPEFSCR] = env->spe_fscr;
 142
 143     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 144         env->spr[SPR_DBAT0U + 2*i] = env->DBAT[0][i];
 145         env->spr[SPR_DBAT0U + 2*i + 1] = env->DBAT[1][i];
 146         env->spr[SPR_IBAT0U + 2*i] = env->IBAT[0][i];
 147         env->spr[SPR_IBAT0U + 2*i + 1] = env->IBAT[1][i];
 148     }
 149     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 150         env->spr[SPR_DBAT4U + 2*i] = env->DBAT[0][i+4];
 151         env->spr[SPR_DBAT4U + 2*i + 1] = env->DBAT[1][i+4];
 152         env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4];
 153         env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4];
 154     }
 155 }
 156
 157 static int cpu_post_load(void *opaque, int version_id)
 158 {
 159     PowerPCCPU *cpu = opaque;
 160     CPUPPCState *env = &cpu->env;
 161     int i;
 162
 163     /*
 164      * We always ignore the source PVR. The user or management
 165      * software has to take care of running QEMU in a compatible mode.
 166      */
 167     env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
 168     env->lr = env->spr[SPR_LR];
 169     env->ctr = env->spr[SPR_CTR];
 170     env->xer = env->spr[SPR_XER];
 171 #if defined(TARGET_PPC64)
 172     env->cfar = env->spr[SPR_CFAR];
 173 #endif
 174     env->spe_fscr = env->spr[SPR_BOOKE_SPEFSCR];
 175
 176     for (i = 0; (i < 4) && (i < env->nb_BATs); i++) {
 177         env->DBAT[0][i] = env->spr[SPR_DBAT0U + 2*i];
 178         env->DBAT[1][i] = env->spr[SPR_DBAT0U + 2*i + 1];
 179         env->IBAT[0][i] = env->spr[SPR_IBAT0U + 2*i];
 180         env->IBAT[1][i] = env->spr[SPR_IBAT0U + 2*i + 1];
 181     }
 182     for (i = 0; (i < 4) && ((i+4) < env->nb_BATs); i++) {
 183         env->DBAT[0][i+4] = env->spr[SPR_DBAT4U + 2*i];
 184         env->DBAT[1][i+4] = env->spr[SPR_DBAT4U + 2*i + 1];
 185         env->IBAT[0][i+4] = env->spr[SPR_IBAT4U + 2*i];
 186         env->IBAT[1][i+4] = env->spr[SPR_IBAT4U + 2*i + 1];
 187     }
 188
 189     if (!env->external_htab) {
 190         /* Restore htab_base and htab_mask variables */
 191         ppc_store_sdr1(env, env->spr[SPR_SDR1]);
 192     }
 193     hreg_compute_hflags(env);
 194     hreg_compute_mem_idx(env);
 195
 196     return 0;
 197 }
 198
 199 static bool fpu_needed(void *opaque)
 200 {
 201     PowerPCCPU *cpu = opaque;
 202
 203     return (cpu->env.insns_flags & PPC_FLOAT);
 204 }
 205
 206 static const VMStateDescription vmstate_fpu = {
 207     .name = "cpu/fpu",
 208     .version_id = 1,
 209     .minimum_version_id = 1,
 210     .fields = (VMStateField[]) {
 211         VMSTATE_FLOAT64_ARRAY(env.fpr, PowerPCCPU, 32),
 212         VMSTATE_UINTTL(env.fpscr, PowerPCCPU),
 213         VMSTATE_END_OF_LIST()
 214     },
 215 };
 216
 217 static bool altivec_needed(void *opaque)
 218 {
 219     PowerPCCPU *cpu = opaque;
 220
 221     return (cpu->env.insns_flags & PPC_ALTIVEC);
 222 }
 223
 224 static const VMStateDescription vmstate_altivec = {
 225     .name = "cpu/altivec",
 226     .version_id = 1,
 227     .minimum_version_id = 1,
 228     .fields = (VMStateField[]) {
 229         VMSTATE_AVR_ARRAY(env.avr, PowerPCCPU, 32),
 230         VMSTATE_UINT32(env.vscr, PowerPCCPU),
 231         VMSTATE_END_OF_LIST()
 232     },
 233 };
 234
 235 static bool vsx_needed(void *opaque)
 236 {
 237     PowerPCCPU *cpu = opaque;
 238
 239     return (cpu->env.insns_flags2 & PPC2_VSX);
 240 }
 241
 242 static const VMStateDescription vmstate_vsx = {
 243     .name = "cpu/vsx",
 244     .version_id = 1,
 245     .minimum_version_id = 1,
 246     .fields = (VMStateField[]) {
 247         VMSTATE_UINT64_ARRAY(env.vsr, PowerPCCPU, 32),
 248         VMSTATE_END_OF_LIST()
 249     },
 250 };
 251
 252 static bool sr_needed(void *opaque)
 253 {
 254 #ifdef TARGET_PPC64
 255     PowerPCCPU *cpu = opaque;
 256
 257     return !(cpu->env.mmu_model & POWERPC_MMU_64);
 258 #else
 259     return true;
 260 #endif
 261 }
 262
 263 static const VMStateDescription vmstate_sr = {
 264     .name = "cpu/sr",
 265     .version_id = 1,
 266     .minimum_version_id = 1,
 267     .fields = (VMStateField[]) {
 268         VMSTATE_UINTTL_ARRAY(env.sr, PowerPCCPU, 32),
 269         VMSTATE_END_OF_LIST()
 270     },
 271 };
 272
 273 #ifdef TARGET_PPC64
 274 static int get_slbe(QEMUFile *f, void *pv, size_t size)
 275 {
 276     ppc_slb_t *v = pv;
 277
 278     v->esid = qemu_get_be64(f);
 279     v->vsid = qemu_get_be64(f);
 280
 281     return 0;
 282 }
 283
 284 static void put_slbe(QEMUFile *f, void *pv, size_t size)
 285 {
 286     ppc_slb_t *v = pv;
 287
 288     qemu_put_be64(f, v->esid);
 289     qemu_put_be64(f, v->vsid);
 290 }
 291
 292 static const VMStateInfo vmstate_info_slbe = {
 293     .name = "slbe",
 294     .get  = get_slbe,
 295     .put  = put_slbe,
 296 };
 297
 298 #define VMSTATE_SLB_ARRAY_V(_f, _s, _n, _v)                       \
 299     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_slbe, ppc_slb_t)
 300
 301 #define VMSTATE_SLB_ARRAY(_f, _s, _n)                             \
 302     VMSTATE_SLB_ARRAY_V(_f, _s, _n, 0)
 303
 304 static bool slb_needed(void *opaque)
 305 {
 306     PowerPCCPU *cpu = opaque;
 307
 308     /* We don't support any of the old segment table based 64-bit CPUs */
 309     return (cpu->env.mmu_model & POWERPC_MMU_64);
 310 }
 311
 312 static const VMStateDescription vmstate_slb = {
 313     .name = "cpu/slb",
 314     .version_id = 1,
 315     .minimum_version_id = 1,
 316     .fields = (VMStateField[]) {
 317         VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
 318         VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
 319         VMSTATE_END_OF_LIST()
 320     }
 321 };
 322 #endif /* TARGET_PPC64 */
 323
 324 static const VMStateDescription vmstate_tlb6xx_entry = {
 325     .name = "cpu/tlb6xx_entry",
 326     .version_id = 1,
 327     .minimum_version_id = 1,
 328     .fields = (VMStateField[]) {
 329         VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
 330         VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
 331         VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
 332         VMSTATE_END_OF_LIST()
 333     },
 334 };
 335
 336 static bool tlb6xx_needed(void *opaque)
 337 {
 338     PowerPCCPU *cpu = opaque;
 339     CPUPPCState *env = &cpu->env;
 340
 341     return env->nb_tlb && (env->tlb_type == TLB_6XX);
 342 }
 343
 344 static const VMStateDescription vmstate_tlb6xx = {
 345     .name = "cpu/tlb6xx",
 346     .version_id = 1,
 347     .minimum_version_id = 1,
 348     .fields = (VMStateField[]) {
 349         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 350         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
 351                                             env.nb_tlb,
 352                                             vmstate_tlb6xx_entry,
 353                                             ppc6xx_tlb_t),
 354         VMSTATE_UINTTL_ARRAY(env.tgpr, PowerPCCPU, 4),
 355         VMSTATE_END_OF_LIST()
 356     }
 357 };
 358
 359 static const VMStateDescription vmstate_tlbemb_entry = {
 360     .name = "cpu/tlbemb_entry",
 361     .version_id = 1,
 362     .minimum_version_id = 1,
 363     .fields = (VMStateField[]) {
 364         VMSTATE_UINT64(RPN, ppcemb_tlb_t),
 365         VMSTATE_UINTTL(EPN, ppcemb_tlb_t),
 366         VMSTATE_UINTTL(PID, ppcemb_tlb_t),
 367         VMSTATE_UINTTL(size, ppcemb_tlb_t),
 368         VMSTATE_UINT32(prot, ppcemb_tlb_t),
 369         VMSTATE_UINT32(attr, ppcemb_tlb_t),
 370         VMSTATE_END_OF_LIST()
 371     },
 372 };
 373
 374 static bool tlbemb_needed(void *opaque)
 375 {
 376     PowerPCCPU *cpu = opaque;
 377     CPUPPCState *env = &cpu->env;
 378
 379     return env->nb_tlb && (env->tlb_type == TLB_EMB);
 380 }
 381
 382 static bool pbr403_needed(void *opaque)
 383 {
 384     PowerPCCPU *cpu = opaque;
 385     uint32_t pvr = cpu->env.spr[SPR_PVR];
 386
 387     return (pvr & 0xffff0000) == 0x00200000;
 388 }
 389
 390 static const VMStateDescription vmstate_pbr403 = {
 391     .name = "cpu/pbr403",
 392     .version_id = 1,
 393     .minimum_version_id = 1,
 394     .fields = (VMStateField[]) {
 395         VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
 396         VMSTATE_END_OF_LIST()
 397     },
 398 };
 399
 400 static const VMStateDescription vmstate_tlbemb = {
 401     .name = "cpu/tlb6xx",
 402     .version_id = 1,
 403     .minimum_version_id = 1,
 404     .fields = (VMStateField[]) {
 405         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 406         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
 407                                             env.nb_tlb,
 408                                             vmstate_tlbemb_entry,
 409                                             ppcemb_tlb_t),
 410         /* 403 protection registers */
 411         VMSTATE_END_OF_LIST()
 412     },
 413     .subsections = (VMStateSubsection []) {
 414         {
 415             .vmsd = &vmstate_pbr403,
 416             .needed = pbr403_needed,
 417         } , {
 418             /* empty */
 419         }
 420     }
 421 };
 422
 423 static const VMStateDescription vmstate_tlbmas_entry = {
 424     .name = "cpu/tlbmas_entry",
 425     .version_id = 1,
 426     .minimum_version_id = 1,
 427     .fields = (VMStateField[]) {
 428         VMSTATE_UINT32(mas8, ppcmas_tlb_t),
 429         VMSTATE_UINT32(mas1, ppcmas_tlb_t),
 430         VMSTATE_UINT64(mas2, ppcmas_tlb_t),
 431         VMSTATE_UINT64(mas7_3, ppcmas_tlb_t),
 432         VMSTATE_END_OF_LIST()
 433     },
 434 };
 435
 436 static bool tlbmas_needed(void *opaque)
 437 {
 438     PowerPCCPU *cpu = opaque;
 439     CPUPPCState *env = &cpu->env;
 440
 441     return env->nb_tlb && (env->tlb_type == TLB_MAS);
 442 }
 443
 444 static const VMStateDescription vmstate_tlbmas = {
 445     .name = "cpu/tlbmas",
 446     .version_id = 1,
 447     .minimum_version_id = 1,
 448     .fields = (VMStateField[]) {
 449         VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
 450         VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
 451                                             env.nb_tlb,
 452                                             vmstate_tlbmas_entry,
 453                                             ppcmas_tlb_t),
 454         VMSTATE_END_OF_LIST()
 455     }
 456 };
 457
 458 const VMStateDescription vmstate_ppc_cpu = {
 459     .name = "cpu",
 460     .version_id = 5,
 461     .minimum_version_id = 5,
 462     .minimum_version_id_old = 4,
 463     .load_state_old = cpu_load_old,
 464     .pre_save = cpu_pre_save,
 465     .post_load = cpu_post_load,
 466     .fields = (VMStateField[]) {
 467         VMSTATE_UNUSED(sizeof(target_ulong)), /* was _EQUAL(env.spr[SPR_PVR]) */
 468
 469         /* User mode architected state */
 470         VMSTATE_UINTTL_ARRAY(env.gpr, PowerPCCPU, 32),
 471 #if !defined(TARGET_PPC64)
 472         VMSTATE_UINTTL_ARRAY(env.gprh, PowerPCCPU, 32),
 473 #endif
 474         VMSTATE_UINT32_ARRAY(env.crf, PowerPCCPU, 8),
 475         VMSTATE_UINTTL(env.nip, PowerPCCPU),
 476
 477         /* SPRs */
 478         VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024),
 479         VMSTATE_UINT64(env.spe_acc, PowerPCCPU),
 480
 481         /* Reservation */
 482         VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU),
 483
 484         /* Supervisor mode architected state */
 485         VMSTATE_UINTTL(env.msr, PowerPCCPU),
 486
 487         /* Internal state */
 488         VMSTATE_UINTTL(env.hflags_nmsr, PowerPCCPU),
 489         /* FIXME: access_type? */
 490
 491         /* Sanity checking */
 492         VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU),
 493         VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU),
 494         VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU),
 495         VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU),
 496         VMSTATE_END_OF_LIST()
 497     },
 498     .subsections = (VMStateSubsection []) {
 499         {
 500             .vmsd = &vmstate_fpu,
 501             .needed = fpu_needed,
 502         } , {
 503             .vmsd = &vmstate_altivec,
 504             .needed = altivec_needed,
 505         } , {
 506             .vmsd = &vmstate_vsx,
 507             .needed = vsx_needed,
 508         } , {
 509             .vmsd = &vmstate_sr,
 510             .needed = sr_needed,
 511         } , {
 512 #ifdef TARGET_PPC64
 513             .vmsd = &vmstate_slb,
 514             .needed = slb_needed,
 515         } , {
 516 #endif /* TARGET_PPC64 */
 517             .vmsd = &vmstate_tlb6xx,
 518             .needed = tlb6xx_needed,
 519         } , {
 520             .vmsd = &vmstate_tlbemb,
 521             .needed = tlbemb_needed,
 522         } , {
 523             .vmsd = &vmstate_tlbmas,
 524             .needed = tlbmas_needed,
 525         } , {
 526             /* empty */
 527         }
 528     }
 529 };