2 * QEMU Hypervisor.framework support for Apple Silicon
4 * Copyright 2020 Alexander Graf <agraf@csgraf.de>
5 * Copyright 2020 Google LLC
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
12 #include "qemu/osdep.h"
13 #include "qemu-common.h"
14 #include "qemu/error-report.h"
16 #include "sysemu/runstate.h"
17 #include "sysemu/hvf.h"
18 #include "sysemu/hvf_int.h"
19 #include "sysemu/hw_accel.h"
22 #include <mach/mach_time.h>
24 #include "exec/address-spaces.h"
26 #include "qemu/main-loop.h"
27 #include "sysemu/cpus.h"
28 #include "arm-powerctl.h"
29 #include "target/arm/cpu.h"
30 #include "target/arm/internals.h"
31 #include "trace/trace-target_arm_hvf.h"
32 #include "migration/vmstate.h"
34 #define HVF_SYSREG(crn, crm, op0, op1, op2) \
35 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2)
36 #define PL1_WRITE_MASK 0x4
38 #define SYSREG_OP0_SHIFT 20
39 #define SYSREG_OP0_MASK 0x3
40 #define SYSREG_OP0(sysreg) ((sysreg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK)
41 #define SYSREG_OP1_SHIFT 14
42 #define SYSREG_OP1_MASK 0x7
43 #define SYSREG_OP1(sysreg) ((sysreg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK)
44 #define SYSREG_CRN_SHIFT 10
45 #define SYSREG_CRN_MASK 0xf
46 #define SYSREG_CRN(sysreg) ((sysreg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK)
47 #define SYSREG_CRM_SHIFT 1
48 #define SYSREG_CRM_MASK 0xf
49 #define SYSREG_CRM(sysreg) ((sysreg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK)
50 #define SYSREG_OP2_SHIFT 17
51 #define SYSREG_OP2_MASK 0x7
52 #define SYSREG_OP2(sysreg) ((sysreg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK)
54 #define SYSREG(op0, op1, crn, crm, op2) \
55 ((op0 << SYSREG_OP0_SHIFT) | \
56 (op1 << SYSREG_OP1_SHIFT) | \
57 (crn << SYSREG_CRN_SHIFT) | \
58 (crm << SYSREG_CRM_SHIFT) | \
59 (op2 << SYSREG_OP2_SHIFT))
61 SYSREG(SYSREG_OP0_MASK, \
66 #define SYSREG_OSLAR_EL1 SYSREG(2, 0, 1, 0, 4)
67 #define SYSREG_OSLSR_EL1 SYSREG(2, 0, 1, 1, 4)
68 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
69 #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1)
70 #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0)
71 #define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0)
72 #define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1)
73 #define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2)
74 #define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2)
75 #define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3)
76 #define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4)
77 #define SYSREG_PMSELR_EL0 SYSREG(3, 3, 9, 12, 5)
78 #define SYSREG_PMCEID0_EL0 SYSREG(3, 3, 9, 12, 6)
79 #define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7)
80 #define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)
81 #define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7)
83 #define WFX_IS_WFE (1 << 0)
85 #define TMR_CTL_ENABLE (1 << 0)
86 #define TMR_CTL_IMASK (1 << 1)
87 #define TMR_CTL_ISTATUS (1 << 2)
89 static void hvf_wfi(CPUState
*cpu
);
91 typedef struct HVFVTimer
{
92 /* Vtimer value during migration and paused state */
96 static HVFVTimer vtimer
;
98 typedef struct ARMHostCPUFeatures
{
102 uint32_t reset_sctlr
;
103 const char *dtb_compatible
;
104 } ARMHostCPUFeatures
;
106 static ARMHostCPUFeatures arm_host_cpu_features
;
108 struct hvf_reg_match
{
113 static const struct hvf_reg_match hvf_reg_match
[] = {
114 { HV_REG_X0
, offsetof(CPUARMState
, xregs
[0]) },
115 { HV_REG_X1
, offsetof(CPUARMState
, xregs
[1]) },
116 { HV_REG_X2
, offsetof(CPUARMState
, xregs
[2]) },
117 { HV_REG_X3
, offsetof(CPUARMState
, xregs
[3]) },
118 { HV_REG_X4
, offsetof(CPUARMState
, xregs
[4]) },
119 { HV_REG_X5
, offsetof(CPUARMState
, xregs
[5]) },
120 { HV_REG_X6
, offsetof(CPUARMState
, xregs
[6]) },
121 { HV_REG_X7
, offsetof(CPUARMState
, xregs
[7]) },
122 { HV_REG_X8
, offsetof(CPUARMState
, xregs
[8]) },
123 { HV_REG_X9
, offsetof(CPUARMState
, xregs
[9]) },
124 { HV_REG_X10
, offsetof(CPUARMState
, xregs
[10]) },
125 { HV_REG_X11
, offsetof(CPUARMState
, xregs
[11]) },
126 { HV_REG_X12
, offsetof(CPUARMState
, xregs
[12]) },
127 { HV_REG_X13
, offsetof(CPUARMState
, xregs
[13]) },
128 { HV_REG_X14
, offsetof(CPUARMState
, xregs
[14]) },
129 { HV_REG_X15
, offsetof(CPUARMState
, xregs
[15]) },
130 { HV_REG_X16
, offsetof(CPUARMState
, xregs
[16]) },
131 { HV_REG_X17
, offsetof(CPUARMState
, xregs
[17]) },
132 { HV_REG_X18
, offsetof(CPUARMState
, xregs
[18]) },
133 { HV_REG_X19
, offsetof(CPUARMState
, xregs
[19]) },
134 { HV_REG_X20
, offsetof(CPUARMState
, xregs
[20]) },
135 { HV_REG_X21
, offsetof(CPUARMState
, xregs
[21]) },
136 { HV_REG_X22
, offsetof(CPUARMState
, xregs
[22]) },
137 { HV_REG_X23
, offsetof(CPUARMState
, xregs
[23]) },
138 { HV_REG_X24
, offsetof(CPUARMState
, xregs
[24]) },
139 { HV_REG_X25
, offsetof(CPUARMState
, xregs
[25]) },
140 { HV_REG_X26
, offsetof(CPUARMState
, xregs
[26]) },
141 { HV_REG_X27
, offsetof(CPUARMState
, xregs
[27]) },
142 { HV_REG_X28
, offsetof(CPUARMState
, xregs
[28]) },
143 { HV_REG_X29
, offsetof(CPUARMState
, xregs
[29]) },
144 { HV_REG_X30
, offsetof(CPUARMState
, xregs
[30]) },
145 { HV_REG_PC
, offsetof(CPUARMState
, pc
) },
148 static const struct hvf_reg_match hvf_fpreg_match
[] = {
149 { HV_SIMD_FP_REG_Q0
, offsetof(CPUARMState
, vfp
.zregs
[0]) },
150 { HV_SIMD_FP_REG_Q1
, offsetof(CPUARMState
, vfp
.zregs
[1]) },
151 { HV_SIMD_FP_REG_Q2
, offsetof(CPUARMState
, vfp
.zregs
[2]) },
152 { HV_SIMD_FP_REG_Q3
, offsetof(CPUARMState
, vfp
.zregs
[3]) },
153 { HV_SIMD_FP_REG_Q4
, offsetof(CPUARMState
, vfp
.zregs
[4]) },
154 { HV_SIMD_FP_REG_Q5
, offsetof(CPUARMState
, vfp
.zregs
[5]) },
155 { HV_SIMD_FP_REG_Q6
, offsetof(CPUARMState
, vfp
.zregs
[6]) },
156 { HV_SIMD_FP_REG_Q7
, offsetof(CPUARMState
, vfp
.zregs
[7]) },
157 { HV_SIMD_FP_REG_Q8
, offsetof(CPUARMState
, vfp
.zregs
[8]) },
158 { HV_SIMD_FP_REG_Q9
, offsetof(CPUARMState
, vfp
.zregs
[9]) },
159 { HV_SIMD_FP_REG_Q10
, offsetof(CPUARMState
, vfp
.zregs
[10]) },
160 { HV_SIMD_FP_REG_Q11
, offsetof(CPUARMState
, vfp
.zregs
[11]) },
161 { HV_SIMD_FP_REG_Q12
, offsetof(CPUARMState
, vfp
.zregs
[12]) },
162 { HV_SIMD_FP_REG_Q13
, offsetof(CPUARMState
, vfp
.zregs
[13]) },
163 { HV_SIMD_FP_REG_Q14
, offsetof(CPUARMState
, vfp
.zregs
[14]) },
164 { HV_SIMD_FP_REG_Q15
, offsetof(CPUARMState
, vfp
.zregs
[15]) },
165 { HV_SIMD_FP_REG_Q16
, offsetof(CPUARMState
, vfp
.zregs
[16]) },
166 { HV_SIMD_FP_REG_Q17
, offsetof(CPUARMState
, vfp
.zregs
[17]) },
167 { HV_SIMD_FP_REG_Q18
, offsetof(CPUARMState
, vfp
.zregs
[18]) },
168 { HV_SIMD_FP_REG_Q19
, offsetof(CPUARMState
, vfp
.zregs
[19]) },
169 { HV_SIMD_FP_REG_Q20
, offsetof(CPUARMState
, vfp
.zregs
[20]) },
170 { HV_SIMD_FP_REG_Q21
, offsetof(CPUARMState
, vfp
.zregs
[21]) },
171 { HV_SIMD_FP_REG_Q22
, offsetof(CPUARMState
, vfp
.zregs
[22]) },
172 { HV_SIMD_FP_REG_Q23
, offsetof(CPUARMState
, vfp
.zregs
[23]) },
173 { HV_SIMD_FP_REG_Q24
, offsetof(CPUARMState
, vfp
.zregs
[24]) },
174 { HV_SIMD_FP_REG_Q25
, offsetof(CPUARMState
, vfp
.zregs
[25]) },
175 { HV_SIMD_FP_REG_Q26
, offsetof(CPUARMState
, vfp
.zregs
[26]) },
176 { HV_SIMD_FP_REG_Q27
, offsetof(CPUARMState
, vfp
.zregs
[27]) },
177 { HV_SIMD_FP_REG_Q28
, offsetof(CPUARMState
, vfp
.zregs
[28]) },
178 { HV_SIMD_FP_REG_Q29
, offsetof(CPUARMState
, vfp
.zregs
[29]) },
179 { HV_SIMD_FP_REG_Q30
, offsetof(CPUARMState
, vfp
.zregs
[30]) },
180 { HV_SIMD_FP_REG_Q31
, offsetof(CPUARMState
, vfp
.zregs
[31]) },
183 struct hvf_sreg_match
{
189 static struct hvf_sreg_match hvf_sreg_match
[] = {
190 { HV_SYS_REG_DBGBVR0_EL1
, HVF_SYSREG(0, 0, 14, 0, 4) },
191 { HV_SYS_REG_DBGBCR0_EL1
, HVF_SYSREG(0, 0, 14, 0, 5) },
192 { HV_SYS_REG_DBGWVR0_EL1
, HVF_SYSREG(0, 0, 14, 0, 6) },
193 { HV_SYS_REG_DBGWCR0_EL1
, HVF_SYSREG(0, 0, 14, 0, 7) },
195 { HV_SYS_REG_DBGBVR1_EL1
, HVF_SYSREG(0, 1, 14, 0, 4) },
196 { HV_SYS_REG_DBGBCR1_EL1
, HVF_SYSREG(0, 1, 14, 0, 5) },
197 { HV_SYS_REG_DBGWVR1_EL1
, HVF_SYSREG(0, 1, 14, 0, 6) },
198 { HV_SYS_REG_DBGWCR1_EL1
, HVF_SYSREG(0, 1, 14, 0, 7) },
200 { HV_SYS_REG_DBGBVR2_EL1
, HVF_SYSREG(0, 2, 14, 0, 4) },
201 { HV_SYS_REG_DBGBCR2_EL1
, HVF_SYSREG(0, 2, 14, 0, 5) },
202 { HV_SYS_REG_DBGWVR2_EL1
, HVF_SYSREG(0, 2, 14, 0, 6) },
203 { HV_SYS_REG_DBGWCR2_EL1
, HVF_SYSREG(0, 2, 14, 0, 7) },
205 { HV_SYS_REG_DBGBVR3_EL1
, HVF_SYSREG(0, 3, 14, 0, 4) },
206 { HV_SYS_REG_DBGBCR3_EL1
, HVF_SYSREG(0, 3, 14, 0, 5) },
207 { HV_SYS_REG_DBGWVR3_EL1
, HVF_SYSREG(0, 3, 14, 0, 6) },
208 { HV_SYS_REG_DBGWCR3_EL1
, HVF_SYSREG(0, 3, 14, 0, 7) },
210 { HV_SYS_REG_DBGBVR4_EL1
, HVF_SYSREG(0, 4, 14, 0, 4) },
211 { HV_SYS_REG_DBGBCR4_EL1
, HVF_SYSREG(0, 4, 14, 0, 5) },
212 { HV_SYS_REG_DBGWVR4_EL1
, HVF_SYSREG(0, 4, 14, 0, 6) },
213 { HV_SYS_REG_DBGWCR4_EL1
, HVF_SYSREG(0, 4, 14, 0, 7) },
215 { HV_SYS_REG_DBGBVR5_EL1
, HVF_SYSREG(0, 5, 14, 0, 4) },
216 { HV_SYS_REG_DBGBCR5_EL1
, HVF_SYSREG(0, 5, 14, 0, 5) },
217 { HV_SYS_REG_DBGWVR5_EL1
, HVF_SYSREG(0, 5, 14, 0, 6) },
218 { HV_SYS_REG_DBGWCR5_EL1
, HVF_SYSREG(0, 5, 14, 0, 7) },
220 { HV_SYS_REG_DBGBVR6_EL1
, HVF_SYSREG(0, 6, 14, 0, 4) },
221 { HV_SYS_REG_DBGBCR6_EL1
, HVF_SYSREG(0, 6, 14, 0, 5) },
222 { HV_SYS_REG_DBGWVR6_EL1
, HVF_SYSREG(0, 6, 14, 0, 6) },
223 { HV_SYS_REG_DBGWCR6_EL1
, HVF_SYSREG(0, 6, 14, 0, 7) },
225 { HV_SYS_REG_DBGBVR7_EL1
, HVF_SYSREG(0, 7, 14, 0, 4) },
226 { HV_SYS_REG_DBGBCR7_EL1
, HVF_SYSREG(0, 7, 14, 0, 5) },
227 { HV_SYS_REG_DBGWVR7_EL1
, HVF_SYSREG(0, 7, 14, 0, 6) },
228 { HV_SYS_REG_DBGWCR7_EL1
, HVF_SYSREG(0, 7, 14, 0, 7) },
230 { HV_SYS_REG_DBGBVR8_EL1
, HVF_SYSREG(0, 8, 14, 0, 4) },
231 { HV_SYS_REG_DBGBCR8_EL1
, HVF_SYSREG(0, 8, 14, 0, 5) },
232 { HV_SYS_REG_DBGWVR8_EL1
, HVF_SYSREG(0, 8, 14, 0, 6) },
233 { HV_SYS_REG_DBGWCR8_EL1
, HVF_SYSREG(0, 8, 14, 0, 7) },
235 { HV_SYS_REG_DBGBVR9_EL1
, HVF_SYSREG(0, 9, 14, 0, 4) },
236 { HV_SYS_REG_DBGBCR9_EL1
, HVF_SYSREG(0, 9, 14, 0, 5) },
237 { HV_SYS_REG_DBGWVR9_EL1
, HVF_SYSREG(0, 9, 14, 0, 6) },
238 { HV_SYS_REG_DBGWCR9_EL1
, HVF_SYSREG(0, 9, 14, 0, 7) },
240 { HV_SYS_REG_DBGBVR10_EL1
, HVF_SYSREG(0, 10, 14, 0, 4) },
241 { HV_SYS_REG_DBGBCR10_EL1
, HVF_SYSREG(0, 10, 14, 0, 5) },
242 { HV_SYS_REG_DBGWVR10_EL1
, HVF_SYSREG(0, 10, 14, 0, 6) },
243 { HV_SYS_REG_DBGWCR10_EL1
, HVF_SYSREG(0, 10, 14, 0, 7) },
245 { HV_SYS_REG_DBGBVR11_EL1
, HVF_SYSREG(0, 11, 14, 0, 4) },
246 { HV_SYS_REG_DBGBCR11_EL1
, HVF_SYSREG(0, 11, 14, 0, 5) },
247 { HV_SYS_REG_DBGWVR11_EL1
, HVF_SYSREG(0, 11, 14, 0, 6) },
248 { HV_SYS_REG_DBGWCR11_EL1
, HVF_SYSREG(0, 11, 14, 0, 7) },
250 { HV_SYS_REG_DBGBVR12_EL1
, HVF_SYSREG(0, 12, 14, 0, 4) },
251 { HV_SYS_REG_DBGBCR12_EL1
, HVF_SYSREG(0, 12, 14, 0, 5) },
252 { HV_SYS_REG_DBGWVR12_EL1
, HVF_SYSREG(0, 12, 14, 0, 6) },
253 { HV_SYS_REG_DBGWCR12_EL1
, HVF_SYSREG(0, 12, 14, 0, 7) },
255 { HV_SYS_REG_DBGBVR13_EL1
, HVF_SYSREG(0, 13, 14, 0, 4) },
256 { HV_SYS_REG_DBGBCR13_EL1
, HVF_SYSREG(0, 13, 14, 0, 5) },
257 { HV_SYS_REG_DBGWVR13_EL1
, HVF_SYSREG(0, 13, 14, 0, 6) },
258 { HV_SYS_REG_DBGWCR13_EL1
, HVF_SYSREG(0, 13, 14, 0, 7) },
260 { HV_SYS_REG_DBGBVR14_EL1
, HVF_SYSREG(0, 14, 14, 0, 4) },
261 { HV_SYS_REG_DBGBCR14_EL1
, HVF_SYSREG(0, 14, 14, 0, 5) },
262 { HV_SYS_REG_DBGWVR14_EL1
, HVF_SYSREG(0, 14, 14, 0, 6) },
263 { HV_SYS_REG_DBGWCR14_EL1
, HVF_SYSREG(0, 14, 14, 0, 7) },
265 { HV_SYS_REG_DBGBVR15_EL1
, HVF_SYSREG(0, 15, 14, 0, 4) },
266 { HV_SYS_REG_DBGBCR15_EL1
, HVF_SYSREG(0, 15, 14, 0, 5) },
267 { HV_SYS_REG_DBGWVR15_EL1
, HVF_SYSREG(0, 15, 14, 0, 6) },
268 { HV_SYS_REG_DBGWCR15_EL1
, HVF_SYSREG(0, 15, 14, 0, 7) },
270 #ifdef SYNC_NO_RAW_REGS
272 * The registers below are manually synced on init because they are
273 * marked as NO_RAW. We still list them to make number space sync easier.
275 { HV_SYS_REG_MDCCINT_EL1
, HVF_SYSREG(0, 2, 2, 0, 0) },
276 { HV_SYS_REG_MIDR_EL1
, HVF_SYSREG(0, 0, 3, 0, 0) },
277 { HV_SYS_REG_MPIDR_EL1
, HVF_SYSREG(0, 0, 3, 0, 5) },
278 { HV_SYS_REG_ID_AA64PFR0_EL1
, HVF_SYSREG(0, 4, 3, 0, 0) },
280 { HV_SYS_REG_ID_AA64PFR1_EL1
, HVF_SYSREG(0, 4, 3, 0, 2) },
281 { HV_SYS_REG_ID_AA64DFR0_EL1
, HVF_SYSREG(0, 5, 3, 0, 0) },
282 { HV_SYS_REG_ID_AA64DFR1_EL1
, HVF_SYSREG(0, 5, 3, 0, 1) },
283 { HV_SYS_REG_ID_AA64ISAR0_EL1
, HVF_SYSREG(0, 6, 3, 0, 0) },
284 { HV_SYS_REG_ID_AA64ISAR1_EL1
, HVF_SYSREG(0, 6, 3, 0, 1) },
286 /* We keep the hardware MMFR0 around. HW limits are there anyway */
287 { HV_SYS_REG_ID_AA64MMFR0_EL1
, HVF_SYSREG(0, 7, 3, 0, 0) },
289 { HV_SYS_REG_ID_AA64MMFR1_EL1
, HVF_SYSREG(0, 7, 3, 0, 1) },
290 { HV_SYS_REG_ID_AA64MMFR2_EL1
, HVF_SYSREG(0, 7, 3, 0, 2) },
292 { HV_SYS_REG_MDSCR_EL1
, HVF_SYSREG(0, 2, 2, 0, 2) },
293 { HV_SYS_REG_SCTLR_EL1
, HVF_SYSREG(1, 0, 3, 0, 0) },
294 { HV_SYS_REG_CPACR_EL1
, HVF_SYSREG(1, 0, 3, 0, 2) },
295 { HV_SYS_REG_TTBR0_EL1
, HVF_SYSREG(2, 0, 3, 0, 0) },
296 { HV_SYS_REG_TTBR1_EL1
, HVF_SYSREG(2, 0, 3, 0, 1) },
297 { HV_SYS_REG_TCR_EL1
, HVF_SYSREG(2, 0, 3, 0, 2) },
299 { HV_SYS_REG_APIAKEYLO_EL1
, HVF_SYSREG(2, 1, 3, 0, 0) },
300 { HV_SYS_REG_APIAKEYHI_EL1
, HVF_SYSREG(2, 1, 3, 0, 1) },
301 { HV_SYS_REG_APIBKEYLO_EL1
, HVF_SYSREG(2, 1, 3, 0, 2) },
302 { HV_SYS_REG_APIBKEYHI_EL1
, HVF_SYSREG(2, 1, 3, 0, 3) },
303 { HV_SYS_REG_APDAKEYLO_EL1
, HVF_SYSREG(2, 2, 3, 0, 0) },
304 { HV_SYS_REG_APDAKEYHI_EL1
, HVF_SYSREG(2, 2, 3, 0, 1) },
305 { HV_SYS_REG_APDBKEYLO_EL1
, HVF_SYSREG(2, 2, 3, 0, 2) },
306 { HV_SYS_REG_APDBKEYHI_EL1
, HVF_SYSREG(2, 2, 3, 0, 3) },
307 { HV_SYS_REG_APGAKEYLO_EL1
, HVF_SYSREG(2, 3, 3, 0, 0) },
308 { HV_SYS_REG_APGAKEYHI_EL1
, HVF_SYSREG(2, 3, 3, 0, 1) },
310 { HV_SYS_REG_SPSR_EL1
, HVF_SYSREG(4, 0, 3, 0, 0) },
311 { HV_SYS_REG_ELR_EL1
, HVF_SYSREG(4, 0, 3, 0, 1) },
312 { HV_SYS_REG_SP_EL0
, HVF_SYSREG(4, 1, 3, 0, 0) },
313 { HV_SYS_REG_AFSR0_EL1
, HVF_SYSREG(5, 1, 3, 0, 0) },
314 { HV_SYS_REG_AFSR1_EL1
, HVF_SYSREG(5, 1, 3, 0, 1) },
315 { HV_SYS_REG_ESR_EL1
, HVF_SYSREG(5, 2, 3, 0, 0) },
316 { HV_SYS_REG_FAR_EL1
, HVF_SYSREG(6, 0, 3, 0, 0) },
317 { HV_SYS_REG_PAR_EL1
, HVF_SYSREG(7, 4, 3, 0, 0) },
318 { HV_SYS_REG_MAIR_EL1
, HVF_SYSREG(10, 2, 3, 0, 0) },
319 { HV_SYS_REG_AMAIR_EL1
, HVF_SYSREG(10, 3, 3, 0, 0) },
320 { HV_SYS_REG_VBAR_EL1
, HVF_SYSREG(12, 0, 3, 0, 0) },
321 { HV_SYS_REG_CONTEXTIDR_EL1
, HVF_SYSREG(13, 0, 3, 0, 1) },
322 { HV_SYS_REG_TPIDR_EL1
, HVF_SYSREG(13, 0, 3, 0, 4) },
323 { HV_SYS_REG_CNTKCTL_EL1
, HVF_SYSREG(14, 1, 3, 0, 0) },
324 { HV_SYS_REG_CSSELR_EL1
, HVF_SYSREG(0, 0, 3, 2, 0) },
325 { HV_SYS_REG_TPIDR_EL0
, HVF_SYSREG(13, 0, 3, 3, 2) },
326 { HV_SYS_REG_TPIDRRO_EL0
, HVF_SYSREG(13, 0, 3, 3, 3) },
327 { HV_SYS_REG_CNTV_CTL_EL0
, HVF_SYSREG(14, 3, 3, 3, 1) },
328 { HV_SYS_REG_CNTV_CVAL_EL0
, HVF_SYSREG(14, 3, 3, 3, 2) },
329 { HV_SYS_REG_SP_EL1
, HVF_SYSREG(4, 1, 3, 4, 0) },
332 int hvf_get_registers(CPUState
*cpu
)
334 ARMCPU
*arm_cpu
= ARM_CPU(cpu
);
335 CPUARMState
*env
= &arm_cpu
->env
;
338 hv_simd_fp_uchar16_t fpval
;
341 for (i
= 0; i
< ARRAY_SIZE(hvf_reg_match
); i
++) {
342 ret
= hv_vcpu_get_reg(cpu
->hvf
->fd
, hvf_reg_match
[i
].reg
, &val
);
343 *(uint64_t *)((void *)env
+ hvf_reg_match
[i
].offset
) = val
;
347 for (i
= 0; i
< ARRAY_SIZE(hvf_fpreg_match
); i
++) {
348 ret
= hv_vcpu_get_simd_fp_reg(cpu
->hvf
->fd
, hvf_fpreg_match
[i
].reg
,
350 memcpy((void *)env
+ hvf_fpreg_match
[i
].offset
, &fpval
, sizeof(fpval
));
355 ret
= hv_vcpu_get_reg(cpu
->hvf
->fd
, HV_REG_FPCR
, &val
);
357 vfp_set_fpcr(env
, val
);
360 ret
= hv_vcpu_get_reg(cpu
->hvf
->fd
, HV_REG_FPSR
, &val
);
362 vfp_set_fpsr(env
, val
);
364 ret
= hv_vcpu_get_reg(cpu
->hvf
->fd
, HV_REG_CPSR
, &val
);
366 pstate_write(env
, val
);
368 for (i
= 0; i
< ARRAY_SIZE(hvf_sreg_match
); i
++) {
369 if (hvf_sreg_match
[i
].cp_idx
== -1) {
373 ret
= hv_vcpu_get_sys_reg(cpu
->hvf
->fd
, hvf_sreg_match
[i
].reg
, &val
);
376 arm_cpu
->cpreg_values
[hvf_sreg_match
[i
].cp_idx
] = val
;
378 assert(write_list_to_cpustate(arm_cpu
));
380 aarch64_restore_sp(env
, arm_current_el(env
));
385 int hvf_put_registers(CPUState
*cpu
)
387 ARMCPU
*arm_cpu
= ARM_CPU(cpu
);
388 CPUARMState
*env
= &arm_cpu
->env
;
391 hv_simd_fp_uchar16_t fpval
;
394 for (i
= 0; i
< ARRAY_SIZE(hvf_reg_match
); i
++) {
395 val
= *(uint64_t *)((void *)env
+ hvf_reg_match
[i
].offset
);
396 ret
= hv_vcpu_set_reg(cpu
->hvf
->fd
, hvf_reg_match
[i
].reg
, val
);
400 for (i
= 0; i
< ARRAY_SIZE(hvf_fpreg_match
); i
++) {
401 memcpy(&fpval
, (void *)env
+ hvf_fpreg_match
[i
].offset
, sizeof(fpval
));
402 ret
= hv_vcpu_set_simd_fp_reg(cpu
->hvf
->fd
, hvf_fpreg_match
[i
].reg
,
407 ret
= hv_vcpu_set_reg(cpu
->hvf
->fd
, HV_REG_FPCR
, vfp_get_fpcr(env
));
410 ret
= hv_vcpu_set_reg(cpu
->hvf
->fd
, HV_REG_FPSR
, vfp_get_fpsr(env
));
413 ret
= hv_vcpu_set_reg(cpu
->hvf
->fd
, HV_REG_CPSR
, pstate_read(env
));
416 aarch64_save_sp(env
, arm_current_el(env
));
418 assert(write_cpustate_to_list(arm_cpu
, false));
419 for (i
= 0; i
< ARRAY_SIZE(hvf_sreg_match
); i
++) {
420 if (hvf_sreg_match
[i
].cp_idx
== -1) {
424 val
= arm_cpu
->cpreg_values
[hvf_sreg_match
[i
].cp_idx
];
425 ret
= hv_vcpu_set_sys_reg(cpu
->hvf
->fd
, hvf_sreg_match
[i
].reg
, val
);
429 ret
= hv_vcpu_set_vtimer_offset(cpu
->hvf
->fd
, hvf_state
->vtimer_offset
);
435 static void flush_cpu_state(CPUState
*cpu
)
437 if (cpu
->vcpu_dirty
) {
438 hvf_put_registers(cpu
);
439 cpu
->vcpu_dirty
= false;
443 static void hvf_set_reg(CPUState
*cpu
, int rt
, uint64_t val
)
447 flush_cpu_state(cpu
);
450 r
= hv_vcpu_set_reg(cpu
->hvf
->fd
, HV_REG_X0
+ rt
, val
);
455 static uint64_t hvf_get_reg(CPUState
*cpu
, int rt
)
460 flush_cpu_state(cpu
);
463 r
= hv_vcpu_get_reg(cpu
->hvf
->fd
, HV_REG_X0
+ rt
, &val
);
470 static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures
*ahcf
)
472 ARMISARegisters host_isar
= {};
473 const struct isar_regs
{
477 { HV_SYS_REG_ID_AA64PFR0_EL1
, &host_isar
.id_aa64pfr0
},
478 { HV_SYS_REG_ID_AA64PFR1_EL1
, &host_isar
.id_aa64pfr1
},
479 { HV_SYS_REG_ID_AA64DFR0_EL1
, &host_isar
.id_aa64dfr0
},
480 { HV_SYS_REG_ID_AA64DFR1_EL1
, &host_isar
.id_aa64dfr1
},
481 { HV_SYS_REG_ID_AA64ISAR0_EL1
, &host_isar
.id_aa64isar0
},
482 { HV_SYS_REG_ID_AA64ISAR1_EL1
, &host_isar
.id_aa64isar1
},
483 { HV_SYS_REG_ID_AA64MMFR0_EL1
, &host_isar
.id_aa64mmfr0
},
484 { HV_SYS_REG_ID_AA64MMFR1_EL1
, &host_isar
.id_aa64mmfr1
},
485 { HV_SYS_REG_ID_AA64MMFR2_EL1
, &host_isar
.id_aa64mmfr2
},
488 hv_return_t r
= HV_SUCCESS
;
489 hv_vcpu_exit_t
*exit
;
492 ahcf
->dtb_compatible
= "arm,arm-v8";
493 ahcf
->features
= (1ULL << ARM_FEATURE_V8
) |
494 (1ULL << ARM_FEATURE_NEON
) |
495 (1ULL << ARM_FEATURE_AARCH64
) |
496 (1ULL << ARM_FEATURE_PMU
) |
497 (1ULL << ARM_FEATURE_GENERIC_TIMER
);
499 /* We set up a small vcpu to extract host registers */
501 if (hv_vcpu_create(&fd
, &exit
, NULL
) != HV_SUCCESS
) {
505 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
506 r
|= hv_vcpu_get_sys_reg(fd
, regs
[i
].reg
, regs
[i
].val
);
508 r
|= hv_vcpu_get_sys_reg(fd
, HV_SYS_REG_MIDR_EL1
, &ahcf
->midr
);
509 r
|= hv_vcpu_destroy(fd
);
511 ahcf
->isar
= host_isar
;
514 * A scratch vCPU returns SCTLR 0, so let's fill our default with the M1
515 * boot SCTLR from https://github.com/AsahiLinux/m1n1/issues/97
517 ahcf
->reset_sctlr
= 0x30100180;
519 * SPAN is disabled by default when SCTLR.SPAN=1. To improve compatibility,
520 * let's disable it on boot and then allow guest software to turn it on by
523 ahcf
->reset_sctlr
|= 0x00800000;
525 /* Make sure we don't advertise AArch32 support for EL0/EL1 */
526 if ((host_isar
.id_aa64pfr0
& 0xff) != 0x11) {
530 return r
== HV_SUCCESS
;
533 void hvf_arm_set_cpu_features_from_host(ARMCPU
*cpu
)
535 if (!arm_host_cpu_features
.dtb_compatible
) {
536 if (!hvf_enabled() ||
537 !hvf_arm_get_host_cpu_features(&arm_host_cpu_features
)) {
539 * We can't report this error yet, so flag that we need to
540 * in arm_cpu_realizefn().
542 cpu
->host_cpu_probe_failed
= true;
547 cpu
->dtb_compatible
= arm_host_cpu_features
.dtb_compatible
;
548 cpu
->isar
= arm_host_cpu_features
.isar
;
549 cpu
->env
.features
= arm_host_cpu_features
.features
;
550 cpu
->midr
= arm_host_cpu_features
.midr
;
551 cpu
->reset_sctlr
= arm_host_cpu_features
.reset_sctlr
;
554 void hvf_arch_vcpu_destroy(CPUState
*cpu
)
558 int hvf_arch_init_vcpu(CPUState
*cpu
)
560 ARMCPU
*arm_cpu
= ARM_CPU(cpu
);
561 CPUARMState
*env
= &arm_cpu
->env
;
562 uint32_t sregs_match_len
= ARRAY_SIZE(hvf_sreg_match
);
563 uint32_t sregs_cnt
= 0;
569 asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu
->gt_cntfrq_hz
));
571 /* Allocate enough space for our sysreg sync */
572 arm_cpu
->cpreg_indexes
= g_renew(uint64_t, arm_cpu
->cpreg_indexes
,
574 arm_cpu
->cpreg_values
= g_renew(uint64_t, arm_cpu
->cpreg_values
,
576 arm_cpu
->cpreg_vmstate_indexes
= g_renew(uint64_t,
577 arm_cpu
->cpreg_vmstate_indexes
,
579 arm_cpu
->cpreg_vmstate_values
= g_renew(uint64_t,
580 arm_cpu
->cpreg_vmstate_values
,
583 memset(arm_cpu
->cpreg_values
, 0, sregs_match_len
* sizeof(uint64_t));
585 /* Populate cp list for all known sysregs */
586 for (i
= 0; i
< sregs_match_len
; i
++) {
587 const ARMCPRegInfo
*ri
;
588 uint32_t key
= hvf_sreg_match
[i
].key
;
590 ri
= get_arm_cp_reginfo(arm_cpu
->cp_regs
, key
);
592 assert(!(ri
->type
& ARM_CP_NO_RAW
));
593 hvf_sreg_match
[i
].cp_idx
= sregs_cnt
;
594 arm_cpu
->cpreg_indexes
[sregs_cnt
++] = cpreg_to_kvm_id(key
);
596 hvf_sreg_match
[i
].cp_idx
= -1;
599 arm_cpu
->cpreg_array_len
= sregs_cnt
;
600 arm_cpu
->cpreg_vmstate_array_len
= sregs_cnt
;
602 assert(write_cpustate_to_list(arm_cpu
, false));
604 /* Set CP_NO_RAW system registers on init */
605 ret
= hv_vcpu_set_sys_reg(cpu
->hvf
->fd
, HV_SYS_REG_MIDR_EL1
,
609 ret
= hv_vcpu_set_sys_reg(cpu
->hvf
->fd
, HV_SYS_REG_MPIDR_EL1
,
610 arm_cpu
->mp_affinity
);
613 ret
= hv_vcpu_get_sys_reg(cpu
->hvf
->fd
, HV_SYS_REG_ID_AA64PFR0_EL1
, &pfr
);
615 pfr
|= env
->gicv3state
? (1 << 24) : 0;
616 ret
= hv_vcpu_set_sys_reg(cpu
->hvf
->fd
, HV_SYS_REG_ID_AA64PFR0_EL1
, pfr
);
619 /* We're limited to underlying hardware caps, override internal versions */
620 ret
= hv_vcpu_get_sys_reg(cpu
->hvf
->fd
, HV_SYS_REG_ID_AA64MMFR0_EL1
,
621 &arm_cpu
->isar
.id_aa64mmfr0
);
627 void hvf_kick_vcpu_thread(CPUState
*cpu
)
629 cpus_kick_thread(cpu
);
630 hv_vcpus_exit(&cpu
->hvf
->fd
, 1);
633 static void hvf_raise_exception(CPUState
*cpu
, uint32_t excp
,
636 ARMCPU
*arm_cpu
= ARM_CPU(cpu
);
637 CPUARMState
*env
= &arm_cpu
->env
;
639 cpu
->exception_index
= excp
;
640 env
->exception
.target_el
= 1;
641 env
->exception
.syndrome
= syndrome
;
643 arm_cpu_do_interrupt(cpu
);
646 static void hvf_psci_cpu_off(ARMCPU
*arm_cpu
)
648 int32_t ret
= arm_set_cpu_off(arm_cpu
->mp_affinity
);
649 assert(ret
== QEMU_ARM_POWERCTL_RET_SUCCESS
);
653 * Handle a PSCI call.
655 * Returns 0 on success
656 * -1 when the PSCI call is unknown,
658 static bool hvf_handle_psci_call(CPUState
*cpu
)
660 ARMCPU
*arm_cpu
= ARM_CPU(cpu
);
661 CPUARMState
*env
= &arm_cpu
->env
;
662 uint64_t param
[4] = {
668 uint64_t context_id
, mpidr
;
669 bool target_aarch64
= true;
670 CPUState
*target_cpu_state
;
676 trace_hvf_psci_call(param
[0], param
[1], param
[2], param
[3],
677 arm_cpu
->mp_affinity
);
680 case QEMU_PSCI_0_2_FN_PSCI_VERSION
:
681 ret
= QEMU_PSCI_0_2_RET_VERSION_0_2
;
683 case QEMU_PSCI_0_2_FN_MIGRATE_INFO_TYPE
:
684 ret
= QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED
; /* No trusted OS */
686 case QEMU_PSCI_0_2_FN_AFFINITY_INFO
:
687 case QEMU_PSCI_0_2_FN64_AFFINITY_INFO
:
692 target_cpu_state
= arm_get_cpu_by_id(mpidr
);
693 if (!target_cpu_state
) {
694 ret
= QEMU_PSCI_RET_INVALID_PARAMS
;
697 target_cpu
= ARM_CPU(target_cpu_state
);
699 ret
= target_cpu
->power_state
;
702 /* Everything above affinity level 0 is always on. */
706 case QEMU_PSCI_0_2_FN_SYSTEM_RESET
:
707 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
709 * QEMU reset and shutdown are async requests, but PSCI
710 * mandates that we never return from the reset/shutdown
711 * call, so power the CPU off now so it doesn't execute
714 hvf_psci_cpu_off(arm_cpu
);
716 case QEMU_PSCI_0_2_FN_SYSTEM_OFF
:
717 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
718 hvf_psci_cpu_off(arm_cpu
);
720 case QEMU_PSCI_0_1_FN_CPU_ON
:
721 case QEMU_PSCI_0_2_FN_CPU_ON
:
722 case QEMU_PSCI_0_2_FN64_CPU_ON
:
725 context_id
= param
[3];
726 ret
= arm_set_cpu_on(mpidr
, entry
, context_id
,
727 target_el
, target_aarch64
);
729 case QEMU_PSCI_0_1_FN_CPU_OFF
:
730 case QEMU_PSCI_0_2_FN_CPU_OFF
:
731 hvf_psci_cpu_off(arm_cpu
);
733 case QEMU_PSCI_0_1_FN_CPU_SUSPEND
:
734 case QEMU_PSCI_0_2_FN_CPU_SUSPEND
:
735 case QEMU_PSCI_0_2_FN64_CPU_SUSPEND
:
736 /* Affinity levels are not supported in QEMU */
737 if (param
[1] & 0xfffe0000) {
738 ret
= QEMU_PSCI_RET_INVALID_PARAMS
;
741 /* Powerdown is not supported, we always go into WFI */
745 case QEMU_PSCI_0_1_FN_MIGRATE
:
746 case QEMU_PSCI_0_2_FN_MIGRATE
:
747 ret
= QEMU_PSCI_RET_NOT_SUPPORTED
;
757 static int hvf_sysreg_read(CPUState
*cpu
, uint32_t reg
, uint32_t rt
)
759 ARMCPU
*arm_cpu
= ARM_CPU(cpu
);
760 CPUARMState
*env
= &arm_cpu
->env
;
764 case SYSREG_CNTPCT_EL0
:
765 val
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) /
766 gt_cntfrq_period_ns(arm_cpu
);
768 case SYSREG_PMCR_EL0
:
769 val
= env
->cp15
.c9_pmcr
;
771 case SYSREG_PMCCNTR_EL0
:
773 val
= env
->cp15
.c15_ccnt
;
776 case SYSREG_PMCNTENCLR_EL0
:
777 val
= env
->cp15
.c9_pmcnten
;
779 case SYSREG_PMOVSCLR_EL0
:
780 val
= env
->cp15
.c9_pmovsr
;
782 case SYSREG_PMSELR_EL0
:
783 val
= env
->cp15
.c9_pmselr
;
785 case SYSREG_PMINTENCLR_EL1
:
786 val
= env
->cp15
.c9_pminten
;
788 case SYSREG_PMCCFILTR_EL0
:
789 val
= env
->cp15
.pmccfiltr_el0
;
791 case SYSREG_PMCNTENSET_EL0
:
792 val
= env
->cp15
.c9_pmcnten
;
794 case SYSREG_PMUSERENR_EL0
:
795 val
= env
->cp15
.c9_pmuserenr
;
797 case SYSREG_PMCEID0_EL0
:
798 case SYSREG_PMCEID1_EL0
:
799 /* We can't really count anything yet, declare all events invalid */
802 case SYSREG_OSLSR_EL1
:
803 val
= env
->cp15
.oslsr_el1
;
805 case SYSREG_OSDLR_EL1
:
809 cpu_synchronize_state(cpu
);
810 trace_hvf_unhandled_sysreg_read(env
->pc
, reg
,
816 hvf_raise_exception(cpu
, EXCP_UDEF
, syn_uncategorized());
820 trace_hvf_sysreg_read(reg
,
827 hvf_set_reg(cpu
, rt
, val
);
832 static void pmu_update_irq(CPUARMState
*env
)
834 ARMCPU
*cpu
= env_archcpu(env
);
835 qemu_set_irq(cpu
->pmu_interrupt
, (env
->cp15
.c9_pmcr
& PMCRE
) &&
836 (env
->cp15
.c9_pminten
& env
->cp15
.c9_pmovsr
));
839 static bool pmu_event_supported(uint16_t number
)
844 /* Returns true if the counter (pass 31 for PMCCNTR) should count events using
845 * the current EL, security state, and register configuration.
847 static bool pmu_counter_enabled(CPUARMState
*env
, uint8_t counter
)
850 bool enabled
, filtered
= true;
851 int el
= arm_current_el(env
);
853 enabled
= (env
->cp15
.c9_pmcr
& PMCRE
) &&
854 (env
->cp15
.c9_pmcnten
& (1 << counter
));
857 filter
= env
->cp15
.pmccfiltr_el0
;
859 filter
= env
->cp15
.c14_pmevtyper
[counter
];
863 filtered
= filter
& PMXEVTYPER_U
;
864 } else if (el
== 1) {
865 filtered
= filter
& PMXEVTYPER_P
;
870 * If not checking PMCCNTR, ensure the counter is setup to an event we
873 uint16_t event
= filter
& PMXEVTYPER_EVTCOUNT
;
874 if (!pmu_event_supported(event
)) {
879 return enabled
&& !filtered
;
882 static void pmswinc_write(CPUARMState
*env
, uint64_t value
)
885 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
886 /* Increment a counter's count iff: */
887 if ((value
& (1 << i
)) && /* counter's bit is set */
888 /* counter is enabled and not filtered */
889 pmu_counter_enabled(env
, i
) &&
890 /* counter is SW_INCR */
891 (env
->cp15
.c14_pmevtyper
[i
] & PMXEVTYPER_EVTCOUNT
) == 0x0) {
893 * Detect if this write causes an overflow since we can't predict
894 * PMSWINC overflows like we can for other events
896 uint32_t new_pmswinc
= env
->cp15
.c14_pmevcntr
[i
] + 1;
898 if (env
->cp15
.c14_pmevcntr
[i
] & ~new_pmswinc
& INT32_MIN
) {
899 env
->cp15
.c9_pmovsr
|= (1 << i
);
903 env
->cp15
.c14_pmevcntr
[i
] = new_pmswinc
;
908 static int hvf_sysreg_write(CPUState
*cpu
, uint32_t reg
, uint64_t val
)
910 ARMCPU
*arm_cpu
= ARM_CPU(cpu
);
911 CPUARMState
*env
= &arm_cpu
->env
;
913 trace_hvf_sysreg_write(reg
,
922 case SYSREG_PMCCNTR_EL0
:
924 env
->cp15
.c15_ccnt
= val
;
927 case SYSREG_PMCR_EL0
:
931 /* The counter has been reset */
932 env
->cp15
.c15_ccnt
= 0;
937 for (i
= 0; i
< pmu_num_counters(env
); i
++) {
938 env
->cp15
.c14_pmevcntr
[i
] = 0;
942 env
->cp15
.c9_pmcr
&= ~PMCR_WRITEABLE_MASK
;
943 env
->cp15
.c9_pmcr
|= (val
& PMCR_WRITEABLE_MASK
);
947 case SYSREG_PMUSERENR_EL0
:
948 env
->cp15
.c9_pmuserenr
= val
& 0xf;
950 case SYSREG_PMCNTENSET_EL0
:
951 env
->cp15
.c9_pmcnten
|= (val
& pmu_counter_mask(env
));
953 case SYSREG_PMCNTENCLR_EL0
:
954 env
->cp15
.c9_pmcnten
&= ~(val
& pmu_counter_mask(env
));
956 case SYSREG_PMINTENCLR_EL1
:
958 env
->cp15
.c9_pminten
|= val
;
961 case SYSREG_PMOVSCLR_EL0
:
963 env
->cp15
.c9_pmovsr
&= ~val
;
966 case SYSREG_PMSWINC_EL0
:
968 pmswinc_write(env
, val
);
971 case SYSREG_PMSELR_EL0
:
972 env
->cp15
.c9_pmselr
= val
& 0x1f;
974 case SYSREG_PMCCFILTR_EL0
:
976 env
->cp15
.pmccfiltr_el0
= val
& PMCCFILTR_EL0
;
979 case SYSREG_OSLAR_EL1
:
980 env
->cp15
.oslsr_el1
= val
& 1;
982 case SYSREG_OSDLR_EL1
:
986 cpu_synchronize_state(cpu
);
987 trace_hvf_unhandled_sysreg_write(env
->pc
, reg
,
993 hvf_raise_exception(cpu
, EXCP_UDEF
, syn_uncategorized());
1000 static int hvf_inject_interrupts(CPUState
*cpu
)
1002 if (cpu
->interrupt_request
& CPU_INTERRUPT_FIQ
) {
1003 trace_hvf_inject_fiq();
1004 hv_vcpu_set_pending_interrupt(cpu
->hvf
->fd
, HV_INTERRUPT_TYPE_FIQ
,
1008 if (cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) {
1009 trace_hvf_inject_irq();
1010 hv_vcpu_set_pending_interrupt(cpu
->hvf
->fd
, HV_INTERRUPT_TYPE_IRQ
,
1017 static uint64_t hvf_vtimer_val_raw(void)
1020 * mach_absolute_time() returns the vtimer value without the VM
1021 * offset that we define. Add our own offset on top.
1023 return mach_absolute_time() - hvf_state
->vtimer_offset
;
1026 static uint64_t hvf_vtimer_val(void)
1028 if (!runstate_is_running()) {
1029 /* VM is paused, the vtimer value is in vtimer.vtimer_val */
1030 return vtimer
.vtimer_val
;
1033 return hvf_vtimer_val_raw();
1036 static void hvf_wait_for_ipi(CPUState
*cpu
, struct timespec
*ts
)
1039 * Use pselect to sleep so that other threads can IPI us while we're
1042 qatomic_mb_set(&cpu
->thread_kicked
, false);
1043 qemu_mutex_unlock_iothread();
1044 pselect(0, 0, 0, 0, ts
, &cpu
->hvf
->unblock_ipi_mask
);
1045 qemu_mutex_lock_iothread();
1048 static void hvf_wfi(CPUState
*cpu
)
1050 ARMCPU
*arm_cpu
= ARM_CPU(cpu
);
1055 int64_t ticks_to_sleep
;
1060 if (cpu
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_FIQ
)) {
1061 /* Interrupt pending, no need to wait */
1065 r
= hv_vcpu_get_sys_reg(cpu
->hvf
->fd
, HV_SYS_REG_CNTV_CTL_EL0
, &ctl
);
1068 if (!(ctl
& 1) || (ctl
& 2)) {
1069 /* Timer disabled or masked, just wait for an IPI. */
1070 hvf_wait_for_ipi(cpu
, NULL
);
1074 r
= hv_vcpu_get_sys_reg(cpu
->hvf
->fd
, HV_SYS_REG_CNTV_CVAL_EL0
, &cval
);
1077 ticks_to_sleep
= cval
- hvf_vtimer_val();
1078 if (ticks_to_sleep
< 0) {
1082 cntfrq
= gt_cntfrq_period_ns(arm_cpu
);
1083 seconds
= muldiv64(ticks_to_sleep
, cntfrq
, NANOSECONDS_PER_SECOND
);
1084 ticks_to_sleep
-= muldiv64(seconds
, NANOSECONDS_PER_SECOND
, cntfrq
);
1085 nanos
= ticks_to_sleep
* cntfrq
;
1088 * Don't sleep for less than the time a context switch would take,
1089 * so that we can satisfy fast timer requests on the same CPU.
1090 * Measurements on M1 show the sweet spot to be ~2ms.
1092 if (!seconds
&& nanos
< (2 * SCALE_MS
)) {
1096 ts
= (struct timespec
) { seconds
, nanos
};
1097 hvf_wait_for_ipi(cpu
, &ts
);
1100 static void hvf_sync_vtimer(CPUState
*cpu
)
1102 ARMCPU
*arm_cpu
= ARM_CPU(cpu
);
1107 if (!cpu
->hvf
->vtimer_masked
) {
1108 /* We will get notified on vtimer changes by hvf, nothing to do */
1112 r
= hv_vcpu_get_sys_reg(cpu
->hvf
->fd
, HV_SYS_REG_CNTV_CTL_EL0
, &ctl
);
1115 irq_state
= (ctl
& (TMR_CTL_ENABLE
| TMR_CTL_IMASK
| TMR_CTL_ISTATUS
)) ==
1116 (TMR_CTL_ENABLE
| TMR_CTL_ISTATUS
);
1117 qemu_set_irq(arm_cpu
->gt_timer_outputs
[GTIMER_VIRT
], irq_state
);
1120 /* Timer no longer asserting, we can unmask it */
1121 hv_vcpu_set_vtimer_mask(cpu
->hvf
->fd
, false);
1122 cpu
->hvf
->vtimer_masked
= false;
1126 int hvf_vcpu_exec(CPUState
*cpu
)
1128 ARMCPU
*arm_cpu
= ARM_CPU(cpu
);
1129 CPUARMState
*env
= &arm_cpu
->env
;
1130 hv_vcpu_exit_t
*hvf_exit
= cpu
->hvf
->exit
;
1132 bool advance_pc
= false;
1134 if (hvf_inject_interrupts(cpu
)) {
1135 return EXCP_INTERRUPT
;
1142 flush_cpu_state(cpu
);
1144 qemu_mutex_unlock_iothread();
1145 assert_hvf_ok(hv_vcpu_run(cpu
->hvf
->fd
));
1148 uint64_t exit_reason
= hvf_exit
->reason
;
1149 uint64_t syndrome
= hvf_exit
->exception
.syndrome
;
1150 uint32_t ec
= syn_get_ec(syndrome
);
1152 qemu_mutex_lock_iothread();
1153 switch (exit_reason
) {
1154 case HV_EXIT_REASON_EXCEPTION
:
1155 /* This is the main one, handle below. */
1157 case HV_EXIT_REASON_VTIMER_ACTIVATED
:
1158 qemu_set_irq(arm_cpu
->gt_timer_outputs
[GTIMER_VIRT
], 1);
1159 cpu
->hvf
->vtimer_masked
= true;
1161 case HV_EXIT_REASON_CANCELED
:
1162 /* we got kicked, no exit to process */
1168 hvf_sync_vtimer(cpu
);
1171 case EC_DATAABORT
: {
1172 bool isv
= syndrome
& ARM_EL_ISV
;
1173 bool iswrite
= (syndrome
>> 6) & 1;
1174 bool s1ptw
= (syndrome
>> 7) & 1;
1175 uint32_t sas
= (syndrome
>> 22) & 3;
1176 uint32_t len
= 1 << sas
;
1177 uint32_t srt
= (syndrome
>> 16) & 0x1f;
1178 uint32_t cm
= (syndrome
>> 8) & 0x1;
1181 trace_hvf_data_abort(env
->pc
, hvf_exit
->exception
.virtual_address
,
1182 hvf_exit
->exception
.physical_address
, isv
,
1183 iswrite
, s1ptw
, len
, srt
);
1186 /* We don't cache MMIO regions */
1194 val
= hvf_get_reg(cpu
, srt
);
1195 address_space_write(&address_space_memory
,
1196 hvf_exit
->exception
.physical_address
,
1197 MEMTXATTRS_UNSPECIFIED
, &val
, len
);
1199 address_space_read(&address_space_memory
,
1200 hvf_exit
->exception
.physical_address
,
1201 MEMTXATTRS_UNSPECIFIED
, &val
, len
);
1202 hvf_set_reg(cpu
, srt
, val
);
1208 case EC_SYSTEMREGISTERTRAP
: {
1209 bool isread
= (syndrome
>> 0) & 1;
1210 uint32_t rt
= (syndrome
>> 5) & 0x1f;
1211 uint32_t reg
= syndrome
& SYSREG_MASK
;
1216 ret
= hvf_sysreg_read(cpu
, reg
, rt
);
1218 val
= hvf_get_reg(cpu
, rt
);
1219 ret
= hvf_sysreg_write(cpu
, reg
, val
);
1227 if (!(syndrome
& WFX_IS_WFE
)) {
1232 cpu_synchronize_state(cpu
);
1233 if (arm_cpu
->psci_conduit
== QEMU_PSCI_CONDUIT_HVC
) {
1234 if (!hvf_handle_psci_call(cpu
)) {
1235 trace_hvf_unknown_hvc(env
->xregs
[0]);
1236 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
1240 trace_hvf_unknown_hvc(env
->xregs
[0]);
1241 hvf_raise_exception(cpu
, EXCP_UDEF
, syn_uncategorized());
1245 cpu_synchronize_state(cpu
);
1246 if (arm_cpu
->psci_conduit
== QEMU_PSCI_CONDUIT_SMC
) {
1249 if (!hvf_handle_psci_call(cpu
)) {
1250 trace_hvf_unknown_smc(env
->xregs
[0]);
1251 /* SMCCC 1.3 section 5.2 says every unknown SMCCC call returns -1 */
1255 trace_hvf_unknown_smc(env
->xregs
[0]);
1256 hvf_raise_exception(cpu
, EXCP_UDEF
, syn_uncategorized());
1260 cpu_synchronize_state(cpu
);
1261 trace_hvf_exit(syndrome
, ec
, env
->pc
);
1262 error_report("0x%llx: unhandled exception ec=0x%x", env
->pc
, ec
);
1268 flush_cpu_state(cpu
);
1270 r
= hv_vcpu_get_reg(cpu
->hvf
->fd
, HV_REG_PC
, &pc
);
1273 r
= hv_vcpu_set_reg(cpu
->hvf
->fd
, HV_REG_PC
, pc
);
1280 static const VMStateDescription vmstate_hvf_vtimer
= {
1281 .name
= "hvf-vtimer",
1283 .minimum_version_id
= 1,
1284 .fields
= (VMStateField
[]) {
1285 VMSTATE_UINT64(vtimer_val
, HVFVTimer
),
1286 VMSTATE_END_OF_LIST()
1290 static void hvf_vm_state_change(void *opaque
, bool running
, RunState state
)
1292 HVFVTimer
*s
= opaque
;
1295 /* Update vtimer offset on all CPUs */
1296 hvf_state
->vtimer_offset
= mach_absolute_time() - s
->vtimer_val
;
1297 cpu_synchronize_all_states();
1299 /* Remember vtimer value on every pause */
1300 s
->vtimer_val
= hvf_vtimer_val_raw();
1304 int hvf_arch_init(void)
1306 hvf_state
->vtimer_offset
= mach_absolute_time();
1307 vmstate_register(NULL
, 0, &vmstate_hvf_vtimer
, &vtimer
);
1308 qemu_add_vm_change_state_handler(hvf_vm_state_change
, &vtimer
);