target-arm/gdbstub.c

   1 /*
   2  * ARM gdb server stub
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  * Copyright (c) 2013 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qemu-common.h"
  22 #include "cpu.h"
  23 #include "exec/gdbstub.h"
  24
  25 /* Old gdb always expect FPA registers.  Newer (xml-aware) gdb only expect
  26    whatever the target description contains.  Due to a historical mishap
  27    the FPA registers appear in between core integer regs and the CPSR.
  28    We hack round this by giving the FPA regs zero size when talking to a
  29    newer gdb.  */
  30
  31 int arm_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
  32 {
  33     ARMCPU *cpu = ARM_CPU(cs);
  34     CPUARMState *env = &cpu->env;
  35
  36     if (n < 16) {
  37         /* Core integer register.  */
  38         return gdb_get_reg32(mem_buf, env->regs[n]);
  39     }
  40     if (n < 24) {
  41         /* FPA registers.  */
  42         if (gdb_has_xml) {
  43             return 0;
  44         }
  45         memset(mem_buf, 0, 12);
  46         return 12;
  47     }
  48     switch (n) {
  49     case 24:
  50         /* FPA status register.  */
  51         if (gdb_has_xml) {
  52             return 0;
  53         }
  54         return gdb_get_reg32(mem_buf, 0);
  55     case 25:
  56         /* CPSR */
  57         return gdb_get_reg32(mem_buf, cpsr_read(env));
  58     }
  59     /* Unknown register.  */
  60     return 0;
  61 }
  62
  63 int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
  64 {
  65     ARMCPU *cpu = ARM_CPU(cs);
  66     CPUARMState *env = &cpu->env;
  67     uint32_t tmp;
  68
  69     tmp = ldl_p(mem_buf);
  70
  71     /* Mask out low bit of PC to workaround gdb bugs.  This will probably
  72        cause problems if we ever implement the Jazelle DBX extensions.  */
  73     if (n == 15) {
  74         tmp &= ~1;
  75     }
  76
  77     if (n < 16) {
  78         /* Core integer register.  */
  79         env->regs[n] = tmp;
  80         return 4;
  81     }
  82     if (n < 24) { /* 16-23 */
  83         /* FPA registers (ignored).  */
  84         if (gdb_has_xml) {
  85             return 0;
  86         }
  87         return 12;
  88     }
  89     switch (n) {
  90     case 24:
  91         /* FPA status register (ignored).  */
  92         if (gdb_has_xml) {
  93             return 0;
  94         }
  95         return 4;
  96     case 25:
  97         /* CPSR */
  98         cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub);
  99         return 4;
 100     }
 101     /* Unknown register.  */
 102     return 0;
 103 }