target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "internals.h"
  25 #include "qemu-common.h"
  26 #include "exec/exec-all.h"
  27 #include "hw/qdev-properties.h"
  28 #if !defined(CONFIG_USER_ONLY)
  29 #include "hw/loader.h"
  30 #endif
  31 #include "hw/arm/arm.h"
  32 #include "sysemu/sysemu.h"
  33 #include "sysemu/kvm.h"
  34 #include "kvm_arm.h"
  35
  36 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  37 {
  38     ARMCPU *cpu = ARM_CPU(cs);
  39
  40     cpu->env.regs[15] = value;
  41 }
  42
  43 static bool arm_cpu_has_work(CPUState *cs)
  44 {
  45     ARMCPU *cpu = ARM_CPU(cs);
  46
  47     return !cpu->powered_off
  48         && cs->interrupt_request &
  49         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  50          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  51          | CPU_INTERRUPT_EXITTB);
  52 }
  53
  54 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
  55                                  void *opaque)
  56 {
  57     /* We currently only support registering a single hook function */
  58     assert(!cpu->el_change_hook);
  59     cpu->el_change_hook = hook;
  60     cpu->el_change_hook_opaque = opaque;
  61 }
  62
  63 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  64 {
  65     /* Reset a single ARMCPRegInfo register */
  66     ARMCPRegInfo *ri = value;
  67     ARMCPU *cpu = opaque;
  68
  69     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  70         return;
  71     }
  72
  73     if (ri->resetfn) {
  74         ri->resetfn(&cpu->env, ri);
  75         return;
  76     }
  77
  78     /* A zero offset is never possible as it would be regs[0]
  79      * so we use it to indicate that reset is being handled elsewhere.
  80      * This is basically only used for fields in non-core coprocessors
  81      * (like the pxa2xx ones).
  82      */
  83     if (!ri->fieldoffset) {
  84         return;
  85     }
  86
  87     if (cpreg_field_is_64bit(ri)) {
  88         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  89     } else {
  90         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  91     }
  92 }
  93
  94 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
  95 {
  96     /* Purely an assertion check: we've already done reset once,
  97      * so now check that running the reset for the cpreg doesn't
  98      * change its value. This traps bugs where two different cpregs
  99      * both try to reset the same state field but to different values.
 100      */
 101     ARMCPRegInfo *ri = value;
 102     ARMCPU *cpu = opaque;
 103     uint64_t oldvalue, newvalue;
 104
 105     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
 106         return;
 107     }
 108
 109     oldvalue = read_raw_cp_reg(&cpu->env, ri);
 110     cp_reg_reset(key, value, opaque);
 111     newvalue = read_raw_cp_reg(&cpu->env, ri);
 112     assert(oldvalue == newvalue);
 113 }
 114
 115 /* CPUClass::reset() */
 116 static void arm_cpu_reset(CPUState *s)
 117 {
 118     ARMCPU *cpu = ARM_CPU(s);
 119     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 120     CPUARMState *env = &cpu->env;
 121
 122     acc->parent_reset(s);
 123
 124     memset(env, 0, offsetof(CPUARMState, features));
 125     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 126     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 127
 128     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 129     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
 130     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
 131     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
 132
 133     cpu->powered_off = cpu->start_powered_off;
 134     s->halted = cpu->start_powered_off;
 135
 136     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 137         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 138     }
 139
 140     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 141         /* 64 bit CPUs always start in 64 bit mode */
 142         env->aarch64 = 1;
 143 #if defined(CONFIG_USER_ONLY)
 144         env->pstate = PSTATE_MODE_EL0t;
 145         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 146         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 147         /* and to the FP/Neon instructions */
 148         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 149 #else
 150         /* Reset into the highest available EL */
 151         if (arm_feature(env, ARM_FEATURE_EL3)) {
 152             env->pstate = PSTATE_MODE_EL3h;
 153         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 154             env->pstate = PSTATE_MODE_EL2h;
 155         } else {
 156             env->pstate = PSTATE_MODE_EL1h;
 157         }
 158         env->pc = cpu->rvbar;
 159 #endif
 160     } else {
 161 #if defined(CONFIG_USER_ONLY)
 162         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 163         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 164 #endif
 165     }
 166
 167 #if defined(CONFIG_USER_ONLY)
 168     env->uncached_cpsr = ARM_CPU_MODE_USR;
 169     /* For user mode we must enable access to coprocessors */
 170     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 171     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 172         env->cp15.c15_cpar = 3;
 173     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 174         env->cp15.c15_cpar = 1;
 175     }
 176 #else
 177     /* SVC mode with interrupts disabled.  */
 178     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 179     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 180     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 181      * clear at reset. Initial SP and PC are loaded from ROM.
 182      */
 183     if (IS_M(env)) {
 184         uint32_t initial_msp; /* Loaded from 0x0 */
 185         uint32_t initial_pc; /* Loaded from 0x4 */
 186         uint8_t *rom;
 187
 188         env->daif &= ~PSTATE_I;
 189         rom = rom_ptr(0);
 190         if (rom) {
 191             /* Address zero is covered by ROM which hasn't yet been
 192              * copied into physical memory.
 193              */
 194             initial_msp = ldl_p(rom);
 195             initial_pc = ldl_p(rom + 4);
 196         } else {
 197             /* Address zero not covered by a ROM blob, or the ROM blob
 198              * is in non-modifiable memory and this is a second reset after
 199              * it got copied into memory. In the latter case, rom_ptr
 200              * will return a NULL pointer and we should use ldl_phys instead.
 201              */
 202             initial_msp = ldl_phys(s->as, 0);
 203             initial_pc = ldl_phys(s->as, 4);
 204         }
 205
 206         env->regs[13] = initial_msp & 0xFFFFFFFC;
 207         env->regs[15] = initial_pc & ~1;
 208         env->thumb = initial_pc & 1;
 209     }
 210
 211     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 212      * executing as AArch32 then check if highvecs are enabled and
 213      * adjust the PC accordingly.
 214      */
 215     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 216         env->regs[15] = 0xFFFF0000;
 217     }
 218
 219     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 220 #endif
 221     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 222     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 223     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 224     set_float_detect_tininess(float_tininess_before_rounding,
 225                               &env->vfp.fp_status);
 226     set_float_detect_tininess(float_tininess_before_rounding,
 227                               &env->vfp.standard_fp_status);
 228     tlb_flush(s, 1);
 229
 230 #ifndef CONFIG_USER_ONLY
 231     if (kvm_enabled()) {
 232         kvm_arm_reset_vcpu(cpu);
 233     }
 234 #endif
 235
 236     hw_breakpoint_update_all(cpu);
 237     hw_watchpoint_update_all(cpu);
 238 }
 239
 240 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 241 {
 242     CPUClass *cc = CPU_GET_CLASS(cs);
 243     CPUARMState *env = cs->env_ptr;
 244     uint32_t cur_el = arm_current_el(env);
 245     bool secure = arm_is_secure(env);
 246     uint32_t target_el;
 247     uint32_t excp_idx;
 248     bool ret = false;
 249
 250     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 251         excp_idx = EXCP_FIQ;
 252         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 253         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 254             cs->exception_index = excp_idx;
 255             env->exception.target_el = target_el;
 256             cc->do_interrupt(cs);
 257             ret = true;
 258         }
 259     }
 260     if (interrupt_request & CPU_INTERRUPT_HARD) {
 261         excp_idx = EXCP_IRQ;
 262         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 263         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 264             cs->exception_index = excp_idx;
 265             env->exception.target_el = target_el;
 266             cc->do_interrupt(cs);
 267             ret = true;
 268         }
 269     }
 270     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 271         excp_idx = EXCP_VIRQ;
 272         target_el = 1;
 273         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 274             cs->exception_index = excp_idx;
 275             env->exception.target_el = target_el;
 276             cc->do_interrupt(cs);
 277             ret = true;
 278         }
 279     }
 280     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 281         excp_idx = EXCP_VFIQ;
 282         target_el = 1;
 283         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 284             cs->exception_index = excp_idx;
 285             env->exception.target_el = target_el;
 286             cc->do_interrupt(cs);
 287             ret = true;
 288         }
 289     }
 290
 291     return ret;
 292 }
 293
 294 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 295 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 296 {
 297     CPUClass *cc = CPU_GET_CLASS(cs);
 298     ARMCPU *cpu = ARM_CPU(cs);
 299     CPUARMState *env = &cpu->env;
 300     bool ret = false;
 301
 302
 303     if (interrupt_request & CPU_INTERRUPT_FIQ
 304         && !(env->daif & PSTATE_F)) {
 305         cs->exception_index = EXCP_FIQ;
 306         cc->do_interrupt(cs);
 307         ret = true;
 308     }
 309     /* ARMv7-M interrupt return works by loading a magic value
 310      * into the PC.  On real hardware the load causes the
 311      * return to occur.  The qemu implementation performs the
 312      * jump normally, then does the exception return when the
 313      * CPU tries to execute code at the magic address.
 314      * This will cause the magic PC value to be pushed to
 315      * the stack if an interrupt occurred at the wrong time.
 316      * We avoid this by disabling interrupts when
 317      * pc contains a magic address.
 318      */
 319     if (interrupt_request & CPU_INTERRUPT_HARD
 320         && !(env->daif & PSTATE_I)
 321         && (env->regs[15] < 0xfffffff0)) {
 322         cs->exception_index = EXCP_IRQ;
 323         cc->do_interrupt(cs);
 324         ret = true;
 325     }
 326     return ret;
 327 }
 328 #endif
 329
 330 #ifndef CONFIG_USER_ONLY
 331 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 332 {
 333     ARMCPU *cpu = opaque;
 334     CPUARMState *env = &cpu->env;
 335     CPUState *cs = CPU(cpu);
 336     static const int mask[] = {
 337         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 338         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 339         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 340         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 341     };
 342
 343     switch (irq) {
 344     case ARM_CPU_VIRQ:
 345     case ARM_CPU_VFIQ:
 346         assert(arm_feature(env, ARM_FEATURE_EL2));
 347         /* fall through */
 348     case ARM_CPU_IRQ:
 349     case ARM_CPU_FIQ:
 350         if (level) {
 351             cpu_interrupt(cs, mask[irq]);
 352         } else {
 353             cpu_reset_interrupt(cs, mask[irq]);
 354         }
 355         break;
 356     default:
 357         g_assert_not_reached();
 358     }
 359 }
 360
 361 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 362 {
 363 #ifdef CONFIG_KVM
 364     ARMCPU *cpu = opaque;
 365     CPUState *cs = CPU(cpu);
 366     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 367
 368     switch (irq) {
 369     case ARM_CPU_IRQ:
 370         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 371         break;
 372     case ARM_CPU_FIQ:
 373         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 374         break;
 375     default:
 376         g_assert_not_reached();
 377     }
 378     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 379     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 380 #endif
 381 }
 382
 383 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 384 {
 385     ARMCPU *cpu = ARM_CPU(cs);
 386     CPUARMState *env = &cpu->env;
 387
 388     cpu_synchronize_state(cs);
 389     return arm_cpu_data_is_big_endian(env);
 390 }
 391
 392 #endif
 393
 394 static inline void set_feature(CPUARMState *env, int feature)
 395 {
 396     env->features |= 1ULL << feature;
 397 }
 398
 399 static inline void unset_feature(CPUARMState *env, int feature)
 400 {
 401     env->features &= ~(1ULL << feature);
 402 }
 403
 404 static int
 405 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 406 {
 407   return print_insn_arm(pc | 1, info);
 408 }
 409
 410 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 411 {
 412     ARMCPU *ac = ARM_CPU(cpu);
 413     CPUARMState *env = &ac->env;
 414
 415     if (is_a64(env)) {
 416         /* We might not be compiled with the A64 disassembler
 417          * because it needs a C++ compiler. Leave print_insn
 418          * unset in this case to use the caller default behaviour.
 419          */
 420 #if defined(CONFIG_ARM_A64_DIS)
 421         info->print_insn = print_insn_arm_a64;
 422 #endif
 423     } else if (env->thumb) {
 424         info->print_insn = print_insn_thumb1;
 425     } else {
 426         info->print_insn = print_insn_arm;
 427     }
 428     if (bswap_code(arm_sctlr_b(env))) {
 429 #ifdef TARGET_WORDS_BIGENDIAN
 430         info->endian = BFD_ENDIAN_LITTLE;
 431 #else
 432         info->endian = BFD_ENDIAN_BIG;
 433 #endif
 434     }
 435 }
 436
 437 #define ARM_CPUS_PER_CLUSTER 8
 438
 439 static void arm_cpu_initfn(Object *obj)
 440 {
 441     CPUState *cs = CPU(obj);
 442     ARMCPU *cpu = ARM_CPU(obj);
 443     static bool inited;
 444     uint32_t Aff1, Aff0;
 445
 446     cs->env_ptr = &cpu->env;
 447     cpu_exec_init(cs, &error_abort);
 448     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 449                                          g_free, g_free);
 450
 451     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 452      * We don't support setting cluster ID ([16..23]) (known as Aff2
 453      * in later ARM ARM versions), or any of the higher affinity level fields,
 454      * so these bits always RAZ.
 455      */
 456     Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
 457     Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
 458     cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 459
 460 #ifndef CONFIG_USER_ONLY
 461     /* Our inbound IRQ and FIQ lines */
 462     if (kvm_enabled()) {
 463         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 464          * the same interface as non-KVM CPUs.
 465          */
 466         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 467     } else {
 468         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 469     }
 470
 471     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 472                                                 arm_gt_ptimer_cb, cpu);
 473     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 474                                                 arm_gt_vtimer_cb, cpu);
 475     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 476                                                 arm_gt_htimer_cb, cpu);
 477     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 478                                                 arm_gt_stimer_cb, cpu);
 479     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 480                        ARRAY_SIZE(cpu->gt_timer_outputs));
 481 #endif
 482
 483     /* DTB consumers generally don't in fact care what the 'compatible'
 484      * string is, so always provide some string and trust that a hypothetical
 485      * picky DTB consumer will also provide a helpful error message.
 486      */
 487     cpu->dtb_compatible = "qemu,unknown";
 488     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 489     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 490
 491     if (tcg_enabled()) {
 492         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 493         if (!inited) {
 494             inited = true;
 495             arm_translate_init();
 496         }
 497     }
 498 }
 499
 500 static Property arm_cpu_reset_cbar_property =
 501             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 502
 503 static Property arm_cpu_reset_hivecs_property =
 504             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 505
 506 static Property arm_cpu_rvbar_property =
 507             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 508
 509 static Property arm_cpu_has_el3_property =
 510             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 511
 512 static Property arm_cpu_has_mpu_property =
 513             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 514
 515 static Property arm_cpu_pmsav7_dregion_property =
 516             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
 517
 518 static void arm_cpu_post_init(Object *obj)
 519 {
 520     ARMCPU *cpu = ARM_CPU(obj);
 521
 522     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 523         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 524         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 525                                  &error_abort);
 526     }
 527
 528     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 529         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 530                                  &error_abort);
 531     }
 532
 533     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 534         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 535                                  &error_abort);
 536     }
 537
 538     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 539         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 540          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 541          */
 542         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 543                                  &error_abort);
 544
 545 #ifndef CONFIG_USER_ONLY
 546         object_property_add_link(obj, "secure-memory",
 547                                  TYPE_MEMORY_REGION,
 548                                  (Object **)&cpu->secure_memory,
 549                                  qdev_prop_allow_set_link_before_realize,
 550                                  OBJ_PROP_LINK_UNREF_ON_RELEASE,
 551                                  &error_abort);
 552 #endif
 553     }
 554
 555     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
 556         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 557                                  &error_abort);
 558         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 559             qdev_property_add_static(DEVICE(obj),
 560                                      &arm_cpu_pmsav7_dregion_property,
 561                                      &error_abort);
 562         }
 563     }
 564
 565 }
 566
 567 static void arm_cpu_finalizefn(Object *obj)
 568 {
 569     ARMCPU *cpu = ARM_CPU(obj);
 570     g_hash_table_destroy(cpu->cp_regs);
 571 }
 572
 573 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 574 {
 575     CPUState *cs = CPU(dev);
 576     ARMCPU *cpu = ARM_CPU(dev);
 577     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 578     CPUARMState *env = &cpu->env;
 579
 580     /* Some features automatically imply others: */
 581     if (arm_feature(env, ARM_FEATURE_V8)) {
 582         set_feature(env, ARM_FEATURE_V7);
 583         set_feature(env, ARM_FEATURE_ARM_DIV);
 584         set_feature(env, ARM_FEATURE_LPAE);
 585     }
 586     if (arm_feature(env, ARM_FEATURE_V7)) {
 587         set_feature(env, ARM_FEATURE_VAPA);
 588         set_feature(env, ARM_FEATURE_THUMB2);
 589         set_feature(env, ARM_FEATURE_MPIDR);
 590         if (!arm_feature(env, ARM_FEATURE_M)) {
 591             set_feature(env, ARM_FEATURE_V6K);
 592         } else {
 593             set_feature(env, ARM_FEATURE_V6);
 594         }
 595     }
 596     if (arm_feature(env, ARM_FEATURE_V6K)) {
 597         set_feature(env, ARM_FEATURE_V6);
 598         set_feature(env, ARM_FEATURE_MVFR);
 599     }
 600     if (arm_feature(env, ARM_FEATURE_V6)) {
 601         set_feature(env, ARM_FEATURE_V5);
 602         if (!arm_feature(env, ARM_FEATURE_M)) {
 603             set_feature(env, ARM_FEATURE_AUXCR);
 604         }
 605     }
 606     if (arm_feature(env, ARM_FEATURE_V5)) {
 607         set_feature(env, ARM_FEATURE_V4T);
 608     }
 609     if (arm_feature(env, ARM_FEATURE_M)) {
 610         set_feature(env, ARM_FEATURE_THUMB_DIV);
 611     }
 612     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 613         set_feature(env, ARM_FEATURE_THUMB_DIV);
 614     }
 615     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 616         set_feature(env, ARM_FEATURE_VFP3);
 617         set_feature(env, ARM_FEATURE_VFP_FP16);
 618     }
 619     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 620         set_feature(env, ARM_FEATURE_VFP);
 621     }
 622     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 623         set_feature(env, ARM_FEATURE_V7MP);
 624         set_feature(env, ARM_FEATURE_PXN);
 625     }
 626     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 627         set_feature(env, ARM_FEATURE_CBAR);
 628     }
 629     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 630         !arm_feature(env, ARM_FEATURE_M)) {
 631         set_feature(env, ARM_FEATURE_THUMB_DSP);
 632     }
 633
 634     if (cpu->reset_hivecs) {
 635             cpu->reset_sctlr |= (1 << 13);
 636     }
 637
 638     if (!cpu->has_el3) {
 639         /* If the has_el3 CPU property is disabled then we need to disable the
 640          * feature.
 641          */
 642         unset_feature(env, ARM_FEATURE_EL3);
 643
 644         /* Disable the security extension feature bits in the processor feature
 645          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 646          */
 647         cpu->id_pfr1 &= ~0xf0;
 648         cpu->id_aa64pfr0 &= ~0xf000;
 649     }
 650
 651     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 652         /* Disable the hypervisor feature bits in the processor feature
 653          * registers if we don't have EL2. These are id_pfr1[15:12] and
 654          * id_aa64pfr0_el1[11:8].
 655          */
 656         cpu->id_aa64pfr0 &= ~0xf00;
 657         cpu->id_pfr1 &= ~0xf000;
 658     }
 659
 660     if (!cpu->has_mpu) {
 661         unset_feature(env, ARM_FEATURE_MPU);
 662     }
 663
 664     if (arm_feature(env, ARM_FEATURE_MPU) &&
 665         arm_feature(env, ARM_FEATURE_V7)) {
 666         uint32_t nr = cpu->pmsav7_dregion;
 667
 668         if (nr > 0xff) {
 669             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
 670             return;
 671         }
 672
 673         if (nr) {
 674             env->pmsav7.drbar = g_new0(uint32_t, nr);
 675             env->pmsav7.drsr = g_new0(uint32_t, nr);
 676             env->pmsav7.dracr = g_new0(uint32_t, nr);
 677         }
 678     }
 679
 680     register_cp_regs_for_features(cpu);
 681     arm_cpu_register_gdb_regs_for_features(cpu);
 682
 683     init_cpreg_list(cpu);
 684
 685 #ifndef CONFIG_USER_ONLY
 686     if (cpu->has_el3) {
 687         cs->num_ases = 2;
 688     } else {
 689         cs->num_ases = 1;
 690     }
 691
 692     if (cpu->has_el3) {
 693         AddressSpace *as;
 694
 695         if (!cpu->secure_memory) {
 696             cpu->secure_memory = cs->memory;
 697         }
 698         as = address_space_init_shareable(cpu->secure_memory,
 699                                           "cpu-secure-memory");
 700         cpu_address_space_init(cs, as, ARMASIdx_S);
 701     }
 702     cpu_address_space_init(cs,
 703                            address_space_init_shareable(cs->memory,
 704                                                         "cpu-memory"),
 705                            ARMASIdx_NS);
 706 #endif
 707
 708     qemu_init_vcpu(cs);
 709     cpu_reset(cs);
 710
 711     acc->parent_realize(dev, errp);
 712 }
 713
 714 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 715 {
 716     ObjectClass *oc;
 717     char *typename;
 718     char **cpuname;
 719
 720     if (!cpu_model) {
 721         return NULL;
 722     }
 723
 724     cpuname = g_strsplit(cpu_model, ",", 1);
 725     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 726     oc = object_class_by_name(typename);
 727     g_strfreev(cpuname);
 728     g_free(typename);
 729     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 730         object_class_is_abstract(oc)) {
 731         return NULL;
 732     }
 733     return oc;
 734 }
 735
 736 /* CPU models. These are not needed for the AArch64 linux-user build. */
 737 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 738
 739 static void arm926_initfn(Object *obj)
 740 {
 741     ARMCPU *cpu = ARM_CPU(obj);
 742
 743     cpu->dtb_compatible = "arm,arm926";
 744     set_feature(&cpu->env, ARM_FEATURE_V5);
 745     set_feature(&cpu->env, ARM_FEATURE_VFP);
 746     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 747     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 748     cpu->midr = 0x41069265;
 749     cpu->reset_fpsid = 0x41011090;
 750     cpu->ctr = 0x1dd20d2;
 751     cpu->reset_sctlr = 0x00090078;
 752 }
 753
 754 static void arm946_initfn(Object *obj)
 755 {
 756     ARMCPU *cpu = ARM_CPU(obj);
 757
 758     cpu->dtb_compatible = "arm,arm946";
 759     set_feature(&cpu->env, ARM_FEATURE_V5);
 760     set_feature(&cpu->env, ARM_FEATURE_MPU);
 761     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 762     cpu->midr = 0x41059461;
 763     cpu->ctr = 0x0f004006;
 764     cpu->reset_sctlr = 0x00000078;
 765 }
 766
 767 static void arm1026_initfn(Object *obj)
 768 {
 769     ARMCPU *cpu = ARM_CPU(obj);
 770
 771     cpu->dtb_compatible = "arm,arm1026";
 772     set_feature(&cpu->env, ARM_FEATURE_V5);
 773     set_feature(&cpu->env, ARM_FEATURE_VFP);
 774     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 775     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 776     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 777     cpu->midr = 0x4106a262;
 778     cpu->reset_fpsid = 0x410110a0;
 779     cpu->ctr = 0x1dd20d2;
 780     cpu->reset_sctlr = 0x00090078;
 781     cpu->reset_auxcr = 1;
 782     {
 783         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 784         ARMCPRegInfo ifar = {
 785             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 786             .access = PL1_RW,
 787             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 788             .resetvalue = 0
 789         };
 790         define_one_arm_cp_reg(cpu, &ifar);
 791     }
 792 }
 793
 794 static void arm1136_r2_initfn(Object *obj)
 795 {
 796     ARMCPU *cpu = ARM_CPU(obj);
 797     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 798      * older core than plain "arm1136". In particular this does not
 799      * have the v6K features.
 800      * These ID register values are correct for 1136 but may be wrong
 801      * for 1136_r2 (in particular r0p2 does not actually implement most
 802      * of the ID registers).
 803      */
 804
 805     cpu->dtb_compatible = "arm,arm1136";
 806     set_feature(&cpu->env, ARM_FEATURE_V6);
 807     set_feature(&cpu->env, ARM_FEATURE_VFP);
 808     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 809     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 810     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 811     cpu->midr = 0x4107b362;
 812     cpu->reset_fpsid = 0x410120b4;
 813     cpu->mvfr0 = 0x11111111;
 814     cpu->mvfr1 = 0x00000000;
 815     cpu->ctr = 0x1dd20d2;
 816     cpu->reset_sctlr = 0x00050078;
 817     cpu->id_pfr0 = 0x111;
 818     cpu->id_pfr1 = 0x1;
 819     cpu->id_dfr0 = 0x2;
 820     cpu->id_afr0 = 0x3;
 821     cpu->id_mmfr0 = 0x01130003;
 822     cpu->id_mmfr1 = 0x10030302;
 823     cpu->id_mmfr2 = 0x01222110;
 824     cpu->id_isar0 = 0x00140011;
 825     cpu->id_isar1 = 0x12002111;
 826     cpu->id_isar2 = 0x11231111;
 827     cpu->id_isar3 = 0x01102131;
 828     cpu->id_isar4 = 0x141;
 829     cpu->reset_auxcr = 7;
 830 }
 831
 832 static void arm1136_initfn(Object *obj)
 833 {
 834     ARMCPU *cpu = ARM_CPU(obj);
 835
 836     cpu->dtb_compatible = "arm,arm1136";
 837     set_feature(&cpu->env, ARM_FEATURE_V6K);
 838     set_feature(&cpu->env, ARM_FEATURE_V6);
 839     set_feature(&cpu->env, ARM_FEATURE_VFP);
 840     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 841     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 842     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 843     cpu->midr = 0x4117b363;
 844     cpu->reset_fpsid = 0x410120b4;
 845     cpu->mvfr0 = 0x11111111;
 846     cpu->mvfr1 = 0x00000000;
 847     cpu->ctr = 0x1dd20d2;
 848     cpu->reset_sctlr = 0x00050078;
 849     cpu->id_pfr0 = 0x111;
 850     cpu->id_pfr1 = 0x1;
 851     cpu->id_dfr0 = 0x2;
 852     cpu->id_afr0 = 0x3;
 853     cpu->id_mmfr0 = 0x01130003;
 854     cpu->id_mmfr1 = 0x10030302;
 855     cpu->id_mmfr2 = 0x01222110;
 856     cpu->id_isar0 = 0x00140011;
 857     cpu->id_isar1 = 0x12002111;
 858     cpu->id_isar2 = 0x11231111;
 859     cpu->id_isar3 = 0x01102131;
 860     cpu->id_isar4 = 0x141;
 861     cpu->reset_auxcr = 7;
 862 }
 863
 864 static void arm1176_initfn(Object *obj)
 865 {
 866     ARMCPU *cpu = ARM_CPU(obj);
 867
 868     cpu->dtb_compatible = "arm,arm1176";
 869     set_feature(&cpu->env, ARM_FEATURE_V6K);
 870     set_feature(&cpu->env, ARM_FEATURE_VFP);
 871     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 872     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 873     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 874     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 875     set_feature(&cpu->env, ARM_FEATURE_EL3);
 876     cpu->midr = 0x410fb767;
 877     cpu->reset_fpsid = 0x410120b5;
 878     cpu->mvfr0 = 0x11111111;
 879     cpu->mvfr1 = 0x00000000;
 880     cpu->ctr = 0x1dd20d2;
 881     cpu->reset_sctlr = 0x00050078;
 882     cpu->id_pfr0 = 0x111;
 883     cpu->id_pfr1 = 0x11;
 884     cpu->id_dfr0 = 0x33;
 885     cpu->id_afr0 = 0;
 886     cpu->id_mmfr0 = 0x01130003;
 887     cpu->id_mmfr1 = 0x10030302;
 888     cpu->id_mmfr2 = 0x01222100;
 889     cpu->id_isar0 = 0x0140011;
 890     cpu->id_isar1 = 0x12002111;
 891     cpu->id_isar2 = 0x11231121;
 892     cpu->id_isar3 = 0x01102131;
 893     cpu->id_isar4 = 0x01141;
 894     cpu->reset_auxcr = 7;
 895 }
 896
 897 static void arm11mpcore_initfn(Object *obj)
 898 {
 899     ARMCPU *cpu = ARM_CPU(obj);
 900
 901     cpu->dtb_compatible = "arm,arm11mpcore";
 902     set_feature(&cpu->env, ARM_FEATURE_V6K);
 903     set_feature(&cpu->env, ARM_FEATURE_VFP);
 904     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 905     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 906     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 907     cpu->midr = 0x410fb022;
 908     cpu->reset_fpsid = 0x410120b4;
 909     cpu->mvfr0 = 0x11111111;
 910     cpu->mvfr1 = 0x00000000;
 911     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 912     cpu->id_pfr0 = 0x111;
 913     cpu->id_pfr1 = 0x1;
 914     cpu->id_dfr0 = 0;
 915     cpu->id_afr0 = 0x2;
 916     cpu->id_mmfr0 = 0x01100103;
 917     cpu->id_mmfr1 = 0x10020302;
 918     cpu->id_mmfr2 = 0x01222000;
 919     cpu->id_isar0 = 0x00100011;
 920     cpu->id_isar1 = 0x12002111;
 921     cpu->id_isar2 = 0x11221011;
 922     cpu->id_isar3 = 0x01102131;
 923     cpu->id_isar4 = 0x141;
 924     cpu->reset_auxcr = 1;
 925 }
 926
 927 static void cortex_m3_initfn(Object *obj)
 928 {
 929     ARMCPU *cpu = ARM_CPU(obj);
 930     set_feature(&cpu->env, ARM_FEATURE_V7);
 931     set_feature(&cpu->env, ARM_FEATURE_M);
 932     cpu->midr = 0x410fc231;
 933 }
 934
 935 static void cortex_m4_initfn(Object *obj)
 936 {
 937     ARMCPU *cpu = ARM_CPU(obj);
 938
 939     set_feature(&cpu->env, ARM_FEATURE_V7);
 940     set_feature(&cpu->env, ARM_FEATURE_M);
 941     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 942     cpu->midr = 0x410fc240; /* r0p0 */
 943 }
 944 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 945 {
 946     CPUClass *cc = CPU_CLASS(oc);
 947
 948 #ifndef CONFIG_USER_ONLY
 949     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 950 #endif
 951
 952     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 953 }
 954
 955 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 956     /* Dummy the TCM region regs for the moment */
 957     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 958       .access = PL1_RW, .type = ARM_CP_CONST },
 959     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 960       .access = PL1_RW, .type = ARM_CP_CONST },
 961     REGINFO_SENTINEL
 962 };
 963
 964 static void cortex_r5_initfn(Object *obj)
 965 {
 966     ARMCPU *cpu = ARM_CPU(obj);
 967
 968     set_feature(&cpu->env, ARM_FEATURE_V7);
 969     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
 970     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 971     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 972     set_feature(&cpu->env, ARM_FEATURE_MPU);
 973     cpu->midr = 0x411fc153; /* r1p3 */
 974     cpu->id_pfr0 = 0x0131;
 975     cpu->id_pfr1 = 0x001;
 976     cpu->id_dfr0 = 0x010400;
 977     cpu->id_afr0 = 0x0;
 978     cpu->id_mmfr0 = 0x0210030;
 979     cpu->id_mmfr1 = 0x00000000;
 980     cpu->id_mmfr2 = 0x01200000;
 981     cpu->id_mmfr3 = 0x0211;
 982     cpu->id_isar0 = 0x2101111;
 983     cpu->id_isar1 = 0x13112111;
 984     cpu->id_isar2 = 0x21232141;
 985     cpu->id_isar3 = 0x01112131;
 986     cpu->id_isar4 = 0x0010142;
 987     cpu->id_isar5 = 0x0;
 988     cpu->mp_is_up = true;
 989     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 990 }
 991
 992 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 993     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 994       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 995     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 996       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 997     REGINFO_SENTINEL
 998 };
 999
1000 static void cortex_a8_initfn(Object *obj)
1001 {
1002     ARMCPU *cpu = ARM_CPU(obj);
1003
1004     cpu->dtb_compatible = "arm,cortex-a8";
1005     set_feature(&cpu->env, ARM_FEATURE_V7);
1006     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1007     set_feature(&cpu->env, ARM_FEATURE_NEON);
1008     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1009     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1010     set_feature(&cpu->env, ARM_FEATURE_EL3);
1011     cpu->midr = 0x410fc080;
1012     cpu->reset_fpsid = 0x410330c0;
1013     cpu->mvfr0 = 0x11110222;
1014     cpu->mvfr1 = 0x00011100;
1015     cpu->ctr = 0x82048004;
1016     cpu->reset_sctlr = 0x00c50078;
1017     cpu->id_pfr0 = 0x1031;
1018     cpu->id_pfr1 = 0x11;
1019     cpu->id_dfr0 = 0x400;
1020     cpu->id_afr0 = 0;
1021     cpu->id_mmfr0 = 0x31100003;
1022     cpu->id_mmfr1 = 0x20000000;
1023     cpu->id_mmfr2 = 0x01202000;
1024     cpu->id_mmfr3 = 0x11;
1025     cpu->id_isar0 = 0x00101111;
1026     cpu->id_isar1 = 0x12112111;
1027     cpu->id_isar2 = 0x21232031;
1028     cpu->id_isar3 = 0x11112131;
1029     cpu->id_isar4 = 0x00111142;
1030     cpu->dbgdidr = 0x15141000;
1031     cpu->clidr = (1 << 27) | (2 << 24) | 3;
1032     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1033     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1034     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1035     cpu->reset_auxcr = 2;
1036     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1037 }
1038
1039 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1040     /* power_control should be set to maximum latency. Again,
1041      * default to 0 and set by private hook
1042      */
1043     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1044       .access = PL1_RW, .resetvalue = 0,
1045       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1046     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1047       .access = PL1_RW, .resetvalue = 0,
1048       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1049     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1050       .access = PL1_RW, .resetvalue = 0,
1051       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1052     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1053       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1054     /* TLB lockdown control */
1055     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1056       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1057     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1058       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1059     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1060       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1061     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1062       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1063     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1064       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1065     REGINFO_SENTINEL
1066 };
1067
1068 static void cortex_a9_initfn(Object *obj)
1069 {
1070     ARMCPU *cpu = ARM_CPU(obj);
1071
1072     cpu->dtb_compatible = "arm,cortex-a9";
1073     set_feature(&cpu->env, ARM_FEATURE_V7);
1074     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1075     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1076     set_feature(&cpu->env, ARM_FEATURE_NEON);
1077     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1078     set_feature(&cpu->env, ARM_FEATURE_EL3);
1079     /* Note that A9 supports the MP extensions even for
1080      * A9UP and single-core A9MP (which are both different
1081      * and valid configurations; we don't model A9UP).
1082      */
1083     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1084     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1085     cpu->midr = 0x410fc090;
1086     cpu->reset_fpsid = 0x41033090;
1087     cpu->mvfr0 = 0x11110222;
1088     cpu->mvfr1 = 0x01111111;
1089     cpu->ctr = 0x80038003;
1090     cpu->reset_sctlr = 0x00c50078;
1091     cpu->id_pfr0 = 0x1031;
1092     cpu->id_pfr1 = 0x11;
1093     cpu->id_dfr0 = 0x000;
1094     cpu->id_afr0 = 0;
1095     cpu->id_mmfr0 = 0x00100103;
1096     cpu->id_mmfr1 = 0x20000000;
1097     cpu->id_mmfr2 = 0x01230000;
1098     cpu->id_mmfr3 = 0x00002111;
1099     cpu->id_isar0 = 0x00101111;
1100     cpu->id_isar1 = 0x13112111;
1101     cpu->id_isar2 = 0x21232041;
1102     cpu->id_isar3 = 0x11112131;
1103     cpu->id_isar4 = 0x00111142;
1104     cpu->dbgdidr = 0x35141000;
1105     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1106     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1107     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1108     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1109 }
1110
1111 #ifndef CONFIG_USER_ONLY
1112 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1113 {
1114     /* Linux wants the number of processors from here.
1115      * Might as well set the interrupt-controller bit too.
1116      */
1117     return ((smp_cpus - 1) << 24) | (1 << 23);
1118 }
1119 #endif
1120
1121 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1122 #ifndef CONFIG_USER_ONLY
1123     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1124       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1125       .writefn = arm_cp_write_ignore, },
1126 #endif
1127     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1128       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1129     REGINFO_SENTINEL
1130 };
1131
1132 static void cortex_a15_initfn(Object *obj)
1133 {
1134     ARMCPU *cpu = ARM_CPU(obj);
1135
1136     cpu->dtb_compatible = "arm,cortex-a15";
1137     set_feature(&cpu->env, ARM_FEATURE_V7);
1138     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1139     set_feature(&cpu->env, ARM_FEATURE_NEON);
1140     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1141     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1142     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1143     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1144     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1145     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1146     set_feature(&cpu->env, ARM_FEATURE_EL3);
1147     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1148     cpu->midr = 0x412fc0f1;
1149     cpu->reset_fpsid = 0x410430f0;
1150     cpu->mvfr0 = 0x10110222;
1151     cpu->mvfr1 = 0x11111111;
1152     cpu->ctr = 0x8444c004;
1153     cpu->reset_sctlr = 0x00c50078;
1154     cpu->id_pfr0 = 0x00001131;
1155     cpu->id_pfr1 = 0x00011011;
1156     cpu->id_dfr0 = 0x02010555;
1157     cpu->pmceid0 = 0x0000000;
1158     cpu->pmceid1 = 0x00000000;
1159     cpu->id_afr0 = 0x00000000;
1160     cpu->id_mmfr0 = 0x10201105;
1161     cpu->id_mmfr1 = 0x20000000;
1162     cpu->id_mmfr2 = 0x01240000;
1163     cpu->id_mmfr3 = 0x02102211;
1164     cpu->id_isar0 = 0x02101110;
1165     cpu->id_isar1 = 0x13112111;
1166     cpu->id_isar2 = 0x21232041;
1167     cpu->id_isar3 = 0x11112131;
1168     cpu->id_isar4 = 0x10011142;
1169     cpu->dbgdidr = 0x3515f021;
1170     cpu->clidr = 0x0a200023;
1171     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1172     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1173     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1174     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1175 }
1176
1177 static void ti925t_initfn(Object *obj)
1178 {
1179     ARMCPU *cpu = ARM_CPU(obj);
1180     set_feature(&cpu->env, ARM_FEATURE_V4T);
1181     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1182     cpu->midr = ARM_CPUID_TI925T;
1183     cpu->ctr = 0x5109149;
1184     cpu->reset_sctlr = 0x00000070;
1185 }
1186
1187 static void sa1100_initfn(Object *obj)
1188 {
1189     ARMCPU *cpu = ARM_CPU(obj);
1190
1191     cpu->dtb_compatible = "intel,sa1100";
1192     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1193     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1194     cpu->midr = 0x4401A11B;
1195     cpu->reset_sctlr = 0x00000070;
1196 }
1197
1198 static void sa1110_initfn(Object *obj)
1199 {
1200     ARMCPU *cpu = ARM_CPU(obj);
1201     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1202     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1203     cpu->midr = 0x6901B119;
1204     cpu->reset_sctlr = 0x00000070;
1205 }
1206
1207 static void pxa250_initfn(Object *obj)
1208 {
1209     ARMCPU *cpu = ARM_CPU(obj);
1210
1211     cpu->dtb_compatible = "marvell,xscale";
1212     set_feature(&cpu->env, ARM_FEATURE_V5);
1213     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1214     cpu->midr = 0x69052100;
1215     cpu->ctr = 0xd172172;
1216     cpu->reset_sctlr = 0x00000078;
1217 }
1218
1219 static void pxa255_initfn(Object *obj)
1220 {
1221     ARMCPU *cpu = ARM_CPU(obj);
1222
1223     cpu->dtb_compatible = "marvell,xscale";
1224     set_feature(&cpu->env, ARM_FEATURE_V5);
1225     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1226     cpu->midr = 0x69052d00;
1227     cpu->ctr = 0xd172172;
1228     cpu->reset_sctlr = 0x00000078;
1229 }
1230
1231 static void pxa260_initfn(Object *obj)
1232 {
1233     ARMCPU *cpu = ARM_CPU(obj);
1234
1235     cpu->dtb_compatible = "marvell,xscale";
1236     set_feature(&cpu->env, ARM_FEATURE_V5);
1237     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1238     cpu->midr = 0x69052903;
1239     cpu->ctr = 0xd172172;
1240     cpu->reset_sctlr = 0x00000078;
1241 }
1242
1243 static void pxa261_initfn(Object *obj)
1244 {
1245     ARMCPU *cpu = ARM_CPU(obj);
1246
1247     cpu->dtb_compatible = "marvell,xscale";
1248     set_feature(&cpu->env, ARM_FEATURE_V5);
1249     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1250     cpu->midr = 0x69052d05;
1251     cpu->ctr = 0xd172172;
1252     cpu->reset_sctlr = 0x00000078;
1253 }
1254
1255 static void pxa262_initfn(Object *obj)
1256 {
1257     ARMCPU *cpu = ARM_CPU(obj);
1258
1259     cpu->dtb_compatible = "marvell,xscale";
1260     set_feature(&cpu->env, ARM_FEATURE_V5);
1261     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1262     cpu->midr = 0x69052d06;
1263     cpu->ctr = 0xd172172;
1264     cpu->reset_sctlr = 0x00000078;
1265 }
1266
1267 static void pxa270a0_initfn(Object *obj)
1268 {
1269     ARMCPU *cpu = ARM_CPU(obj);
1270
1271     cpu->dtb_compatible = "marvell,xscale";
1272     set_feature(&cpu->env, ARM_FEATURE_V5);
1273     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1274     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1275     cpu->midr = 0x69054110;
1276     cpu->ctr = 0xd172172;
1277     cpu->reset_sctlr = 0x00000078;
1278 }
1279
1280 static void pxa270a1_initfn(Object *obj)
1281 {
1282     ARMCPU *cpu = ARM_CPU(obj);
1283
1284     cpu->dtb_compatible = "marvell,xscale";
1285     set_feature(&cpu->env, ARM_FEATURE_V5);
1286     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1287     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1288     cpu->midr = 0x69054111;
1289     cpu->ctr = 0xd172172;
1290     cpu->reset_sctlr = 0x00000078;
1291 }
1292
1293 static void pxa270b0_initfn(Object *obj)
1294 {
1295     ARMCPU *cpu = ARM_CPU(obj);
1296
1297     cpu->dtb_compatible = "marvell,xscale";
1298     set_feature(&cpu->env, ARM_FEATURE_V5);
1299     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1300     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1301     cpu->midr = 0x69054112;
1302     cpu->ctr = 0xd172172;
1303     cpu->reset_sctlr = 0x00000078;
1304 }
1305
1306 static void pxa270b1_initfn(Object *obj)
1307 {
1308     ARMCPU *cpu = ARM_CPU(obj);
1309
1310     cpu->dtb_compatible = "marvell,xscale";
1311     set_feature(&cpu->env, ARM_FEATURE_V5);
1312     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1313     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1314     cpu->midr = 0x69054113;
1315     cpu->ctr = 0xd172172;
1316     cpu->reset_sctlr = 0x00000078;
1317 }
1318
1319 static void pxa270c0_initfn(Object *obj)
1320 {
1321     ARMCPU *cpu = ARM_CPU(obj);
1322
1323     cpu->dtb_compatible = "marvell,xscale";
1324     set_feature(&cpu->env, ARM_FEATURE_V5);
1325     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1326     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1327     cpu->midr = 0x69054114;
1328     cpu->ctr = 0xd172172;
1329     cpu->reset_sctlr = 0x00000078;
1330 }
1331
1332 static void pxa270c5_initfn(Object *obj)
1333 {
1334     ARMCPU *cpu = ARM_CPU(obj);
1335
1336     cpu->dtb_compatible = "marvell,xscale";
1337     set_feature(&cpu->env, ARM_FEATURE_V5);
1338     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1339     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1340     cpu->midr = 0x69054117;
1341     cpu->ctr = 0xd172172;
1342     cpu->reset_sctlr = 0x00000078;
1343 }
1344
1345 #ifdef CONFIG_USER_ONLY
1346 static void arm_any_initfn(Object *obj)
1347 {
1348     ARMCPU *cpu = ARM_CPU(obj);
1349     set_feature(&cpu->env, ARM_FEATURE_V8);
1350     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1351     set_feature(&cpu->env, ARM_FEATURE_NEON);
1352     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1353     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1354     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1355     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1356     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1357     set_feature(&cpu->env, ARM_FEATURE_CRC);
1358     cpu->midr = 0xffffffff;
1359 }
1360 #endif
1361
1362 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1363
1364 typedef struct ARMCPUInfo {
1365     const char *name;
1366     void (*initfn)(Object *obj);
1367     void (*class_init)(ObjectClass *oc, void *data);
1368 } ARMCPUInfo;
1369
1370 static const ARMCPUInfo arm_cpus[] = {
1371 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1372     { .name = "arm926",      .initfn = arm926_initfn },
1373     { .name = "arm946",      .initfn = arm946_initfn },
1374     { .name = "arm1026",     .initfn = arm1026_initfn },
1375     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1376      * older core than plain "arm1136". In particular this does not
1377      * have the v6K features.
1378      */
1379     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1380     { .name = "arm1136",     .initfn = arm1136_initfn },
1381     { .name = "arm1176",     .initfn = arm1176_initfn },
1382     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1383     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1384                              .class_init = arm_v7m_class_init },
1385     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1386                              .class_init = arm_v7m_class_init },
1387     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1388     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1389     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1390     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1391     { .name = "ti925t",      .initfn = ti925t_initfn },
1392     { .name = "sa1100",      .initfn = sa1100_initfn },
1393     { .name = "sa1110",      .initfn = sa1110_initfn },
1394     { .name = "pxa250",      .initfn = pxa250_initfn },
1395     { .name = "pxa255",      .initfn = pxa255_initfn },
1396     { .name = "pxa260",      .initfn = pxa260_initfn },
1397     { .name = "pxa261",      .initfn = pxa261_initfn },
1398     { .name = "pxa262",      .initfn = pxa262_initfn },
1399     /* "pxa270" is an alias for "pxa270-a0" */
1400     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1401     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1402     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1403     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1404     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1405     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1406     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1407 #ifdef CONFIG_USER_ONLY
1408     { .name = "any",         .initfn = arm_any_initfn },
1409 #endif
1410 #endif
1411     { .name = NULL }
1412 };
1413
1414 static Property arm_cpu_properties[] = {
1415     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1416     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1417     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1418     DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, 0),
1419     DEFINE_PROP_END_OF_LIST()
1420 };
1421
1422 #ifdef CONFIG_USER_ONLY
1423 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1424                                     int mmu_idx)
1425 {
1426     ARMCPU *cpu = ARM_CPU(cs);
1427     CPUARMState *env = &cpu->env;
1428
1429     env->exception.vaddress = address;
1430     if (rw == 2) {
1431         cs->exception_index = EXCP_PREFETCH_ABORT;
1432     } else {
1433         cs->exception_index = EXCP_DATA_ABORT;
1434     }
1435     return 1;
1436 }
1437 #endif
1438
1439 static gchar *arm_gdb_arch_name(CPUState *cs)
1440 {
1441     ARMCPU *cpu = ARM_CPU(cs);
1442     CPUARMState *env = &cpu->env;
1443
1444     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1445         return g_strdup("iwmmxt");
1446     }
1447     return g_strdup("arm");
1448 }
1449
1450 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1451 {
1452     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1453     CPUClass *cc = CPU_CLASS(acc);
1454     DeviceClass *dc = DEVICE_CLASS(oc);
1455
1456     acc->parent_realize = dc->realize;
1457     dc->realize = arm_cpu_realizefn;
1458     dc->props = arm_cpu_properties;
1459
1460     acc->parent_reset = cc->reset;
1461     cc->reset = arm_cpu_reset;
1462
1463     cc->class_by_name = arm_cpu_class_by_name;
1464     cc->has_work = arm_cpu_has_work;
1465     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1466     cc->dump_state = arm_cpu_dump_state;
1467     cc->set_pc = arm_cpu_set_pc;
1468     cc->gdb_read_register = arm_cpu_gdb_read_register;
1469     cc->gdb_write_register = arm_cpu_gdb_write_register;
1470 #ifdef CONFIG_USER_ONLY
1471     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1472 #else
1473     cc->do_interrupt = arm_cpu_do_interrupt;
1474     cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1475     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1476     cc->asidx_from_attrs = arm_asidx_from_attrs;
1477     cc->vmsd = &vmstate_arm_cpu;
1478     cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1479     cc->write_elf64_note = arm_cpu_write_elf64_note;
1480     cc->write_elf32_note = arm_cpu_write_elf32_note;
1481 #endif
1482     cc->gdb_num_core_regs = 26;
1483     cc->gdb_core_xml_file = "arm-core.xml";
1484     cc->gdb_arch_name = arm_gdb_arch_name;
1485     cc->gdb_stop_before_watchpoint = true;
1486     cc->debug_excp_handler = arm_debug_excp_handler;
1487     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1488
1489     cc->disas_set_info = arm_disas_set_info;
1490
1491     /*
1492      * Reason: arm_cpu_initfn() calls cpu_exec_init(), which saves
1493      * the object in cpus -> dangling pointer after final
1494      * object_unref().
1495      *
1496      * Once this is fixed, the devices that create ARM CPUs should be
1497      * updated not to set cannot_destroy_with_object_finalize_yet,
1498      * unless they still screw up something else.
1499      */
1500     dc->cannot_destroy_with_object_finalize_yet = true;
1501 }
1502
1503 static void cpu_register(const ARMCPUInfo *info)
1504 {
1505     TypeInfo type_info = {
1506         .parent = TYPE_ARM_CPU,
1507         .instance_size = sizeof(ARMCPU),
1508         .instance_init = info->initfn,
1509         .class_size = sizeof(ARMCPUClass),
1510         .class_init = info->class_init,
1511     };
1512
1513     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1514     type_register(&type_info);
1515     g_free((void *)type_info.name);
1516 }
1517
1518 static const TypeInfo arm_cpu_type_info = {
1519     .name = TYPE_ARM_CPU,
1520     .parent = TYPE_CPU,
1521     .instance_size = sizeof(ARMCPU),
1522     .instance_init = arm_cpu_initfn,
1523     .instance_post_init = arm_cpu_post_init,
1524     .instance_finalize = arm_cpu_finalizefn,
1525     .abstract = true,
1526     .class_size = sizeof(ARMCPUClass),
1527     .class_init = arm_cpu_class_init,
1528 };
1529
1530 static void arm_cpu_register_types(void)
1531 {
1532     const ARMCPUInfo *info = arm_cpus;
1533
1534     type_register_static(&arm_cpu_type_info);
1535
1536     while (info->name) {
1537         cpu_register(info);
1538         info++;
1539     }
1540 }
1541
1542 type_init(arm_cpu_register_types)