target-s390x/cpu.h

   1 /*
   2  * S/390 virtual CPU header
   3  *
   4  *  Copyright (c) 2009 Ulrich Hecht
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * Contributions after 2012-10-29 are licensed under the terms of the
  17  * GNU GPL, version 2 or (at your option) any later version.
  18  *
  19  * You should have received a copy of the GNU (Lesser) General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22 #ifndef CPU_S390X_H
  23 #define CPU_S390X_H
  24
  25 #include "config.h"
  26 #include "qemu-common.h"
  27
  28 #define TARGET_LONG_BITS 64
  29
  30 #define ELF_MACHINE     EM_S390
  31 #define ELF_MACHINE_UNAME "S390X"
  32
  33 #define CPUArchState struct CPUS390XState
  34
  35 #include "exec/cpu-defs.h"
  36 #define TARGET_PAGE_BITS 12
  37
  38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
  39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
  40
  41 #include "exec/cpu-all.h"
  42
  43 #include "fpu/softfloat.h"
  44
  45 #define NB_MMU_MODES 3
  46
  47 #define MMU_MODE0_SUFFIX _primary
  48 #define MMU_MODE1_SUFFIX _secondary
  49 #define MMU_MODE2_SUFFIX _home
  50
  51 #define MMU_USER_IDX 1
  52
  53 #define MAX_EXT_QUEUE 16
  54 #define MAX_IO_QUEUE 16
  55 #define MAX_MCHK_QUEUE 16
  56
  57 #define PSW_MCHK_MASK 0x0004000000000000
  58 #define PSW_IO_MASK 0x0200000000000000
  59
  60 typedef struct PSW {
  61     uint64_t mask;
  62     uint64_t addr;
  63 } PSW;
  64
  65 typedef struct ExtQueue {
  66     uint32_t code;
  67     uint32_t param;
  68     uint32_t param64;
  69 } ExtQueue;
  70
  71 typedef struct IOIntQueue {
  72     uint16_t id;
  73     uint16_t nr;
  74     uint32_t parm;
  75     uint32_t word;
  76 } IOIntQueue;
  77
  78 typedef struct MchkQueue {
  79     uint16_t type;
  80 } MchkQueue;
  81
  82 typedef struct CPUS390XState {
  83     uint64_t regs[16];     /* GP registers */
  84     CPU_DoubleU fregs[16]; /* FP registers */
  85     uint32_t aregs[16];    /* access registers */
  86
  87     uint32_t fpc;          /* floating-point control register */
  88     uint32_t cc_op;
  89
  90     float_status fpu_status; /* passed to softfloat lib */
  91
  92     /* The low part of a 128-bit return, or remainder of a divide.  */
  93     uint64_t retxl;
  94
  95     PSW psw;
  96
  97     uint64_t cc_src;
  98     uint64_t cc_dst;
  99     uint64_t cc_vr;
 100
 101     uint64_t __excp_addr;
 102     uint64_t psa;
 103
 104     uint32_t int_pgm_code;
 105     uint32_t int_pgm_ilen;
 106
 107     uint32_t int_svc_code;
 108     uint32_t int_svc_ilen;
 109
 110     uint64_t cregs[16]; /* control registers */
 111
 112     ExtQueue ext_queue[MAX_EXT_QUEUE];
 113     IOIntQueue io_queue[MAX_IO_QUEUE][8];
 114     MchkQueue mchk_queue[MAX_MCHK_QUEUE];
 115
 116     int pending_int;
 117     int ext_index;
 118     int io_index[8];
 119     int mchk_index;
 120
 121     uint64_t ckc;
 122     uint64_t cputm;
 123     uint32_t todpr;
 124
 125     uint64_t pfault_token;
 126     uint64_t pfault_compare;
 127     uint64_t pfault_select;
 128
 129     uint64_t gbea;
 130     uint64_t pp;
 131
 132     CPU_COMMON
 133
 134     /* reset does memset(0) up to here */
 135
 136     int cpu_num;
 137     uint8_t *storage_keys;
 138
 139     uint64_t tod_offset;
 140     uint64_t tod_basetime;
 141     QEMUTimer *tod_timer;
 142
 143     QEMUTimer *cpu_timer;
 144 } CPUS390XState;
 145
 146 #include "cpu-qom.h"
 147 #include <sysemu/kvm.h>
 148
 149 /* distinguish between 24 bit and 31 bit addressing */
 150 #define HIGH_ORDER_BIT 0x80000000
 151
 152 /* Interrupt Codes */
 153 /* Program Interrupts */
 154 #define PGM_OPERATION                   0x0001
 155 #define PGM_PRIVILEGED                  0x0002
 156 #define PGM_EXECUTE                     0x0003
 157 #define PGM_PROTECTION                  0x0004
 158 #define PGM_ADDRESSING                  0x0005
 159 #define PGM_SPECIFICATION               0x0006
 160 #define PGM_DATA                        0x0007
 161 #define PGM_FIXPT_OVERFLOW              0x0008
 162 #define PGM_FIXPT_DIVIDE                0x0009
 163 #define PGM_DEC_OVERFLOW                0x000a
 164 #define PGM_DEC_DIVIDE                  0x000b
 165 #define PGM_HFP_EXP_OVERFLOW            0x000c
 166 #define PGM_HFP_EXP_UNDERFLOW           0x000d
 167 #define PGM_HFP_SIGNIFICANCE            0x000e
 168 #define PGM_HFP_DIVIDE                  0x000f
 169 #define PGM_SEGMENT_TRANS               0x0010
 170 #define PGM_PAGE_TRANS                  0x0011
 171 #define PGM_TRANS_SPEC                  0x0012
 172 #define PGM_SPECIAL_OP                  0x0013
 173 #define PGM_OPERAND                     0x0015
 174 #define PGM_TRACE_TABLE                 0x0016
 175 #define PGM_SPACE_SWITCH                0x001c
 176 #define PGM_HFP_SQRT                    0x001d
 177 #define PGM_PC_TRANS_SPEC               0x001f
 178 #define PGM_AFX_TRANS                   0x0020
 179 #define PGM_ASX_TRANS                   0x0021
 180 #define PGM_LX_TRANS                    0x0022
 181 #define PGM_EX_TRANS                    0x0023
 182 #define PGM_PRIM_AUTH                   0x0024
 183 #define PGM_SEC_AUTH                    0x0025
 184 #define PGM_ALET_SPEC                   0x0028
 185 #define PGM_ALEN_SPEC                   0x0029
 186 #define PGM_ALE_SEQ                     0x002a
 187 #define PGM_ASTE_VALID                  0x002b
 188 #define PGM_ASTE_SEQ                    0x002c
 189 #define PGM_EXT_AUTH                    0x002d
 190 #define PGM_STACK_FULL                  0x0030
 191 #define PGM_STACK_EMPTY                 0x0031
 192 #define PGM_STACK_SPEC                  0x0032
 193 #define PGM_STACK_TYPE                  0x0033
 194 #define PGM_STACK_OP                    0x0034
 195 #define PGM_ASCE_TYPE                   0x0038
 196 #define PGM_REG_FIRST_TRANS             0x0039
 197 #define PGM_REG_SEC_TRANS               0x003a
 198 #define PGM_REG_THIRD_TRANS             0x003b
 199 #define PGM_MONITOR                     0x0040
 200 #define PGM_PER                         0x0080
 201 #define PGM_CRYPTO                      0x0119
 202
 203 /* External Interrupts */
 204 #define EXT_INTERRUPT_KEY               0x0040
 205 #define EXT_CLOCK_COMP                  0x1004
 206 #define EXT_CPU_TIMER                   0x1005
 207 #define EXT_MALFUNCTION                 0x1200
 208 #define EXT_EMERGENCY                   0x1201
 209 #define EXT_EXTERNAL_CALL               0x1202
 210 #define EXT_ETR                         0x1406
 211 #define EXT_SERVICE                     0x2401
 212 #define EXT_VIRTIO                      0x2603
 213
 214 /* PSW defines */
 215 #undef PSW_MASK_PER
 216 #undef PSW_MASK_DAT
 217 #undef PSW_MASK_IO
 218 #undef PSW_MASK_EXT
 219 #undef PSW_MASK_KEY
 220 #undef PSW_SHIFT_KEY
 221 #undef PSW_MASK_MCHECK
 222 #undef PSW_MASK_WAIT
 223 #undef PSW_MASK_PSTATE
 224 #undef PSW_MASK_ASC
 225 #undef PSW_MASK_CC
 226 #undef PSW_MASK_PM
 227 #undef PSW_MASK_64
 228 #undef PSW_MASK_32
 229 #undef PSW_MASK_ESA_ADDR
 230
 231 #define PSW_MASK_PER            0x4000000000000000ULL
 232 #define PSW_MASK_DAT            0x0400000000000000ULL
 233 #define PSW_MASK_IO             0x0200000000000000ULL
 234 #define PSW_MASK_EXT            0x0100000000000000ULL
 235 #define PSW_MASK_KEY            0x00F0000000000000ULL
 236 #define PSW_SHIFT_KEY           56
 237 #define PSW_MASK_MCHECK         0x0004000000000000ULL
 238 #define PSW_MASK_WAIT           0x0002000000000000ULL
 239 #define PSW_MASK_PSTATE         0x0001000000000000ULL
 240 #define PSW_MASK_ASC            0x0000C00000000000ULL
 241 #define PSW_MASK_CC             0x0000300000000000ULL
 242 #define PSW_MASK_PM             0x00000F0000000000ULL
 243 #define PSW_MASK_64             0x0000000100000000ULL
 244 #define PSW_MASK_32             0x0000000080000000ULL
 245 #define PSW_MASK_ESA_ADDR       0x000000007fffffffULL
 246
 247 #undef PSW_ASC_PRIMARY
 248 #undef PSW_ASC_ACCREG
 249 #undef PSW_ASC_SECONDARY
 250 #undef PSW_ASC_HOME
 251
 252 #define PSW_ASC_PRIMARY         0x0000000000000000ULL
 253 #define PSW_ASC_ACCREG          0x0000400000000000ULL
 254 #define PSW_ASC_SECONDARY       0x0000800000000000ULL
 255 #define PSW_ASC_HOME            0x0000C00000000000ULL
 256
 257 /* tb flags */
 258
 259 #define FLAG_MASK_PER           (PSW_MASK_PER    >> 32)
 260 #define FLAG_MASK_DAT           (PSW_MASK_DAT    >> 32)
 261 #define FLAG_MASK_IO            (PSW_MASK_IO     >> 32)
 262 #define FLAG_MASK_EXT           (PSW_MASK_EXT    >> 32)
 263 #define FLAG_MASK_KEY           (PSW_MASK_KEY    >> 32)
 264 #define FLAG_MASK_MCHECK        (PSW_MASK_MCHECK >> 32)
 265 #define FLAG_MASK_WAIT          (PSW_MASK_WAIT   >> 32)
 266 #define FLAG_MASK_PSTATE        (PSW_MASK_PSTATE >> 32)
 267 #define FLAG_MASK_ASC           (PSW_MASK_ASC    >> 32)
 268 #define FLAG_MASK_CC            (PSW_MASK_CC     >> 32)
 269 #define FLAG_MASK_PM            (PSW_MASK_PM     >> 32)
 270 #define FLAG_MASK_64            (PSW_MASK_64     >> 32)
 271 #define FLAG_MASK_32            0x00001000
 272
 273 /* Control register 0 bits */
 274 #define CR0_EDAT                0x0000000000800000ULL
 275
 276 static inline int cpu_mmu_index (CPUS390XState *env)
 277 {
 278     if (env->psw.mask & PSW_MASK_PSTATE) {
 279         return 1;
 280     }
 281
 282     return 0;
 283 }
 284
 285 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
 286                                         target_ulong *cs_base, int *flags)
 287 {
 288     *pc = env->psw.addr;
 289     *cs_base = 0;
 290     *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
 291              ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
 292 }
 293
 294 /* While the PoO talks about ILC (a number between 1-3) what is actually
 295    stored in LowCore is shifted left one bit (an even between 2-6).  As
 296    this is the actual length of the insn and therefore more useful, that
 297    is what we want to pass around and manipulate.  To make sure that we
 298    have applied this distinction universally, rename the "ILC" to "ILEN".  */
 299 static inline int get_ilen(uint8_t opc)
 300 {
 301     switch (opc >> 6) {
 302     case 0:
 303         return 2;
 304     case 1:
 305     case 2:
 306         return 4;
 307     default:
 308         return 6;
 309     }
 310 }
 311
 312 #ifndef CONFIG_USER_ONLY
 313 /* In several cases of runtime exceptions, we havn't recorded the true
 314    instruction length.  Use these codes when raising exceptions in order
 315    to re-compute the length by examining the insn in memory.  */
 316 #define ILEN_LATER       0x20
 317 #define ILEN_LATER_INC   0x21
 318 #endif
 319
 320 S390CPU *cpu_s390x_init(const char *cpu_model);
 321 void s390x_translate_init(void);
 322 int cpu_s390x_exec(CPUS390XState *s);
 323
 324 /* you can call this signal handler from your SIGBUS and SIGSEGV
 325    signal handlers to inform the virtual CPU of exceptions. non zero
 326    is returned if the signal was handled by the virtual CPU.  */
 327 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
 328                            void *puc);
 329 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 330                               int mmu_idx);
 331
 332 #include "ioinst.h"
 333
 334 #ifndef CONFIG_USER_ONLY
 335 void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
 336                                    int is_write);
 337 void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
 338                                     int is_write);
 339 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb)
 340 {
 341     hwaddr addr = 0;
 342     uint8_t reg;
 343
 344     reg = ipb >> 28;
 345     if (reg > 0) {
 346         addr = env->regs[reg];
 347     }
 348     addr += (ipb >> 16) & 0xfff;
 349
 350     return addr;
 351 }
 352
 353 /* Base/displacement are at the same locations. */
 354 #define decode_basedisp_rs decode_basedisp_s
 355
 356 void s390x_tod_timer(void *opaque);
 357 void s390x_cpu_timer(void *opaque);
 358
 359 int s390_virtio_hypercall(CPUS390XState *env);
 360
 361 #ifdef CONFIG_KVM
 362 void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code);
 363 void kvm_s390_virtio_irq(S390CPU *cpu, int config_change, uint64_t token);
 364 void kvm_s390_interrupt_internal(S390CPU *cpu, int type, uint32_t parm,
 365                                  uint64_t parm64, int vm);
 366 #else
 367 static inline void kvm_s390_interrupt(S390CPU *cpu, int type, uint32_t code)
 368 {
 369 }
 370
 371 static inline void kvm_s390_virtio_irq(S390CPU *cpu, int config_change,
 372                                        uint64_t token)
 373 {
 374 }
 375
 376 static inline void kvm_s390_interrupt_internal(S390CPU *cpu, int type,
 377                                                uint32_t parm, uint64_t parm64,
 378                                                int vm)
 379 {
 380 }
 381 #endif
 382 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
 383 void s390_add_running_cpu(S390CPU *cpu);
 384 unsigned s390_del_running_cpu(S390CPU *cpu);
 385
 386 /* service interrupts are floating therefore we must not pass an cpustate */
 387 void s390_sclp_extint(uint32_t parm);
 388
 389 /* from s390-virtio-bus */
 390 extern const hwaddr virtio_size;
 391
 392 #else
 393 static inline void s390_add_running_cpu(S390CPU *cpu)
 394 {
 395 }
 396
 397 static inline unsigned s390_del_running_cpu(S390CPU *cpu)
 398 {
 399     return 0;
 400 }
 401 #endif
 402 void cpu_lock(void);
 403 void cpu_unlock(void);
 404
 405 typedef struct SubchDev SubchDev;
 406
 407 #ifndef CONFIG_USER_ONLY
 408 extern void io_subsystem_reset(void);
 409 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 410                          uint16_t schid);
 411 bool css_subch_visible(SubchDev *sch);
 412 void css_conditional_io_interrupt(SubchDev *sch);
 413 int css_do_stsch(SubchDev *sch, SCHIB *schib);
 414 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
 415 int css_do_msch(SubchDev *sch, SCHIB *schib);
 416 int css_do_xsch(SubchDev *sch);
 417 int css_do_csch(SubchDev *sch);
 418 int css_do_hsch(SubchDev *sch);
 419 int css_do_ssch(SubchDev *sch, ORB *orb);
 420 int css_do_tsch(SubchDev *sch, IRB *irb);
 421 int css_do_stcrw(CRW *crw);
 422 int css_do_tpi(IOIntCode *int_code, int lowcore);
 423 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
 424                          int rfmt, void *buf);
 425 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
 426 int css_enable_mcsse(void);
 427 int css_enable_mss(void);
 428 int css_do_rsch(SubchDev *sch);
 429 int css_do_rchp(uint8_t cssid, uint8_t chpid);
 430 bool css_present(uint8_t cssid);
 431 #else
 432 static inline SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
 433                                        uint16_t schid)
 434 {
 435     return NULL;
 436 }
 437 static inline bool css_subch_visible(SubchDev *sch)
 438 {
 439     return false;
 440 }
 441 static inline void css_conditional_io_interrupt(SubchDev *sch)
 442 {
 443 }
 444 static inline int css_do_stsch(SubchDev *sch, SCHIB *schib)
 445 {
 446     return -ENODEV;
 447 }
 448 static inline bool css_schid_final(uint8_t cssid, uint8_t ssid, uint16_t schid)
 449 {
 450     return true;
 451 }
 452 static inline int css_do_msch(SubchDev *sch, SCHIB *schib)
 453 {
 454     return -ENODEV;
 455 }
 456 static inline int css_do_xsch(SubchDev *sch)
 457 {
 458     return -ENODEV;
 459 }
 460 static inline int css_do_csch(SubchDev *sch)
 461 {
 462     return -ENODEV;
 463 }
 464 static inline int css_do_hsch(SubchDev *sch)
 465 {
 466     return -ENODEV;
 467 }
 468 static inline int css_do_ssch(SubchDev *sch, ORB *orb)
 469 {
 470     return -ENODEV;
 471 }
 472 static inline int css_do_tsch(SubchDev *sch, IRB *irb)
 473 {
 474     return -ENODEV;
 475 }
 476 static inline int css_do_stcrw(CRW *crw)
 477 {
 478     return 1;
 479 }
 480 static inline int css_do_tpi(IOIntCode *int_code, int lowcore)
 481 {
 482     return 0;
 483 }
 484 static inline int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid,
 485                                        int rfmt, uint8_t l_chpid, void *buf)
 486 {
 487     return 0;
 488 }
 489 static inline void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo)
 490 {
 491 }
 492 static inline int css_enable_mss(void)
 493 {
 494     return -EINVAL;
 495 }
 496 static inline int css_enable_mcsse(void)
 497 {
 498     return -EINVAL;
 499 }
 500 static inline int css_do_rsch(SubchDev *sch)
 501 {
 502     return -ENODEV;
 503 }
 504 static inline int css_do_rchp(uint8_t cssid, uint8_t chpid)
 505 {
 506     return -ENODEV;
 507 }
 508 static inline bool css_present(uint8_t cssid)
 509 {
 510     return false;
 511 }
 512 #endif
 513
 514 #define cpu_init(model) (&cpu_s390x_init(model)->env)
 515 #define cpu_exec cpu_s390x_exec
 516 #define cpu_gen_code cpu_s390x_gen_code
 517 #define cpu_signal_handler cpu_s390x_signal_handler
 518
 519 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 520 #define cpu_list s390_cpu_list
 521
 522 #include "exec/exec-all.h"
 523
 524 #define EXCP_EXT 1 /* external interrupt */
 525 #define EXCP_SVC 2 /* supervisor call (syscall) */
 526 #define EXCP_PGM 3 /* program interruption */
 527 #define EXCP_IO  7 /* I/O interrupt */
 528 #define EXCP_MCHK 8 /* machine check */
 529
 530 #define INTERRUPT_EXT        (1 << 0)
 531 #define INTERRUPT_TOD        (1 << 1)
 532 #define INTERRUPT_CPUTIMER   (1 << 2)
 533 #define INTERRUPT_IO         (1 << 3)
 534 #define INTERRUPT_MCHK       (1 << 4)
 535
 536 /* Program Status Word.  */
 537 #define S390_PSWM_REGNUM 0
 538 #define S390_PSWA_REGNUM 1
 539 /* General Purpose Registers.  */
 540 #define S390_R0_REGNUM 2
 541 #define S390_R1_REGNUM 3
 542 #define S390_R2_REGNUM 4
 543 #define S390_R3_REGNUM 5
 544 #define S390_R4_REGNUM 6
 545 #define S390_R5_REGNUM 7
 546 #define S390_R6_REGNUM 8
 547 #define S390_R7_REGNUM 9
 548 #define S390_R8_REGNUM 10
 549 #define S390_R9_REGNUM 11
 550 #define S390_R10_REGNUM 12
 551 #define S390_R11_REGNUM 13
 552 #define S390_R12_REGNUM 14
 553 #define S390_R13_REGNUM 15
 554 #define S390_R14_REGNUM 16
 555 #define S390_R15_REGNUM 17
 556 /* Access Registers.  */
 557 #define S390_A0_REGNUM 18
 558 #define S390_A1_REGNUM 19
 559 #define S390_A2_REGNUM 20
 560 #define S390_A3_REGNUM 21
 561 #define S390_A4_REGNUM 22
 562 #define S390_A5_REGNUM 23
 563 #define S390_A6_REGNUM 24
 564 #define S390_A7_REGNUM 25
 565 #define S390_A8_REGNUM 26
 566 #define S390_A9_REGNUM 27
 567 #define S390_A10_REGNUM 28
 568 #define S390_A11_REGNUM 29
 569 #define S390_A12_REGNUM 30
 570 #define S390_A13_REGNUM 31
 571 #define S390_A14_REGNUM 32
 572 #define S390_A15_REGNUM 33
 573 /* Floating Point Control Word.  */
 574 #define S390_FPC_REGNUM 34
 575 /* Floating Point Registers.  */
 576 #define S390_F0_REGNUM 35
 577 #define S390_F1_REGNUM 36
 578 #define S390_F2_REGNUM 37
 579 #define S390_F3_REGNUM 38
 580 #define S390_F4_REGNUM 39
 581 #define S390_F5_REGNUM 40
 582 #define S390_F6_REGNUM 41
 583 #define S390_F7_REGNUM 42
 584 #define S390_F8_REGNUM 43
 585 #define S390_F9_REGNUM 44
 586 #define S390_F10_REGNUM 45
 587 #define S390_F11_REGNUM 46
 588 #define S390_F12_REGNUM 47
 589 #define S390_F13_REGNUM 48
 590 #define S390_F14_REGNUM 49
 591 #define S390_F15_REGNUM 50
 592 /* Total.  */
 593 #define S390_NUM_REGS 51
 594
 595 /* CC optimization */
 596
 597 enum cc_op {
 598     CC_OP_CONST0 = 0,           /* CC is 0 */
 599     CC_OP_CONST1,               /* CC is 1 */
 600     CC_OP_CONST2,               /* CC is 2 */
 601     CC_OP_CONST3,               /* CC is 3 */
 602
 603     CC_OP_DYNAMIC,              /* CC calculation defined by env->cc_op */
 604     CC_OP_STATIC,               /* CC value is env->cc_op */
 605
 606     CC_OP_NZ,                   /* env->cc_dst != 0 */
 607     CC_OP_LTGT_32,              /* signed less/greater than (32bit) */
 608     CC_OP_LTGT_64,              /* signed less/greater than (64bit) */
 609     CC_OP_LTUGTU_32,            /* unsigned less/greater than (32bit) */
 610     CC_OP_LTUGTU_64,            /* unsigned less/greater than (64bit) */
 611     CC_OP_LTGT0_32,             /* signed less/greater than 0 (32bit) */
 612     CC_OP_LTGT0_64,             /* signed less/greater than 0 (64bit) */
 613
 614     CC_OP_ADD_64,               /* overflow on add (64bit) */
 615     CC_OP_ADDU_64,              /* overflow on unsigned add (64bit) */
 616     CC_OP_ADDC_64,              /* overflow on unsigned add-carry (64bit) */
 617     CC_OP_SUB_64,               /* overflow on subtraction (64bit) */
 618     CC_OP_SUBU_64,              /* overflow on unsigned subtraction (64bit) */
 619     CC_OP_SUBB_64,              /* overflow on unsigned sub-borrow (64bit) */
 620     CC_OP_ABS_64,               /* sign eval on abs (64bit) */
 621     CC_OP_NABS_64,              /* sign eval on nabs (64bit) */
 622
 623     CC_OP_ADD_32,               /* overflow on add (32bit) */
 624     CC_OP_ADDU_32,              /* overflow on unsigned add (32bit) */
 625     CC_OP_ADDC_32,              /* overflow on unsigned add-carry (32bit) */
 626     CC_OP_SUB_32,               /* overflow on subtraction (32bit) */
 627     CC_OP_SUBU_32,              /* overflow on unsigned subtraction (32bit) */
 628     CC_OP_SUBB_32,              /* overflow on unsigned sub-borrow (32bit) */
 629     CC_OP_ABS_32,               /* sign eval on abs (64bit) */
 630     CC_OP_NABS_32,              /* sign eval on nabs (64bit) */
 631
 632     CC_OP_COMP_32,              /* complement */
 633     CC_OP_COMP_64,              /* complement */
 634
 635     CC_OP_TM_32,                /* test under mask (32bit) */
 636     CC_OP_TM_64,                /* test under mask (64bit) */
 637
 638     CC_OP_NZ_F32,               /* FP dst != 0 (32bit) */
 639     CC_OP_NZ_F64,               /* FP dst != 0 (64bit) */
 640     CC_OP_NZ_F128,              /* FP dst != 0 (128bit) */
 641
 642     CC_OP_ICM,                  /* insert characters under mask */
 643     CC_OP_SLA_32,               /* Calculate shift left signed (32bit) */
 644     CC_OP_SLA_64,               /* Calculate shift left signed (64bit) */
 645     CC_OP_FLOGR,                /* find leftmost one */
 646     CC_OP_MAX
 647 };
 648
 649 static const char *cc_names[] = {
 650     [CC_OP_CONST0]    = "CC_OP_CONST0",
 651     [CC_OP_CONST1]    = "CC_OP_CONST1",
 652     [CC_OP_CONST2]    = "CC_OP_CONST2",
 653     [CC_OP_CONST3]    = "CC_OP_CONST3",
 654     [CC_OP_DYNAMIC]   = "CC_OP_DYNAMIC",
 655     [CC_OP_STATIC]    = "CC_OP_STATIC",
 656     [CC_OP_NZ]        = "CC_OP_NZ",
 657     [CC_OP_LTGT_32]   = "CC_OP_LTGT_32",
 658     [CC_OP_LTGT_64]   = "CC_OP_LTGT_64",
 659     [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
 660     [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
 661     [CC_OP_LTGT0_32]  = "CC_OP_LTGT0_32",
 662     [CC_OP_LTGT0_64]  = "CC_OP_LTGT0_64",
 663     [CC_OP_ADD_64]    = "CC_OP_ADD_64",
 664     [CC_OP_ADDU_64]   = "CC_OP_ADDU_64",
 665     [CC_OP_ADDC_64]   = "CC_OP_ADDC_64",
 666     [CC_OP_SUB_64]    = "CC_OP_SUB_64",
 667     [CC_OP_SUBU_64]   = "CC_OP_SUBU_64",
 668     [CC_OP_SUBB_64]   = "CC_OP_SUBB_64",
 669     [CC_OP_ABS_64]    = "CC_OP_ABS_64",
 670     [CC_OP_NABS_64]   = "CC_OP_NABS_64",
 671     [CC_OP_ADD_32]    = "CC_OP_ADD_32",
 672     [CC_OP_ADDU_32]   = "CC_OP_ADDU_32",
 673     [CC_OP_ADDC_32]   = "CC_OP_ADDC_32",
 674     [CC_OP_SUB_32]    = "CC_OP_SUB_32",
 675     [CC_OP_SUBU_32]   = "CC_OP_SUBU_32",
 676     [CC_OP_SUBB_32]   = "CC_OP_SUBB_32",
 677     [CC_OP_ABS_32]    = "CC_OP_ABS_32",
 678     [CC_OP_NABS_32]   = "CC_OP_NABS_32",
 679     [CC_OP_COMP_32]   = "CC_OP_COMP_32",
 680     [CC_OP_COMP_64]   = "CC_OP_COMP_64",
 681     [CC_OP_TM_32]     = "CC_OP_TM_32",
 682     [CC_OP_TM_64]     = "CC_OP_TM_64",
 683     [CC_OP_NZ_F32]    = "CC_OP_NZ_F32",
 684     [CC_OP_NZ_F64]    = "CC_OP_NZ_F64",
 685     [CC_OP_NZ_F128]   = "CC_OP_NZ_F128",
 686     [CC_OP_ICM]       = "CC_OP_ICM",
 687     [CC_OP_SLA_32]    = "CC_OP_SLA_32",
 688     [CC_OP_SLA_64]    = "CC_OP_SLA_64",
 689     [CC_OP_FLOGR]     = "CC_OP_FLOGR",
 690 };
 691
 692 static inline const char *cc_name(int cc_op)
 693 {
 694     return cc_names[cc_op];
 695 }
 696
 697 static inline void setcc(S390CPU *cpu, uint64_t cc)
 698 {
 699     CPUS390XState *env = &cpu->env;
 700
 701     env->psw.mask &= ~(3ull << 44);
 702     env->psw.mask |= (cc & 3) << 44;
 703 }
 704
 705 typedef struct LowCore
 706 {
 707     /* prefix area: defined by architecture */
 708     uint32_t        ccw1[2];                  /* 0x000 */
 709     uint32_t        ccw2[4];                  /* 0x008 */
 710     uint8_t         pad1[0x80-0x18];          /* 0x018 */
 711     uint32_t        ext_params;               /* 0x080 */
 712     uint16_t        cpu_addr;                 /* 0x084 */
 713     uint16_t        ext_int_code;             /* 0x086 */
 714     uint16_t        svc_ilen;                 /* 0x088 */
 715     uint16_t        svc_code;                 /* 0x08a */
 716     uint16_t        pgm_ilen;                 /* 0x08c */
 717     uint16_t        pgm_code;                 /* 0x08e */
 718     uint32_t        data_exc_code;            /* 0x090 */
 719     uint16_t        mon_class_num;            /* 0x094 */
 720     uint16_t        per_perc_atmid;           /* 0x096 */
 721     uint64_t        per_address;              /* 0x098 */
 722     uint8_t         exc_access_id;            /* 0x0a0 */
 723     uint8_t         per_access_id;            /* 0x0a1 */
 724     uint8_t         op_access_id;             /* 0x0a2 */
 725     uint8_t         ar_access_id;             /* 0x0a3 */
 726     uint8_t         pad2[0xA8-0xA4];          /* 0x0a4 */
 727     uint64_t        trans_exc_code;           /* 0x0a8 */
 728     uint64_t        monitor_code;             /* 0x0b0 */
 729     uint16_t        subchannel_id;            /* 0x0b8 */
 730     uint16_t        subchannel_nr;            /* 0x0ba */
 731     uint32_t        io_int_parm;              /* 0x0bc */
 732     uint32_t        io_int_word;              /* 0x0c0 */
 733     uint8_t         pad3[0xc8-0xc4];          /* 0x0c4 */
 734     uint32_t        stfl_fac_list;            /* 0x0c8 */
 735     uint8_t         pad4[0xe8-0xcc];          /* 0x0cc */
 736     uint32_t        mcck_interruption_code[2]; /* 0x0e8 */
 737     uint8_t         pad5[0xf4-0xf0];          /* 0x0f0 */
 738     uint32_t        external_damage_code;     /* 0x0f4 */
 739     uint64_t        failing_storage_address;  /* 0x0f8 */
 740     uint8_t         pad6[0x120-0x100];        /* 0x100 */
 741     PSW             restart_old_psw;          /* 0x120 */
 742     PSW             external_old_psw;         /* 0x130 */
 743     PSW             svc_old_psw;              /* 0x140 */
 744     PSW             program_old_psw;          /* 0x150 */
 745     PSW             mcck_old_psw;             /* 0x160 */
 746     PSW             io_old_psw;               /* 0x170 */
 747     uint8_t         pad7[0x1a0-0x180];        /* 0x180 */
 748     PSW             restart_psw;              /* 0x1a0 */
 749     PSW             external_new_psw;         /* 0x1b0 */
 750     PSW             svc_new_psw;              /* 0x1c0 */
 751     PSW             program_new_psw;          /* 0x1d0 */
 752     PSW             mcck_new_psw;             /* 0x1e0 */
 753     PSW             io_new_psw;               /* 0x1f0 */
 754     PSW             return_psw;               /* 0x200 */
 755     uint8_t         irb[64];                  /* 0x210 */
 756     uint64_t        sync_enter_timer;         /* 0x250 */
 757     uint64_t        async_enter_timer;        /* 0x258 */
 758     uint64_t        exit_timer;               /* 0x260 */
 759     uint64_t        last_update_timer;        /* 0x268 */
 760     uint64_t        user_timer;               /* 0x270 */
 761     uint64_t        system_timer;             /* 0x278 */
 762     uint64_t        last_update_clock;        /* 0x280 */
 763     uint64_t        steal_clock;              /* 0x288 */
 764     PSW             return_mcck_psw;          /* 0x290 */
 765     uint8_t         pad8[0xc00-0x2a0];        /* 0x2a0 */
 766     /* System info area */
 767     uint64_t        save_area[16];            /* 0xc00 */
 768     uint8_t         pad9[0xd40-0xc80];        /* 0xc80 */
 769     uint64_t        kernel_stack;             /* 0xd40 */
 770     uint64_t        thread_info;              /* 0xd48 */
 771     uint64_t        async_stack;              /* 0xd50 */
 772     uint64_t        kernel_asce;              /* 0xd58 */
 773     uint64_t        user_asce;                /* 0xd60 */
 774     uint64_t        panic_stack;              /* 0xd68 */
 775     uint64_t        user_exec_asce;           /* 0xd70 */
 776     uint8_t         pad10[0xdc0-0xd78];       /* 0xd78 */
 777
 778     /* SMP info area: defined by DJB */
 779     uint64_t        clock_comparator;         /* 0xdc0 */
 780     uint64_t        ext_call_fast;            /* 0xdc8 */
 781     uint64_t        percpu_offset;            /* 0xdd0 */
 782     uint64_t        current_task;             /* 0xdd8 */
 783     uint32_t        softirq_pending;          /* 0xde0 */
 784     uint32_t        pad_0x0de4;               /* 0xde4 */
 785     uint64_t        int_clock;                /* 0xde8 */
 786     uint8_t         pad12[0xe00-0xdf0];       /* 0xdf0 */
 787
 788     /* 0xe00 is used as indicator for dump tools */
 789     /* whether the kernel died with panic() or not */
 790     uint32_t        panic_magic;              /* 0xe00 */
 791
 792     uint8_t         pad13[0x11b8-0xe04];      /* 0xe04 */
 793
 794     /* 64 bit extparam used for pfault, diag 250 etc  */
 795     uint64_t        ext_params2;               /* 0x11B8 */
 796
 797     uint8_t         pad14[0x1200-0x11C0];      /* 0x11C0 */
 798
 799     /* System info area */
 800
 801     uint64_t        floating_pt_save_area[16]; /* 0x1200 */
 802     uint64_t        gpregs_save_area[16];      /* 0x1280 */
 803     uint32_t        st_status_fixed_logout[4]; /* 0x1300 */
 804     uint8_t         pad15[0x1318-0x1310];      /* 0x1310 */
 805     uint32_t        prefixreg_save_area;       /* 0x1318 */
 806     uint32_t        fpt_creg_save_area;        /* 0x131c */
 807     uint8_t         pad16[0x1324-0x1320];      /* 0x1320 */
 808     uint32_t        tod_progreg_save_area;     /* 0x1324 */
 809     uint32_t        cpu_timer_save_area[2];    /* 0x1328 */
 810     uint32_t        clock_comp_save_area[2];   /* 0x1330 */
 811     uint8_t         pad17[0x1340-0x1338];      /* 0x1338 */
 812     uint32_t        access_regs_save_area[16]; /* 0x1340 */
 813     uint64_t        cregs_save_area[16];       /* 0x1380 */
 814
 815     /* align to the top of the prefix area */
 816
 817     uint8_t         pad18[0x2000-0x1400];      /* 0x1400 */
 818 } QEMU_PACKED LowCore;
 819
 820 /* STSI */
 821 #define STSI_LEVEL_MASK         0x00000000f0000000ULL
 822 #define STSI_LEVEL_CURRENT      0x0000000000000000ULL
 823 #define STSI_LEVEL_1            0x0000000010000000ULL
 824 #define STSI_LEVEL_2            0x0000000020000000ULL
 825 #define STSI_LEVEL_3            0x0000000030000000ULL
 826 #define STSI_R0_RESERVED_MASK   0x000000000fffff00ULL
 827 #define STSI_R0_SEL1_MASK       0x00000000000000ffULL
 828 #define STSI_R1_RESERVED_MASK   0x00000000ffff0000ULL
 829 #define STSI_R1_SEL2_MASK       0x000000000000ffffULL
 830
 831 /* Basic Machine Configuration */
 832 struct sysib_111 {
 833     uint32_t res1[8];
 834     uint8_t  manuf[16];
 835     uint8_t  type[4];
 836     uint8_t  res2[12];
 837     uint8_t  model[16];
 838     uint8_t  sequence[16];
 839     uint8_t  plant[4];
 840     uint8_t  res3[156];
 841 };
 842
 843 /* Basic Machine CPU */
 844 struct sysib_121 {
 845     uint32_t res1[80];
 846     uint8_t  sequence[16];
 847     uint8_t  plant[4];
 848     uint8_t  res2[2];
 849     uint16_t cpu_addr;
 850     uint8_t  res3[152];
 851 };
 852
 853 /* Basic Machine CPUs */
 854 struct sysib_122 {
 855     uint8_t res1[32];
 856     uint32_t capability;
 857     uint16_t total_cpus;
 858     uint16_t active_cpus;
 859     uint16_t standby_cpus;
 860     uint16_t reserved_cpus;
 861     uint16_t adjustments[2026];
 862 };
 863
 864 /* LPAR CPU */
 865 struct sysib_221 {
 866     uint32_t res1[80];
 867     uint8_t  sequence[16];
 868     uint8_t  plant[4];
 869     uint16_t cpu_id;
 870     uint16_t cpu_addr;
 871     uint8_t  res3[152];
 872 };
 873
 874 /* LPAR CPUs */
 875 struct sysib_222 {
 876     uint32_t res1[32];
 877     uint16_t lpar_num;
 878     uint8_t  res2;
 879     uint8_t  lcpuc;
 880     uint16_t total_cpus;
 881     uint16_t conf_cpus;
 882     uint16_t standby_cpus;
 883     uint16_t reserved_cpus;
 884     uint8_t  name[8];
 885     uint32_t caf;
 886     uint8_t  res3[16];
 887     uint16_t dedicated_cpus;
 888     uint16_t shared_cpus;
 889     uint8_t  res4[180];
 890 };
 891
 892 /* VM CPUs */
 893 struct sysib_322 {
 894     uint8_t  res1[31];
 895     uint8_t  count;
 896     struct {
 897         uint8_t  res2[4];
 898         uint16_t total_cpus;
 899         uint16_t conf_cpus;
 900         uint16_t standby_cpus;
 901         uint16_t reserved_cpus;
 902         uint8_t  name[8];
 903         uint32_t caf;
 904         uint8_t  cpi[16];
 905         uint8_t  res3[24];
 906     } vm[8];
 907     uint8_t res4[3552];
 908 };
 909
 910 /* MMU defines */
 911 #define _ASCE_ORIGIN            ~0xfffULL /* segment table origin             */
 912 #define _ASCE_SUBSPACE          0x200     /* subspace group control           */
 913 #define _ASCE_PRIVATE_SPACE     0x100     /* private space control            */
 914 #define _ASCE_ALT_EVENT         0x80      /* storage alteration event control */
 915 #define _ASCE_SPACE_SWITCH      0x40      /* space switch event               */
 916 #define _ASCE_REAL_SPACE        0x20      /* real space control               */
 917 #define _ASCE_TYPE_MASK         0x0c      /* asce table type mask             */
 918 #define _ASCE_TYPE_REGION1      0x0c      /* region first table type          */
 919 #define _ASCE_TYPE_REGION2      0x08      /* region second table type         */
 920 #define _ASCE_TYPE_REGION3      0x04      /* region third table type          */
 921 #define _ASCE_TYPE_SEGMENT      0x00      /* segment table type               */
 922 #define _ASCE_TABLE_LENGTH      0x03      /* region table length              */
 923
 924 #define _REGION_ENTRY_ORIGIN    ~0xfffULL /* region/segment table origin      */
 925 #define _REGION_ENTRY_INV       0x20      /* invalid region table entry       */
 926 #define _REGION_ENTRY_TYPE_MASK 0x0c      /* region/segment table type mask   */
 927 #define _REGION_ENTRY_TYPE_R1   0x0c      /* region first table type          */
 928 #define _REGION_ENTRY_TYPE_R2   0x08      /* region second table type         */
 929 #define _REGION_ENTRY_TYPE_R3   0x04      /* region third table type          */
 930 #define _REGION_ENTRY_LENGTH    0x03      /* region third length              */
 931
 932 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffULL /* segment table origin             */
 933 #define _SEGMENT_ENTRY_FC       0x400     /* format control                   */
 934 #define _SEGMENT_ENTRY_RO       0x200     /* page protection bit              */
 935 #define _SEGMENT_ENTRY_INV      0x20      /* invalid segment table entry      */
 936
 937 #define _PAGE_RO        0x200            /* HW read-only bit  */
 938 #define _PAGE_INVALID   0x400            /* HW invalid bit    */
 939
 940 #define SK_C                    (0x1 << 1)
 941 #define SK_R                    (0x1 << 2)
 942 #define SK_F                    (0x1 << 3)
 943 #define SK_ACC_MASK             (0xf << 4)
 944
 945 #define SIGP_SENSE             0x01
 946 #define SIGP_EXTERNAL_CALL     0x02
 947 #define SIGP_EMERGENCY         0x03
 948 #define SIGP_START             0x04
 949 #define SIGP_STOP              0x05
 950 #define SIGP_RESTART           0x06
 951 #define SIGP_STOP_STORE_STATUS 0x09
 952 #define SIGP_INITIAL_CPU_RESET 0x0b
 953 #define SIGP_CPU_RESET         0x0c
 954 #define SIGP_SET_PREFIX        0x0d
 955 #define SIGP_STORE_STATUS_ADDR 0x0e
 956 #define SIGP_SET_ARCH          0x12
 957
 958 /* cpu status bits */
 959 #define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
 960 #define SIGP_STAT_INCORRECT_STATE   0x00000200UL
 961 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
 962 #define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
 963 #define SIGP_STAT_STOPPED           0x00000040UL
 964 #define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
 965 #define SIGP_STAT_CHECK_STOP        0x00000010UL
 966 #define SIGP_STAT_INOPERATIVE       0x00000004UL
 967 #define SIGP_STAT_INVALID_ORDER     0x00000002UL
 968 #define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
 969
 970 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
 971 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
 972                   target_ulong *raddr, int *flags);
 973 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
 974 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
 975                  uint64_t vr);
 976
 977 #define TARGET_HAS_ICE 1
 978
 979 /* The value of the TOD clock for 1.1.1970. */
 980 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
 981
 982 /* Converts ns to s390's clock format */
 983 static inline uint64_t time2tod(uint64_t ns) {
 984     return (ns << 9) / 125;
 985 }
 986
 987 static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
 988                                   uint64_t param64)
 989 {
 990     CPUS390XState *env = &cpu->env;
 991
 992     if (env->ext_index == MAX_EXT_QUEUE - 1) {
 993         /* ugh - can't queue anymore. Let's drop. */
 994         return;
 995     }
 996
 997     env->ext_index++;
 998     assert(env->ext_index < MAX_EXT_QUEUE);
 999
1000     env->ext_queue[env->ext_index].code = code;
1001     env->ext_queue[env->ext_index].param = param;
1002     env->ext_queue[env->ext_index].param64 = param64;
1003
1004     env->pending_int |= INTERRUPT_EXT;
1005     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1006 }
1007
1008 static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1009                                  uint16_t subchannel_number,
1010                                  uint32_t io_int_parm, uint32_t io_int_word)
1011 {
1012     CPUS390XState *env = &cpu->env;
1013     int isc = IO_INT_WORD_ISC(io_int_word);
1014
1015     if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1016         /* ugh - can't queue anymore. Let's drop. */
1017         return;
1018     }
1019
1020     env->io_index[isc]++;
1021     assert(env->io_index[isc] < MAX_IO_QUEUE);
1022
1023     env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1024     env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1025     env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1026     env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1027
1028     env->pending_int |= INTERRUPT_IO;
1029     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1030 }
1031
1032 static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1033 {
1034     CPUS390XState *env = &cpu->env;
1035
1036     if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1037         /* ugh - can't queue anymore. Let's drop. */
1038         return;
1039     }
1040
1041     env->mchk_index++;
1042     assert(env->mchk_index < MAX_MCHK_QUEUE);
1043
1044     env->mchk_queue[env->mchk_index].type = 1;
1045
1046     env->pending_int |= INTERRUPT_MCHK;
1047     cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1048 }
1049
1050 /* fpu_helper.c */
1051 uint32_t set_cc_nz_f32(float32 v);
1052 uint32_t set_cc_nz_f64(float64 v);
1053 uint32_t set_cc_nz_f128(float128 v);
1054
1055 /* misc_helper.c */
1056 #ifndef CONFIG_USER_ONLY
1057 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1058 #endif
1059 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1060 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1061                                      uintptr_t retaddr);
1062
1063 #ifdef CONFIG_KVM
1064 void kvm_s390_io_interrupt(S390CPU *cpu, uint16_t subchannel_id,
1065                            uint16_t subchannel_nr, uint32_t io_int_parm,
1066                            uint32_t io_int_word);
1067 void kvm_s390_crw_mchk(S390CPU *cpu);
1068 void kvm_s390_enable_css_support(S390CPU *cpu);
1069 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1070                                     int vq, bool assign);
1071 int kvm_s390_cpu_restart(S390CPU *cpu);
1072 #else
1073 static inline void kvm_s390_io_interrupt(S390CPU *cpu,
1074                                         uint16_t subchannel_id,
1075                                         uint16_t subchannel_nr,
1076                                         uint32_t io_int_parm,
1077                                         uint32_t io_int_word)
1078 {
1079 }
1080 static inline void kvm_s390_crw_mchk(S390CPU *cpu)
1081 {
1082 }
1083 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1084 {
1085 }
1086 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1087                                                   uint32_t sch, int vq,
1088                                                   bool assign)
1089 {
1090     return -ENOSYS;
1091 }
1092 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1093 {
1094     return -ENOSYS;
1095 }
1096 #endif
1097
1098 static inline int s390_cpu_restart(S390CPU *cpu)
1099 {
1100     if (kvm_enabled()) {
1101         return kvm_s390_cpu_restart(cpu);
1102     }
1103     return -ENOSYS;
1104 }
1105
1106 static inline void s390_io_interrupt(S390CPU *cpu,
1107                                      uint16_t subchannel_id,
1108                                      uint16_t subchannel_nr,
1109                                      uint32_t io_int_parm,
1110                                      uint32_t io_int_word)
1111 {
1112     if (kvm_enabled()) {
1113         kvm_s390_io_interrupt(cpu, subchannel_id, subchannel_nr, io_int_parm,
1114                               io_int_word);
1115     } else {
1116         cpu_inject_io(cpu, subchannel_id, subchannel_nr, io_int_parm,
1117                       io_int_word);
1118     }
1119 }
1120
1121 static inline void s390_crw_mchk(S390CPU *cpu)
1122 {
1123     if (kvm_enabled()) {
1124         kvm_s390_crw_mchk(cpu);
1125     } else {
1126         cpu_inject_crw_mchk(cpu);
1127     }
1128 }
1129
1130 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1131                                               uint32_t sch_id, int vq,
1132                                               bool assign)
1133 {
1134     if (kvm_enabled()) {
1135         return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1136     } else {
1137         return -ENOSYS;
1138     }
1139 }
1140
1141 #endif