2 * QEMU MIPS Jazz support
4 * Copyright (c) 2007-2008 Hervé Poussineau
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
27 #include "hw/mips/mips.h"
28 #include "hw/mips/cpudevs.h"
29 #include "hw/i386/pc.h"
30 #include "hw/char/serial.h"
31 #include "hw/isa/isa.h"
32 #include "hw/block/fdc.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/arch_init.h"
35 #include "hw/boards.h"
37 #include "hw/scsi/esp.h"
38 #include "hw/mips/bios.h"
39 #include "hw/loader.h"
40 #include "hw/timer/mc146818rtc.h"
41 #include "hw/timer/i8254.h"
42 #include "hw/audio/pcspk.h"
43 #include "sysemu/block-backend.h"
44 #include "hw/sysbus.h"
45 #include "exec/address-spaces.h"
46 #include "sysemu/qtest.h"
47 #include "qemu/error-report.h"
48 #include "qemu/help_option.h"
56 static void main_cpu_reset(void *opaque
)
58 MIPSCPU
*cpu
= opaque
;
63 static uint64_t rtc_read(void *opaque
, hwaddr addr
, unsigned size
)
66 address_space_read(&address_space_memory
, 0x90000071,
67 MEMTXATTRS_UNSPECIFIED
, &val
, 1);
71 static void rtc_write(void *opaque
, hwaddr addr
,
72 uint64_t val
, unsigned size
)
74 uint8_t buf
= val
& 0xff;
75 address_space_write(&address_space_memory
, 0x90000071,
76 MEMTXATTRS_UNSPECIFIED
, &buf
, 1);
79 static const MemoryRegionOps rtc_ops
= {
82 .endianness
= DEVICE_NATIVE_ENDIAN
,
85 static uint64_t dma_dummy_read(void *opaque
, hwaddr addr
,
88 /* Nothing to do. That is only to ensure that
89 * the current DMA acknowledge cycle is completed. */
93 static void dma_dummy_write(void *opaque
, hwaddr addr
,
94 uint64_t val
, unsigned size
)
96 /* Nothing to do. That is only to ensure that
97 * the current DMA acknowledge cycle is completed. */
100 static const MemoryRegionOps dma_dummy_ops
= {
101 .read
= dma_dummy_read
,
102 .write
= dma_dummy_write
,
103 .endianness
= DEVICE_NATIVE_ENDIAN
,
106 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
107 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
109 static CPUUnassignedAccess real_do_unassigned_access
;
110 static void mips_jazz_do_unassigned_access(CPUState
*cpu
, hwaddr addr
,
111 bool is_write
, bool is_exec
,
112 int opaque
, unsigned size
)
115 /* ignore invalid access (ie do not raise exception) */
118 (*real_do_unassigned_access
)(cpu
, addr
, is_write
, is_exec
, opaque
, size
);
121 static void mips_jazz_init(MachineState
*machine
,
122 enum jazz_model_e jazz_model
)
124 MemoryRegion
*address_space
= get_system_memory();
132 IOMMUMemoryRegion
*rc4030_dma_mr
;
133 MemoryRegion
*isa_mem
= g_new(MemoryRegion
, 1);
134 MemoryRegion
*isa_io
= g_new(MemoryRegion
, 1);
135 MemoryRegion
*rtc
= g_new(MemoryRegion
, 1);
136 MemoryRegion
*i8042
= g_new(MemoryRegion
, 1);
137 MemoryRegion
*dma_dummy
= g_new(MemoryRegion
, 1);
139 DeviceState
*dev
, *rc4030
;
140 SysBusDevice
*sysbus
;
143 DriveInfo
*fds
[MAX_FD
];
144 qemu_irq esp_reset
, dma_enable
;
145 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
146 MemoryRegion
*bios
= g_new(MemoryRegion
, 1);
147 MemoryRegion
*bios2
= g_new(MemoryRegion
, 1);
150 cpu
= MIPS_CPU(cpu_create(machine
->cpu_type
));
152 qemu_register_reset(main_cpu_reset
, cpu
);
154 /* Chipset returns 0 in invalid reads and do not raise data exceptions.
155 * However, we can't simply add a global memory region to catch
156 * everything, as memory core directly call unassigned_mem_read/write
157 * on some invalid accesses, which call do_unassigned_access on the
158 * CPU, which raise an exception.
159 * Handle that case by hijacking the do_unassigned_access method on
160 * the CPU, and do not raise exceptions for data access. */
161 cc
= CPU_GET_CLASS(cpu
);
162 real_do_unassigned_access
= cc
->do_unassigned_access
;
163 cc
->do_unassigned_access
= mips_jazz_do_unassigned_access
;
166 memory_region_allocate_system_memory(ram
, NULL
, "mips_jazz.ram",
168 memory_region_add_subregion(address_space
, 0, ram
);
170 memory_region_init_ram(bios
, NULL
, "mips_jazz.bios", MAGNUM_BIOS_SIZE
,
172 memory_region_set_readonly(bios
, true);
173 memory_region_init_alias(bios2
, NULL
, "mips_jazz.bios", bios
,
174 0, MAGNUM_BIOS_SIZE
);
175 memory_region_add_subregion(address_space
, 0x1fc00000LL
, bios
);
176 memory_region_add_subregion(address_space
, 0xfff00000LL
, bios2
);
178 /* load the BIOS image. */
179 if (bios_name
== NULL
)
180 bios_name
= BIOS_FILENAME
;
181 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
183 bios_size
= load_image_targphys(filename
, 0xfff00000LL
,
189 if ((bios_size
< 0 || bios_size
> MAGNUM_BIOS_SIZE
) && !qtest_enabled()) {
190 error_report("Could not load MIPS bios '%s'", bios_name
);
194 /* Init CPU internal devices */
195 cpu_mips_irq_init_cpu(cpu
);
196 cpu_mips_clock_init(cpu
);
199 rc4030
= rc4030_init(&dmas
, &rc4030_dma_mr
);
200 sysbus
= SYS_BUS_DEVICE(rc4030
);
201 sysbus_connect_irq(sysbus
, 0, env
->irq
[6]);
202 sysbus_connect_irq(sysbus
, 1, env
->irq
[3]);
203 memory_region_add_subregion(address_space
, 0x80000000,
204 sysbus_mmio_get_region(sysbus
, 0));
205 memory_region_add_subregion(address_space
, 0xf0000000,
206 sysbus_mmio_get_region(sysbus
, 1));
207 memory_region_init_io(dma_dummy
, NULL
, &dma_dummy_ops
, NULL
, "dummy_dma", 0x1000);
208 memory_region_add_subregion(address_space
, 0x8000d000, dma_dummy
);
210 /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
211 memory_region_init(isa_io
, NULL
, "isa-io", 0x00010000);
212 memory_region_init(isa_mem
, NULL
, "isa-mem", 0x01000000);
213 memory_region_add_subregion(address_space
, 0x90000000, isa_io
);
214 memory_region_add_subregion(address_space
, 0x91000000, isa_mem
);
215 isa_bus
= isa_bus_new(NULL
, isa_mem
, isa_io
, &error_abort
);
218 i8259
= i8259_init(isa_bus
, env
->irq
[4]);
219 isa_bus_irqs(isa_bus
, i8259
);
220 DMA_init(isa_bus
, 0);
221 pit
= i8254_pit_init(isa_bus
, 0x40, 0, NULL
);
222 pcspk_init(isa_bus
, pit
);
225 switch (jazz_model
) {
227 dev
= qdev_create(NULL
, "sysbus-g364");
228 qdev_init_nofail(dev
);
229 sysbus
= SYS_BUS_DEVICE(dev
);
230 sysbus_mmio_map(sysbus
, 0, 0x60080000);
231 sysbus_mmio_map(sysbus
, 1, 0x40000000);
232 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(rc4030
, 3));
234 /* Simple ROM, so user doesn't have to provide one */
235 MemoryRegion
*rom_mr
= g_new(MemoryRegion
, 1);
236 memory_region_init_ram(rom_mr
, NULL
, "g364fb.rom", 0x80000,
238 memory_region_set_readonly(rom_mr
, true);
239 uint8_t *rom
= memory_region_get_ram_ptr(rom_mr
);
240 memory_region_add_subregion(address_space
, 0x60000000, rom_mr
);
241 rom
[0] = 0x10; /* Mips G364 */
245 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
251 /* Network controller */
252 for (n
= 0; n
< nb_nics
; n
++) {
255 nd
->model
= g_strdup("dp83932");
256 if (strcmp(nd
->model
, "dp83932") == 0) {
257 qemu_check_nic_model(nd
, "dp83932");
259 dev
= qdev_create(NULL
, "dp8393x");
260 qdev_set_nic_properties(dev
, nd
);
261 qdev_prop_set_uint8(dev
, "it_shift", 2);
262 qdev_prop_set_ptr(dev
, "dma_mr", rc4030_dma_mr
);
263 qdev_init_nofail(dev
);
264 sysbus
= SYS_BUS_DEVICE(dev
);
265 sysbus_mmio_map(sysbus
, 0, 0x80001000);
266 sysbus_mmio_map(sysbus
, 1, 0x8000b000);
267 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(rc4030
, 4));
269 } else if (is_help_option(nd
->model
)) {
270 fprintf(stderr
, "qemu: Supported NICs: dp83932\n");
273 fprintf(stderr
, "qemu: Unsupported NIC: %s\n", nd
->model
);
279 esp_init(0x80002000, 0,
280 rc4030_dma_read
, rc4030_dma_write
, dmas
[0],
281 qdev_get_gpio_in(rc4030
, 5), &esp_reset
, &dma_enable
);
284 for (n
= 0; n
< MAX_FD
; n
++) {
285 fds
[n
] = drive_get(IF_FLOPPY
, 0, n
);
287 /* FIXME: we should enable DMA with a custom IsaDma device */
288 fdctrl_init_sysbus(qdev_get_gpio_in(rc4030
, 1), -1, 0x80003000, fds
);
290 /* Real time clock */
291 rtc_init(isa_bus
, 1980, NULL
);
292 memory_region_init_io(rtc
, NULL
, &rtc_ops
, NULL
, "rtc", 0x1000);
293 memory_region_add_subregion(address_space
, 0x80004000, rtc
);
295 /* Keyboard (i8042) */
296 i8042_mm_init(qdev_get_gpio_in(rc4030
, 6), qdev_get_gpio_in(rc4030
, 7),
298 memory_region_add_subregion(address_space
, 0x80005000, i8042
);
302 serial_mm_init(address_space
, 0x80006000, 0,
303 qdev_get_gpio_in(rc4030
, 8), 8000000/16,
304 serial_hds
[0], DEVICE_NATIVE_ENDIAN
);
307 serial_mm_init(address_space
, 0x80007000, 0,
308 qdev_get_gpio_in(rc4030
, 9), 8000000/16,
309 serial_hds
[1], DEVICE_NATIVE_ENDIAN
);
314 parallel_mm_init(address_space
, 0x80008000, 0,
315 qdev_get_gpio_in(rc4030
, 0), parallel_hds
[0]);
317 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
320 dev
= qdev_create(NULL
, "ds1225y");
321 qdev_init_nofail(dev
);
322 sysbus
= SYS_BUS_DEVICE(dev
);
323 sysbus_mmio_map(sysbus
, 0, 0x80009000);
326 sysbus_create_simple("jazz-led", 0x8000f000, NULL
);
330 void mips_magnum_init(MachineState
*machine
)
332 mips_jazz_init(machine
, JAZZ_MAGNUM
);
336 void mips_pica61_init(MachineState
*machine
)
338 mips_jazz_init(machine
, JAZZ_PICA61
);
341 static void mips_magnum_class_init(ObjectClass
*oc
, void *data
)
343 MachineClass
*mc
= MACHINE_CLASS(oc
);
345 mc
->desc
= "MIPS Magnum";
346 mc
->init
= mips_magnum_init
;
347 mc
->block_default_type
= IF_SCSI
;
348 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("R4000");
351 static const TypeInfo mips_magnum_type
= {
352 .name
= MACHINE_TYPE_NAME("magnum"),
353 .parent
= TYPE_MACHINE
,
354 .class_init
= mips_magnum_class_init
,
357 static void mips_pica61_class_init(ObjectClass
*oc
, void *data
)
359 MachineClass
*mc
= MACHINE_CLASS(oc
);
361 mc
->desc
= "Acer Pica 61";
362 mc
->init
= mips_pica61_init
;
363 mc
->block_default_type
= IF_SCSI
;
364 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("R4000");
367 static const TypeInfo mips_pica61_type
= {
368 .name
= MACHINE_TYPE_NAME("pica61"),
369 .parent
= TYPE_MACHINE
,
370 .class_init
= mips_pica61_class_init
,
373 static void mips_jazz_machine_init(void)
375 type_register_static(&mips_magnum_type
);
376 type_register_static(&mips_pica61_type
);
379 type_init(mips_jazz_machine_init
)