4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
40 static TCGv_i64 cpu_X
[32];
41 static TCGv_i64 cpu_pc
;
43 /* Load/store exclusive handling */
44 static TCGv_i64 cpu_exclusive_high
;
45 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
);
47 static const char *regnames
[] = {
48 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
49 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
50 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
51 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
55 A64_SHIFT_TYPE_LSL
= 0,
56 A64_SHIFT_TYPE_LSR
= 1,
57 A64_SHIFT_TYPE_ASR
= 2,
58 A64_SHIFT_TYPE_ROR
= 3
61 /* Table based decoder typedefs - used when the relevant bits for decode
62 * are too awkwardly scattered across the instruction (eg SIMD).
64 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
66 typedef struct AArch64DecodeTable
{
69 AArch64DecodeFn
*disas_fn
;
72 /* Function prototype for gen_ functions for calling Neon helpers */
73 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
74 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
75 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
77 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
79 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
80 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
81 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
82 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
83 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
84 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
85 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
86 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
87 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
89 /* Note that the gvec expanders operate on offsets + sizes. */
90 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
91 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
93 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
94 uint32_t, uint32_t, uint32_t);
96 /* initialize TCG globals. */
97 void a64_translate_init(void)
101 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
102 offsetof(CPUARMState
, pc
),
104 for (i
= 0; i
< 32; i
++) {
105 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
106 offsetof(CPUARMState
, xregs
[i
]),
110 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
111 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
114 static inline int get_a64_user_mem_index(DisasContext
*s
)
116 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
117 * if EL1, access as if EL0; otherwise access at current EL
121 switch (s
->mmu_idx
) {
122 case ARMMMUIdx_S12NSE1
:
123 useridx
= ARMMMUIdx_S12NSE0
;
125 case ARMMMUIdx_S1SE1
:
126 useridx
= ARMMMUIdx_S1SE0
;
129 g_assert_not_reached();
131 useridx
= s
->mmu_idx
;
134 return arm_to_core_mmu_idx(useridx
);
137 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
138 fprintf_function cpu_fprintf
, int flags
)
140 ARMCPU
*cpu
= ARM_CPU(cs
);
141 CPUARMState
*env
= &cpu
->env
;
142 uint32_t psr
= pstate_read(env
);
144 int el
= arm_current_el(env
);
145 const char *ns_status
;
147 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
148 env
->pc
, env
->xregs
[31]);
149 for (i
= 0; i
< 31; i
++) {
150 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
152 cpu_fprintf(f
, "\n");
158 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
159 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
164 cpu_fprintf(f
, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
166 psr
& PSTATE_N
? 'N' : '-',
167 psr
& PSTATE_Z
? 'Z' : '-',
168 psr
& PSTATE_C
? 'C' : '-',
169 psr
& PSTATE_V
? 'V' : '-',
172 psr
& PSTATE_SP
? 'h' : 't');
174 if (flags
& CPU_DUMP_FPU
) {
176 for (i
= 0; i
< numvfpregs
; i
++) {
177 uint64_t *q
= aa64_vfp_qreg(env
, i
);
180 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"%c",
181 i
, vhi
, vlo
, (i
& 1 ? '\n' : ' '));
183 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
184 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
188 void gen_a64_set_pc_im(uint64_t val
)
190 tcg_gen_movi_i64(cpu_pc
, val
);
193 /* Load the PC from a generic TCG variable.
195 * If address tagging is enabled via the TCR TBI bits, then loading
196 * an address into the PC will clear out any tag in the it:
197 * + for EL2 and EL3 there is only one TBI bit, and if it is set
198 * then the address is zero-extended, clearing bits [63:56]
199 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
200 * and TBI1 controls addressses with bit 55 == 1.
201 * If the appropriate TBI bit is set for the address then
202 * the address is sign-extended from bit 55 into bits [63:56]
204 * We can avoid doing this for relative-branches, because the
205 * PC + offset can never overflow into the tag bits (assuming
206 * that virtual addresses are less than 56 bits wide, as they
207 * are currently), but we must handle it for branch-to-register.
209 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
212 if (s
->current_el
<= 1) {
213 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
214 * examine bit 55 of address, can just generate code.
215 * If mixed, then test via generated code
217 if (s
->tbi0
&& s
->tbi1
) {
218 TCGv_i64 tmp_reg
= tcg_temp_new_i64();
219 /* Both bits set, sign extension from bit 55 into [63:56] will
222 tcg_gen_shli_i64(tmp_reg
, src
, 8);
223 tcg_gen_sari_i64(cpu_pc
, tmp_reg
, 8);
224 tcg_temp_free_i64(tmp_reg
);
225 } else if (!s
->tbi0
&& !s
->tbi1
) {
226 /* Neither bit set, just load it as-is */
227 tcg_gen_mov_i64(cpu_pc
, src
);
229 TCGv_i64 tcg_tmpval
= tcg_temp_new_i64();
230 TCGv_i64 tcg_bit55
= tcg_temp_new_i64();
231 TCGv_i64 tcg_zero
= tcg_const_i64(0);
233 tcg_gen_andi_i64(tcg_bit55
, src
, (1ull << 55));
236 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
237 tcg_gen_andi_i64(tcg_tmpval
, src
,
238 0x00FFFFFFFFFFFFFFull
);
239 tcg_gen_movcond_i64(TCG_COND_EQ
, cpu_pc
, tcg_bit55
, tcg_zero
,
242 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
243 tcg_gen_ori_i64(tcg_tmpval
, src
,
244 0xFF00000000000000ull
);
245 tcg_gen_movcond_i64(TCG_COND_NE
, cpu_pc
, tcg_bit55
, tcg_zero
,
248 tcg_temp_free_i64(tcg_zero
);
249 tcg_temp_free_i64(tcg_bit55
);
250 tcg_temp_free_i64(tcg_tmpval
);
252 } else { /* EL > 1 */
254 /* Force tag byte to all zero */
255 tcg_gen_andi_i64(cpu_pc
, src
, 0x00FFFFFFFFFFFFFFull
);
257 /* Load unmodified address */
258 tcg_gen_mov_i64(cpu_pc
, src
);
263 typedef struct DisasCompare64
{
268 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
272 arm_test_cc(&c32
, cc
);
274 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
275 * properly. The NE/EQ comparisons are also fine with this choice. */
276 c64
->cond
= c32
.cond
;
277 c64
->value
= tcg_temp_new_i64();
278 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
283 static void a64_free_cc(DisasCompare64
*c64
)
285 tcg_temp_free_i64(c64
->value
);
288 static void gen_exception_internal(int excp
)
290 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
292 assert(excp_is_internal(excp
));
293 gen_helper_exception_internal(cpu_env
, tcg_excp
);
294 tcg_temp_free_i32(tcg_excp
);
297 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
299 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
300 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
301 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
303 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
305 tcg_temp_free_i32(tcg_el
);
306 tcg_temp_free_i32(tcg_syn
);
307 tcg_temp_free_i32(tcg_excp
);
310 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
312 gen_a64_set_pc_im(s
->pc
- offset
);
313 gen_exception_internal(excp
);
314 s
->base
.is_jmp
= DISAS_NORETURN
;
317 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
318 uint32_t syndrome
, uint32_t target_el
)
320 gen_a64_set_pc_im(s
->pc
- offset
);
321 gen_exception(excp
, syndrome
, target_el
);
322 s
->base
.is_jmp
= DISAS_NORETURN
;
325 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
330 gen_a64_set_pc_im(s
->pc
- offset
);
331 tcg_syn
= tcg_const_i32(syndrome
);
332 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
333 tcg_temp_free_i32(tcg_syn
);
334 s
->base
.is_jmp
= DISAS_NORETURN
;
337 static void gen_ss_advance(DisasContext
*s
)
339 /* If the singlestep state is Active-not-pending, advance to
344 gen_helper_clear_pstate_ss(cpu_env
);
348 static void gen_step_complete_exception(DisasContext
*s
)
350 /* We just completed step of an insn. Move from Active-not-pending
351 * to Active-pending, and then also take the swstep exception.
352 * This corresponds to making the (IMPDEF) choice to prioritize
353 * swstep exceptions over asynchronous exceptions taken to an exception
354 * level where debug is disabled. This choice has the advantage that
355 * we do not need to maintain internal state corresponding to the
356 * ISV/EX syndrome bits between completion of the step and generation
357 * of the exception, and our syndrome information is always correct.
360 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
361 default_exception_el(s
));
362 s
->base
.is_jmp
= DISAS_NORETURN
;
365 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
367 /* No direct tb linking with singlestep (either QEMU's or the ARM
368 * debug architecture kind) or deterministic io
370 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
371 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
375 #ifndef CONFIG_USER_ONLY
376 /* Only link tbs from inside the same guest page */
377 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
385 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
387 TranslationBlock
*tb
;
390 if (use_goto_tb(s
, n
, dest
)) {
392 gen_a64_set_pc_im(dest
);
393 tcg_gen_exit_tb((intptr_t)tb
+ n
);
394 s
->base
.is_jmp
= DISAS_NORETURN
;
396 gen_a64_set_pc_im(dest
);
398 gen_step_complete_exception(s
);
399 } else if (s
->base
.singlestep_enabled
) {
400 gen_exception_internal(EXCP_DEBUG
);
402 tcg_gen_lookup_and_goto_ptr();
403 s
->base
.is_jmp
= DISAS_NORETURN
;
408 static void unallocated_encoding(DisasContext
*s
)
410 /* Unallocated and reserved encodings are uncategorized */
411 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
412 default_exception_el(s
));
415 #define unsupported_encoding(s, insn) \
417 qemu_log_mask(LOG_UNIMP, \
418 "%s:%d: unsupported instruction encoding 0x%08x " \
419 "at pc=%016" PRIx64 "\n", \
420 __FILE__, __LINE__, insn, s->pc - 4); \
421 unallocated_encoding(s); \
424 static void init_tmp_a64_array(DisasContext
*s
)
426 #ifdef CONFIG_DEBUG_TCG
427 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
429 s
->tmp_a64_count
= 0;
432 static void free_tmp_a64(DisasContext
*s
)
435 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
436 tcg_temp_free_i64(s
->tmp_a64
[i
]);
438 init_tmp_a64_array(s
);
441 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
443 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
444 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
447 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
449 TCGv_i64 t
= new_tmp_a64(s
);
450 tcg_gen_movi_i64(t
, 0);
455 * Register access functions
457 * These functions are used for directly accessing a register in where
458 * changes to the final register value are likely to be made. If you
459 * need to use a register for temporary calculation (e.g. index type
460 * operations) use the read_* form.
462 * B1.2.1 Register mappings
464 * In instruction register encoding 31 can refer to ZR (zero register) or
465 * the SP (stack pointer) depending on context. In QEMU's case we map SP
466 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
467 * This is the point of the _sp forms.
469 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
472 return new_tmp_a64_zero(s
);
478 /* register access for when 31 == SP */
479 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
484 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
485 * representing the register contents. This TCGv is an auto-freed
486 * temporary so it need not be explicitly freed, and may be modified.
488 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
490 TCGv_i64 v
= new_tmp_a64(s
);
493 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
495 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
498 tcg_gen_movi_i64(v
, 0);
503 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
505 TCGv_i64 v
= new_tmp_a64(s
);
507 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
509 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
514 /* We should have at some point before trying to access an FP register
515 * done the necessary access check, so assert that
516 * (a) we did the check and
517 * (b) we didn't then just plough ahead anyway if it failed.
518 * Print the instruction pattern in the abort message so we can figure
519 * out what we need to fix if a user encounters this problem in the wild.
521 static inline void assert_fp_access_checked(DisasContext
*s
)
523 #ifdef CONFIG_DEBUG_TCG
524 if (unlikely(!s
->fp_access_checked
|| s
->fp_excp_el
)) {
525 fprintf(stderr
, "target-arm: FP access check missing for "
526 "instruction 0x%08x\n", s
->insn
);
532 /* Return the offset into CPUARMState of an element of specified
533 * size, 'element' places in from the least significant end of
534 * the FP/vector register Qn.
536 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
537 int element
, TCGMemOp size
)
540 #ifdef HOST_WORDS_BIGENDIAN
541 /* This is complicated slightly because vfp.zregs[n].d[0] is
542 * still the low half and vfp.zregs[n].d[1] the high half
543 * of the 128 bit vector, even on big endian systems.
544 * Calculate the offset assuming a fully bigendian 128 bits,
545 * then XOR to account for the order of the two 64 bit halves.
547 offs
+= (16 - ((element
+ 1) * (1 << size
)));
550 offs
+= element
* (1 << size
);
552 offs
+= offsetof(CPUARMState
, vfp
.zregs
[regno
]);
553 assert_fp_access_checked(s
);
557 /* Return the offset info CPUARMState of the "whole" vector register Qn. */
558 static inline int vec_full_reg_offset(DisasContext
*s
, int regno
)
560 assert_fp_access_checked(s
);
561 return offsetof(CPUARMState
, vfp
.zregs
[regno
]);
564 /* Return a newly allocated pointer to the vector register. */
565 static TCGv_ptr
vec_full_reg_ptr(DisasContext
*s
, int regno
)
567 TCGv_ptr ret
= tcg_temp_new_ptr();
568 tcg_gen_addi_ptr(ret
, cpu_env
, vec_full_reg_offset(s
, regno
));
572 /* Return the byte size of the "whole" vector register, VL / 8. */
573 static inline int vec_full_reg_size(DisasContext
*s
)
575 /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags.
576 In the meantime this is just the AdvSIMD length of 128. */
580 /* Return the offset into CPUARMState of a slice (from
581 * the least significant end) of FP register Qn (ie
583 * (Note that this is not the same mapping as for A32; see cpu.h)
585 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
587 return vec_reg_offset(s
, regno
, 0, size
);
590 /* Offset of the high half of the 128 bit vector Qn */
591 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
593 return vec_reg_offset(s
, regno
, 1, MO_64
);
596 /* Convenience accessors for reading and writing single and double
597 * FP registers. Writing clears the upper parts of the associated
598 * 128 bit vector register, as required by the architecture.
599 * Note that unlike the GP register accessors, the values returned
600 * by the read functions must be manually freed.
602 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
604 TCGv_i64 v
= tcg_temp_new_i64();
606 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
610 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
612 TCGv_i32 v
= tcg_temp_new_i32();
614 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
618 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
620 TCGv_i32 v
= tcg_temp_new_i32();
622 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
626 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
627 * If SVE is not enabled, then there are only 128 bits in the vector.
629 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
631 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
632 unsigned vsz
= vec_full_reg_size(s
);
635 TCGv_i64 tcg_zero
= tcg_const_i64(0);
636 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
637 tcg_temp_free_i64(tcg_zero
);
640 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
644 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
646 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
648 tcg_gen_st_i64(v
, cpu_env
, ofs
);
649 clear_vec_high(s
, false, reg
);
652 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
654 TCGv_i64 tmp
= tcg_temp_new_i64();
656 tcg_gen_extu_i32_i64(tmp
, v
);
657 write_fp_dreg(s
, reg
, tmp
);
658 tcg_temp_free_i64(tmp
);
661 static TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
663 TCGv_ptr statusptr
= tcg_temp_new_ptr();
666 /* In A64 all instructions (both FP and Neon) use the FPCR; there
667 * is no equivalent of the A32 Neon "standard FPSCR value".
668 * However half-precision operations operate under a different
669 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
672 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
674 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
676 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
680 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
681 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
682 GVecGen2Fn
*gvec_fn
, int vece
)
684 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
685 is_q
? 16 : 8, vec_full_reg_size(s
));
688 /* Expand a 2-operand + immediate AdvSIMD vector operation using
689 * an expander function.
691 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
692 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
694 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
695 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
698 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
699 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
700 GVecGen3Fn
*gvec_fn
, int vece
)
702 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
703 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
706 /* Expand a 2-operand + immediate AdvSIMD vector operation using
709 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
710 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
712 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
713 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
716 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
717 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
718 int rn
, int rm
, const GVecGen3
*gvec_op
)
720 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
721 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
722 vec_full_reg_size(s
), gvec_op
);
725 /* Expand a 3-operand + env pointer operation using
726 * an out-of-line helper.
728 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
729 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
731 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
732 vec_full_reg_offset(s
, rn
),
733 vec_full_reg_offset(s
, rm
), cpu_env
,
734 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
737 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
738 * an out-of-line helper.
740 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
741 int rm
, bool is_fp16
, int data
,
742 gen_helper_gvec_3_ptr
*fn
)
744 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
745 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
746 vec_full_reg_offset(s
, rn
),
747 vec_full_reg_offset(s
, rm
), fpst
,
748 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
749 tcg_temp_free_ptr(fpst
);
752 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
753 * than the 32 bit equivalent.
755 static inline void gen_set_NZ64(TCGv_i64 result
)
757 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
758 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
761 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
762 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
765 gen_set_NZ64(result
);
767 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
768 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
770 tcg_gen_movi_i32(cpu_CF
, 0);
771 tcg_gen_movi_i32(cpu_VF
, 0);
774 /* dest = T0 + T1; compute C, N, V and Z flags */
775 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
778 TCGv_i64 result
, flag
, tmp
;
779 result
= tcg_temp_new_i64();
780 flag
= tcg_temp_new_i64();
781 tmp
= tcg_temp_new_i64();
783 tcg_gen_movi_i64(tmp
, 0);
784 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
786 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
788 gen_set_NZ64(result
);
790 tcg_gen_xor_i64(flag
, result
, t0
);
791 tcg_gen_xor_i64(tmp
, t0
, t1
);
792 tcg_gen_andc_i64(flag
, flag
, tmp
);
793 tcg_temp_free_i64(tmp
);
794 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
796 tcg_gen_mov_i64(dest
, result
);
797 tcg_temp_free_i64(result
);
798 tcg_temp_free_i64(flag
);
800 /* 32 bit arithmetic */
801 TCGv_i32 t0_32
= tcg_temp_new_i32();
802 TCGv_i32 t1_32
= tcg_temp_new_i32();
803 TCGv_i32 tmp
= tcg_temp_new_i32();
805 tcg_gen_movi_i32(tmp
, 0);
806 tcg_gen_extrl_i64_i32(t0_32
, t0
);
807 tcg_gen_extrl_i64_i32(t1_32
, t1
);
808 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
809 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
810 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
811 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
812 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
813 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
815 tcg_temp_free_i32(tmp
);
816 tcg_temp_free_i32(t0_32
);
817 tcg_temp_free_i32(t1_32
);
821 /* dest = T0 - T1; compute C, N, V and Z flags */
822 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
825 /* 64 bit arithmetic */
826 TCGv_i64 result
, flag
, tmp
;
828 result
= tcg_temp_new_i64();
829 flag
= tcg_temp_new_i64();
830 tcg_gen_sub_i64(result
, t0
, t1
);
832 gen_set_NZ64(result
);
834 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
835 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
837 tcg_gen_xor_i64(flag
, result
, t0
);
838 tmp
= tcg_temp_new_i64();
839 tcg_gen_xor_i64(tmp
, t0
, t1
);
840 tcg_gen_and_i64(flag
, flag
, tmp
);
841 tcg_temp_free_i64(tmp
);
842 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
843 tcg_gen_mov_i64(dest
, result
);
844 tcg_temp_free_i64(flag
);
845 tcg_temp_free_i64(result
);
847 /* 32 bit arithmetic */
848 TCGv_i32 t0_32
= tcg_temp_new_i32();
849 TCGv_i32 t1_32
= tcg_temp_new_i32();
852 tcg_gen_extrl_i64_i32(t0_32
, t0
);
853 tcg_gen_extrl_i64_i32(t1_32
, t1
);
854 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
855 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
856 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
857 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
858 tmp
= tcg_temp_new_i32();
859 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
860 tcg_temp_free_i32(t0_32
);
861 tcg_temp_free_i32(t1_32
);
862 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
863 tcg_temp_free_i32(tmp
);
864 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
868 /* dest = T0 + T1 + CF; do not compute flags. */
869 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
871 TCGv_i64 flag
= tcg_temp_new_i64();
872 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
873 tcg_gen_add_i64(dest
, t0
, t1
);
874 tcg_gen_add_i64(dest
, dest
, flag
);
875 tcg_temp_free_i64(flag
);
878 tcg_gen_ext32u_i64(dest
, dest
);
882 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
883 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
886 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
887 result
= tcg_temp_new_i64();
888 cf_64
= tcg_temp_new_i64();
889 vf_64
= tcg_temp_new_i64();
890 tmp
= tcg_const_i64(0);
892 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
893 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
894 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
895 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
896 gen_set_NZ64(result
);
898 tcg_gen_xor_i64(vf_64
, result
, t0
);
899 tcg_gen_xor_i64(tmp
, t0
, t1
);
900 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
901 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
903 tcg_gen_mov_i64(dest
, result
);
905 tcg_temp_free_i64(tmp
);
906 tcg_temp_free_i64(vf_64
);
907 tcg_temp_free_i64(cf_64
);
908 tcg_temp_free_i64(result
);
910 TCGv_i32 t0_32
, t1_32
, tmp
;
911 t0_32
= tcg_temp_new_i32();
912 t1_32
= tcg_temp_new_i32();
913 tmp
= tcg_const_i32(0);
915 tcg_gen_extrl_i64_i32(t0_32
, t0
);
916 tcg_gen_extrl_i64_i32(t1_32
, t1
);
917 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
918 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
920 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
921 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
922 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
923 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
924 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
926 tcg_temp_free_i32(tmp
);
927 tcg_temp_free_i32(t1_32
);
928 tcg_temp_free_i32(t0_32
);
933 * Load/Store generators
937 * Store from GPR register to memory.
939 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
940 TCGv_i64 tcg_addr
, int size
, int memidx
,
942 unsigned int iss_srt
,
943 bool iss_sf
, bool iss_ar
)
946 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
951 syn
= syn_data_abort_with_iss(0,
957 0, 0, 0, 0, 0, false);
958 disas_set_insn_syndrome(s
, syn
);
962 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
963 TCGv_i64 tcg_addr
, int size
,
965 unsigned int iss_srt
,
966 bool iss_sf
, bool iss_ar
)
968 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
969 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
973 * Load from memory to GPR register
975 static void do_gpr_ld_memidx(DisasContext
*s
,
976 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
977 int size
, bool is_signed
,
978 bool extend
, int memidx
,
979 bool iss_valid
, unsigned int iss_srt
,
980 bool iss_sf
, bool iss_ar
)
982 TCGMemOp memop
= s
->be_data
+ size
;
990 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
992 if (extend
&& is_signed
) {
994 tcg_gen_ext32u_i64(dest
, dest
);
1000 syn
= syn_data_abort_with_iss(0,
1006 0, 0, 0, 0, 0, false);
1007 disas_set_insn_syndrome(s
, syn
);
1011 static void do_gpr_ld(DisasContext
*s
,
1012 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1013 int size
, bool is_signed
, bool extend
,
1014 bool iss_valid
, unsigned int iss_srt
,
1015 bool iss_sf
, bool iss_ar
)
1017 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1019 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1023 * Store from FP register to memory
1025 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1027 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1028 TCGv_i64 tmp
= tcg_temp_new_i64();
1029 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1031 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1034 bool be
= s
->be_data
== MO_BE
;
1035 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1037 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1038 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1040 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1041 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1043 tcg_temp_free_i64(tcg_hiaddr
);
1046 tcg_temp_free_i64(tmp
);
1050 * Load from memory to FP register
1052 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1054 /* This always zero-extends and writes to a full 128 bit wide vector */
1055 TCGv_i64 tmplo
= tcg_temp_new_i64();
1059 TCGMemOp memop
= s
->be_data
+ size
;
1060 tmphi
= tcg_const_i64(0);
1061 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1063 bool be
= s
->be_data
== MO_BE
;
1064 TCGv_i64 tcg_hiaddr
;
1066 tmphi
= tcg_temp_new_i64();
1067 tcg_hiaddr
= tcg_temp_new_i64();
1069 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1070 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1072 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1074 tcg_temp_free_i64(tcg_hiaddr
);
1077 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1078 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1080 tcg_temp_free_i64(tmplo
);
1081 tcg_temp_free_i64(tmphi
);
1083 clear_vec_high(s
, true, destidx
);
1087 * Vector load/store helpers.
1089 * The principal difference between this and a FP load is that we don't
1090 * zero extend as we are filling a partial chunk of the vector register.
1091 * These functions don't support 128 bit loads/stores, which would be
1092 * normal load/store operations.
1094 * The _i32 versions are useful when operating on 32 bit quantities
1095 * (eg for floating point single or using Neon helper functions).
1098 /* Get value of an element within a vector register */
1099 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1100 int element
, TCGMemOp memop
)
1102 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1105 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1108 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1111 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1114 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1117 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1120 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1124 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1127 g_assert_not_reached();
1131 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1132 int element
, TCGMemOp memop
)
1134 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1137 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1140 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1143 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1146 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1150 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1153 g_assert_not_reached();
1157 /* Set value of an element within a vector register */
1158 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1159 int element
, TCGMemOp memop
)
1161 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1164 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1167 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1170 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1173 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1176 g_assert_not_reached();
1180 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1181 int destidx
, int element
, TCGMemOp memop
)
1183 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1186 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1189 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1192 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1195 g_assert_not_reached();
1199 /* Store from vector register to memory */
1200 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1201 TCGv_i64 tcg_addr
, int size
)
1203 TCGMemOp memop
= s
->be_data
+ size
;
1204 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1206 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1207 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1209 tcg_temp_free_i64(tcg_tmp
);
1212 /* Load from memory to vector register */
1213 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1214 TCGv_i64 tcg_addr
, int size
)
1216 TCGMemOp memop
= s
->be_data
+ size
;
1217 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1219 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
1220 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1222 tcg_temp_free_i64(tcg_tmp
);
1225 /* Check that FP/Neon access is enabled. If it is, return
1226 * true. If not, emit code to generate an appropriate exception,
1227 * and return false; the caller should not emit any code for
1228 * the instruction. Note that this check must happen after all
1229 * unallocated-encoding checks (otherwise the syndrome information
1230 * for the resulting exception will be incorrect).
1232 static inline bool fp_access_check(DisasContext
*s
)
1234 assert(!s
->fp_access_checked
);
1235 s
->fp_access_checked
= true;
1237 if (!s
->fp_excp_el
) {
1241 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1246 /* Check that SVE access is enabled. If it is, return true.
1247 * If not, emit code to generate an appropriate exception and return false.
1249 static inline bool sve_access_check(DisasContext
*s
)
1251 if (s
->sve_excp_el
) {
1252 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1260 * This utility function is for doing register extension with an
1261 * optional shift. You will likely want to pass a temporary for the
1262 * destination register. See DecodeRegExtend() in the ARM ARM.
1264 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1265 int option
, unsigned int shift
)
1267 int extsize
= extract32(option
, 0, 2);
1268 bool is_signed
= extract32(option
, 2, 1);
1273 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1276 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1279 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1282 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1288 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1291 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1294 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1297 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1303 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1307 static inline void gen_check_sp_alignment(DisasContext
*s
)
1309 /* The AArch64 architecture mandates that (if enabled via PSTATE
1310 * or SCTLR bits) there is a check that SP is 16-aligned on every
1311 * SP-relative load or store (with an exception generated if it is not).
1312 * In line with general QEMU practice regarding misaligned accesses,
1313 * we omit these checks for the sake of guest program performance.
1314 * This function is provided as a hook so we can more easily add these
1315 * checks in future (possibly as a "favour catching guest program bugs
1316 * over speed" user selectable option).
1321 * This provides a simple table based table lookup decoder. It is
1322 * intended to be used when the relevant bits for decode are too
1323 * awkwardly placed and switch/if based logic would be confusing and
1324 * deeply nested. Since it's a linear search through the table, tables
1325 * should be kept small.
1327 * It returns the first handler where insn & mask == pattern, or
1328 * NULL if there is no match.
1329 * The table is terminated by an empty mask (i.e. 0)
1331 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1334 const AArch64DecodeTable
*tptr
= table
;
1336 while (tptr
->mask
) {
1337 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1338 return tptr
->disas_fn
;
1346 * The instruction disassembly implemented here matches
1347 * the instruction encoding classifications in chapter C4
1348 * of the ARM Architecture Reference Manual (DDI0487B_a);
1349 * classification names and decode diagrams here should generally
1350 * match up with those in the manual.
1353 /* Unconditional branch (immediate)
1355 * +----+-----------+-------------------------------------+
1356 * | op | 0 0 1 0 1 | imm26 |
1357 * +----+-----------+-------------------------------------+
1359 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1361 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1363 if (insn
& (1U << 31)) {
1364 /* BL Branch with link */
1365 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1368 /* B Branch / BL Branch with link */
1369 gen_goto_tb(s
, 0, addr
);
1372 /* Compare and branch (immediate)
1373 * 31 30 25 24 23 5 4 0
1374 * +----+-------------+----+---------------------+--------+
1375 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1376 * +----+-------------+----+---------------------+--------+
1378 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1380 unsigned int sf
, op
, rt
;
1382 TCGLabel
*label_match
;
1385 sf
= extract32(insn
, 31, 1);
1386 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1387 rt
= extract32(insn
, 0, 5);
1388 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1390 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1391 label_match
= gen_new_label();
1393 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1394 tcg_cmp
, 0, label_match
);
1396 gen_goto_tb(s
, 0, s
->pc
);
1397 gen_set_label(label_match
);
1398 gen_goto_tb(s
, 1, addr
);
1401 /* Test and branch (immediate)
1402 * 31 30 25 24 23 19 18 5 4 0
1403 * +----+-------------+----+-------+-------------+------+
1404 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1405 * +----+-------------+----+-------+-------------+------+
1407 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1409 unsigned int bit_pos
, op
, rt
;
1411 TCGLabel
*label_match
;
1414 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1415 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1416 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1417 rt
= extract32(insn
, 0, 5);
1419 tcg_cmp
= tcg_temp_new_i64();
1420 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1421 label_match
= gen_new_label();
1422 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1423 tcg_cmp
, 0, label_match
);
1424 tcg_temp_free_i64(tcg_cmp
);
1425 gen_goto_tb(s
, 0, s
->pc
);
1426 gen_set_label(label_match
);
1427 gen_goto_tb(s
, 1, addr
);
1430 /* Conditional branch (immediate)
1431 * 31 25 24 23 5 4 3 0
1432 * +---------------+----+---------------------+----+------+
1433 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1434 * +---------------+----+---------------------+----+------+
1436 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1441 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1442 unallocated_encoding(s
);
1445 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1446 cond
= extract32(insn
, 0, 4);
1449 /* genuinely conditional branches */
1450 TCGLabel
*label_match
= gen_new_label();
1451 arm_gen_test_cc(cond
, label_match
);
1452 gen_goto_tb(s
, 0, s
->pc
);
1453 gen_set_label(label_match
);
1454 gen_goto_tb(s
, 1, addr
);
1456 /* 0xe and 0xf are both "always" conditions */
1457 gen_goto_tb(s
, 0, addr
);
1461 /* HINT instruction group, including various allocated HINTs */
1462 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1463 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1465 unsigned int selector
= crm
<< 3 | op2
;
1468 unallocated_encoding(s
);
1476 s
->base
.is_jmp
= DISAS_WFI
;
1478 /* When running in MTTCG we don't generate jumps to the yield and
1479 * WFE helpers as it won't affect the scheduling of other vCPUs.
1480 * If we wanted to more completely model WFE/SEV so we don't busy
1481 * spin unnecessarily we would need to do something more involved.
1484 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1485 s
->base
.is_jmp
= DISAS_YIELD
;
1489 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1490 s
->base
.is_jmp
= DISAS_WFE
;
1495 /* we treat all as NOP at least for now */
1498 /* default specified as NOP equivalent */
1503 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1505 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1508 /* CLREX, DSB, DMB, ISB */
1509 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1510 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1515 unallocated_encoding(s
);
1526 case 1: /* MBReqTypes_Reads */
1527 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1529 case 2: /* MBReqTypes_Writes */
1530 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1532 default: /* MBReqTypes_All */
1533 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1539 /* We need to break the TB after this insn to execute
1540 * a self-modified code correctly and also to take
1541 * any pending interrupts immediately.
1543 gen_goto_tb(s
, 0, s
->pc
);
1546 unallocated_encoding(s
);
1551 /* MSR (immediate) - move immediate to processor state field */
1552 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1553 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1555 int op
= op1
<< 3 | op2
;
1557 case 0x05: /* SPSel */
1558 if (s
->current_el
== 0) {
1559 unallocated_encoding(s
);
1563 case 0x1e: /* DAIFSet */
1564 case 0x1f: /* DAIFClear */
1566 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1567 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1568 gen_a64_set_pc_im(s
->pc
- 4);
1569 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1570 tcg_temp_free_i32(tcg_imm
);
1571 tcg_temp_free_i32(tcg_op
);
1572 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1573 gen_a64_set_pc_im(s
->pc
);
1574 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1578 unallocated_encoding(s
);
1583 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1585 TCGv_i32 tmp
= tcg_temp_new_i32();
1586 TCGv_i32 nzcv
= tcg_temp_new_i32();
1588 /* build bit 31, N */
1589 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1590 /* build bit 30, Z */
1591 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1592 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1593 /* build bit 29, C */
1594 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1595 /* build bit 28, V */
1596 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1597 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1598 /* generate result */
1599 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1601 tcg_temp_free_i32(nzcv
);
1602 tcg_temp_free_i32(tmp
);
1605 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1608 TCGv_i32 nzcv
= tcg_temp_new_i32();
1610 /* take NZCV from R[t] */
1611 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1614 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1616 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1617 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1619 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1620 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1622 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1623 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1624 tcg_temp_free_i32(nzcv
);
1627 /* MRS - move from system register
1628 * MSR (register) - move to system register
1631 * These are all essentially the same insn in 'read' and 'write'
1632 * versions, with varying op0 fields.
1634 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1635 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1636 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1638 const ARMCPRegInfo
*ri
;
1641 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1642 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1643 crn
, crm
, op0
, op1
, op2
));
1646 /* Unknown register; this might be a guest error or a QEMU
1647 * unimplemented feature.
1649 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1650 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1651 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1652 unallocated_encoding(s
);
1656 /* Check access permissions */
1657 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1658 unallocated_encoding(s
);
1663 /* Emit code to perform further access permissions checks at
1664 * runtime; this may result in an exception.
1667 TCGv_i32 tcg_syn
, tcg_isread
;
1670 gen_a64_set_pc_im(s
->pc
- 4);
1671 tmpptr
= tcg_const_ptr(ri
);
1672 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1673 tcg_syn
= tcg_const_i32(syndrome
);
1674 tcg_isread
= tcg_const_i32(isread
);
1675 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1676 tcg_temp_free_ptr(tmpptr
);
1677 tcg_temp_free_i32(tcg_syn
);
1678 tcg_temp_free_i32(tcg_isread
);
1681 /* Handle special cases first */
1682 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1686 tcg_rt
= cpu_reg(s
, rt
);
1688 gen_get_nzcv(tcg_rt
);
1690 gen_set_nzcv(tcg_rt
);
1693 case ARM_CP_CURRENTEL
:
1694 /* Reads as current EL value from pstate, which is
1695 * guaranteed to be constant by the tb flags.
1697 tcg_rt
= cpu_reg(s
, rt
);
1698 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1701 /* Writes clear the aligned block of memory which rt points into. */
1702 tcg_rt
= cpu_reg(s
, rt
);
1703 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1708 if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1711 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1715 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1719 tcg_rt
= cpu_reg(s
, rt
);
1722 if (ri
->type
& ARM_CP_CONST
) {
1723 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1724 } else if (ri
->readfn
) {
1726 tmpptr
= tcg_const_ptr(ri
);
1727 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1728 tcg_temp_free_ptr(tmpptr
);
1730 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1733 if (ri
->type
& ARM_CP_CONST
) {
1734 /* If not forbidden by access permissions, treat as WI */
1736 } else if (ri
->writefn
) {
1738 tmpptr
= tcg_const_ptr(ri
);
1739 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1740 tcg_temp_free_ptr(tmpptr
);
1742 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1746 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1747 /* I/O operations must end the TB here (whether read or write) */
1749 s
->base
.is_jmp
= DISAS_UPDATE
;
1750 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1751 /* We default to ending the TB on a coprocessor register write,
1752 * but allow this to be suppressed by the register definition
1753 * (usually only necessary to work around guest bugs).
1755 s
->base
.is_jmp
= DISAS_UPDATE
;
1760 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1761 * +---------------------+---+-----+-----+-------+-------+-----+------+
1762 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1763 * +---------------------+---+-----+-----+-------+-------+-----+------+
1765 static void disas_system(DisasContext
*s
, uint32_t insn
)
1767 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1768 l
= extract32(insn
, 21, 1);
1769 op0
= extract32(insn
, 19, 2);
1770 op1
= extract32(insn
, 16, 3);
1771 crn
= extract32(insn
, 12, 4);
1772 crm
= extract32(insn
, 8, 4);
1773 op2
= extract32(insn
, 5, 3);
1774 rt
= extract32(insn
, 0, 5);
1777 if (l
|| rt
!= 31) {
1778 unallocated_encoding(s
);
1782 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1783 handle_hint(s
, insn
, op1
, op2
, crm
);
1785 case 3: /* CLREX, DSB, DMB, ISB */
1786 handle_sync(s
, insn
, op1
, op2
, crm
);
1788 case 4: /* MSR (immediate) */
1789 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1792 unallocated_encoding(s
);
1797 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1800 /* Exception generation
1802 * 31 24 23 21 20 5 4 2 1 0
1803 * +-----------------+-----+------------------------+-----+----+
1804 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1805 * +-----------------------+------------------------+----------+
1807 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1809 int opc
= extract32(insn
, 21, 3);
1810 int op2_ll
= extract32(insn
, 0, 5);
1811 int imm16
= extract32(insn
, 5, 16);
1816 /* For SVC, HVC and SMC we advance the single-step state
1817 * machine before taking the exception. This is architecturally
1818 * mandated, to ensure that single-stepping a system call
1819 * instruction works properly.
1824 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1825 default_exception_el(s
));
1828 if (s
->current_el
== 0) {
1829 unallocated_encoding(s
);
1832 /* The pre HVC helper handles cases when HVC gets trapped
1833 * as an undefined insn by runtime configuration.
1835 gen_a64_set_pc_im(s
->pc
- 4);
1836 gen_helper_pre_hvc(cpu_env
);
1838 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1841 if (s
->current_el
== 0) {
1842 unallocated_encoding(s
);
1845 gen_a64_set_pc_im(s
->pc
- 4);
1846 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1847 gen_helper_pre_smc(cpu_env
, tmp
);
1848 tcg_temp_free_i32(tmp
);
1850 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1853 unallocated_encoding(s
);
1859 unallocated_encoding(s
);
1863 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1867 unallocated_encoding(s
);
1870 /* HLT. This has two purposes.
1871 * Architecturally, it is an external halting debug instruction.
1872 * Since QEMU doesn't implement external debug, we treat this as
1873 * it is required for halting debug disabled: it will UNDEF.
1874 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1876 if (semihosting_enabled() && imm16
== 0xf000) {
1877 #ifndef CONFIG_USER_ONLY
1878 /* In system mode, don't allow userspace access to semihosting,
1879 * to provide some semblance of security (and for consistency
1880 * with our 32-bit semihosting).
1882 if (s
->current_el
== 0) {
1883 unsupported_encoding(s
, insn
);
1887 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1889 unsupported_encoding(s
, insn
);
1893 if (op2_ll
< 1 || op2_ll
> 3) {
1894 unallocated_encoding(s
);
1897 /* DCPS1, DCPS2, DCPS3 */
1898 unsupported_encoding(s
, insn
);
1901 unallocated_encoding(s
);
1906 /* Unconditional branch (register)
1907 * 31 25 24 21 20 16 15 10 9 5 4 0
1908 * +---------------+-------+-------+-------+------+-------+
1909 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1910 * +---------------+-------+-------+-------+------+-------+
1912 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1914 unsigned int opc
, op2
, op3
, rn
, op4
;
1916 opc
= extract32(insn
, 21, 4);
1917 op2
= extract32(insn
, 16, 5);
1918 op3
= extract32(insn
, 10, 6);
1919 rn
= extract32(insn
, 5, 5);
1920 op4
= extract32(insn
, 0, 5);
1922 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1923 unallocated_encoding(s
);
1931 gen_a64_set_pc(s
, cpu_reg(s
, rn
));
1932 /* BLR also needs to load return address */
1934 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1938 if (s
->current_el
== 0) {
1939 unallocated_encoding(s
);
1942 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
1945 gen_helper_exception_return(cpu_env
);
1946 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
1949 /* Must exit loop to check un-masked IRQs */
1950 s
->base
.is_jmp
= DISAS_EXIT
;
1954 unallocated_encoding(s
);
1956 unsupported_encoding(s
, insn
);
1960 unallocated_encoding(s
);
1964 s
->base
.is_jmp
= DISAS_JUMP
;
1967 /* Branches, exception generating and system instructions */
1968 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1970 switch (extract32(insn
, 25, 7)) {
1971 case 0x0a: case 0x0b:
1972 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1973 disas_uncond_b_imm(s
, insn
);
1975 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1976 disas_comp_b_imm(s
, insn
);
1978 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1979 disas_test_b_imm(s
, insn
);
1981 case 0x2a: /* Conditional branch (immediate) */
1982 disas_cond_b_imm(s
, insn
);
1984 case 0x6a: /* Exception generation / System */
1985 if (insn
& (1 << 24)) {
1986 disas_system(s
, insn
);
1991 case 0x6b: /* Unconditional branch (register) */
1992 disas_uncond_b_reg(s
, insn
);
1995 unallocated_encoding(s
);
2001 * Load/Store exclusive instructions are implemented by remembering
2002 * the value/address loaded, and seeing if these are the same
2003 * when the store is performed. This is not actually the architecturally
2004 * mandated semantics, but it works for typical guest code sequences
2005 * and avoids having to monitor regular stores.
2007 * The store exclusive uses the atomic cmpxchg primitives to avoid
2008 * races in multi-threaded linux-user and when MTTCG softmmu is
2011 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2012 TCGv_i64 addr
, int size
, bool is_pair
)
2014 int idx
= get_mem_index(s
);
2015 TCGMemOp memop
= s
->be_data
;
2017 g_assert(size
<= 3);
2019 g_assert(size
>= 2);
2021 /* The pair must be single-copy atomic for the doubleword. */
2022 memop
|= MO_64
| MO_ALIGN
;
2023 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2024 if (s
->be_data
== MO_LE
) {
2025 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2026 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2028 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2029 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2032 /* The pair must be single-copy atomic for *each* doubleword, not
2033 the entire quadword, however it must be quadword aligned. */
2035 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2036 memop
| MO_ALIGN_16
);
2038 TCGv_i64 addr2
= tcg_temp_new_i64();
2039 tcg_gen_addi_i64(addr2
, addr
, 8);
2040 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2041 tcg_temp_free_i64(addr2
);
2043 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2044 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2047 memop
|= size
| MO_ALIGN
;
2048 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2049 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2051 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2054 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2055 TCGv_i64 addr
, int size
, int is_pair
)
2057 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2058 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2061 * [addr + datasize] = {Rt2};
2067 * env->exclusive_addr = -1;
2069 TCGLabel
*fail_label
= gen_new_label();
2070 TCGLabel
*done_label
= gen_new_label();
2073 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2075 tmp
= tcg_temp_new_i64();
2078 if (s
->be_data
== MO_LE
) {
2079 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2081 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2083 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2084 cpu_exclusive_val
, tmp
,
2086 MO_64
| MO_ALIGN
| s
->be_data
);
2087 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2088 } else if (s
->be_data
== MO_LE
) {
2089 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2090 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2095 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2096 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2099 if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2100 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2105 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2106 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2110 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2111 cpu_reg(s
, rt
), get_mem_index(s
),
2112 size
| MO_ALIGN
| s
->be_data
);
2113 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2115 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2116 tcg_temp_free_i64(tmp
);
2117 tcg_gen_br(done_label
);
2119 gen_set_label(fail_label
);
2120 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2121 gen_set_label(done_label
);
2122 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2125 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2128 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2129 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2130 int memidx
= get_mem_index(s
);
2131 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2134 gen_check_sp_alignment(s
);
2136 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, addr
, tcg_rs
, tcg_rt
, memidx
,
2137 size
| MO_ALIGN
| s
->be_data
);
2140 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2143 TCGv_i64 s1
= cpu_reg(s
, rs
);
2144 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2145 TCGv_i64 t1
= cpu_reg(s
, rt
);
2146 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2147 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2148 int memidx
= get_mem_index(s
);
2151 gen_check_sp_alignment(s
);
2155 TCGv_i64 cmp
= tcg_temp_new_i64();
2156 TCGv_i64 val
= tcg_temp_new_i64();
2158 if (s
->be_data
== MO_LE
) {
2159 tcg_gen_concat32_i64(val
, t1
, t2
);
2160 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2162 tcg_gen_concat32_i64(val
, t2
, t1
);
2163 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2166 tcg_gen_atomic_cmpxchg_i64(cmp
, addr
, cmp
, val
, memidx
,
2167 MO_64
| MO_ALIGN
| s
->be_data
);
2168 tcg_temp_free_i64(val
);
2170 if (s
->be_data
== MO_LE
) {
2171 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2173 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2175 tcg_temp_free_i64(cmp
);
2176 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2177 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2179 if (s
->be_data
== MO_LE
) {
2180 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2182 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2184 tcg_temp_free_i32(tcg_rs
);
2186 TCGv_i64 d1
= tcg_temp_new_i64();
2187 TCGv_i64 d2
= tcg_temp_new_i64();
2188 TCGv_i64 a2
= tcg_temp_new_i64();
2189 TCGv_i64 c1
= tcg_temp_new_i64();
2190 TCGv_i64 c2
= tcg_temp_new_i64();
2191 TCGv_i64 zero
= tcg_const_i64(0);
2193 /* Load the two words, in memory order. */
2194 tcg_gen_qemu_ld_i64(d1
, addr
, memidx
,
2195 MO_64
| MO_ALIGN_16
| s
->be_data
);
2196 tcg_gen_addi_i64(a2
, addr
, 8);
2197 tcg_gen_qemu_ld_i64(d2
, addr
, memidx
, MO_64
| s
->be_data
);
2199 /* Compare the two words, also in memory order. */
2200 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2201 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2202 tcg_gen_and_i64(c2
, c2
, c1
);
2204 /* If compare equal, write back new data, else write back old data. */
2205 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2206 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2207 tcg_gen_qemu_st_i64(c1
, addr
, memidx
, MO_64
| s
->be_data
);
2208 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2209 tcg_temp_free_i64(a2
);
2210 tcg_temp_free_i64(c1
);
2211 tcg_temp_free_i64(c2
);
2212 tcg_temp_free_i64(zero
);
2214 /* Write back the data from memory to Rs. */
2215 tcg_gen_mov_i64(s1
, d1
);
2216 tcg_gen_mov_i64(s2
, d2
);
2217 tcg_temp_free_i64(d1
);
2218 tcg_temp_free_i64(d2
);
2222 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2223 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2225 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2227 int opc0
= extract32(opc
, 0, 1);
2231 regsize
= opc0
? 32 : 64;
2233 regsize
= size
== 3 ? 64 : 32;
2235 return regsize
== 64;
2238 /* Load/store exclusive
2240 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2241 * +-----+-------------+----+---+----+------+----+-------+------+------+
2242 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2243 * +-----+-------------+----+---+----+------+----+-------+------+------+
2245 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2246 * L: 0 -> store, 1 -> load
2247 * o2: 0 -> exclusive, 1 -> not
2248 * o1: 0 -> single register, 1 -> register pair
2249 * o0: 1 -> load-acquire/store-release, 0 -> not
2251 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2253 int rt
= extract32(insn
, 0, 5);
2254 int rn
= extract32(insn
, 5, 5);
2255 int rt2
= extract32(insn
, 10, 5);
2256 int rs
= extract32(insn
, 16, 5);
2257 int is_lasr
= extract32(insn
, 15, 1);
2258 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2259 int size
= extract32(insn
, 30, 2);
2262 switch (o2_L_o1_o0
) {
2263 case 0x0: /* STXR */
2264 case 0x1: /* STLXR */
2266 gen_check_sp_alignment(s
);
2269 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2271 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2272 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, false);
2275 case 0x4: /* LDXR */
2276 case 0x5: /* LDAXR */
2278 gen_check_sp_alignment(s
);
2280 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2282 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, false);
2284 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2288 case 0x9: /* STLR */
2289 /* Generate ISS for non-exclusive accesses including LASR. */
2291 gen_check_sp_alignment(s
);
2293 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2294 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2295 do_gpr_st(s
, cpu_reg(s
, rt
), tcg_addr
, size
, true, rt
,
2296 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2299 case 0xd: /* LDAR */
2300 /* Generate ISS for non-exclusive accesses including LASR. */
2302 gen_check_sp_alignment(s
);
2304 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2305 do_gpr_ld(s
, cpu_reg(s
, rt
), tcg_addr
, size
, false, false, true, rt
,
2306 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2307 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2310 case 0x2: case 0x3: /* CASP / STXP */
2311 if (size
& 2) { /* STXP / STLXP */
2313 gen_check_sp_alignment(s
);
2316 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2318 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2319 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, true);
2323 && ((rt
| rs
) & 1) == 0
2324 && arm_dc_feature(s
, ARM_FEATURE_V8_ATOMICS
)) {
2326 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2331 case 0x6: case 0x7: /* CASPA / LDXP */
2332 if (size
& 2) { /* LDXP / LDAXP */
2334 gen_check_sp_alignment(s
);
2336 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2338 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, true);
2340 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2345 && ((rt
| rs
) & 1) == 0
2346 && arm_dc_feature(s
, ARM_FEATURE_V8_ATOMICS
)) {
2347 /* CASPA / CASPAL */
2348 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2354 case 0xb: /* CASL */
2355 case 0xe: /* CASA */
2356 case 0xf: /* CASAL */
2357 if (rt2
== 31 && arm_dc_feature(s
, ARM_FEATURE_V8_ATOMICS
)) {
2358 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2363 unallocated_encoding(s
);
2367 * Load register (literal)
2369 * 31 30 29 27 26 25 24 23 5 4 0
2370 * +-----+-------+---+-----+-------------------+-------+
2371 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2372 * +-----+-------+---+-----+-------------------+-------+
2374 * V: 1 -> vector (simd/fp)
2375 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2376 * 10-> 32 bit signed, 11 -> prefetch
2377 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2379 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2381 int rt
= extract32(insn
, 0, 5);
2382 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2383 bool is_vector
= extract32(insn
, 26, 1);
2384 int opc
= extract32(insn
, 30, 2);
2385 bool is_signed
= false;
2387 TCGv_i64 tcg_rt
, tcg_addr
;
2391 unallocated_encoding(s
);
2395 if (!fp_access_check(s
)) {
2400 /* PRFM (literal) : prefetch */
2403 size
= 2 + extract32(opc
, 0, 1);
2404 is_signed
= extract32(opc
, 1, 1);
2407 tcg_rt
= cpu_reg(s
, rt
);
2409 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2411 do_fp_ld(s
, rt
, tcg_addr
, size
);
2413 /* Only unsigned 32bit loads target 32bit registers. */
2414 bool iss_sf
= opc
!= 0;
2416 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2417 true, rt
, iss_sf
, false);
2419 tcg_temp_free_i64(tcg_addr
);
2423 * LDNP (Load Pair - non-temporal hint)
2424 * LDP (Load Pair - non vector)
2425 * LDPSW (Load Pair Signed Word - non vector)
2426 * STNP (Store Pair - non-temporal hint)
2427 * STP (Store Pair - non vector)
2428 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2429 * LDP (Load Pair of SIMD&FP)
2430 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2431 * STP (Store Pair of SIMD&FP)
2433 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2434 * +-----+-------+---+---+-------+---+-----------------------------+
2435 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2436 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2438 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2440 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2441 * V: 0 -> GPR, 1 -> Vector
2442 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2443 * 10 -> signed offset, 11 -> pre-index
2444 * L: 0 -> Store 1 -> Load
2446 * Rt, Rt2 = GPR or SIMD registers to be stored
2447 * Rn = general purpose register containing address
2448 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2450 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2452 int rt
= extract32(insn
, 0, 5);
2453 int rn
= extract32(insn
, 5, 5);
2454 int rt2
= extract32(insn
, 10, 5);
2455 uint64_t offset
= sextract64(insn
, 15, 7);
2456 int index
= extract32(insn
, 23, 2);
2457 bool is_vector
= extract32(insn
, 26, 1);
2458 bool is_load
= extract32(insn
, 22, 1);
2459 int opc
= extract32(insn
, 30, 2);
2461 bool is_signed
= false;
2462 bool postindex
= false;
2465 TCGv_i64 tcg_addr
; /* calculated address */
2469 unallocated_encoding(s
);
2476 size
= 2 + extract32(opc
, 1, 1);
2477 is_signed
= extract32(opc
, 0, 1);
2478 if (!is_load
&& is_signed
) {
2479 unallocated_encoding(s
);
2485 case 1: /* post-index */
2490 /* signed offset with "non-temporal" hint. Since we don't emulate
2491 * caches we don't care about hints to the cache system about
2492 * data access patterns, and handle this identically to plain
2496 /* There is no non-temporal-hint version of LDPSW */
2497 unallocated_encoding(s
);
2502 case 2: /* signed offset, rn not updated */
2505 case 3: /* pre-index */
2511 if (is_vector
&& !fp_access_check(s
)) {
2518 gen_check_sp_alignment(s
);
2521 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2524 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2529 do_fp_ld(s
, rt
, tcg_addr
, size
);
2531 do_fp_st(s
, rt
, tcg_addr
, size
);
2533 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2535 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2537 do_fp_st(s
, rt2
, tcg_addr
, size
);
2540 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2541 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2544 TCGv_i64 tmp
= tcg_temp_new_i64();
2546 /* Do not modify tcg_rt before recognizing any exception
2547 * from the second load.
2549 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2550 false, 0, false, false);
2551 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2552 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2553 false, 0, false, false);
2555 tcg_gen_mov_i64(tcg_rt
, tmp
);
2556 tcg_temp_free_i64(tmp
);
2558 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2559 false, 0, false, false);
2560 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2561 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2562 false, 0, false, false);
2568 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2570 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2572 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2577 * Load/store (immediate post-indexed)
2578 * Load/store (immediate pre-indexed)
2579 * Load/store (unscaled immediate)
2581 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2582 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2583 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2584 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2586 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2588 * V = 0 -> non-vector
2589 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2590 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2592 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2598 int rn
= extract32(insn
, 5, 5);
2599 int imm9
= sextract32(insn
, 12, 9);
2600 int idx
= extract32(insn
, 10, 2);
2601 bool is_signed
= false;
2602 bool is_store
= false;
2603 bool is_extended
= false;
2604 bool is_unpriv
= (idx
== 2);
2605 bool iss_valid
= !is_vector
;
2612 size
|= (opc
& 2) << 1;
2613 if (size
> 4 || is_unpriv
) {
2614 unallocated_encoding(s
);
2617 is_store
= ((opc
& 1) == 0);
2618 if (!fp_access_check(s
)) {
2622 if (size
== 3 && opc
== 2) {
2623 /* PRFM - prefetch */
2625 unallocated_encoding(s
);
2630 if (opc
== 3 && size
> 1) {
2631 unallocated_encoding(s
);
2634 is_store
= (opc
== 0);
2635 is_signed
= extract32(opc
, 1, 1);
2636 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2654 g_assert_not_reached();
2658 gen_check_sp_alignment(s
);
2660 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2663 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2668 do_fp_st(s
, rt
, tcg_addr
, size
);
2670 do_fp_ld(s
, rt
, tcg_addr
, size
);
2673 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2674 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2675 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2678 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2679 iss_valid
, rt
, iss_sf
, false);
2681 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2682 is_signed
, is_extended
, memidx
,
2683 iss_valid
, rt
, iss_sf
, false);
2688 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2690 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2692 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2697 * Load/store (register offset)
2699 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2700 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2701 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2702 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2705 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2706 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2708 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2709 * opc<0>: 0 -> store, 1 -> load
2710 * V: 1 -> vector/simd
2711 * opt: extend encoding (see DecodeRegExtend)
2712 * S: if S=1 then scale (essentially index by sizeof(size))
2713 * Rt: register to transfer into/out of
2714 * Rn: address register or SP for base
2715 * Rm: offset register or ZR for offset
2717 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2723 int rn
= extract32(insn
, 5, 5);
2724 int shift
= extract32(insn
, 12, 1);
2725 int rm
= extract32(insn
, 16, 5);
2726 int opt
= extract32(insn
, 13, 3);
2727 bool is_signed
= false;
2728 bool is_store
= false;
2729 bool is_extended
= false;
2734 if (extract32(opt
, 1, 1) == 0) {
2735 unallocated_encoding(s
);
2740 size
|= (opc
& 2) << 1;
2742 unallocated_encoding(s
);
2745 is_store
= !extract32(opc
, 0, 1);
2746 if (!fp_access_check(s
)) {
2750 if (size
== 3 && opc
== 2) {
2751 /* PRFM - prefetch */
2754 if (opc
== 3 && size
> 1) {
2755 unallocated_encoding(s
);
2758 is_store
= (opc
== 0);
2759 is_signed
= extract32(opc
, 1, 1);
2760 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2764 gen_check_sp_alignment(s
);
2766 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2768 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2769 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2771 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2775 do_fp_st(s
, rt
, tcg_addr
, size
);
2777 do_fp_ld(s
, rt
, tcg_addr
, size
);
2780 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2781 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2783 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2784 true, rt
, iss_sf
, false);
2786 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
2787 is_signed
, is_extended
,
2788 true, rt
, iss_sf
, false);
2794 * Load/store (unsigned immediate)
2796 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2797 * +----+-------+---+-----+-----+------------+-------+------+
2798 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2799 * +----+-------+---+-----+-----+------------+-------+------+
2802 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2803 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2805 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2806 * opc<0>: 0 -> store, 1 -> load
2807 * Rn: base address register (inc SP)
2808 * Rt: target register
2810 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
2816 int rn
= extract32(insn
, 5, 5);
2817 unsigned int imm12
= extract32(insn
, 10, 12);
2818 unsigned int offset
;
2823 bool is_signed
= false;
2824 bool is_extended
= false;
2827 size
|= (opc
& 2) << 1;
2829 unallocated_encoding(s
);
2832 is_store
= !extract32(opc
, 0, 1);
2833 if (!fp_access_check(s
)) {
2837 if (size
== 3 && opc
== 2) {
2838 /* PRFM - prefetch */
2841 if (opc
== 3 && size
> 1) {
2842 unallocated_encoding(s
);
2845 is_store
= (opc
== 0);
2846 is_signed
= extract32(opc
, 1, 1);
2847 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2851 gen_check_sp_alignment(s
);
2853 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2854 offset
= imm12
<< size
;
2855 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2859 do_fp_st(s
, rt
, tcg_addr
, size
);
2861 do_fp_ld(s
, rt
, tcg_addr
, size
);
2864 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2865 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2867 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2868 true, rt
, iss_sf
, false);
2870 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
2871 true, rt
, iss_sf
, false);
2876 /* Atomic memory operations
2878 * 31 30 27 26 24 22 21 16 15 12 10 5 0
2879 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
2880 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
2881 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
2883 * Rt: the result register
2884 * Rn: base address or SP
2885 * Rs: the source register for the operation
2886 * V: vector flag (always 0 as of v8.3)
2890 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
2891 int size
, int rt
, bool is_vector
)
2893 int rs
= extract32(insn
, 16, 5);
2894 int rn
= extract32(insn
, 5, 5);
2895 int o3_opc
= extract32(insn
, 12, 4);
2896 int feature
= ARM_FEATURE_V8_ATOMICS
;
2897 TCGv_i64 tcg_rn
, tcg_rs
;
2898 AtomicThreeOpFn
*fn
;
2901 unallocated_encoding(s
);
2905 case 000: /* LDADD */
2906 fn
= tcg_gen_atomic_fetch_add_i64
;
2908 case 001: /* LDCLR */
2909 fn
= tcg_gen_atomic_fetch_and_i64
;
2911 case 002: /* LDEOR */
2912 fn
= tcg_gen_atomic_fetch_xor_i64
;
2914 case 003: /* LDSET */
2915 fn
= tcg_gen_atomic_fetch_or_i64
;
2917 case 004: /* LDSMAX */
2918 fn
= tcg_gen_atomic_fetch_smax_i64
;
2920 case 005: /* LDSMIN */
2921 fn
= tcg_gen_atomic_fetch_smin_i64
;
2923 case 006: /* LDUMAX */
2924 fn
= tcg_gen_atomic_fetch_umax_i64
;
2926 case 007: /* LDUMIN */
2927 fn
= tcg_gen_atomic_fetch_umin_i64
;
2930 fn
= tcg_gen_atomic_xchg_i64
;
2933 unallocated_encoding(s
);
2936 if (!arm_dc_feature(s
, feature
)) {
2937 unallocated_encoding(s
);
2942 gen_check_sp_alignment(s
);
2944 tcg_rn
= cpu_reg_sp(s
, rn
);
2945 tcg_rs
= read_cpu_reg(s
, rs
, true);
2947 if (o3_opc
== 1) { /* LDCLR */
2948 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
2951 /* The tcg atomic primitives are all full barriers. Therefore we
2952 * can ignore the Acquire and Release bits of this instruction.
2954 fn(cpu_reg(s
, rt
), tcg_rn
, tcg_rs
, get_mem_index(s
),
2955 s
->be_data
| size
| MO_ALIGN
);
2958 /* Load/store register (all forms) */
2959 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2961 int rt
= extract32(insn
, 0, 5);
2962 int opc
= extract32(insn
, 22, 2);
2963 bool is_vector
= extract32(insn
, 26, 1);
2964 int size
= extract32(insn
, 30, 2);
2966 switch (extract32(insn
, 24, 2)) {
2968 if (extract32(insn
, 21, 1) == 0) {
2969 /* Load/store register (unscaled immediate)
2970 * Load/store immediate pre/post-indexed
2971 * Load/store register unprivileged
2973 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
2976 switch (extract32(insn
, 10, 2)) {
2978 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
2981 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
2986 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
2989 unallocated_encoding(s
);
2992 /* AdvSIMD load/store multiple structures
2994 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2995 * +---+---+---------------+---+-------------+--------+------+------+------+
2996 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2997 * +---+---+---------------+---+-------------+--------+------+------+------+
2999 * AdvSIMD load/store multiple structures (post-indexed)
3001 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3002 * +---+---+---------------+---+---+---------+--------+------+------+------+
3003 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3004 * +---+---+---------------+---+---+---------+--------+------+------+------+
3006 * Rt: first (or only) SIMD&FP register to be transferred
3007 * Rn: base address or SP
3008 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3010 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3012 int rt
= extract32(insn
, 0, 5);
3013 int rn
= extract32(insn
, 5, 5);
3014 int size
= extract32(insn
, 10, 2);
3015 int opcode
= extract32(insn
, 12, 4);
3016 bool is_store
= !extract32(insn
, 22, 1);
3017 bool is_postidx
= extract32(insn
, 23, 1);
3018 bool is_q
= extract32(insn
, 30, 1);
3019 TCGv_i64 tcg_addr
, tcg_rn
;
3021 int ebytes
= 1 << size
;
3022 int elements
= (is_q
? 128 : 64) / (8 << size
);
3023 int rpt
; /* num iterations */
3024 int selem
; /* structure elements */
3027 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3028 unallocated_encoding(s
);
3032 /* From the shared decode logic */
3063 unallocated_encoding(s
);
3067 if (size
== 3 && !is_q
&& selem
!= 1) {
3069 unallocated_encoding(s
);
3073 if (!fp_access_check(s
)) {
3078 gen_check_sp_alignment(s
);
3081 tcg_rn
= cpu_reg_sp(s
, rn
);
3082 tcg_addr
= tcg_temp_new_i64();
3083 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3085 for (r
= 0; r
< rpt
; r
++) {
3087 for (e
= 0; e
< elements
; e
++) {
3088 int tt
= (rt
+ r
) % 32;
3090 for (xs
= 0; xs
< selem
; xs
++) {
3092 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
3094 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
3096 /* For non-quad operations, setting a slice of the low
3097 * 64 bits of the register clears the high 64 bits (in
3098 * the ARM ARM pseudocode this is implicit in the fact
3099 * that 'rval' is a 64 bit wide variable).
3100 * For quad operations, we might still need to zero the
3101 * high bits of SVE. We optimize by noticing that we only
3102 * need to do this the first time we touch a register.
3104 if (e
== 0 && (r
== 0 || xs
== selem
- 1)) {
3105 clear_vec_high(s
, is_q
, tt
);
3108 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
3115 int rm
= extract32(insn
, 16, 5);
3117 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3119 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3122 tcg_temp_free_i64(tcg_addr
);
3125 /* AdvSIMD load/store single structure
3127 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3128 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3129 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3130 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3132 * AdvSIMD load/store single structure (post-indexed)
3134 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3135 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3136 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3137 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3139 * Rt: first (or only) SIMD&FP register to be transferred
3140 * Rn: base address or SP
3141 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3142 * index = encoded in Q:S:size dependent on size
3144 * lane_size = encoded in R, opc
3145 * transfer width = encoded in opc, S, size
3147 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3149 int rt
= extract32(insn
, 0, 5);
3150 int rn
= extract32(insn
, 5, 5);
3151 int size
= extract32(insn
, 10, 2);
3152 int S
= extract32(insn
, 12, 1);
3153 int opc
= extract32(insn
, 13, 3);
3154 int R
= extract32(insn
, 21, 1);
3155 int is_load
= extract32(insn
, 22, 1);
3156 int is_postidx
= extract32(insn
, 23, 1);
3157 int is_q
= extract32(insn
, 30, 1);
3159 int scale
= extract32(opc
, 1, 2);
3160 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3161 bool replicate
= false;
3162 int index
= is_q
<< 3 | S
<< 2 | size
;
3164 TCGv_i64 tcg_addr
, tcg_rn
;
3168 if (!is_load
|| S
) {
3169 unallocated_encoding(s
);
3178 if (extract32(size
, 0, 1)) {
3179 unallocated_encoding(s
);
3185 if (extract32(size
, 1, 1)) {
3186 unallocated_encoding(s
);
3189 if (!extract32(size
, 0, 1)) {
3193 unallocated_encoding(s
);
3201 g_assert_not_reached();
3204 if (!fp_access_check(s
)) {
3208 ebytes
= 1 << scale
;
3211 gen_check_sp_alignment(s
);
3214 tcg_rn
= cpu_reg_sp(s
, rn
);
3215 tcg_addr
= tcg_temp_new_i64();
3216 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3218 for (xs
= 0; xs
< selem
; xs
++) {
3220 /* Load and replicate to all elements */
3222 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3224 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
3225 get_mem_index(s
), s
->be_data
+ scale
);
3228 mulconst
= 0x0101010101010101ULL
;
3231 mulconst
= 0x0001000100010001ULL
;
3234 mulconst
= 0x0000000100000001ULL
;
3240 g_assert_not_reached();
3243 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
3245 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
3247 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
3249 tcg_temp_free_i64(tcg_tmp
);
3250 clear_vec_high(s
, is_q
, rt
);
3252 /* Load/store one element per register */
3254 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
);
3256 do_vec_st(s
, rt
, index
, tcg_addr
, scale
);
3259 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
3264 int rm
= extract32(insn
, 16, 5);
3266 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3268 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3271 tcg_temp_free_i64(tcg_addr
);
3274 /* Loads and stores */
3275 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3277 switch (extract32(insn
, 24, 6)) {
3278 case 0x08: /* Load/store exclusive */
3279 disas_ldst_excl(s
, insn
);
3281 case 0x18: case 0x1c: /* Load register (literal) */
3282 disas_ld_lit(s
, insn
);
3284 case 0x28: case 0x29:
3285 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3286 disas_ldst_pair(s
, insn
);
3288 case 0x38: case 0x39:
3289 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3290 disas_ldst_reg(s
, insn
);
3292 case 0x0c: /* AdvSIMD load/store multiple structures */
3293 disas_ldst_multiple_struct(s
, insn
);
3295 case 0x0d: /* AdvSIMD load/store single structure */
3296 disas_ldst_single_struct(s
, insn
);
3299 unallocated_encoding(s
);
3304 /* PC-rel. addressing
3305 * 31 30 29 28 24 23 5 4 0
3306 * +----+-------+-----------+-------------------+------+
3307 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3308 * +----+-------+-----------+-------------------+------+
3310 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3312 unsigned int page
, rd
;
3316 page
= extract32(insn
, 31, 1);
3317 /* SignExtend(immhi:immlo) -> offset */
3318 offset
= sextract64(insn
, 5, 19);
3319 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3320 rd
= extract32(insn
, 0, 5);
3324 /* ADRP (page based) */
3329 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3333 * Add/subtract (immediate)
3335 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3336 * +--+--+--+-----------+-----+-------------+-----+-----+
3337 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3338 * +--+--+--+-----------+-----+-------------+-----+-----+
3340 * sf: 0 -> 32bit, 1 -> 64bit
3341 * op: 0 -> add , 1 -> sub
3343 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3345 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3347 int rd
= extract32(insn
, 0, 5);
3348 int rn
= extract32(insn
, 5, 5);
3349 uint64_t imm
= extract32(insn
, 10, 12);
3350 int shift
= extract32(insn
, 22, 2);
3351 bool setflags
= extract32(insn
, 29, 1);
3352 bool sub_op
= extract32(insn
, 30, 1);
3353 bool is_64bit
= extract32(insn
, 31, 1);
3355 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3356 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3357 TCGv_i64 tcg_result
;
3366 unallocated_encoding(s
);
3370 tcg_result
= tcg_temp_new_i64();
3373 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3375 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3378 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3380 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3382 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3384 tcg_temp_free_i64(tcg_imm
);
3388 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3390 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3393 tcg_temp_free_i64(tcg_result
);
3396 /* The input should be a value in the bottom e bits (with higher
3397 * bits zero); returns that value replicated into every element
3398 * of size e in a 64 bit integer.
3400 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3410 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3411 static inline uint64_t bitmask64(unsigned int length
)
3413 assert(length
> 0 && length
<= 64);
3414 return ~0ULL >> (64 - length
);
3417 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3418 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3419 * value (ie should cause a guest UNDEF exception), and true if they are
3420 * valid, in which case the decoded bit pattern is written to result.
3422 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3423 unsigned int imms
, unsigned int immr
)
3426 unsigned e
, levels
, s
, r
;
3429 assert(immn
< 2 && imms
< 64 && immr
< 64);
3431 /* The bit patterns we create here are 64 bit patterns which
3432 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3433 * 64 bits each. Each element contains the same value: a run
3434 * of between 1 and e-1 non-zero bits, rotated within the
3435 * element by between 0 and e-1 bits.
3437 * The element size and run length are encoded into immn (1 bit)
3438 * and imms (6 bits) as follows:
3439 * 64 bit elements: immn = 1, imms = <length of run - 1>
3440 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3441 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3442 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3443 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3444 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3445 * Notice that immn = 0, imms = 11111x is the only combination
3446 * not covered by one of the above options; this is reserved.
3447 * Further, <length of run - 1> all-ones is a reserved pattern.
3449 * In all cases the rotation is by immr % e (and immr is 6 bits).
3452 /* First determine the element size */
3453 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3455 /* This is the immn == 0, imms == 0x11111x case */
3465 /* <length of run - 1> mustn't be all-ones. */
3469 /* Create the value of one element: s+1 set bits rotated
3470 * by r within the element (which is e bits wide)...
3472 mask
= bitmask64(s
+ 1);
3474 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3475 mask
&= bitmask64(e
);
3477 /* ...then replicate the element over the whole 64 bit value */
3478 mask
= bitfield_replicate(mask
, e
);
3483 /* Logical (immediate)
3484 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3485 * +----+-----+-------------+---+------+------+------+------+
3486 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3487 * +----+-----+-------------+---+------+------+------+------+
3489 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3491 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3492 TCGv_i64 tcg_rd
, tcg_rn
;
3494 bool is_and
= false;
3496 sf
= extract32(insn
, 31, 1);
3497 opc
= extract32(insn
, 29, 2);
3498 is_n
= extract32(insn
, 22, 1);
3499 immr
= extract32(insn
, 16, 6);
3500 imms
= extract32(insn
, 10, 6);
3501 rn
= extract32(insn
, 5, 5);
3502 rd
= extract32(insn
, 0, 5);
3505 unallocated_encoding(s
);
3509 if (opc
== 0x3) { /* ANDS */
3510 tcg_rd
= cpu_reg(s
, rd
);
3512 tcg_rd
= cpu_reg_sp(s
, rd
);
3514 tcg_rn
= cpu_reg(s
, rn
);
3516 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3517 /* some immediate field values are reserved */
3518 unallocated_encoding(s
);
3523 wmask
&= 0xffffffff;
3527 case 0x3: /* ANDS */
3529 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3533 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3536 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3539 assert(FALSE
); /* must handle all above */
3543 if (!sf
&& !is_and
) {
3544 /* zero extend final result; we know we can skip this for AND
3545 * since the immediate had the high 32 bits clear.
3547 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3550 if (opc
== 3) { /* ANDS */
3551 gen_logic_CC(sf
, tcg_rd
);
3556 * Move wide (immediate)
3558 * 31 30 29 28 23 22 21 20 5 4 0
3559 * +--+-----+-------------+-----+----------------+------+
3560 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3561 * +--+-----+-------------+-----+----------------+------+
3563 * sf: 0 -> 32 bit, 1 -> 64 bit
3564 * opc: 00 -> N, 10 -> Z, 11 -> K
3565 * hw: shift/16 (0,16, and sf only 32, 48)
3567 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3569 int rd
= extract32(insn
, 0, 5);
3570 uint64_t imm
= extract32(insn
, 5, 16);
3571 int sf
= extract32(insn
, 31, 1);
3572 int opc
= extract32(insn
, 29, 2);
3573 int pos
= extract32(insn
, 21, 2) << 4;
3574 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3577 if (!sf
&& (pos
>= 32)) {
3578 unallocated_encoding(s
);
3592 tcg_gen_movi_i64(tcg_rd
, imm
);
3595 tcg_imm
= tcg_const_i64(imm
);
3596 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3597 tcg_temp_free_i64(tcg_imm
);
3599 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3603 unallocated_encoding(s
);
3609 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3610 * +----+-----+-------------+---+------+------+------+------+
3611 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3612 * +----+-----+-------------+---+------+------+------+------+
3614 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3616 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3617 TCGv_i64 tcg_rd
, tcg_tmp
;
3619 sf
= extract32(insn
, 31, 1);
3620 opc
= extract32(insn
, 29, 2);
3621 n
= extract32(insn
, 22, 1);
3622 ri
= extract32(insn
, 16, 6);
3623 si
= extract32(insn
, 10, 6);
3624 rn
= extract32(insn
, 5, 5);
3625 rd
= extract32(insn
, 0, 5);
3626 bitsize
= sf
? 64 : 32;
3628 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3629 unallocated_encoding(s
);
3633 tcg_rd
= cpu_reg(s
, rd
);
3635 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3636 to be smaller than bitsize, we'll never reference data outside the
3637 low 32-bits anyway. */
3638 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3640 /* Recognize simple(r) extractions. */
3642 /* Wd<s-r:0> = Wn<s:r> */
3643 len
= (si
- ri
) + 1;
3644 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3645 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3647 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3648 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3651 /* opc == 1, BXFIL fall through to deposit */
3652 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3655 /* Handle the ri > si case with a deposit
3656 * Wd<32+s-r,32-r> = Wn<s:0>
3659 pos
= (bitsize
- ri
) & (bitsize
- 1);
3662 if (opc
== 0 && len
< ri
) {
3663 /* SBFM: sign extend the destination field from len to fill
3664 the balance of the word. Let the deposit below insert all
3665 of those sign bits. */
3666 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3670 if (opc
== 1) { /* BFM, BXFIL */
3671 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3673 /* SBFM or UBFM: We start with zero, and we haven't modified
3674 any bits outside bitsize, therefore the zero-extension
3675 below is unneeded. */
3676 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3681 if (!sf
) { /* zero extend final result */
3682 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3687 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3688 * +----+------+-------------+---+----+------+--------+------+------+
3689 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3690 * +----+------+-------------+---+----+------+--------+------+------+
3692 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3694 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3696 sf
= extract32(insn
, 31, 1);
3697 n
= extract32(insn
, 22, 1);
3698 rm
= extract32(insn
, 16, 5);
3699 imm
= extract32(insn
, 10, 6);
3700 rn
= extract32(insn
, 5, 5);
3701 rd
= extract32(insn
, 0, 5);
3702 op21
= extract32(insn
, 29, 2);
3703 op0
= extract32(insn
, 21, 1);
3704 bitsize
= sf
? 64 : 32;
3706 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3707 unallocated_encoding(s
);
3709 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3711 tcg_rd
= cpu_reg(s
, rd
);
3713 if (unlikely(imm
== 0)) {
3714 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3715 * so an extract from bit 0 is a special case.
3718 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3720 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3722 } else if (rm
== rn
) { /* ROR */
3723 tcg_rm
= cpu_reg(s
, rm
);
3725 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
3727 TCGv_i32 tmp
= tcg_temp_new_i32();
3728 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
3729 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
3730 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
3731 tcg_temp_free_i32(tmp
);
3734 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3735 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3736 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
3737 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
3738 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
3740 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3746 /* Data processing - immediate */
3747 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
3749 switch (extract32(insn
, 23, 6)) {
3750 case 0x20: case 0x21: /* PC-rel. addressing */
3751 disas_pc_rel_adr(s
, insn
);
3753 case 0x22: case 0x23: /* Add/subtract (immediate) */
3754 disas_add_sub_imm(s
, insn
);
3756 case 0x24: /* Logical (immediate) */
3757 disas_logic_imm(s
, insn
);
3759 case 0x25: /* Move wide (immediate) */
3760 disas_movw_imm(s
, insn
);
3762 case 0x26: /* Bitfield */
3763 disas_bitfield(s
, insn
);
3765 case 0x27: /* Extract */
3766 disas_extract(s
, insn
);
3769 unallocated_encoding(s
);
3774 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3775 * Note that it is the caller's responsibility to ensure that the
3776 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3777 * mandated semantics for out of range shifts.
3779 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3780 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3782 switch (shift_type
) {
3783 case A64_SHIFT_TYPE_LSL
:
3784 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3786 case A64_SHIFT_TYPE_LSR
:
3787 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3789 case A64_SHIFT_TYPE_ASR
:
3791 tcg_gen_ext32s_i64(dst
, src
);
3793 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3795 case A64_SHIFT_TYPE_ROR
:
3797 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3800 t0
= tcg_temp_new_i32();
3801 t1
= tcg_temp_new_i32();
3802 tcg_gen_extrl_i64_i32(t0
, src
);
3803 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
3804 tcg_gen_rotr_i32(t0
, t0
, t1
);
3805 tcg_gen_extu_i32_i64(dst
, t0
);
3806 tcg_temp_free_i32(t0
);
3807 tcg_temp_free_i32(t1
);
3811 assert(FALSE
); /* all shift types should be handled */
3815 if (!sf
) { /* zero extend final result */
3816 tcg_gen_ext32u_i64(dst
, dst
);
3820 /* Shift a TCGv src by immediate, put result in dst.
3821 * The shift amount must be in range (this should always be true as the
3822 * relevant instructions will UNDEF on bad shift immediates).
3824 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3825 enum a64_shift_type shift_type
, unsigned int shift_i
)
3827 assert(shift_i
< (sf
? 64 : 32));
3830 tcg_gen_mov_i64(dst
, src
);
3832 TCGv_i64 shift_const
;
3834 shift_const
= tcg_const_i64(shift_i
);
3835 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3836 tcg_temp_free_i64(shift_const
);
3840 /* Logical (shifted register)
3841 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3842 * +----+-----+-----------+-------+---+------+--------+------+------+
3843 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3844 * +----+-----+-----------+-------+---+------+--------+------+------+
3846 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3848 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3849 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3851 sf
= extract32(insn
, 31, 1);
3852 opc
= extract32(insn
, 29, 2);
3853 shift_type
= extract32(insn
, 22, 2);
3854 invert
= extract32(insn
, 21, 1);
3855 rm
= extract32(insn
, 16, 5);
3856 shift_amount
= extract32(insn
, 10, 6);
3857 rn
= extract32(insn
, 5, 5);
3858 rd
= extract32(insn
, 0, 5);
3860 if (!sf
&& (shift_amount
& (1 << 5))) {
3861 unallocated_encoding(s
);
3865 tcg_rd
= cpu_reg(s
, rd
);
3867 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3868 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3869 * register-register MOV and MVN, so it is worth special casing.
3871 tcg_rm
= cpu_reg(s
, rm
);
3873 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3875 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3879 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3881 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3887 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3890 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3893 tcg_rn
= cpu_reg(s
, rn
);
3895 switch (opc
| (invert
<< 2)) {
3898 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3901 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3904 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3908 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3911 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3914 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3922 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3926 gen_logic_CC(sf
, tcg_rd
);
3931 * Add/subtract (extended register)
3933 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3934 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3935 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3936 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3938 * sf: 0 -> 32bit, 1 -> 64bit
3939 * op: 0 -> add , 1 -> sub
3942 * option: extension type (see DecodeRegExtend)
3943 * imm3: optional shift to Rm
3945 * Rd = Rn + LSL(extend(Rm), amount)
3947 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3949 int rd
= extract32(insn
, 0, 5);
3950 int rn
= extract32(insn
, 5, 5);
3951 int imm3
= extract32(insn
, 10, 3);
3952 int option
= extract32(insn
, 13, 3);
3953 int rm
= extract32(insn
, 16, 5);
3954 bool setflags
= extract32(insn
, 29, 1);
3955 bool sub_op
= extract32(insn
, 30, 1);
3956 bool sf
= extract32(insn
, 31, 1);
3958 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3960 TCGv_i64 tcg_result
;
3963 unallocated_encoding(s
);
3967 /* non-flag setting ops may use SP */
3969 tcg_rd
= cpu_reg_sp(s
, rd
);
3971 tcg_rd
= cpu_reg(s
, rd
);
3973 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3975 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3976 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3978 tcg_result
= tcg_temp_new_i64();
3982 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3984 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3988 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3990 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3995 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3997 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4000 tcg_temp_free_i64(tcg_result
);
4004 * Add/subtract (shifted register)
4006 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4007 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4008 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4009 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4011 * sf: 0 -> 32bit, 1 -> 64bit
4012 * op: 0 -> add , 1 -> sub
4014 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4015 * imm6: Shift amount to apply to Rm before the add/sub
4017 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4019 int rd
= extract32(insn
, 0, 5);
4020 int rn
= extract32(insn
, 5, 5);
4021 int imm6
= extract32(insn
, 10, 6);
4022 int rm
= extract32(insn
, 16, 5);
4023 int shift_type
= extract32(insn
, 22, 2);
4024 bool setflags
= extract32(insn
, 29, 1);
4025 bool sub_op
= extract32(insn
, 30, 1);
4026 bool sf
= extract32(insn
, 31, 1);
4028 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4029 TCGv_i64 tcg_rn
, tcg_rm
;
4030 TCGv_i64 tcg_result
;
4032 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4033 unallocated_encoding(s
);
4037 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4038 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4040 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4042 tcg_result
= tcg_temp_new_i64();
4046 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4048 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4052 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4054 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4059 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4061 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4064 tcg_temp_free_i64(tcg_result
);
4067 /* Data-processing (3 source)
4069 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4070 * +--+------+-----------+------+------+----+------+------+------+
4071 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4072 * +--+------+-----------+------+------+----+------+------+------+
4074 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4076 int rd
= extract32(insn
, 0, 5);
4077 int rn
= extract32(insn
, 5, 5);
4078 int ra
= extract32(insn
, 10, 5);
4079 int rm
= extract32(insn
, 16, 5);
4080 int op_id
= (extract32(insn
, 29, 3) << 4) |
4081 (extract32(insn
, 21, 3) << 1) |
4082 extract32(insn
, 15, 1);
4083 bool sf
= extract32(insn
, 31, 1);
4084 bool is_sub
= extract32(op_id
, 0, 1);
4085 bool is_high
= extract32(op_id
, 2, 1);
4086 bool is_signed
= false;
4091 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4093 case 0x42: /* SMADDL */
4094 case 0x43: /* SMSUBL */
4095 case 0x44: /* SMULH */
4098 case 0x0: /* MADD (32bit) */
4099 case 0x1: /* MSUB (32bit) */
4100 case 0x40: /* MADD (64bit) */
4101 case 0x41: /* MSUB (64bit) */
4102 case 0x4a: /* UMADDL */
4103 case 0x4b: /* UMSUBL */
4104 case 0x4c: /* UMULH */
4107 unallocated_encoding(s
);
4112 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4113 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4114 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4115 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4118 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4120 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4123 tcg_temp_free_i64(low_bits
);
4127 tcg_op1
= tcg_temp_new_i64();
4128 tcg_op2
= tcg_temp_new_i64();
4129 tcg_tmp
= tcg_temp_new_i64();
4132 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4133 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4136 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4137 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4139 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4140 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4144 if (ra
== 31 && !is_sub
) {
4145 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4146 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4148 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4150 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4152 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4157 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4160 tcg_temp_free_i64(tcg_op1
);
4161 tcg_temp_free_i64(tcg_op2
);
4162 tcg_temp_free_i64(tcg_tmp
);
4165 /* Add/subtract (with carry)
4166 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4167 * +--+--+--+------------------------+------+---------+------+-----+
4168 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
4169 * +--+--+--+------------------------+------+---------+------+-----+
4173 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4175 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4176 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4178 if (extract32(insn
, 10, 6) != 0) {
4179 unallocated_encoding(s
);
4183 sf
= extract32(insn
, 31, 1);
4184 op
= extract32(insn
, 30, 1);
4185 setflags
= extract32(insn
, 29, 1);
4186 rm
= extract32(insn
, 16, 5);
4187 rn
= extract32(insn
, 5, 5);
4188 rd
= extract32(insn
, 0, 5);
4190 tcg_rd
= cpu_reg(s
, rd
);
4191 tcg_rn
= cpu_reg(s
, rn
);
4194 tcg_y
= new_tmp_a64(s
);
4195 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4197 tcg_y
= cpu_reg(s
, rm
);
4201 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4203 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4207 /* Conditional compare (immediate / register)
4208 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4209 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4210 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4211 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4214 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4216 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4217 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4218 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4221 if (!extract32(insn
, 29, 1)) {
4222 unallocated_encoding(s
);
4225 if (insn
& (1 << 10 | 1 << 4)) {
4226 unallocated_encoding(s
);
4229 sf
= extract32(insn
, 31, 1);
4230 op
= extract32(insn
, 30, 1);
4231 is_imm
= extract32(insn
, 11, 1);
4232 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4233 cond
= extract32(insn
, 12, 4);
4234 rn
= extract32(insn
, 5, 5);
4235 nzcv
= extract32(insn
, 0, 4);
4237 /* Set T0 = !COND. */
4238 tcg_t0
= tcg_temp_new_i32();
4239 arm_test_cc(&c
, cond
);
4240 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4243 /* Load the arguments for the new comparison. */
4245 tcg_y
= new_tmp_a64(s
);
4246 tcg_gen_movi_i64(tcg_y
, y
);
4248 tcg_y
= cpu_reg(s
, y
);
4250 tcg_rn
= cpu_reg(s
, rn
);
4252 /* Set the flags for the new comparison. */
4253 tcg_tmp
= tcg_temp_new_i64();
4255 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4257 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4259 tcg_temp_free_i64(tcg_tmp
);
4261 /* If COND was false, force the flags to #nzcv. Compute two masks
4262 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4263 * For tcg hosts that support ANDC, we can make do with just T1.
4264 * In either case, allow the tcg optimizer to delete any unused mask.
4266 tcg_t1
= tcg_temp_new_i32();
4267 tcg_t2
= tcg_temp_new_i32();
4268 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4269 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4271 if (nzcv
& 8) { /* N */
4272 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4274 if (TCG_TARGET_HAS_andc_i32
) {
4275 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4277 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4280 if (nzcv
& 4) { /* Z */
4281 if (TCG_TARGET_HAS_andc_i32
) {
4282 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4284 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4287 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4289 if (nzcv
& 2) { /* C */
4290 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4292 if (TCG_TARGET_HAS_andc_i32
) {
4293 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4295 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4298 if (nzcv
& 1) { /* V */
4299 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4301 if (TCG_TARGET_HAS_andc_i32
) {
4302 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4304 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4307 tcg_temp_free_i32(tcg_t0
);
4308 tcg_temp_free_i32(tcg_t1
);
4309 tcg_temp_free_i32(tcg_t2
);
4312 /* Conditional select
4313 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4314 * +----+----+---+-----------------+------+------+-----+------+------+
4315 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4316 * +----+----+---+-----------------+------+------+-----+------+------+
4318 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4320 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4321 TCGv_i64 tcg_rd
, zero
;
4324 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4325 /* S == 1 or op2<1> == 1 */
4326 unallocated_encoding(s
);
4329 sf
= extract32(insn
, 31, 1);
4330 else_inv
= extract32(insn
, 30, 1);
4331 rm
= extract32(insn
, 16, 5);
4332 cond
= extract32(insn
, 12, 4);
4333 else_inc
= extract32(insn
, 10, 1);
4334 rn
= extract32(insn
, 5, 5);
4335 rd
= extract32(insn
, 0, 5);
4337 tcg_rd
= cpu_reg(s
, rd
);
4339 a64_test_cc(&c
, cond
);
4340 zero
= tcg_const_i64(0);
4342 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4344 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4346 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4349 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4350 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4351 if (else_inv
&& else_inc
) {
4352 tcg_gen_neg_i64(t_false
, t_false
);
4353 } else if (else_inv
) {
4354 tcg_gen_not_i64(t_false
, t_false
);
4355 } else if (else_inc
) {
4356 tcg_gen_addi_i64(t_false
, t_false
, 1);
4358 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4361 tcg_temp_free_i64(zero
);
4365 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4369 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4370 unsigned int rn
, unsigned int rd
)
4372 TCGv_i64 tcg_rd
, tcg_rn
;
4373 tcg_rd
= cpu_reg(s
, rd
);
4374 tcg_rn
= cpu_reg(s
, rn
);
4377 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4379 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4380 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4381 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4382 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4383 tcg_temp_free_i32(tcg_tmp32
);
4387 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4388 unsigned int rn
, unsigned int rd
)
4390 TCGv_i64 tcg_rd
, tcg_rn
;
4391 tcg_rd
= cpu_reg(s
, rd
);
4392 tcg_rn
= cpu_reg(s
, rn
);
4395 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4397 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4398 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4399 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4400 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4401 tcg_temp_free_i32(tcg_tmp32
);
4405 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4406 unsigned int rn
, unsigned int rd
)
4408 TCGv_i64 tcg_rd
, tcg_rn
;
4409 tcg_rd
= cpu_reg(s
, rd
);
4410 tcg_rn
= cpu_reg(s
, rn
);
4413 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4415 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4416 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4417 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4418 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4419 tcg_temp_free_i32(tcg_tmp32
);
4423 /* REV with sf==1, opcode==3 ("REV64") */
4424 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4425 unsigned int rn
, unsigned int rd
)
4428 unallocated_encoding(s
);
4431 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4434 /* REV with sf==0, opcode==2
4435 * REV32 (sf==1, opcode==2)
4437 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4438 unsigned int rn
, unsigned int rd
)
4440 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4443 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4444 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4446 /* bswap32_i64 requires zero high word */
4447 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4448 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4449 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4450 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4451 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4453 tcg_temp_free_i64(tcg_tmp
);
4455 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4456 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4460 /* REV16 (opcode==1) */
4461 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4462 unsigned int rn
, unsigned int rd
)
4464 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4465 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4466 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4467 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4469 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4470 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4471 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4472 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4473 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4475 tcg_temp_free_i64(mask
);
4476 tcg_temp_free_i64(tcg_tmp
);
4479 /* Data-processing (1 source)
4480 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4481 * +----+---+---+-----------------+---------+--------+------+------+
4482 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4483 * +----+---+---+-----------------+---------+--------+------+------+
4485 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4487 unsigned int sf
, opcode
, rn
, rd
;
4489 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
4490 unallocated_encoding(s
);
4494 sf
= extract32(insn
, 31, 1);
4495 opcode
= extract32(insn
, 10, 6);
4496 rn
= extract32(insn
, 5, 5);
4497 rd
= extract32(insn
, 0, 5);
4501 handle_rbit(s
, sf
, rn
, rd
);
4504 handle_rev16(s
, sf
, rn
, rd
);
4507 handle_rev32(s
, sf
, rn
, rd
);
4510 handle_rev64(s
, sf
, rn
, rd
);
4513 handle_clz(s
, sf
, rn
, rd
);
4516 handle_cls(s
, sf
, rn
, rd
);
4521 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4522 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4524 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4525 tcg_rd
= cpu_reg(s
, rd
);
4527 if (!sf
&& is_signed
) {
4528 tcg_n
= new_tmp_a64(s
);
4529 tcg_m
= new_tmp_a64(s
);
4530 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4531 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4533 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4534 tcg_m
= read_cpu_reg(s
, rm
, sf
);
4538 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
4540 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
4543 if (!sf
) { /* zero extend final result */
4544 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4548 /* LSLV, LSRV, ASRV, RORV */
4549 static void handle_shift_reg(DisasContext
*s
,
4550 enum a64_shift_type shift_type
, unsigned int sf
,
4551 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4553 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
4554 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4555 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4557 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
4558 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
4559 tcg_temp_free_i64(tcg_shift
);
4562 /* CRC32[BHWX], CRC32C[BHWX] */
4563 static void handle_crc32(DisasContext
*s
,
4564 unsigned int sf
, unsigned int sz
, bool crc32c
,
4565 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4567 TCGv_i64 tcg_acc
, tcg_val
;
4570 if (!arm_dc_feature(s
, ARM_FEATURE_CRC
)
4571 || (sf
== 1 && sz
!= 3)
4572 || (sf
== 0 && sz
== 3)) {
4573 unallocated_encoding(s
);
4578 tcg_val
= cpu_reg(s
, rm
);
4592 g_assert_not_reached();
4594 tcg_val
= new_tmp_a64(s
);
4595 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
4598 tcg_acc
= cpu_reg(s
, rn
);
4599 tcg_bytes
= tcg_const_i32(1 << sz
);
4602 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4604 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
4607 tcg_temp_free_i32(tcg_bytes
);
4610 /* Data-processing (2 source)
4611 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4612 * +----+---+---+-----------------+------+--------+------+------+
4613 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4614 * +----+---+---+-----------------+------+--------+------+------+
4616 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
4618 unsigned int sf
, rm
, opcode
, rn
, rd
;
4619 sf
= extract32(insn
, 31, 1);
4620 rm
= extract32(insn
, 16, 5);
4621 opcode
= extract32(insn
, 10, 6);
4622 rn
= extract32(insn
, 5, 5);
4623 rd
= extract32(insn
, 0, 5);
4625 if (extract32(insn
, 29, 1)) {
4626 unallocated_encoding(s
);
4632 handle_div(s
, false, sf
, rm
, rn
, rd
);
4635 handle_div(s
, true, sf
, rm
, rn
, rd
);
4638 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
4641 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
4644 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
4647 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
4656 case 23: /* CRC32 */
4658 int sz
= extract32(opcode
, 0, 2);
4659 bool crc32c
= extract32(opcode
, 2, 1);
4660 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
4664 unallocated_encoding(s
);
4669 /* Data processing - register */
4670 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
4672 switch (extract32(insn
, 24, 5)) {
4673 case 0x0a: /* Logical (shifted register) */
4674 disas_logic_reg(s
, insn
);
4676 case 0x0b: /* Add/subtract */
4677 if (insn
& (1 << 21)) { /* (extended register) */
4678 disas_add_sub_ext_reg(s
, insn
);
4680 disas_add_sub_reg(s
, insn
);
4683 case 0x1b: /* Data-processing (3 source) */
4684 disas_data_proc_3src(s
, insn
);
4687 switch (extract32(insn
, 21, 3)) {
4688 case 0x0: /* Add/subtract (with carry) */
4689 disas_adc_sbc(s
, insn
);
4691 case 0x2: /* Conditional compare */
4692 disas_cc(s
, insn
); /* both imm and reg forms */
4694 case 0x4: /* Conditional select */
4695 disas_cond_select(s
, insn
);
4697 case 0x6: /* Data-processing */
4698 if (insn
& (1 << 30)) { /* (1 source) */
4699 disas_data_proc_1src(s
, insn
);
4700 } else { /* (2 source) */
4701 disas_data_proc_2src(s
, insn
);
4705 unallocated_encoding(s
);
4710 unallocated_encoding(s
);
4715 static void handle_fp_compare(DisasContext
*s
, int size
,
4716 unsigned int rn
, unsigned int rm
,
4717 bool cmp_with_zero
, bool signal_all_nans
)
4719 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
4720 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
4722 if (size
== MO_64
) {
4723 TCGv_i64 tcg_vn
, tcg_vm
;
4725 tcg_vn
= read_fp_dreg(s
, rn
);
4726 if (cmp_with_zero
) {
4727 tcg_vm
= tcg_const_i64(0);
4729 tcg_vm
= read_fp_dreg(s
, rm
);
4731 if (signal_all_nans
) {
4732 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4734 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4736 tcg_temp_free_i64(tcg_vn
);
4737 tcg_temp_free_i64(tcg_vm
);
4739 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
4740 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
4742 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
4743 if (cmp_with_zero
) {
4744 tcg_gen_movi_i32(tcg_vm
, 0);
4746 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
4751 if (signal_all_nans
) {
4752 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4754 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4758 if (signal_all_nans
) {
4759 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4761 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
4765 g_assert_not_reached();
4768 tcg_temp_free_i32(tcg_vn
);
4769 tcg_temp_free_i32(tcg_vm
);
4772 tcg_temp_free_ptr(fpst
);
4774 gen_set_nzcv(tcg_flags
);
4776 tcg_temp_free_i64(tcg_flags
);
4779 /* Floating point compare
4780 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4781 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4782 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4783 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4785 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
4787 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
4790 mos
= extract32(insn
, 29, 3);
4791 type
= extract32(insn
, 22, 2);
4792 rm
= extract32(insn
, 16, 5);
4793 op
= extract32(insn
, 14, 2);
4794 rn
= extract32(insn
, 5, 5);
4795 opc
= extract32(insn
, 3, 2);
4796 op2r
= extract32(insn
, 0, 3);
4798 if (mos
|| op
|| op2r
) {
4799 unallocated_encoding(s
);
4812 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
4817 unallocated_encoding(s
);
4821 if (!fp_access_check(s
)) {
4825 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
4828 /* Floating point conditional compare
4829 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4830 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4831 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4832 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4834 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
4836 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
4838 TCGLabel
*label_continue
= NULL
;
4841 mos
= extract32(insn
, 29, 3);
4842 type
= extract32(insn
, 22, 2);
4843 rm
= extract32(insn
, 16, 5);
4844 cond
= extract32(insn
, 12, 4);
4845 rn
= extract32(insn
, 5, 5);
4846 op
= extract32(insn
, 4, 1);
4847 nzcv
= extract32(insn
, 0, 4);
4850 unallocated_encoding(s
);
4863 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
4868 unallocated_encoding(s
);
4872 if (!fp_access_check(s
)) {
4876 if (cond
< 0x0e) { /* not always */
4877 TCGLabel
*label_match
= gen_new_label();
4878 label_continue
= gen_new_label();
4879 arm_gen_test_cc(cond
, label_match
);
4881 tcg_flags
= tcg_const_i64(nzcv
<< 28);
4882 gen_set_nzcv(tcg_flags
);
4883 tcg_temp_free_i64(tcg_flags
);
4884 tcg_gen_br(label_continue
);
4885 gen_set_label(label_match
);
4888 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
4891 gen_set_label(label_continue
);
4895 /* Floating point conditional select
4896 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4897 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4898 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4899 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4901 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4903 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4904 TCGv_i64 t_true
, t_false
, t_zero
;
4908 mos
= extract32(insn
, 29, 3);
4909 type
= extract32(insn
, 22, 2);
4910 rm
= extract32(insn
, 16, 5);
4911 cond
= extract32(insn
, 12, 4);
4912 rn
= extract32(insn
, 5, 5);
4913 rd
= extract32(insn
, 0, 5);
4916 unallocated_encoding(s
);
4929 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
4934 unallocated_encoding(s
);
4938 if (!fp_access_check(s
)) {
4942 /* Zero extend sreg & hreg inputs to 64 bits now. */
4943 t_true
= tcg_temp_new_i64();
4944 t_false
= tcg_temp_new_i64();
4945 read_vec_element(s
, t_true
, rn
, 0, sz
);
4946 read_vec_element(s
, t_false
, rm
, 0, sz
);
4948 a64_test_cc(&c
, cond
);
4949 t_zero
= tcg_const_i64(0);
4950 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
4951 tcg_temp_free_i64(t_zero
);
4952 tcg_temp_free_i64(t_false
);
4955 /* Note that sregs & hregs write back zeros to the high bits,
4956 and we've already done the zero-extension. */
4957 write_fp_dreg(s
, rd
, t_true
);
4958 tcg_temp_free_i64(t_true
);
4961 /* Floating-point data-processing (1 source) - half precision */
4962 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
4964 TCGv_ptr fpst
= NULL
;
4965 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
4966 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4969 case 0x0: /* FMOV */
4970 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4972 case 0x1: /* FABS */
4973 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
4975 case 0x2: /* FNEG */
4976 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
4978 case 0x3: /* FSQRT */
4979 gen_helper_sqrt_f16(tcg_res
, tcg_op
, cpu_env
);
4981 case 0x8: /* FRINTN */
4982 case 0x9: /* FRINTP */
4983 case 0xa: /* FRINTM */
4984 case 0xb: /* FRINTZ */
4985 case 0xc: /* FRINTA */
4987 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4988 fpst
= get_fpstatus_ptr(true);
4990 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
4991 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
4993 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
4994 tcg_temp_free_i32(tcg_rmode
);
4997 case 0xe: /* FRINTX */
4998 fpst
= get_fpstatus_ptr(true);
4999 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5001 case 0xf: /* FRINTI */
5002 fpst
= get_fpstatus_ptr(true);
5003 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5009 write_fp_sreg(s
, rd
, tcg_res
);
5012 tcg_temp_free_ptr(fpst
);
5014 tcg_temp_free_i32(tcg_op
);
5015 tcg_temp_free_i32(tcg_res
);
5018 /* Floating-point data-processing (1 source) - single precision */
5019 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5025 fpst
= get_fpstatus_ptr(false);
5026 tcg_op
= read_fp_sreg(s
, rn
);
5027 tcg_res
= tcg_temp_new_i32();
5030 case 0x0: /* FMOV */
5031 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5033 case 0x1: /* FABS */
5034 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5036 case 0x2: /* FNEG */
5037 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5039 case 0x3: /* FSQRT */
5040 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5042 case 0x8: /* FRINTN */
5043 case 0x9: /* FRINTP */
5044 case 0xa: /* FRINTM */
5045 case 0xb: /* FRINTZ */
5046 case 0xc: /* FRINTA */
5048 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5050 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5051 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5053 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5054 tcg_temp_free_i32(tcg_rmode
);
5057 case 0xe: /* FRINTX */
5058 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
5060 case 0xf: /* FRINTI */
5061 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5067 write_fp_sreg(s
, rd
, tcg_res
);
5069 tcg_temp_free_ptr(fpst
);
5070 tcg_temp_free_i32(tcg_op
);
5071 tcg_temp_free_i32(tcg_res
);
5074 /* Floating-point data-processing (1 source) - double precision */
5075 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5082 case 0x0: /* FMOV */
5083 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5087 fpst
= get_fpstatus_ptr(false);
5088 tcg_op
= read_fp_dreg(s
, rn
);
5089 tcg_res
= tcg_temp_new_i64();
5092 case 0x1: /* FABS */
5093 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5095 case 0x2: /* FNEG */
5096 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5098 case 0x3: /* FSQRT */
5099 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5101 case 0x8: /* FRINTN */
5102 case 0x9: /* FRINTP */
5103 case 0xa: /* FRINTM */
5104 case 0xb: /* FRINTZ */
5105 case 0xc: /* FRINTA */
5107 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5109 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5110 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5112 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5113 tcg_temp_free_i32(tcg_rmode
);
5116 case 0xe: /* FRINTX */
5117 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
5119 case 0xf: /* FRINTI */
5120 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5126 write_fp_dreg(s
, rd
, tcg_res
);
5128 tcg_temp_free_ptr(fpst
);
5129 tcg_temp_free_i64(tcg_op
);
5130 tcg_temp_free_i64(tcg_res
);
5133 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5134 int rd
, int rn
, int dtype
, int ntype
)
5139 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5141 /* Single to double */
5142 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5143 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5144 write_fp_dreg(s
, rd
, tcg_rd
);
5145 tcg_temp_free_i64(tcg_rd
);
5147 /* Single to half */
5148 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5149 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
5150 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5151 write_fp_sreg(s
, rd
, tcg_rd
);
5152 tcg_temp_free_i32(tcg_rd
);
5154 tcg_temp_free_i32(tcg_rn
);
5159 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5160 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5162 /* Double to single */
5163 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5165 /* Double to half */
5166 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
5167 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5169 write_fp_sreg(s
, rd
, tcg_rd
);
5170 tcg_temp_free_i32(tcg_rd
);
5171 tcg_temp_free_i64(tcg_rn
);
5176 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5177 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5179 /* Half to single */
5180 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5181 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
5182 write_fp_sreg(s
, rd
, tcg_rd
);
5183 tcg_temp_free_i32(tcg_rd
);
5185 /* Half to double */
5186 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5187 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
5188 write_fp_dreg(s
, rd
, tcg_rd
);
5189 tcg_temp_free_i64(tcg_rd
);
5191 tcg_temp_free_i32(tcg_rn
);
5199 /* Floating point data-processing (1 source)
5200 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5201 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5202 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5203 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5205 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5207 int type
= extract32(insn
, 22, 2);
5208 int opcode
= extract32(insn
, 15, 6);
5209 int rn
= extract32(insn
, 5, 5);
5210 int rd
= extract32(insn
, 0, 5);
5213 case 0x4: case 0x5: case 0x7:
5215 /* FCVT between half, single and double precision */
5216 int dtype
= extract32(opcode
, 0, 2);
5217 if (type
== 2 || dtype
== type
) {
5218 unallocated_encoding(s
);
5221 if (!fp_access_check(s
)) {
5225 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5231 /* 32-to-32 and 64-to-64 ops */
5234 if (!fp_access_check(s
)) {
5238 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5241 if (!fp_access_check(s
)) {
5245 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5248 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
5249 unallocated_encoding(s
);
5253 if (!fp_access_check(s
)) {
5257 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5260 unallocated_encoding(s
);
5264 unallocated_encoding(s
);
5269 /* Floating-point data-processing (2 source) - single precision */
5270 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5271 int rd
, int rn
, int rm
)
5278 tcg_res
= tcg_temp_new_i32();
5279 fpst
= get_fpstatus_ptr(false);
5280 tcg_op1
= read_fp_sreg(s
, rn
);
5281 tcg_op2
= read_fp_sreg(s
, rm
);
5284 case 0x0: /* FMUL */
5285 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5287 case 0x1: /* FDIV */
5288 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5290 case 0x2: /* FADD */
5291 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5293 case 0x3: /* FSUB */
5294 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5296 case 0x4: /* FMAX */
5297 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5299 case 0x5: /* FMIN */
5300 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5302 case 0x6: /* FMAXNM */
5303 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5305 case 0x7: /* FMINNM */
5306 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5308 case 0x8: /* FNMUL */
5309 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5310 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5314 write_fp_sreg(s
, rd
, tcg_res
);
5316 tcg_temp_free_ptr(fpst
);
5317 tcg_temp_free_i32(tcg_op1
);
5318 tcg_temp_free_i32(tcg_op2
);
5319 tcg_temp_free_i32(tcg_res
);
5322 /* Floating-point data-processing (2 source) - double precision */
5323 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5324 int rd
, int rn
, int rm
)
5331 tcg_res
= tcg_temp_new_i64();
5332 fpst
= get_fpstatus_ptr(false);
5333 tcg_op1
= read_fp_dreg(s
, rn
);
5334 tcg_op2
= read_fp_dreg(s
, rm
);
5337 case 0x0: /* FMUL */
5338 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5340 case 0x1: /* FDIV */
5341 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5343 case 0x2: /* FADD */
5344 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5346 case 0x3: /* FSUB */
5347 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5349 case 0x4: /* FMAX */
5350 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5352 case 0x5: /* FMIN */
5353 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5355 case 0x6: /* FMAXNM */
5356 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5358 case 0x7: /* FMINNM */
5359 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5361 case 0x8: /* FNMUL */
5362 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5363 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5367 write_fp_dreg(s
, rd
, tcg_res
);
5369 tcg_temp_free_ptr(fpst
);
5370 tcg_temp_free_i64(tcg_op1
);
5371 tcg_temp_free_i64(tcg_op2
);
5372 tcg_temp_free_i64(tcg_res
);
5375 /* Floating-point data-processing (2 source) - half precision */
5376 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5377 int rd
, int rn
, int rm
)
5384 tcg_res
= tcg_temp_new_i32();
5385 fpst
= get_fpstatus_ptr(true);
5386 tcg_op1
= read_fp_hreg(s
, rn
);
5387 tcg_op2
= read_fp_hreg(s
, rm
);
5390 case 0x0: /* FMUL */
5391 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5393 case 0x1: /* FDIV */
5394 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5396 case 0x2: /* FADD */
5397 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5399 case 0x3: /* FSUB */
5400 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5402 case 0x4: /* FMAX */
5403 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5405 case 0x5: /* FMIN */
5406 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5408 case 0x6: /* FMAXNM */
5409 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5411 case 0x7: /* FMINNM */
5412 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5414 case 0x8: /* FNMUL */
5415 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5416 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
5419 g_assert_not_reached();
5422 write_fp_sreg(s
, rd
, tcg_res
);
5424 tcg_temp_free_ptr(fpst
);
5425 tcg_temp_free_i32(tcg_op1
);
5426 tcg_temp_free_i32(tcg_op2
);
5427 tcg_temp_free_i32(tcg_res
);
5430 /* Floating point data-processing (2 source)
5431 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5432 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5433 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5434 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5436 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
5438 int type
= extract32(insn
, 22, 2);
5439 int rd
= extract32(insn
, 0, 5);
5440 int rn
= extract32(insn
, 5, 5);
5441 int rm
= extract32(insn
, 16, 5);
5442 int opcode
= extract32(insn
, 12, 4);
5445 unallocated_encoding(s
);
5451 if (!fp_access_check(s
)) {
5454 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
5457 if (!fp_access_check(s
)) {
5460 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
5463 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
5464 unallocated_encoding(s
);
5467 if (!fp_access_check(s
)) {
5470 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
5473 unallocated_encoding(s
);
5477 /* Floating-point data-processing (3 source) - single precision */
5478 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
5479 int rd
, int rn
, int rm
, int ra
)
5481 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5482 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5483 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5485 tcg_op1
= read_fp_sreg(s
, rn
);
5486 tcg_op2
= read_fp_sreg(s
, rm
);
5487 tcg_op3
= read_fp_sreg(s
, ra
);
5489 /* These are fused multiply-add, and must be done as one
5490 * floating point operation with no rounding between the
5491 * multiplication and addition steps.
5492 * NB that doing the negations here as separate steps is
5493 * correct : an input NaN should come out with its sign bit
5494 * flipped if it is a negated-input.
5497 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
5501 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
5504 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5506 write_fp_sreg(s
, rd
, tcg_res
);
5508 tcg_temp_free_ptr(fpst
);
5509 tcg_temp_free_i32(tcg_op1
);
5510 tcg_temp_free_i32(tcg_op2
);
5511 tcg_temp_free_i32(tcg_op3
);
5512 tcg_temp_free_i32(tcg_res
);
5515 /* Floating-point data-processing (3 source) - double precision */
5516 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
5517 int rd
, int rn
, int rm
, int ra
)
5519 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
5520 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5521 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5523 tcg_op1
= read_fp_dreg(s
, rn
);
5524 tcg_op2
= read_fp_dreg(s
, rm
);
5525 tcg_op3
= read_fp_dreg(s
, ra
);
5527 /* These are fused multiply-add, and must be done as one
5528 * floating point operation with no rounding between the
5529 * multiplication and addition steps.
5530 * NB that doing the negations here as separate steps is
5531 * correct : an input NaN should come out with its sign bit
5532 * flipped if it is a negated-input.
5535 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
5539 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
5542 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5544 write_fp_dreg(s
, rd
, tcg_res
);
5546 tcg_temp_free_ptr(fpst
);
5547 tcg_temp_free_i64(tcg_op1
);
5548 tcg_temp_free_i64(tcg_op2
);
5549 tcg_temp_free_i64(tcg_op3
);
5550 tcg_temp_free_i64(tcg_res
);
5553 /* Floating-point data-processing (3 source) - half precision */
5554 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
5555 int rd
, int rn
, int rm
, int ra
)
5557 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5558 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5559 TCGv_ptr fpst
= get_fpstatus_ptr(true);
5561 tcg_op1
= read_fp_hreg(s
, rn
);
5562 tcg_op2
= read_fp_hreg(s
, rm
);
5563 tcg_op3
= read_fp_hreg(s
, ra
);
5565 /* These are fused multiply-add, and must be done as one
5566 * floating point operation with no rounding between the
5567 * multiplication and addition steps.
5568 * NB that doing the negations here as separate steps is
5569 * correct : an input NaN should come out with its sign bit
5570 * flipped if it is a negated-input.
5573 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
5577 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
5580 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5582 write_fp_sreg(s
, rd
, tcg_res
);
5584 tcg_temp_free_ptr(fpst
);
5585 tcg_temp_free_i32(tcg_op1
);
5586 tcg_temp_free_i32(tcg_op2
);
5587 tcg_temp_free_i32(tcg_op3
);
5588 tcg_temp_free_i32(tcg_res
);
5591 /* Floating point data-processing (3 source)
5592 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
5593 * +---+---+---+-----------+------+----+------+----+------+------+------+
5594 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
5595 * +---+---+---+-----------+------+----+------+----+------+------+------+
5597 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
5599 int type
= extract32(insn
, 22, 2);
5600 int rd
= extract32(insn
, 0, 5);
5601 int rn
= extract32(insn
, 5, 5);
5602 int ra
= extract32(insn
, 10, 5);
5603 int rm
= extract32(insn
, 16, 5);
5604 bool o0
= extract32(insn
, 15, 1);
5605 bool o1
= extract32(insn
, 21, 1);
5609 if (!fp_access_check(s
)) {
5612 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5615 if (!fp_access_check(s
)) {
5618 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5621 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
5622 unallocated_encoding(s
);
5625 if (!fp_access_check(s
)) {
5628 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
5631 unallocated_encoding(s
);
5635 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
5636 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
5637 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
5639 static uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
5645 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5646 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
5647 extract32(imm8
, 0, 6);
5651 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5652 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
5653 (extract32(imm8
, 0, 6) << 3);
5657 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
5658 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
5659 (extract32(imm8
, 0, 6) << 6);
5662 g_assert_not_reached();
5667 /* Floating point immediate
5668 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
5669 * +---+---+---+-----------+------+---+------------+-------+------+------+
5670 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
5671 * +---+---+---+-----------+------+---+------------+-------+------+------+
5673 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
5675 int rd
= extract32(insn
, 0, 5);
5676 int imm8
= extract32(insn
, 13, 8);
5677 int is_double
= extract32(insn
, 22, 2);
5681 if (is_double
> 1) {
5682 unallocated_encoding(s
);
5686 if (!fp_access_check(s
)) {
5690 imm
= vfp_expand_imm(MO_32
+ is_double
, imm8
);
5692 tcg_res
= tcg_const_i64(imm
);
5693 write_fp_dreg(s
, rd
, tcg_res
);
5694 tcg_temp_free_i64(tcg_res
);
5697 /* Handle floating point <=> fixed point conversions. Note that we can
5698 * also deal with fp <=> integer conversions as a special case (scale == 64)
5699 * OPTME: consider handling that special case specially or at least skipping
5700 * the call to scalbn in the helpers for zero shifts.
5702 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
5703 bool itof
, int rmode
, int scale
, int sf
, int type
)
5705 bool is_signed
= !(opcode
& 1);
5706 TCGv_ptr tcg_fpstatus
;
5707 TCGv_i32 tcg_shift
, tcg_single
;
5708 TCGv_i64 tcg_double
;
5710 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
5712 tcg_shift
= tcg_const_i32(64 - scale
);
5715 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
5717 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
5720 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
5722 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
5725 tcg_int
= tcg_extend
;
5729 case 1: /* float64 */
5730 tcg_double
= tcg_temp_new_i64();
5732 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
5733 tcg_shift
, tcg_fpstatus
);
5735 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
5736 tcg_shift
, tcg_fpstatus
);
5738 write_fp_dreg(s
, rd
, tcg_double
);
5739 tcg_temp_free_i64(tcg_double
);
5742 case 0: /* float32 */
5743 tcg_single
= tcg_temp_new_i32();
5745 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
5746 tcg_shift
, tcg_fpstatus
);
5748 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
5749 tcg_shift
, tcg_fpstatus
);
5751 write_fp_sreg(s
, rd
, tcg_single
);
5752 tcg_temp_free_i32(tcg_single
);
5755 case 3: /* float16 */
5756 tcg_single
= tcg_temp_new_i32();
5758 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
5759 tcg_shift
, tcg_fpstatus
);
5761 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
5762 tcg_shift
, tcg_fpstatus
);
5764 write_fp_sreg(s
, rd
, tcg_single
);
5765 tcg_temp_free_i32(tcg_single
);
5769 g_assert_not_reached();
5772 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
5775 if (extract32(opcode
, 2, 1)) {
5776 /* There are too many rounding modes to all fit into rmode,
5777 * so FCVTA[US] is a special case.
5779 rmode
= FPROUNDING_TIEAWAY
;
5782 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
5784 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
5787 case 1: /* float64 */
5788 tcg_double
= read_fp_dreg(s
, rn
);
5791 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
5792 tcg_shift
, tcg_fpstatus
);
5794 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
5795 tcg_shift
, tcg_fpstatus
);
5799 gen_helper_vfp_tould(tcg_int
, tcg_double
,
5800 tcg_shift
, tcg_fpstatus
);
5802 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
5803 tcg_shift
, tcg_fpstatus
);
5807 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
5809 tcg_temp_free_i64(tcg_double
);
5812 case 0: /* float32 */
5813 tcg_single
= read_fp_sreg(s
, rn
);
5816 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
5817 tcg_shift
, tcg_fpstatus
);
5819 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
5820 tcg_shift
, tcg_fpstatus
);
5823 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5825 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
5826 tcg_shift
, tcg_fpstatus
);
5828 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
5829 tcg_shift
, tcg_fpstatus
);
5831 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5832 tcg_temp_free_i32(tcg_dest
);
5834 tcg_temp_free_i32(tcg_single
);
5837 case 3: /* float16 */
5838 tcg_single
= read_fp_sreg(s
, rn
);
5841 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
5842 tcg_shift
, tcg_fpstatus
);
5844 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
5845 tcg_shift
, tcg_fpstatus
);
5848 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
5850 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
5851 tcg_shift
, tcg_fpstatus
);
5853 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
5854 tcg_shift
, tcg_fpstatus
);
5856 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
5857 tcg_temp_free_i32(tcg_dest
);
5859 tcg_temp_free_i32(tcg_single
);
5863 g_assert_not_reached();
5866 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
5867 tcg_temp_free_i32(tcg_rmode
);
5870 tcg_temp_free_ptr(tcg_fpstatus
);
5871 tcg_temp_free_i32(tcg_shift
);
5874 /* Floating point <-> fixed point conversions
5875 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5876 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5877 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5878 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5880 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
5882 int rd
= extract32(insn
, 0, 5);
5883 int rn
= extract32(insn
, 5, 5);
5884 int scale
= extract32(insn
, 10, 6);
5885 int opcode
= extract32(insn
, 16, 3);
5886 int rmode
= extract32(insn
, 19, 2);
5887 int type
= extract32(insn
, 22, 2);
5888 bool sbit
= extract32(insn
, 29, 1);
5889 bool sf
= extract32(insn
, 31, 1);
5892 if (sbit
|| (!sf
&& scale
< 32)) {
5893 unallocated_encoding(s
);
5898 case 0: /* float32 */
5899 case 1: /* float64 */
5901 case 3: /* float16 */
5902 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
5907 unallocated_encoding(s
);
5911 switch ((rmode
<< 3) | opcode
) {
5912 case 0x2: /* SCVTF */
5913 case 0x3: /* UCVTF */
5916 case 0x18: /* FCVTZS */
5917 case 0x19: /* FCVTZU */
5921 unallocated_encoding(s
);
5925 if (!fp_access_check(s
)) {
5929 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
5932 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
5934 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5935 * without conversion.
5939 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5945 tmp
= tcg_temp_new_i64();
5946 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
5947 write_fp_dreg(s
, rd
, tmp
);
5948 tcg_temp_free_i64(tmp
);
5952 write_fp_dreg(s
, rd
, tcg_rn
);
5955 /* 64 bit to top half. */
5956 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
5957 clear_vec_high(s
, true, rd
);
5961 tmp
= tcg_temp_new_i64();
5962 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
5963 write_fp_dreg(s
, rd
, tmp
);
5964 tcg_temp_free_i64(tmp
);
5967 g_assert_not_reached();
5970 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5975 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
5979 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
5982 /* 64 bits from top half */
5983 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
5987 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
5990 g_assert_not_reached();
5995 /* Floating point <-> integer conversions
5996 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5997 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5998 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5999 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6001 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6003 int rd
= extract32(insn
, 0, 5);
6004 int rn
= extract32(insn
, 5, 5);
6005 int opcode
= extract32(insn
, 16, 3);
6006 int rmode
= extract32(insn
, 19, 2);
6007 int type
= extract32(insn
, 22, 2);
6008 bool sbit
= extract32(insn
, 29, 1);
6009 bool sf
= extract32(insn
, 31, 1);
6012 unallocated_encoding(s
);
6018 bool itof
= opcode
& 1;
6021 unallocated_encoding(s
);
6025 switch (sf
<< 3 | type
<< 1 | rmode
) {
6026 case 0x0: /* 32 bit */
6027 case 0xa: /* 64 bit */
6028 case 0xd: /* 64 bit to top half of quad */
6030 case 0x6: /* 16-bit float, 32-bit int */
6031 case 0xe: /* 16-bit float, 64-bit int */
6032 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
6037 /* all other sf/type/rmode combinations are invalid */
6038 unallocated_encoding(s
);
6042 if (!fp_access_check(s
)) {
6045 handle_fmov(s
, rd
, rn
, type
, itof
);
6047 /* actual FP conversions */
6048 bool itof
= extract32(opcode
, 1, 1);
6050 if (rmode
!= 0 && opcode
> 1) {
6051 unallocated_encoding(s
);
6055 case 0: /* float32 */
6056 case 1: /* float64 */
6058 case 3: /* float16 */
6059 if (arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
6064 unallocated_encoding(s
);
6068 if (!fp_access_check(s
)) {
6071 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6075 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6076 * 31 30 29 28 25 24 0
6077 * +---+---+---+---------+-----------------------------+
6078 * | | 0 | | 1 1 1 1 | |
6079 * +---+---+---+---------+-----------------------------+
6081 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6083 if (extract32(insn
, 24, 1)) {
6084 /* Floating point data-processing (3 source) */
6085 disas_fp_3src(s
, insn
);
6086 } else if (extract32(insn
, 21, 1) == 0) {
6087 /* Floating point to fixed point conversions */
6088 disas_fp_fixed_conv(s
, insn
);
6090 switch (extract32(insn
, 10, 2)) {
6092 /* Floating point conditional compare */
6093 disas_fp_ccomp(s
, insn
);
6096 /* Floating point data-processing (2 source) */
6097 disas_fp_2src(s
, insn
);
6100 /* Floating point conditional select */
6101 disas_fp_csel(s
, insn
);
6104 switch (ctz32(extract32(insn
, 12, 4))) {
6105 case 0: /* [15:12] == xxx1 */
6106 /* Floating point immediate */
6107 disas_fp_imm(s
, insn
);
6109 case 1: /* [15:12] == xx10 */
6110 /* Floating point compare */
6111 disas_fp_compare(s
, insn
);
6113 case 2: /* [15:12] == x100 */
6114 /* Floating point data-processing (1 source) */
6115 disas_fp_1src(s
, insn
);
6117 case 3: /* [15:12] == 1000 */
6118 unallocated_encoding(s
);
6120 default: /* [15:12] == 0000 */
6121 /* Floating point <-> integer conversions */
6122 disas_fp_int_conv(s
, insn
);
6130 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6133 /* Extract 64 bits from the middle of two concatenated 64 bit
6134 * vector register slices left:right. The extracted bits start
6135 * at 'pos' bits into the right (least significant) side.
6136 * We return the result in tcg_right, and guarantee not to
6139 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6140 assert(pos
> 0 && pos
< 64);
6142 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6143 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6144 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6146 tcg_temp_free_i64(tcg_tmp
);
6150 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6151 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6152 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6153 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6155 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6157 int is_q
= extract32(insn
, 30, 1);
6158 int op2
= extract32(insn
, 22, 2);
6159 int imm4
= extract32(insn
, 11, 4);
6160 int rm
= extract32(insn
, 16, 5);
6161 int rn
= extract32(insn
, 5, 5);
6162 int rd
= extract32(insn
, 0, 5);
6163 int pos
= imm4
<< 3;
6164 TCGv_i64 tcg_resl
, tcg_resh
;
6166 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6167 unallocated_encoding(s
);
6171 if (!fp_access_check(s
)) {
6175 tcg_resh
= tcg_temp_new_i64();
6176 tcg_resl
= tcg_temp_new_i64();
6178 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6179 * either extracting 128 bits from a 128:128 concatenation, or
6180 * extracting 64 bits from a 64:64 concatenation.
6183 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6185 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6186 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6188 tcg_gen_movi_i64(tcg_resh
, 0);
6195 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6196 EltPosns
*elt
= eltposns
;
6203 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6205 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6208 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6209 tcg_hh
= tcg_temp_new_i64();
6210 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6211 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6212 tcg_temp_free_i64(tcg_hh
);
6216 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6217 tcg_temp_free_i64(tcg_resl
);
6218 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6219 tcg_temp_free_i64(tcg_resh
);
6223 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6224 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6225 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6226 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6228 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6230 int op2
= extract32(insn
, 22, 2);
6231 int is_q
= extract32(insn
, 30, 1);
6232 int rm
= extract32(insn
, 16, 5);
6233 int rn
= extract32(insn
, 5, 5);
6234 int rd
= extract32(insn
, 0, 5);
6235 int is_tblx
= extract32(insn
, 12, 1);
6236 int len
= extract32(insn
, 13, 2);
6237 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6238 TCGv_i32 tcg_regno
, tcg_numregs
;
6241 unallocated_encoding(s
);
6245 if (!fp_access_check(s
)) {
6249 /* This does a table lookup: for every byte element in the input
6250 * we index into a table formed from up to four vector registers,
6251 * and then the output is the result of the lookups. Our helper
6252 * function does the lookup operation for a single 64 bit part of
6255 tcg_resl
= tcg_temp_new_i64();
6256 tcg_resh
= tcg_temp_new_i64();
6259 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6261 tcg_gen_movi_i64(tcg_resl
, 0);
6263 if (is_tblx
&& is_q
) {
6264 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6266 tcg_gen_movi_i64(tcg_resh
, 0);
6269 tcg_idx
= tcg_temp_new_i64();
6270 tcg_regno
= tcg_const_i32(rn
);
6271 tcg_numregs
= tcg_const_i32(len
+ 1);
6272 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6273 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6274 tcg_regno
, tcg_numregs
);
6276 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6277 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6278 tcg_regno
, tcg_numregs
);
6280 tcg_temp_free_i64(tcg_idx
);
6281 tcg_temp_free_i32(tcg_regno
);
6282 tcg_temp_free_i32(tcg_numregs
);
6284 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6285 tcg_temp_free_i64(tcg_resl
);
6286 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6287 tcg_temp_free_i64(tcg_resh
);
6291 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6292 * +---+---+-------------+------+---+------+---+------------------+------+
6293 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6294 * +---+---+-------------+------+---+------+---+------------------+------+
6296 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6298 int rd
= extract32(insn
, 0, 5);
6299 int rn
= extract32(insn
, 5, 5);
6300 int rm
= extract32(insn
, 16, 5);
6301 int size
= extract32(insn
, 22, 2);
6302 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6303 * bit 2 indicates 1 vs 2 variant of the insn.
6305 int opcode
= extract32(insn
, 12, 2);
6306 bool part
= extract32(insn
, 14, 1);
6307 bool is_q
= extract32(insn
, 30, 1);
6308 int esize
= 8 << size
;
6310 int datasize
= is_q
? 128 : 64;
6311 int elements
= datasize
/ esize
;
6312 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6314 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6315 unallocated_encoding(s
);
6319 if (!fp_access_check(s
)) {
6323 tcg_resl
= tcg_const_i64(0);
6324 tcg_resh
= tcg_const_i64(0);
6325 tcg_res
= tcg_temp_new_i64();
6327 for (i
= 0; i
< elements
; i
++) {
6329 case 1: /* UZP1/2 */
6331 int midpoint
= elements
/ 2;
6333 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6335 read_vec_element(s
, tcg_res
, rm
,
6336 2 * (i
- midpoint
) + part
, size
);
6340 case 2: /* TRN1/2 */
6342 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6344 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6347 case 3: /* ZIP1/2 */
6349 int base
= part
* elements
/ 2;
6351 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6353 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6358 g_assert_not_reached();
6363 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6364 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6366 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6367 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6371 tcg_temp_free_i64(tcg_res
);
6373 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6374 tcg_temp_free_i64(tcg_resl
);
6375 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6376 tcg_temp_free_i64(tcg_resh
);
6380 * do_reduction_op helper
6382 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6383 * important for correct NaN propagation that we do these
6384 * operations in exactly the order specified by the pseudocode.
6386 * This is a recursive function, TCG temps should be freed by the
6387 * calling function once it is done with the values.
6389 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
6390 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
6392 if (esize
== size
) {
6394 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
6397 /* We should have one register left here */
6398 assert(ctpop8(vmap
) == 1);
6399 element
= ctz32(vmap
);
6400 assert(element
< 8);
6402 tcg_elem
= tcg_temp_new_i32();
6403 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
6406 int bits
= size
/ 2;
6407 int shift
= ctpop8(vmap
) / 2;
6408 int vmap_lo
= (vmap
>> shift
) & vmap
;
6409 int vmap_hi
= (vmap
& ~vmap_lo
);
6410 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
6412 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
6413 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
6414 tcg_res
= tcg_temp_new_i32();
6417 case 0x0c: /* fmaxnmv half-precision */
6418 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6420 case 0x0f: /* fmaxv half-precision */
6421 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6423 case 0x1c: /* fminnmv half-precision */
6424 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6426 case 0x1f: /* fminv half-precision */
6427 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6429 case 0x2c: /* fmaxnmv */
6430 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6432 case 0x2f: /* fmaxv */
6433 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6435 case 0x3c: /* fminnmv */
6436 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6438 case 0x3f: /* fminv */
6439 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6442 g_assert_not_reached();
6445 tcg_temp_free_i32(tcg_hi
);
6446 tcg_temp_free_i32(tcg_lo
);
6451 /* AdvSIMD across lanes
6452 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6453 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6454 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6455 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6457 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
6459 int rd
= extract32(insn
, 0, 5);
6460 int rn
= extract32(insn
, 5, 5);
6461 int size
= extract32(insn
, 22, 2);
6462 int opcode
= extract32(insn
, 12, 5);
6463 bool is_q
= extract32(insn
, 30, 1);
6464 bool is_u
= extract32(insn
, 29, 1);
6466 bool is_min
= false;
6470 TCGv_i64 tcg_res
, tcg_elt
;
6473 case 0x1b: /* ADDV */
6475 unallocated_encoding(s
);
6479 case 0x3: /* SADDLV, UADDLV */
6480 case 0xa: /* SMAXV, UMAXV */
6481 case 0x1a: /* SMINV, UMINV */
6482 if (size
== 3 || (size
== 2 && !is_q
)) {
6483 unallocated_encoding(s
);
6487 case 0xc: /* FMAXNMV, FMINNMV */
6488 case 0xf: /* FMAXV, FMINV */
6489 /* Bit 1 of size field encodes min vs max and the actual size
6490 * depends on the encoding of the U bit. If not set (and FP16
6491 * enabled) then we do half-precision float instead of single
6494 is_min
= extract32(size
, 1, 1);
6496 if (!is_u
&& arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
6498 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
6499 unallocated_encoding(s
);
6506 unallocated_encoding(s
);
6510 if (!fp_access_check(s
)) {
6515 elements
= (is_q
? 128 : 64) / esize
;
6517 tcg_res
= tcg_temp_new_i64();
6518 tcg_elt
= tcg_temp_new_i64();
6520 /* These instructions operate across all lanes of a vector
6521 * to produce a single result. We can guarantee that a 64
6522 * bit intermediate is sufficient:
6523 * + for [US]ADDLV the maximum element size is 32 bits, and
6524 * the result type is 64 bits
6525 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
6526 * same as the element size, which is 32 bits at most
6527 * For the integer operations we can choose to work at 64
6528 * or 32 bits and truncate at the end; for simplicity
6529 * we use 64 bits always. The floating point
6530 * ops do require 32 bit intermediates, though.
6533 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
6535 for (i
= 1; i
< elements
; i
++) {
6536 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
6539 case 0x03: /* SADDLV / UADDLV */
6540 case 0x1b: /* ADDV */
6541 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
6543 case 0x0a: /* SMAXV / UMAXV */
6545 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
6547 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
6550 case 0x1a: /* SMINV / UMINV */
6552 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
6554 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
6558 g_assert_not_reached();
6563 /* Floating point vector reduction ops which work across 32
6564 * bit (single) or 16 bit (half-precision) intermediates.
6565 * Note that correct NaN propagation requires that we do these
6566 * operations in exactly the order specified by the pseudocode.
6568 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
6569 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
6570 int vmap
= (1 << elements
) - 1;
6571 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
6572 (is_q
? 128 : 64), vmap
, fpst
);
6573 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
6574 tcg_temp_free_i32(tcg_res32
);
6575 tcg_temp_free_ptr(fpst
);
6578 tcg_temp_free_i64(tcg_elt
);
6580 /* Now truncate the result to the width required for the final output */
6581 if (opcode
== 0x03) {
6582 /* SADDLV, UADDLV: result is 2*esize */
6588 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
6591 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
6594 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6599 g_assert_not_reached();
6602 write_fp_dreg(s
, rd
, tcg_res
);
6603 tcg_temp_free_i64(tcg_res
);
6606 /* DUP (Element, Vector)
6608 * 31 30 29 21 20 16 15 10 9 5 4 0
6609 * +---+---+-------------------+--------+-------------+------+------+
6610 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6611 * +---+---+-------------------+--------+-------------+------+------+
6613 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6615 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
6618 int size
= ctz32(imm5
);
6619 int index
= imm5
>> (size
+ 1);
6621 if (size
> 3 || (size
== 3 && !is_q
)) {
6622 unallocated_encoding(s
);
6626 if (!fp_access_check(s
)) {
6630 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
6631 vec_reg_offset(s
, rn
, index
, size
),
6632 is_q
? 16 : 8, vec_full_reg_size(s
));
6635 /* DUP (element, scalar)
6636 * 31 21 20 16 15 10 9 5 4 0
6637 * +-----------------------+--------+-------------+------+------+
6638 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6639 * +-----------------------+--------+-------------+------+------+
6641 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
6644 int size
= ctz32(imm5
);
6649 unallocated_encoding(s
);
6653 if (!fp_access_check(s
)) {
6657 index
= imm5
>> (size
+ 1);
6659 /* This instruction just extracts the specified element and
6660 * zero-extends it into the bottom of the destination register.
6662 tmp
= tcg_temp_new_i64();
6663 read_vec_element(s
, tmp
, rn
, index
, size
);
6664 write_fp_dreg(s
, rd
, tmp
);
6665 tcg_temp_free_i64(tmp
);
6670 * 31 30 29 21 20 16 15 10 9 5 4 0
6671 * +---+---+-------------------+--------+-------------+------+------+
6672 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
6673 * +---+---+-------------------+--------+-------------+------+------+
6675 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6677 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
6680 int size
= ctz32(imm5
);
6681 uint32_t dofs
, oprsz
, maxsz
;
6683 if (size
> 3 || ((size
== 3) && !is_q
)) {
6684 unallocated_encoding(s
);
6688 if (!fp_access_check(s
)) {
6692 dofs
= vec_full_reg_offset(s
, rd
);
6693 oprsz
= is_q
? 16 : 8;
6694 maxsz
= vec_full_reg_size(s
);
6696 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
6701 * 31 21 20 16 15 14 11 10 9 5 4 0
6702 * +-----------------------+--------+------------+---+------+------+
6703 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6704 * +-----------------------+--------+------------+---+------+------+
6706 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6707 * index: encoded in imm5<4:size+1>
6709 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
6712 int size
= ctz32(imm5
);
6713 int src_index
, dst_index
;
6717 unallocated_encoding(s
);
6721 if (!fp_access_check(s
)) {
6725 dst_index
= extract32(imm5
, 1+size
, 5);
6726 src_index
= extract32(imm4
, size
, 4);
6728 tmp
= tcg_temp_new_i64();
6730 read_vec_element(s
, tmp
, rn
, src_index
, size
);
6731 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
6733 tcg_temp_free_i64(tmp
);
6739 * 31 21 20 16 15 10 9 5 4 0
6740 * +-----------------------+--------+-------------+------+------+
6741 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
6742 * +-----------------------+--------+-------------+------+------+
6744 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6745 * index: encoded in imm5<4:size+1>
6747 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
6749 int size
= ctz32(imm5
);
6753 unallocated_encoding(s
);
6757 if (!fp_access_check(s
)) {
6761 idx
= extract32(imm5
, 1 + size
, 4 - size
);
6762 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
6769 * 31 30 29 21 20 16 15 12 10 9 5 4 0
6770 * +---+---+-------------------+--------+-------------+------+------+
6771 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
6772 * +---+---+-------------------+--------+-------------+------+------+
6774 * U: unsigned when set
6775 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6777 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
6778 int rn
, int rd
, int imm5
)
6780 int size
= ctz32(imm5
);
6784 /* Check for UnallocatedEncodings */
6786 if (size
> 2 || (size
== 2 && !is_q
)) {
6787 unallocated_encoding(s
);
6792 || (size
< 3 && is_q
)
6793 || (size
== 3 && !is_q
)) {
6794 unallocated_encoding(s
);
6799 if (!fp_access_check(s
)) {
6803 element
= extract32(imm5
, 1+size
, 4);
6805 tcg_rd
= cpu_reg(s
, rd
);
6806 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
6807 if (is_signed
&& !is_q
) {
6808 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
6813 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6814 * +---+---+----+-----------------+------+---+------+---+------+------+
6815 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6816 * +---+---+----+-----------------+------+---+------+---+------+------+
6818 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
6820 int rd
= extract32(insn
, 0, 5);
6821 int rn
= extract32(insn
, 5, 5);
6822 int imm4
= extract32(insn
, 11, 4);
6823 int op
= extract32(insn
, 29, 1);
6824 int is_q
= extract32(insn
, 30, 1);
6825 int imm5
= extract32(insn
, 16, 5);
6830 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
6832 unallocated_encoding(s
);
6837 /* DUP (element - vector) */
6838 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
6842 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
6847 handle_simd_insg(s
, rd
, rn
, imm5
);
6849 unallocated_encoding(s
);
6854 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6855 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
6858 unallocated_encoding(s
);
6864 /* AdvSIMD modified immediate
6865 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6866 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6867 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6868 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6870 * There are a number of operations that can be carried out here:
6871 * MOVI - move (shifted) imm into register
6872 * MVNI - move inverted (shifted) imm into register
6873 * ORR - bitwise OR of (shifted) imm with register
6874 * BIC - bitwise clear of (shifted) imm with register
6875 * With ARMv8.2 we also have:
6876 * FMOV half-precision
6878 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
6880 int rd
= extract32(insn
, 0, 5);
6881 int cmode
= extract32(insn
, 12, 4);
6882 int cmode_3_1
= extract32(cmode
, 1, 3);
6883 int cmode_0
= extract32(cmode
, 0, 1);
6884 int o2
= extract32(insn
, 11, 1);
6885 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
6886 bool is_neg
= extract32(insn
, 29, 1);
6887 bool is_q
= extract32(insn
, 30, 1);
6890 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
6891 /* Check for FMOV (vector, immediate) - half-precision */
6892 if (!(arm_dc_feature(s
, ARM_FEATURE_V8_FP16
) && o2
&& cmode
== 0xf)) {
6893 unallocated_encoding(s
);
6898 if (!fp_access_check(s
)) {
6902 /* See AdvSIMDExpandImm() in ARM ARM */
6903 switch (cmode_3_1
) {
6904 case 0: /* Replicate(Zeros(24):imm8, 2) */
6905 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6906 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6907 case 3: /* Replicate(imm8:Zeros(24), 2) */
6909 int shift
= cmode_3_1
* 8;
6910 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
6913 case 4: /* Replicate(Zeros(8):imm8, 4) */
6914 case 5: /* Replicate(imm8:Zeros(8), 4) */
6916 int shift
= (cmode_3_1
& 0x1) * 8;
6917 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
6922 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6923 imm
= (abcdefgh
<< 16) | 0xffff;
6925 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6926 imm
= (abcdefgh
<< 8) | 0xff;
6928 imm
= bitfield_replicate(imm
, 32);
6931 if (!cmode_0
&& !is_neg
) {
6932 imm
= bitfield_replicate(abcdefgh
, 8);
6933 } else if (!cmode_0
&& is_neg
) {
6936 for (i
= 0; i
< 8; i
++) {
6937 if ((abcdefgh
) & (1 << i
)) {
6938 imm
|= 0xffULL
<< (i
* 8);
6941 } else if (cmode_0
) {
6943 imm
= (abcdefgh
& 0x3f) << 48;
6944 if (abcdefgh
& 0x80) {
6945 imm
|= 0x8000000000000000ULL
;
6947 if (abcdefgh
& 0x40) {
6948 imm
|= 0x3fc0000000000000ULL
;
6950 imm
|= 0x4000000000000000ULL
;
6954 /* FMOV (vector, immediate) - half-precision */
6955 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
6956 /* now duplicate across the lanes */
6957 imm
= bitfield_replicate(imm
, 16);
6959 imm
= (abcdefgh
& 0x3f) << 19;
6960 if (abcdefgh
& 0x80) {
6963 if (abcdefgh
& 0x40) {
6974 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
6975 g_assert_not_reached();
6978 if (cmode_3_1
!= 7 && is_neg
) {
6982 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
6983 /* MOVI or MVNI, with MVNI negation handled above. */
6984 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
6985 vec_full_reg_size(s
), imm
);
6987 /* ORR or BIC, with BIC negation to AND handled above. */
6989 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
6991 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
6996 /* AdvSIMD scalar copy
6997 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6998 * +-----+----+-----------------+------+---+------+---+------+------+
6999 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7000 * +-----+----+-----------------+------+---+------+---+------+------+
7002 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7004 int rd
= extract32(insn
, 0, 5);
7005 int rn
= extract32(insn
, 5, 5);
7006 int imm4
= extract32(insn
, 11, 4);
7007 int imm5
= extract32(insn
, 16, 5);
7008 int op
= extract32(insn
, 29, 1);
7010 if (op
!= 0 || imm4
!= 0) {
7011 unallocated_encoding(s
);
7015 /* DUP (element, scalar) */
7016 handle_simd_dupes(s
, rd
, rn
, imm5
);
7019 /* AdvSIMD scalar pairwise
7020 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7021 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7022 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7023 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7025 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7027 int u
= extract32(insn
, 29, 1);
7028 int size
= extract32(insn
, 22, 2);
7029 int opcode
= extract32(insn
, 12, 5);
7030 int rn
= extract32(insn
, 5, 5);
7031 int rd
= extract32(insn
, 0, 5);
7034 /* For some ops (the FP ones), size[1] is part of the encoding.
7035 * For ADDP strictly it is not but size[1] is always 1 for valid
7038 opcode
|= (extract32(size
, 1, 1) << 5);
7041 case 0x3b: /* ADDP */
7042 if (u
|| size
!= 3) {
7043 unallocated_encoding(s
);
7046 if (!fp_access_check(s
)) {
7052 case 0xc: /* FMAXNMP */
7053 case 0xd: /* FADDP */
7054 case 0xf: /* FMAXP */
7055 case 0x2c: /* FMINNMP */
7056 case 0x2f: /* FMINP */
7057 /* FP op, size[0] is 32 or 64 bit*/
7059 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
7060 unallocated_encoding(s
);
7066 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7069 if (!fp_access_check(s
)) {
7073 fpst
= get_fpstatus_ptr(size
== MO_16
);
7076 unallocated_encoding(s
);
7080 if (size
== MO_64
) {
7081 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7082 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7083 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7085 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7086 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7089 case 0x3b: /* ADDP */
7090 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7092 case 0xc: /* FMAXNMP */
7093 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7095 case 0xd: /* FADDP */
7096 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7098 case 0xf: /* FMAXP */
7099 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7101 case 0x2c: /* FMINNMP */
7102 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7104 case 0x2f: /* FMINP */
7105 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7108 g_assert_not_reached();
7111 write_fp_dreg(s
, rd
, tcg_res
);
7113 tcg_temp_free_i64(tcg_op1
);
7114 tcg_temp_free_i64(tcg_op2
);
7115 tcg_temp_free_i64(tcg_res
);
7117 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7118 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7119 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7121 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7122 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7124 if (size
== MO_16
) {
7126 case 0xc: /* FMAXNMP */
7127 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7129 case 0xd: /* FADDP */
7130 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7132 case 0xf: /* FMAXP */
7133 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7135 case 0x2c: /* FMINNMP */
7136 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7138 case 0x2f: /* FMINP */
7139 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7142 g_assert_not_reached();
7146 case 0xc: /* FMAXNMP */
7147 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7149 case 0xd: /* FADDP */
7150 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7152 case 0xf: /* FMAXP */
7153 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7155 case 0x2c: /* FMINNMP */
7156 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7158 case 0x2f: /* FMINP */
7159 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7162 g_assert_not_reached();
7166 write_fp_sreg(s
, rd
, tcg_res
);
7168 tcg_temp_free_i32(tcg_op1
);
7169 tcg_temp_free_i32(tcg_op2
);
7170 tcg_temp_free_i32(tcg_res
);
7174 tcg_temp_free_ptr(fpst
);
7179 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7181 * This code is handles the common shifting code and is used by both
7182 * the vector and scalar code.
7184 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7185 TCGv_i64 tcg_rnd
, bool accumulate
,
7186 bool is_u
, int size
, int shift
)
7188 bool extended_result
= false;
7189 bool round
= tcg_rnd
!= NULL
;
7191 TCGv_i64 tcg_src_hi
;
7193 if (round
&& size
== 3) {
7194 extended_result
= true;
7195 ext_lshift
= 64 - shift
;
7196 tcg_src_hi
= tcg_temp_new_i64();
7197 } else if (shift
== 64) {
7198 if (!accumulate
&& is_u
) {
7199 /* result is zero */
7200 tcg_gen_movi_i64(tcg_res
, 0);
7205 /* Deal with the rounding step */
7207 if (extended_result
) {
7208 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7210 /* take care of sign extending tcg_res */
7211 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7212 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7213 tcg_src
, tcg_src_hi
,
7216 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7220 tcg_temp_free_i64(tcg_zero
);
7222 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7226 /* Now do the shift right */
7227 if (round
&& extended_result
) {
7228 /* extended case, >64 bit precision required */
7229 if (ext_lshift
== 0) {
7230 /* special case, only high bits matter */
7231 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7233 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7234 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7235 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7240 /* essentially shifting in 64 zeros */
7241 tcg_gen_movi_i64(tcg_src
, 0);
7243 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7247 /* effectively extending the sign-bit */
7248 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7250 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7256 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7258 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7261 if (extended_result
) {
7262 tcg_temp_free_i64(tcg_src_hi
);
7266 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7267 static void handle_scalar_simd_shri(DisasContext
*s
,
7268 bool is_u
, int immh
, int immb
,
7269 int opcode
, int rn
, int rd
)
7272 int immhb
= immh
<< 3 | immb
;
7273 int shift
= 2 * (8 << size
) - immhb
;
7274 bool accumulate
= false;
7276 bool insert
= false;
7281 if (!extract32(immh
, 3, 1)) {
7282 unallocated_encoding(s
);
7286 if (!fp_access_check(s
)) {
7291 case 0x02: /* SSRA / USRA (accumulate) */
7294 case 0x04: /* SRSHR / URSHR (rounding) */
7297 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7298 accumulate
= round
= true;
7300 case 0x08: /* SRI */
7306 uint64_t round_const
= 1ULL << (shift
- 1);
7307 tcg_round
= tcg_const_i64(round_const
);
7312 tcg_rn
= read_fp_dreg(s
, rn
);
7313 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7316 /* shift count same as element size is valid but does nothing;
7317 * special case to avoid potential shift by 64.
7319 int esize
= 8 << size
;
7320 if (shift
!= esize
) {
7321 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7322 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7325 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7326 accumulate
, is_u
, size
, shift
);
7329 write_fp_dreg(s
, rd
, tcg_rd
);
7331 tcg_temp_free_i64(tcg_rn
);
7332 tcg_temp_free_i64(tcg_rd
);
7334 tcg_temp_free_i64(tcg_round
);
7338 /* SHL/SLI - Scalar shift left */
7339 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7340 int immh
, int immb
, int opcode
,
7343 int size
= 32 - clz32(immh
) - 1;
7344 int immhb
= immh
<< 3 | immb
;
7345 int shift
= immhb
- (8 << size
);
7346 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7347 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7349 if (!extract32(immh
, 3, 1)) {
7350 unallocated_encoding(s
);
7354 if (!fp_access_check(s
)) {
7358 tcg_rn
= read_fp_dreg(s
, rn
);
7359 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7362 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7364 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7367 write_fp_dreg(s
, rd
, tcg_rd
);
7369 tcg_temp_free_i64(tcg_rn
);
7370 tcg_temp_free_i64(tcg_rd
);
7373 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7374 * (signed/unsigned) narrowing */
7375 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7376 bool is_u_shift
, bool is_u_narrow
,
7377 int immh
, int immb
, int opcode
,
7380 int immhb
= immh
<< 3 | immb
;
7381 int size
= 32 - clz32(immh
) - 1;
7382 int esize
= 8 << size
;
7383 int shift
= (2 * esize
) - immhb
;
7384 int elements
= is_scalar
? 1 : (64 / esize
);
7385 bool round
= extract32(opcode
, 0, 1);
7386 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
7387 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
7388 TCGv_i32 tcg_rd_narrowed
;
7391 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
7392 { gen_helper_neon_narrow_sat_s8
,
7393 gen_helper_neon_unarrow_sat8
},
7394 { gen_helper_neon_narrow_sat_s16
,
7395 gen_helper_neon_unarrow_sat16
},
7396 { gen_helper_neon_narrow_sat_s32
,
7397 gen_helper_neon_unarrow_sat32
},
7400 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
7401 gen_helper_neon_narrow_sat_u8
,
7402 gen_helper_neon_narrow_sat_u16
,
7403 gen_helper_neon_narrow_sat_u32
,
7406 NeonGenNarrowEnvFn
*narrowfn
;
7412 if (extract32(immh
, 3, 1)) {
7413 unallocated_encoding(s
);
7417 if (!fp_access_check(s
)) {
7422 narrowfn
= unsigned_narrow_fns
[size
];
7424 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
7427 tcg_rn
= tcg_temp_new_i64();
7428 tcg_rd
= tcg_temp_new_i64();
7429 tcg_rd_narrowed
= tcg_temp_new_i32();
7430 tcg_final
= tcg_const_i64(0);
7433 uint64_t round_const
= 1ULL << (shift
- 1);
7434 tcg_round
= tcg_const_i64(round_const
);
7439 for (i
= 0; i
< elements
; i
++) {
7440 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
7441 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7442 false, is_u_shift
, size
+1, shift
);
7443 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
7444 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
7445 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
7449 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
7451 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
7455 tcg_temp_free_i64(tcg_round
);
7457 tcg_temp_free_i64(tcg_rn
);
7458 tcg_temp_free_i64(tcg_rd
);
7459 tcg_temp_free_i32(tcg_rd_narrowed
);
7460 tcg_temp_free_i64(tcg_final
);
7462 clear_vec_high(s
, is_q
, rd
);
7465 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
7466 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
7467 bool src_unsigned
, bool dst_unsigned
,
7468 int immh
, int immb
, int rn
, int rd
)
7470 int immhb
= immh
<< 3 | immb
;
7471 int size
= 32 - clz32(immh
) - 1;
7472 int shift
= immhb
- (8 << size
);
7476 assert(!(scalar
&& is_q
));
7479 if (!is_q
&& extract32(immh
, 3, 1)) {
7480 unallocated_encoding(s
);
7484 /* Since we use the variable-shift helpers we must
7485 * replicate the shift count into each element of
7486 * the tcg_shift value.
7490 shift
|= shift
<< 8;
7493 shift
|= shift
<< 16;
7499 g_assert_not_reached();
7503 if (!fp_access_check(s
)) {
7508 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
7509 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
7510 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
7511 { NULL
, gen_helper_neon_qshl_u64
},
7513 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
7514 int maxpass
= is_q
? 2 : 1;
7516 for (pass
= 0; pass
< maxpass
; pass
++) {
7517 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7519 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7520 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7521 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7523 tcg_temp_free_i64(tcg_op
);
7525 tcg_temp_free_i64(tcg_shift
);
7526 clear_vec_high(s
, is_q
, rd
);
7528 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
7529 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
7531 { gen_helper_neon_qshl_s8
,
7532 gen_helper_neon_qshl_s16
,
7533 gen_helper_neon_qshl_s32
},
7534 { gen_helper_neon_qshlu_s8
,
7535 gen_helper_neon_qshlu_s16
,
7536 gen_helper_neon_qshlu_s32
}
7538 { NULL
, NULL
, NULL
},
7539 { gen_helper_neon_qshl_u8
,
7540 gen_helper_neon_qshl_u16
,
7541 gen_helper_neon_qshl_u32
}
7544 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
7545 TCGMemOp memop
= scalar
? size
: MO_32
;
7546 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
7548 for (pass
= 0; pass
< maxpass
; pass
++) {
7549 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7551 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
7552 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
7556 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
7559 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
7564 g_assert_not_reached();
7566 write_fp_sreg(s
, rd
, tcg_op
);
7568 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
7571 tcg_temp_free_i32(tcg_op
);
7573 tcg_temp_free_i32(tcg_shift
);
7576 clear_vec_high(s
, is_q
, rd
);
7581 /* Common vector code for handling integer to FP conversion */
7582 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
7583 int elements
, int is_signed
,
7584 int fracbits
, int size
)
7586 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
7587 TCGv_i32 tcg_shift
= NULL
;
7589 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
7592 if (fracbits
|| size
== MO_64
) {
7593 tcg_shift
= tcg_const_i32(fracbits
);
7596 if (size
== MO_64
) {
7597 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
7598 TCGv_i64 tcg_double
= tcg_temp_new_i64();
7600 for (pass
= 0; pass
< elements
; pass
++) {
7601 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
7604 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
7605 tcg_shift
, tcg_fpst
);
7607 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
7608 tcg_shift
, tcg_fpst
);
7610 if (elements
== 1) {
7611 write_fp_dreg(s
, rd
, tcg_double
);
7613 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
7617 tcg_temp_free_i64(tcg_int64
);
7618 tcg_temp_free_i64(tcg_double
);
7621 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
7622 TCGv_i32 tcg_float
= tcg_temp_new_i32();
7624 for (pass
= 0; pass
< elements
; pass
++) {
7625 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
7631 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
7632 tcg_shift
, tcg_fpst
);
7634 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
7635 tcg_shift
, tcg_fpst
);
7639 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
7641 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
7648 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
7649 tcg_shift
, tcg_fpst
);
7651 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
7652 tcg_shift
, tcg_fpst
);
7656 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
7658 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
7663 g_assert_not_reached();
7666 if (elements
== 1) {
7667 write_fp_sreg(s
, rd
, tcg_float
);
7669 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
7673 tcg_temp_free_i32(tcg_int32
);
7674 tcg_temp_free_i32(tcg_float
);
7677 tcg_temp_free_ptr(tcg_fpst
);
7679 tcg_temp_free_i32(tcg_shift
);
7682 clear_vec_high(s
, elements
<< size
== 16, rd
);
7685 /* UCVTF/SCVTF - Integer to FP conversion */
7686 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
7687 bool is_q
, bool is_u
,
7688 int immh
, int immb
, int opcode
,
7691 int size
, elements
, fracbits
;
7692 int immhb
= immh
<< 3 | immb
;
7696 if (!is_scalar
&& !is_q
) {
7697 unallocated_encoding(s
);
7700 } else if (immh
& 4) {
7702 } else if (immh
& 2) {
7704 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
7705 unallocated_encoding(s
);
7709 /* immh == 0 would be a failure of the decode logic */
7710 g_assert(immh
== 1);
7711 unallocated_encoding(s
);
7718 elements
= (8 << is_q
) >> size
;
7720 fracbits
= (16 << size
) - immhb
;
7722 if (!fp_access_check(s
)) {
7726 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
7729 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
7730 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
7731 bool is_q
, bool is_u
,
7732 int immh
, int immb
, int rn
, int rd
)
7734 int immhb
= immh
<< 3 | immb
;
7735 int pass
, size
, fracbits
;
7736 TCGv_ptr tcg_fpstatus
;
7737 TCGv_i32 tcg_rmode
, tcg_shift
;
7741 if (!is_scalar
&& !is_q
) {
7742 unallocated_encoding(s
);
7745 } else if (immh
& 0x4) {
7747 } else if (immh
& 0x2) {
7749 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
7750 unallocated_encoding(s
);
7754 /* Should have split out AdvSIMD modified immediate earlier. */
7756 unallocated_encoding(s
);
7760 if (!fp_access_check(s
)) {
7764 assert(!(is_scalar
&& is_q
));
7766 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
7767 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
7768 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7769 fracbits
= (16 << size
) - immhb
;
7770 tcg_shift
= tcg_const_i32(fracbits
);
7772 if (size
== MO_64
) {
7773 int maxpass
= is_scalar
? 1 : 2;
7775 for (pass
= 0; pass
< maxpass
; pass
++) {
7776 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7778 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7780 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7782 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7784 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
7785 tcg_temp_free_i64(tcg_op
);
7787 clear_vec_high(s
, is_q
, rd
);
7789 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
7790 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
7795 fn
= gen_helper_vfp_touhh
;
7797 fn
= gen_helper_vfp_toshh
;
7802 fn
= gen_helper_vfp_touls
;
7804 fn
= gen_helper_vfp_tosls
;
7808 g_assert_not_reached();
7811 for (pass
= 0; pass
< maxpass
; pass
++) {
7812 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7814 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
7815 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
7817 write_fp_sreg(s
, rd
, tcg_op
);
7819 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
7821 tcg_temp_free_i32(tcg_op
);
7824 clear_vec_high(s
, is_q
, rd
);
7828 tcg_temp_free_ptr(tcg_fpstatus
);
7829 tcg_temp_free_i32(tcg_shift
);
7830 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7831 tcg_temp_free_i32(tcg_rmode
);
7834 /* AdvSIMD scalar shift by immediate
7835 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
7836 * +-----+---+-------------+------+------+--------+---+------+------+
7837 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
7838 * +-----+---+-------------+------+------+--------+---+------+------+
7840 * This is the scalar version so it works on a fixed sized registers
7842 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
7844 int rd
= extract32(insn
, 0, 5);
7845 int rn
= extract32(insn
, 5, 5);
7846 int opcode
= extract32(insn
, 11, 5);
7847 int immb
= extract32(insn
, 16, 3);
7848 int immh
= extract32(insn
, 19, 4);
7849 bool is_u
= extract32(insn
, 29, 1);
7852 unallocated_encoding(s
);
7857 case 0x08: /* SRI */
7859 unallocated_encoding(s
);
7863 case 0x00: /* SSHR / USHR */
7864 case 0x02: /* SSRA / USRA */
7865 case 0x04: /* SRSHR / URSHR */
7866 case 0x06: /* SRSRA / URSRA */
7867 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7869 case 0x0a: /* SHL / SLI */
7870 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
7872 case 0x1c: /* SCVTF, UCVTF */
7873 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
7876 case 0x10: /* SQSHRUN, SQSHRUN2 */
7877 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
7879 unallocated_encoding(s
);
7882 handle_vec_simd_sqshrn(s
, true, false, false, true,
7883 immh
, immb
, opcode
, rn
, rd
);
7885 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7886 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7887 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
7888 immh
, immb
, opcode
, rn
, rd
);
7890 case 0xc: /* SQSHLU */
7892 unallocated_encoding(s
);
7895 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
7897 case 0xe: /* SQSHL, UQSHL */
7898 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
7900 case 0x1f: /* FCVTZS, FCVTZU */
7901 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
7904 unallocated_encoding(s
);
7909 /* AdvSIMD scalar three different
7910 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7911 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7912 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7913 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7915 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
7917 bool is_u
= extract32(insn
, 29, 1);
7918 int size
= extract32(insn
, 22, 2);
7919 int opcode
= extract32(insn
, 12, 4);
7920 int rm
= extract32(insn
, 16, 5);
7921 int rn
= extract32(insn
, 5, 5);
7922 int rd
= extract32(insn
, 0, 5);
7925 unallocated_encoding(s
);
7930 case 0x9: /* SQDMLAL, SQDMLAL2 */
7931 case 0xb: /* SQDMLSL, SQDMLSL2 */
7932 case 0xd: /* SQDMULL, SQDMULL2 */
7933 if (size
== 0 || size
== 3) {
7934 unallocated_encoding(s
);
7939 unallocated_encoding(s
);
7943 if (!fp_access_check(s
)) {
7948 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7949 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7950 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7952 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
7953 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
7955 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
7956 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7959 case 0xd: /* SQDMULL, SQDMULL2 */
7961 case 0xb: /* SQDMLSL, SQDMLSL2 */
7962 tcg_gen_neg_i64(tcg_res
, tcg_res
);
7964 case 0x9: /* SQDMLAL, SQDMLAL2 */
7965 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
7966 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
7970 g_assert_not_reached();
7973 write_fp_dreg(s
, rd
, tcg_res
);
7975 tcg_temp_free_i64(tcg_op1
);
7976 tcg_temp_free_i64(tcg_op2
);
7977 tcg_temp_free_i64(tcg_res
);
7979 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
7980 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
7981 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7983 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
7984 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
7987 case 0xd: /* SQDMULL, SQDMULL2 */
7989 case 0xb: /* SQDMLSL, SQDMLSL2 */
7990 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
7992 case 0x9: /* SQDMLAL, SQDMLAL2 */
7994 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
7995 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
7996 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
7998 tcg_temp_free_i64(tcg_op3
);
8002 g_assert_not_reached();
8005 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8006 write_fp_dreg(s
, rd
, tcg_res
);
8008 tcg_temp_free_i32(tcg_op1
);
8009 tcg_temp_free_i32(tcg_op2
);
8010 tcg_temp_free_i64(tcg_res
);
8014 /* CMTST : test is "if (X & Y != 0)". */
8015 static void gen_cmtst_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
8017 tcg_gen_and_i32(d
, a
, b
);
8018 tcg_gen_setcondi_i32(TCG_COND_NE
, d
, d
, 0);
8019 tcg_gen_neg_i32(d
, d
);
8022 static void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
8024 tcg_gen_and_i64(d
, a
, b
);
8025 tcg_gen_setcondi_i64(TCG_COND_NE
, d
, d
, 0);
8026 tcg_gen_neg_i64(d
, d
);
8029 static void gen_cmtst_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
8031 tcg_gen_and_vec(vece
, d
, a
, b
);
8032 tcg_gen_dupi_vec(vece
, a
, 0);
8033 tcg_gen_cmp_vec(TCG_COND_NE
, vece
, d
, d
, a
);
8036 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8037 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8039 /* Handle 64x64->64 opcodes which are shared between the scalar
8040 * and vector 3-same groups. We cover every opcode where size == 3
8041 * is valid in either the three-reg-same (integer, not pairwise)
8042 * or scalar-three-reg-same groups.
8047 case 0x1: /* SQADD */
8049 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8051 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8054 case 0x5: /* SQSUB */
8056 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8058 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8061 case 0x6: /* CMGT, CMHI */
8062 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8063 * We implement this using setcond (test) and then negating.
8065 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8067 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8068 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8070 case 0x7: /* CMGE, CMHS */
8071 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8073 case 0x11: /* CMTST, CMEQ */
8078 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8080 case 0x8: /* SSHL, USHL */
8082 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8084 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8087 case 0x9: /* SQSHL, UQSHL */
8089 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8091 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8094 case 0xa: /* SRSHL, URSHL */
8096 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8098 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8101 case 0xb: /* SQRSHL, UQRSHL */
8103 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8105 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8108 case 0x10: /* ADD, SUB */
8110 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8112 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8116 g_assert_not_reached();
8120 /* Handle the 3-same-operands float operations; shared by the scalar
8121 * and vector encodings. The caller must filter out any encodings
8122 * not allocated for the encoding it is dealing with.
8124 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8125 int fpopcode
, int rd
, int rn
, int rm
)
8128 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8130 for (pass
= 0; pass
< elements
; pass
++) {
8133 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8134 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8135 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8137 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8138 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8141 case 0x39: /* FMLS */
8142 /* As usual for ARM, separate negation for fused multiply-add */
8143 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8145 case 0x19: /* FMLA */
8146 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8147 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8150 case 0x18: /* FMAXNM */
8151 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8153 case 0x1a: /* FADD */
8154 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8156 case 0x1b: /* FMULX */
8157 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8159 case 0x1c: /* FCMEQ */
8160 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8162 case 0x1e: /* FMAX */
8163 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8165 case 0x1f: /* FRECPS */
8166 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8168 case 0x38: /* FMINNM */
8169 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8171 case 0x3a: /* FSUB */
8172 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8174 case 0x3e: /* FMIN */
8175 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8177 case 0x3f: /* FRSQRTS */
8178 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8180 case 0x5b: /* FMUL */
8181 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8183 case 0x5c: /* FCMGE */
8184 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8186 case 0x5d: /* FACGE */
8187 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8189 case 0x5f: /* FDIV */
8190 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8192 case 0x7a: /* FABD */
8193 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8194 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8196 case 0x7c: /* FCMGT */
8197 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8199 case 0x7d: /* FACGT */
8200 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8203 g_assert_not_reached();
8206 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8208 tcg_temp_free_i64(tcg_res
);
8209 tcg_temp_free_i64(tcg_op1
);
8210 tcg_temp_free_i64(tcg_op2
);
8213 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8214 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8215 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8217 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8218 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8221 case 0x39: /* FMLS */
8222 /* As usual for ARM, separate negation for fused multiply-add */
8223 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8225 case 0x19: /* FMLA */
8226 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8227 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8230 case 0x1a: /* FADD */
8231 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8233 case 0x1b: /* FMULX */
8234 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8236 case 0x1c: /* FCMEQ */
8237 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8239 case 0x1e: /* FMAX */
8240 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8242 case 0x1f: /* FRECPS */
8243 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8245 case 0x18: /* FMAXNM */
8246 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8248 case 0x38: /* FMINNM */
8249 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8251 case 0x3a: /* FSUB */
8252 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8254 case 0x3e: /* FMIN */
8255 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8257 case 0x3f: /* FRSQRTS */
8258 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8260 case 0x5b: /* FMUL */
8261 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8263 case 0x5c: /* FCMGE */
8264 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8266 case 0x5d: /* FACGE */
8267 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8269 case 0x5f: /* FDIV */
8270 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8272 case 0x7a: /* FABD */
8273 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8274 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8276 case 0x7c: /* FCMGT */
8277 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8279 case 0x7d: /* FACGT */
8280 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8283 g_assert_not_reached();
8286 if (elements
== 1) {
8287 /* scalar single so clear high part */
8288 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8290 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8291 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8292 tcg_temp_free_i64(tcg_tmp
);
8294 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8297 tcg_temp_free_i32(tcg_res
);
8298 tcg_temp_free_i32(tcg_op1
);
8299 tcg_temp_free_i32(tcg_op2
);
8303 tcg_temp_free_ptr(fpst
);
8305 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8308 /* AdvSIMD scalar three same
8309 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8310 * +-----+---+-----------+------+---+------+--------+---+------+------+
8311 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8312 * +-----+---+-----------+------+---+------+--------+---+------+------+
8314 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8316 int rd
= extract32(insn
, 0, 5);
8317 int rn
= extract32(insn
, 5, 5);
8318 int opcode
= extract32(insn
, 11, 5);
8319 int rm
= extract32(insn
, 16, 5);
8320 int size
= extract32(insn
, 22, 2);
8321 bool u
= extract32(insn
, 29, 1);
8324 if (opcode
>= 0x18) {
8325 /* Floating point: U, size[1] and opcode indicate operation */
8326 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8328 case 0x1b: /* FMULX */
8329 case 0x1f: /* FRECPS */
8330 case 0x3f: /* FRSQRTS */
8331 case 0x5d: /* FACGE */
8332 case 0x7d: /* FACGT */
8333 case 0x1c: /* FCMEQ */
8334 case 0x5c: /* FCMGE */
8335 case 0x7c: /* FCMGT */
8336 case 0x7a: /* FABD */
8339 unallocated_encoding(s
);
8343 if (!fp_access_check(s
)) {
8347 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8352 case 0x1: /* SQADD, UQADD */
8353 case 0x5: /* SQSUB, UQSUB */
8354 case 0x9: /* SQSHL, UQSHL */
8355 case 0xb: /* SQRSHL, UQRSHL */
8357 case 0x8: /* SSHL, USHL */
8358 case 0xa: /* SRSHL, URSHL */
8359 case 0x6: /* CMGT, CMHI */
8360 case 0x7: /* CMGE, CMHS */
8361 case 0x11: /* CMTST, CMEQ */
8362 case 0x10: /* ADD, SUB (vector) */
8364 unallocated_encoding(s
);
8368 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8369 if (size
!= 1 && size
!= 2) {
8370 unallocated_encoding(s
);
8375 unallocated_encoding(s
);
8379 if (!fp_access_check(s
)) {
8383 tcg_rd
= tcg_temp_new_i64();
8386 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8387 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8389 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8390 tcg_temp_free_i64(tcg_rn
);
8391 tcg_temp_free_i64(tcg_rm
);
8393 /* Do a single operation on the lowest element in the vector.
8394 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8395 * no side effects for all these operations.
8396 * OPTME: special-purpose helpers would avoid doing some
8397 * unnecessary work in the helper for the 8 and 16 bit cases.
8399 NeonGenTwoOpEnvFn
*genenvfn
;
8400 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8401 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8402 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8404 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8405 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
8408 case 0x1: /* SQADD, UQADD */
8410 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8411 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8412 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8413 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8415 genenvfn
= fns
[size
][u
];
8418 case 0x5: /* SQSUB, UQSUB */
8420 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8421 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8422 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8423 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8425 genenvfn
= fns
[size
][u
];
8428 case 0x9: /* SQSHL, UQSHL */
8430 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8431 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8432 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8433 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8435 genenvfn
= fns
[size
][u
];
8438 case 0xb: /* SQRSHL, UQRSHL */
8440 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8441 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8442 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8443 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
8445 genenvfn
= fns
[size
][u
];
8448 case 0x16: /* SQDMULH, SQRDMULH */
8450 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
8451 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
8452 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
8454 assert(size
== 1 || size
== 2);
8455 genenvfn
= fns
[size
- 1][u
];
8459 g_assert_not_reached();
8462 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
8463 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
8464 tcg_temp_free_i32(tcg_rd32
);
8465 tcg_temp_free_i32(tcg_rn
);
8466 tcg_temp_free_i32(tcg_rm
);
8469 write_fp_dreg(s
, rd
, tcg_rd
);
8471 tcg_temp_free_i64(tcg_rd
);
8474 /* AdvSIMD scalar three same FP16
8475 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
8476 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8477 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
8478 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8479 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
8480 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
8482 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
8485 int rd
= extract32(insn
, 0, 5);
8486 int rn
= extract32(insn
, 5, 5);
8487 int opcode
= extract32(insn
, 11, 3);
8488 int rm
= extract32(insn
, 16, 5);
8489 bool u
= extract32(insn
, 29, 1);
8490 bool a
= extract32(insn
, 23, 1);
8491 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
8498 case 0x03: /* FMULX */
8499 case 0x04: /* FCMEQ (reg) */
8500 case 0x07: /* FRECPS */
8501 case 0x0f: /* FRSQRTS */
8502 case 0x14: /* FCMGE (reg) */
8503 case 0x15: /* FACGE */
8504 case 0x1a: /* FABD */
8505 case 0x1c: /* FCMGT (reg) */
8506 case 0x1d: /* FACGT */
8509 unallocated_encoding(s
);
8513 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
8514 unallocated_encoding(s
);
8517 if (!fp_access_check(s
)) {
8521 fpst
= get_fpstatus_ptr(true);
8523 tcg_op1
= read_fp_hreg(s
, rn
);
8524 tcg_op2
= read_fp_hreg(s
, rm
);
8525 tcg_res
= tcg_temp_new_i32();
8528 case 0x03: /* FMULX */
8529 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8531 case 0x04: /* FCMEQ (reg) */
8532 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8534 case 0x07: /* FRECPS */
8535 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8537 case 0x0f: /* FRSQRTS */
8538 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8540 case 0x14: /* FCMGE (reg) */
8541 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8543 case 0x15: /* FACGE */
8544 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8546 case 0x1a: /* FABD */
8547 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8548 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
8550 case 0x1c: /* FCMGT (reg) */
8551 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8553 case 0x1d: /* FACGT */
8554 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8557 g_assert_not_reached();
8560 write_fp_sreg(s
, rd
, tcg_res
);
8563 tcg_temp_free_i32(tcg_res
);
8564 tcg_temp_free_i32(tcg_op1
);
8565 tcg_temp_free_i32(tcg_op2
);
8566 tcg_temp_free_ptr(fpst
);
8569 /* AdvSIMD scalar three same extra
8570 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
8571 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8572 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
8573 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8575 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
8578 int rd
= extract32(insn
, 0, 5);
8579 int rn
= extract32(insn
, 5, 5);
8580 int opcode
= extract32(insn
, 11, 4);
8581 int rm
= extract32(insn
, 16, 5);
8582 int size
= extract32(insn
, 22, 2);
8583 bool u
= extract32(insn
, 29, 1);
8584 TCGv_i32 ele1
, ele2
, ele3
;
8588 switch (u
* 16 + opcode
) {
8589 case 0x10: /* SQRDMLAH (vector) */
8590 case 0x11: /* SQRDMLSH (vector) */
8591 if (size
!= 1 && size
!= 2) {
8592 unallocated_encoding(s
);
8595 feature
= ARM_FEATURE_V8_RDM
;
8598 unallocated_encoding(s
);
8601 if (!arm_dc_feature(s
, feature
)) {
8602 unallocated_encoding(s
);
8605 if (!fp_access_check(s
)) {
8609 /* Do a single operation on the lowest element in the vector.
8610 * We use the standard Neon helpers and rely on 0 OP 0 == 0
8611 * with no side effects for all these operations.
8612 * OPTME: special-purpose helpers would avoid doing some
8613 * unnecessary work in the helper for the 16 bit cases.
8615 ele1
= tcg_temp_new_i32();
8616 ele2
= tcg_temp_new_i32();
8617 ele3
= tcg_temp_new_i32();
8619 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
8620 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
8621 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
8624 case 0x0: /* SQRDMLAH */
8626 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8628 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8631 case 0x1: /* SQRDMLSH */
8633 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8635 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
8639 g_assert_not_reached();
8641 tcg_temp_free_i32(ele1
);
8642 tcg_temp_free_i32(ele2
);
8644 res
= tcg_temp_new_i64();
8645 tcg_gen_extu_i32_i64(res
, ele3
);
8646 tcg_temp_free_i32(ele3
);
8648 write_fp_dreg(s
, rd
, res
);
8649 tcg_temp_free_i64(res
);
8652 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
8653 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
8654 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
8656 /* Handle 64->64 opcodes which are shared between the scalar and
8657 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
8658 * is valid in either group and also the double-precision fp ops.
8659 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
8665 case 0x4: /* CLS, CLZ */
8667 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
8669 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
8673 /* This opcode is shared with CNT and RBIT but we have earlier
8674 * enforced that size == 3 if and only if this is the NOT insn.
8676 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
8678 case 0x7: /* SQABS, SQNEG */
8680 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
8682 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
8685 case 0xa: /* CMLT */
8686 /* 64 bit integer comparison against zero, result is
8687 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
8692 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
8693 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8695 case 0x8: /* CMGT, CMGE */
8696 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
8698 case 0x9: /* CMEQ, CMLE */
8699 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
8701 case 0xb: /* ABS, NEG */
8703 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
8705 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8706 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
8707 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
8709 tcg_temp_free_i64(tcg_zero
);
8712 case 0x2f: /* FABS */
8713 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
8715 case 0x6f: /* FNEG */
8716 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
8718 case 0x7f: /* FSQRT */
8719 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
8721 case 0x1a: /* FCVTNS */
8722 case 0x1b: /* FCVTMS */
8723 case 0x1c: /* FCVTAS */
8724 case 0x3a: /* FCVTPS */
8725 case 0x3b: /* FCVTZS */
8727 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8728 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8729 tcg_temp_free_i32(tcg_shift
);
8732 case 0x5a: /* FCVTNU */
8733 case 0x5b: /* FCVTMU */
8734 case 0x5c: /* FCVTAU */
8735 case 0x7a: /* FCVTPU */
8736 case 0x7b: /* FCVTZU */
8738 TCGv_i32 tcg_shift
= tcg_const_i32(0);
8739 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
8740 tcg_temp_free_i32(tcg_shift
);
8743 case 0x18: /* FRINTN */
8744 case 0x19: /* FRINTM */
8745 case 0x38: /* FRINTP */
8746 case 0x39: /* FRINTZ */
8747 case 0x58: /* FRINTA */
8748 case 0x79: /* FRINTI */
8749 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
8751 case 0x59: /* FRINTX */
8752 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
8755 g_assert_not_reached();
8759 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
8760 bool is_scalar
, bool is_u
, bool is_q
,
8761 int size
, int rn
, int rd
)
8763 bool is_double
= (size
== MO_64
);
8766 if (!fp_access_check(s
)) {
8770 fpst
= get_fpstatus_ptr(size
== MO_16
);
8773 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8774 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8775 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8776 NeonGenTwoDoubleOPFn
*genfn
;
8781 case 0x2e: /* FCMLT (zero) */
8784 case 0x2c: /* FCMGT (zero) */
8785 genfn
= gen_helper_neon_cgt_f64
;
8787 case 0x2d: /* FCMEQ (zero) */
8788 genfn
= gen_helper_neon_ceq_f64
;
8790 case 0x6d: /* FCMLE (zero) */
8793 case 0x6c: /* FCMGE (zero) */
8794 genfn
= gen_helper_neon_cge_f64
;
8797 g_assert_not_reached();
8800 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8801 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8803 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
8805 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
8807 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8809 tcg_temp_free_i64(tcg_res
);
8810 tcg_temp_free_i64(tcg_zero
);
8811 tcg_temp_free_i64(tcg_op
);
8813 clear_vec_high(s
, !is_scalar
, rd
);
8815 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8816 TCGv_i32 tcg_zero
= tcg_const_i32(0);
8817 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8818 NeonGenTwoSingleOPFn
*genfn
;
8820 int pass
, maxpasses
;
8822 if (size
== MO_16
) {
8824 case 0x2e: /* FCMLT (zero) */
8827 case 0x2c: /* FCMGT (zero) */
8828 genfn
= gen_helper_advsimd_cgt_f16
;
8830 case 0x2d: /* FCMEQ (zero) */
8831 genfn
= gen_helper_advsimd_ceq_f16
;
8833 case 0x6d: /* FCMLE (zero) */
8836 case 0x6c: /* FCMGE (zero) */
8837 genfn
= gen_helper_advsimd_cge_f16
;
8840 g_assert_not_reached();
8844 case 0x2e: /* FCMLT (zero) */
8847 case 0x2c: /* FCMGT (zero) */
8848 genfn
= gen_helper_neon_cgt_f32
;
8850 case 0x2d: /* FCMEQ (zero) */
8851 genfn
= gen_helper_neon_ceq_f32
;
8853 case 0x6d: /* FCMLE (zero) */
8856 case 0x6c: /* FCMGE (zero) */
8857 genfn
= gen_helper_neon_cge_f32
;
8860 g_assert_not_reached();
8867 int vector_size
= 8 << is_q
;
8868 maxpasses
= vector_size
>> size
;
8871 for (pass
= 0; pass
< maxpasses
; pass
++) {
8872 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8874 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
8876 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
8879 write_fp_sreg(s
, rd
, tcg_res
);
8881 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
8884 tcg_temp_free_i32(tcg_res
);
8885 tcg_temp_free_i32(tcg_zero
);
8886 tcg_temp_free_i32(tcg_op
);
8888 clear_vec_high(s
, is_q
, rd
);
8892 tcg_temp_free_ptr(fpst
);
8895 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
8896 bool is_scalar
, bool is_u
, bool is_q
,
8897 int size
, int rn
, int rd
)
8899 bool is_double
= (size
== 3);
8900 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8903 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8904 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8907 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
8908 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8910 case 0x3d: /* FRECPE */
8911 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
8913 case 0x3f: /* FRECPX */
8914 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
8916 case 0x7d: /* FRSQRTE */
8917 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
8920 g_assert_not_reached();
8922 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8924 tcg_temp_free_i64(tcg_res
);
8925 tcg_temp_free_i64(tcg_op
);
8926 clear_vec_high(s
, !is_scalar
, rd
);
8928 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8929 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8930 int pass
, maxpasses
;
8935 maxpasses
= is_q
? 4 : 2;
8938 for (pass
= 0; pass
< maxpasses
; pass
++) {
8939 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
8942 case 0x3c: /* URECPE */
8943 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
8945 case 0x3d: /* FRECPE */
8946 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
8948 case 0x3f: /* FRECPX */
8949 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
8951 case 0x7d: /* FRSQRTE */
8952 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
8955 g_assert_not_reached();
8959 write_fp_sreg(s
, rd
, tcg_res
);
8961 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8964 tcg_temp_free_i32(tcg_res
);
8965 tcg_temp_free_i32(tcg_op
);
8967 clear_vec_high(s
, is_q
, rd
);
8970 tcg_temp_free_ptr(fpst
);
8973 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
8974 int opcode
, bool u
, bool is_q
,
8975 int size
, int rn
, int rd
)
8977 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
8978 * in the source becomes a size element in the destination).
8981 TCGv_i32 tcg_res
[2];
8982 int destelt
= is_q
? 2 : 0;
8983 int passes
= scalar
? 1 : 2;
8986 tcg_res
[1] = tcg_const_i32(0);
8989 for (pass
= 0; pass
< passes
; pass
++) {
8990 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8991 NeonGenNarrowFn
*genfn
= NULL
;
8992 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
8995 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
8997 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8999 tcg_res
[pass
] = tcg_temp_new_i32();
9002 case 0x12: /* XTN, SQXTUN */
9004 static NeonGenNarrowFn
* const xtnfns
[3] = {
9005 gen_helper_neon_narrow_u8
,
9006 gen_helper_neon_narrow_u16
,
9007 tcg_gen_extrl_i64_i32
,
9009 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9010 gen_helper_neon_unarrow_sat8
,
9011 gen_helper_neon_unarrow_sat16
,
9012 gen_helper_neon_unarrow_sat32
,
9015 genenvfn
= sqxtunfns
[size
];
9017 genfn
= xtnfns
[size
];
9021 case 0x14: /* SQXTN, UQXTN */
9023 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9024 { gen_helper_neon_narrow_sat_s8
,
9025 gen_helper_neon_narrow_sat_u8
},
9026 { gen_helper_neon_narrow_sat_s16
,
9027 gen_helper_neon_narrow_sat_u16
},
9028 { gen_helper_neon_narrow_sat_s32
,
9029 gen_helper_neon_narrow_sat_u32
},
9031 genenvfn
= fns
[size
][u
];
9034 case 0x16: /* FCVTN, FCVTN2 */
9035 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9037 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9039 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9040 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9041 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9042 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
9043 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
9044 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9045 tcg_temp_free_i32(tcg_lo
);
9046 tcg_temp_free_i32(tcg_hi
);
9049 case 0x56: /* FCVTXN, FCVTXN2 */
9050 /* 64 bit to 32 bit float conversion
9051 * with von Neumann rounding (round to odd)
9054 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9057 g_assert_not_reached();
9061 genfn(tcg_res
[pass
], tcg_op
);
9062 } else if (genenvfn
) {
9063 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9066 tcg_temp_free_i64(tcg_op
);
9069 for (pass
= 0; pass
< 2; pass
++) {
9070 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9071 tcg_temp_free_i32(tcg_res
[pass
]);
9073 clear_vec_high(s
, is_q
, rd
);
9076 /* Remaining saturating accumulating ops */
9077 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9078 bool is_q
, int size
, int rn
, int rd
)
9080 bool is_double
= (size
== 3);
9083 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9084 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9087 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9088 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9089 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9091 if (is_u
) { /* USQADD */
9092 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9093 } else { /* SUQADD */
9094 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9096 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9098 tcg_temp_free_i64(tcg_rd
);
9099 tcg_temp_free_i64(tcg_rn
);
9100 clear_vec_high(s
, !is_scalar
, rd
);
9102 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9103 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9104 int pass
, maxpasses
;
9109 maxpasses
= is_q
? 4 : 2;
9112 for (pass
= 0; pass
< maxpasses
; pass
++) {
9114 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9115 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9117 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9118 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9121 if (is_u
) { /* USQADD */
9124 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9127 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9130 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9133 g_assert_not_reached();
9135 } else { /* SUQADD */
9138 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9141 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9144 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9147 g_assert_not_reached();
9152 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9153 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9154 tcg_temp_free_i64(tcg_zero
);
9156 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9158 tcg_temp_free_i32(tcg_rd
);
9159 tcg_temp_free_i32(tcg_rn
);
9160 clear_vec_high(s
, is_q
, rd
);
9164 /* AdvSIMD scalar two reg misc
9165 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9166 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9167 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9168 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9170 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9172 int rd
= extract32(insn
, 0, 5);
9173 int rn
= extract32(insn
, 5, 5);
9174 int opcode
= extract32(insn
, 12, 5);
9175 int size
= extract32(insn
, 22, 2);
9176 bool u
= extract32(insn
, 29, 1);
9177 bool is_fcvt
= false;
9180 TCGv_ptr tcg_fpstatus
;
9183 case 0x3: /* USQADD / SUQADD*/
9184 if (!fp_access_check(s
)) {
9187 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9189 case 0x7: /* SQABS / SQNEG */
9191 case 0xa: /* CMLT */
9193 unallocated_encoding(s
);
9197 case 0x8: /* CMGT, CMGE */
9198 case 0x9: /* CMEQ, CMLE */
9199 case 0xb: /* ABS, NEG */
9201 unallocated_encoding(s
);
9205 case 0x12: /* SQXTUN */
9207 unallocated_encoding(s
);
9211 case 0x14: /* SQXTN, UQXTN */
9213 unallocated_encoding(s
);
9216 if (!fp_access_check(s
)) {
9219 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9224 /* Floating point: U, size[1] and opcode indicate operation;
9225 * size[0] indicates single or double precision.
9227 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9228 size
= extract32(size
, 0, 1) ? 3 : 2;
9230 case 0x2c: /* FCMGT (zero) */
9231 case 0x2d: /* FCMEQ (zero) */
9232 case 0x2e: /* FCMLT (zero) */
9233 case 0x6c: /* FCMGE (zero) */
9234 case 0x6d: /* FCMLE (zero) */
9235 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9237 case 0x1d: /* SCVTF */
9238 case 0x5d: /* UCVTF */
9240 bool is_signed
= (opcode
== 0x1d);
9241 if (!fp_access_check(s
)) {
9244 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9247 case 0x3d: /* FRECPE */
9248 case 0x3f: /* FRECPX */
9249 case 0x7d: /* FRSQRTE */
9250 if (!fp_access_check(s
)) {
9253 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9255 case 0x1a: /* FCVTNS */
9256 case 0x1b: /* FCVTMS */
9257 case 0x3a: /* FCVTPS */
9258 case 0x3b: /* FCVTZS */
9259 case 0x5a: /* FCVTNU */
9260 case 0x5b: /* FCVTMU */
9261 case 0x7a: /* FCVTPU */
9262 case 0x7b: /* FCVTZU */
9264 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9266 case 0x1c: /* FCVTAS */
9267 case 0x5c: /* FCVTAU */
9268 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9270 rmode
= FPROUNDING_TIEAWAY
;
9272 case 0x56: /* FCVTXN, FCVTXN2 */
9274 unallocated_encoding(s
);
9277 if (!fp_access_check(s
)) {
9280 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9283 unallocated_encoding(s
);
9288 unallocated_encoding(s
);
9292 if (!fp_access_check(s
)) {
9297 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9298 tcg_fpstatus
= get_fpstatus_ptr(false);
9299 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9302 tcg_fpstatus
= NULL
;
9306 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9307 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9309 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9310 write_fp_dreg(s
, rd
, tcg_rd
);
9311 tcg_temp_free_i64(tcg_rd
);
9312 tcg_temp_free_i64(tcg_rn
);
9314 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9315 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9317 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9320 case 0x7: /* SQABS, SQNEG */
9322 NeonGenOneOpEnvFn
*genfn
;
9323 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9324 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9325 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9326 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9328 genfn
= fns
[size
][u
];
9329 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9332 case 0x1a: /* FCVTNS */
9333 case 0x1b: /* FCVTMS */
9334 case 0x1c: /* FCVTAS */
9335 case 0x3a: /* FCVTPS */
9336 case 0x3b: /* FCVTZS */
9338 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9339 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9340 tcg_temp_free_i32(tcg_shift
);
9343 case 0x5a: /* FCVTNU */
9344 case 0x5b: /* FCVTMU */
9345 case 0x5c: /* FCVTAU */
9346 case 0x7a: /* FCVTPU */
9347 case 0x7b: /* FCVTZU */
9349 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9350 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9351 tcg_temp_free_i32(tcg_shift
);
9355 g_assert_not_reached();
9358 write_fp_sreg(s
, rd
, tcg_rd
);
9359 tcg_temp_free_i32(tcg_rd
);
9360 tcg_temp_free_i32(tcg_rn
);
9364 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9365 tcg_temp_free_i32(tcg_rmode
);
9366 tcg_temp_free_ptr(tcg_fpstatus
);
9370 static void gen_ssra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9372 tcg_gen_vec_sar8i_i64(a
, a
, shift
);
9373 tcg_gen_vec_add8_i64(d
, d
, a
);
9376 static void gen_ssra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9378 tcg_gen_vec_sar16i_i64(a
, a
, shift
);
9379 tcg_gen_vec_add16_i64(d
, d
, a
);
9382 static void gen_ssra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9384 tcg_gen_sari_i32(a
, a
, shift
);
9385 tcg_gen_add_i32(d
, d
, a
);
9388 static void gen_ssra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9390 tcg_gen_sari_i64(a
, a
, shift
);
9391 tcg_gen_add_i64(d
, d
, a
);
9394 static void gen_ssra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9396 tcg_gen_sari_vec(vece
, a
, a
, sh
);
9397 tcg_gen_add_vec(vece
, d
, d
, a
);
9400 static void gen_usra8_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9402 tcg_gen_vec_shr8i_i64(a
, a
, shift
);
9403 tcg_gen_vec_add8_i64(d
, d
, a
);
9406 static void gen_usra16_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9408 tcg_gen_vec_shr16i_i64(a
, a
, shift
);
9409 tcg_gen_vec_add16_i64(d
, d
, a
);
9412 static void gen_usra32_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9414 tcg_gen_shri_i32(a
, a
, shift
);
9415 tcg_gen_add_i32(d
, d
, a
);
9418 static void gen_usra64_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9420 tcg_gen_shri_i64(a
, a
, shift
);
9421 tcg_gen_add_i64(d
, d
, a
);
9424 static void gen_usra_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9426 tcg_gen_shri_vec(vece
, a
, a
, sh
);
9427 tcg_gen_add_vec(vece
, d
, d
, a
);
9430 static void gen_shr8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9432 uint64_t mask
= dup_const(MO_8
, 0xff >> shift
);
9433 TCGv_i64 t
= tcg_temp_new_i64();
9435 tcg_gen_shri_i64(t
, a
, shift
);
9436 tcg_gen_andi_i64(t
, t
, mask
);
9437 tcg_gen_andi_i64(d
, d
, ~mask
);
9438 tcg_gen_or_i64(d
, d
, t
);
9439 tcg_temp_free_i64(t
);
9442 static void gen_shr16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9444 uint64_t mask
= dup_const(MO_16
, 0xffff >> shift
);
9445 TCGv_i64 t
= tcg_temp_new_i64();
9447 tcg_gen_shri_i64(t
, a
, shift
);
9448 tcg_gen_andi_i64(t
, t
, mask
);
9449 tcg_gen_andi_i64(d
, d
, ~mask
);
9450 tcg_gen_or_i64(d
, d
, t
);
9451 tcg_temp_free_i64(t
);
9454 static void gen_shr32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9456 tcg_gen_shri_i32(a
, a
, shift
);
9457 tcg_gen_deposit_i32(d
, d
, a
, 0, 32 - shift
);
9460 static void gen_shr64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9462 tcg_gen_shri_i64(a
, a
, shift
);
9463 tcg_gen_deposit_i64(d
, d
, a
, 0, 64 - shift
);
9466 static void gen_shr_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9468 uint64_t mask
= (2ull << ((8 << vece
) - 1)) - 1;
9469 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
9470 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
9472 tcg_gen_dupi_vec(vece
, m
, mask
^ (mask
>> sh
));
9473 tcg_gen_shri_vec(vece
, t
, a
, sh
);
9474 tcg_gen_and_vec(vece
, d
, d
, m
);
9475 tcg_gen_or_vec(vece
, d
, d
, t
);
9477 tcg_temp_free_vec(t
);
9478 tcg_temp_free_vec(m
);
9481 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9482 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9483 int immh
, int immb
, int opcode
, int rn
, int rd
)
9485 static const GVecGen2i ssra_op
[4] = {
9486 { .fni8
= gen_ssra8_i64
,
9487 .fniv
= gen_ssra_vec
,
9489 .opc
= INDEX_op_sari_vec
,
9491 { .fni8
= gen_ssra16_i64
,
9492 .fniv
= gen_ssra_vec
,
9494 .opc
= INDEX_op_sari_vec
,
9496 { .fni4
= gen_ssra32_i32
,
9497 .fniv
= gen_ssra_vec
,
9499 .opc
= INDEX_op_sari_vec
,
9501 { .fni8
= gen_ssra64_i64
,
9502 .fniv
= gen_ssra_vec
,
9503 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9505 .opc
= INDEX_op_sari_vec
,
9508 static const GVecGen2i usra_op
[4] = {
9509 { .fni8
= gen_usra8_i64
,
9510 .fniv
= gen_usra_vec
,
9512 .opc
= INDEX_op_shri_vec
,
9514 { .fni8
= gen_usra16_i64
,
9515 .fniv
= gen_usra_vec
,
9517 .opc
= INDEX_op_shri_vec
,
9519 { .fni4
= gen_usra32_i32
,
9520 .fniv
= gen_usra_vec
,
9522 .opc
= INDEX_op_shri_vec
,
9524 { .fni8
= gen_usra64_i64
,
9525 .fniv
= gen_usra_vec
,
9526 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9528 .opc
= INDEX_op_shri_vec
,
9531 static const GVecGen2i sri_op
[4] = {
9532 { .fni8
= gen_shr8_ins_i64
,
9533 .fniv
= gen_shr_ins_vec
,
9535 .opc
= INDEX_op_shri_vec
,
9537 { .fni8
= gen_shr16_ins_i64
,
9538 .fniv
= gen_shr_ins_vec
,
9540 .opc
= INDEX_op_shri_vec
,
9542 { .fni4
= gen_shr32_ins_i32
,
9543 .fniv
= gen_shr_ins_vec
,
9545 .opc
= INDEX_op_shri_vec
,
9547 { .fni8
= gen_shr64_ins_i64
,
9548 .fniv
= gen_shr_ins_vec
,
9549 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9551 .opc
= INDEX_op_shri_vec
,
9555 int size
= 32 - clz32(immh
) - 1;
9556 int immhb
= immh
<< 3 | immb
;
9557 int shift
= 2 * (8 << size
) - immhb
;
9558 bool accumulate
= false;
9559 int dsize
= is_q
? 128 : 64;
9560 int esize
= 8 << size
;
9561 int elements
= dsize
/esize
;
9562 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9563 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9564 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9566 uint64_t round_const
;
9569 if (extract32(immh
, 3, 1) && !is_q
) {
9570 unallocated_encoding(s
);
9573 tcg_debug_assert(size
<= 3);
9575 if (!fp_access_check(s
)) {
9580 case 0x02: /* SSRA / USRA (accumulate) */
9582 /* Shift count same as element size produces zero to add. */
9583 if (shift
== 8 << size
) {
9586 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
9588 /* Shift count same as element size produces all sign to add. */
9589 if (shift
== 8 << size
) {
9592 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
9595 case 0x08: /* SRI */
9596 /* Shift count same as element size is valid but does nothing. */
9597 if (shift
== 8 << size
) {
9600 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
9603 case 0x00: /* SSHR / USHR */
9605 if (shift
== 8 << size
) {
9606 /* Shift count the same size as element size produces zero. */
9607 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
9608 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
9610 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
9613 /* Shift count the same size as element size produces all sign. */
9614 if (shift
== 8 << size
) {
9617 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
9621 case 0x04: /* SRSHR / URSHR (rounding) */
9623 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9627 g_assert_not_reached();
9630 round_const
= 1ULL << (shift
- 1);
9631 tcg_round
= tcg_const_i64(round_const
);
9633 for (i
= 0; i
< elements
; i
++) {
9634 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
9636 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
9639 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9640 accumulate
, is_u
, size
, shift
);
9642 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
9644 tcg_temp_free_i64(tcg_round
);
9647 clear_vec_high(s
, is_q
, rd
);
9650 static void gen_shl8_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9652 uint64_t mask
= dup_const(MO_8
, 0xff << shift
);
9653 TCGv_i64 t
= tcg_temp_new_i64();
9655 tcg_gen_shli_i64(t
, a
, shift
);
9656 tcg_gen_andi_i64(t
, t
, mask
);
9657 tcg_gen_andi_i64(d
, d
, ~mask
);
9658 tcg_gen_or_i64(d
, d
, t
);
9659 tcg_temp_free_i64(t
);
9662 static void gen_shl16_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9664 uint64_t mask
= dup_const(MO_16
, 0xffff << shift
);
9665 TCGv_i64 t
= tcg_temp_new_i64();
9667 tcg_gen_shli_i64(t
, a
, shift
);
9668 tcg_gen_andi_i64(t
, t
, mask
);
9669 tcg_gen_andi_i64(d
, d
, ~mask
);
9670 tcg_gen_or_i64(d
, d
, t
);
9671 tcg_temp_free_i64(t
);
9674 static void gen_shl32_ins_i32(TCGv_i32 d
, TCGv_i32 a
, int32_t shift
)
9676 tcg_gen_deposit_i32(d
, d
, a
, shift
, 32 - shift
);
9679 static void gen_shl64_ins_i64(TCGv_i64 d
, TCGv_i64 a
, int64_t shift
)
9681 tcg_gen_deposit_i64(d
, d
, a
, shift
, 64 - shift
);
9684 static void gen_shl_ins_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, int64_t sh
)
9686 uint64_t mask
= (1ull << sh
) - 1;
9687 TCGv_vec t
= tcg_temp_new_vec_matching(d
);
9688 TCGv_vec m
= tcg_temp_new_vec_matching(d
);
9690 tcg_gen_dupi_vec(vece
, m
, mask
);
9691 tcg_gen_shli_vec(vece
, t
, a
, sh
);
9692 tcg_gen_and_vec(vece
, d
, d
, m
);
9693 tcg_gen_or_vec(vece
, d
, d
, t
);
9695 tcg_temp_free_vec(t
);
9696 tcg_temp_free_vec(m
);
9699 /* SHL/SLI - Vector shift left */
9700 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
9701 int immh
, int immb
, int opcode
, int rn
, int rd
)
9703 static const GVecGen2i shi_op
[4] = {
9704 { .fni8
= gen_shl8_ins_i64
,
9705 .fniv
= gen_shl_ins_vec
,
9706 .opc
= INDEX_op_shli_vec
,
9707 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9710 { .fni8
= gen_shl16_ins_i64
,
9711 .fniv
= gen_shl_ins_vec
,
9712 .opc
= INDEX_op_shli_vec
,
9713 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9716 { .fni4
= gen_shl32_ins_i32
,
9717 .fniv
= gen_shl_ins_vec
,
9718 .opc
= INDEX_op_shli_vec
,
9719 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9722 { .fni8
= gen_shl64_ins_i64
,
9723 .fniv
= gen_shl_ins_vec
,
9724 .opc
= INDEX_op_shli_vec
,
9725 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
9729 int size
= 32 - clz32(immh
) - 1;
9730 int immhb
= immh
<< 3 | immb
;
9731 int shift
= immhb
- (8 << size
);
9733 if (extract32(immh
, 3, 1) && !is_q
) {
9734 unallocated_encoding(s
);
9738 if (size
> 3 && !is_q
) {
9739 unallocated_encoding(s
);
9743 if (!fp_access_check(s
)) {
9748 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &shi_op
[size
]);
9750 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
9754 /* USHLL/SHLL - Vector shift left with widening */
9755 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
9756 int immh
, int immb
, int opcode
, int rn
, int rd
)
9758 int size
= 32 - clz32(immh
) - 1;
9759 int immhb
= immh
<< 3 | immb
;
9760 int shift
= immhb
- (8 << size
);
9762 int esize
= 8 << size
;
9763 int elements
= dsize
/esize
;
9764 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9765 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9769 unallocated_encoding(s
);
9773 if (!fp_access_check(s
)) {
9777 /* For the LL variants the store is larger than the load,
9778 * so if rd == rn we would overwrite parts of our input.
9779 * So load everything right now and use shifts in the main loop.
9781 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
9783 for (i
= 0; i
< elements
; i
++) {
9784 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
9785 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
9786 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
9787 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
9791 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
9792 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
9793 int immh
, int immb
, int opcode
, int rn
, int rd
)
9795 int immhb
= immh
<< 3 | immb
;
9796 int size
= 32 - clz32(immh
) - 1;
9798 int esize
= 8 << size
;
9799 int elements
= dsize
/esize
;
9800 int shift
= (2 * esize
) - immhb
;
9801 bool round
= extract32(opcode
, 0, 1);
9802 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
9806 if (extract32(immh
, 3, 1)) {
9807 unallocated_encoding(s
);
9811 if (!fp_access_check(s
)) {
9815 tcg_rn
= tcg_temp_new_i64();
9816 tcg_rd
= tcg_temp_new_i64();
9817 tcg_final
= tcg_temp_new_i64();
9818 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
9821 uint64_t round_const
= 1ULL << (shift
- 1);
9822 tcg_round
= tcg_const_i64(round_const
);
9827 for (i
= 0; i
< elements
; i
++) {
9828 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
9829 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9830 false, true, size
+1, shift
);
9832 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
9836 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
9838 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
9841 tcg_temp_free_i64(tcg_round
);
9843 tcg_temp_free_i64(tcg_rn
);
9844 tcg_temp_free_i64(tcg_rd
);
9845 tcg_temp_free_i64(tcg_final
);
9847 clear_vec_high(s
, is_q
, rd
);
9851 /* AdvSIMD shift by immediate
9852 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9853 * +---+---+---+-------------+------+------+--------+---+------+------+
9854 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9855 * +---+---+---+-------------+------+------+--------+---+------+------+
9857 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
9859 int rd
= extract32(insn
, 0, 5);
9860 int rn
= extract32(insn
, 5, 5);
9861 int opcode
= extract32(insn
, 11, 5);
9862 int immb
= extract32(insn
, 16, 3);
9863 int immh
= extract32(insn
, 19, 4);
9864 bool is_u
= extract32(insn
, 29, 1);
9865 bool is_q
= extract32(insn
, 30, 1);
9868 case 0x08: /* SRI */
9870 unallocated_encoding(s
);
9874 case 0x00: /* SSHR / USHR */
9875 case 0x02: /* SSRA / USRA (accumulate) */
9876 case 0x04: /* SRSHR / URSHR (rounding) */
9877 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9878 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9880 case 0x0a: /* SHL / SLI */
9881 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9883 case 0x10: /* SHRN */
9884 case 0x11: /* RSHRN / SQRSHRUN */
9886 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
9889 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
9892 case 0x12: /* SQSHRN / UQSHRN */
9893 case 0x13: /* SQRSHRN / UQRSHRN */
9894 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
9897 case 0x14: /* SSHLL / USHLL */
9898 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9900 case 0x1c: /* SCVTF / UCVTF */
9901 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
9904 case 0xc: /* SQSHLU */
9906 unallocated_encoding(s
);
9909 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
9911 case 0xe: /* SQSHL, UQSHL */
9912 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
9914 case 0x1f: /* FCVTZS/ FCVTZU */
9915 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
9918 unallocated_encoding(s
);
9923 /* Generate code to do a "long" addition or subtraction, ie one done in
9924 * TCGv_i64 on vector lanes twice the width specified by size.
9926 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
9927 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
9929 static NeonGenTwo64OpFn
* const fns
[3][2] = {
9930 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
9931 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
9932 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
9934 NeonGenTwo64OpFn
*genfn
;
9937 genfn
= fns
[size
][is_sub
];
9938 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9941 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
9942 int opcode
, int rd
, int rn
, int rm
)
9944 /* 3-reg-different widening insns: 64 x 64 -> 128 */
9945 TCGv_i64 tcg_res
[2];
9948 tcg_res
[0] = tcg_temp_new_i64();
9949 tcg_res
[1] = tcg_temp_new_i64();
9951 /* Does this op do an adding accumulate, a subtracting accumulate,
9952 * or no accumulate at all?
9970 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
9971 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
9974 /* size == 2 means two 32x32->64 operations; this is worth special
9975 * casing because we can generally handle it inline.
9978 for (pass
= 0; pass
< 2; pass
++) {
9979 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9980 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9981 TCGv_i64 tcg_passres
;
9982 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
9984 int elt
= pass
+ is_q
* 2;
9986 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
9987 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
9990 tcg_passres
= tcg_res
[pass
];
9992 tcg_passres
= tcg_temp_new_i64();
9996 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9997 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
9999 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10000 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10002 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10003 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10005 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10006 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10008 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10009 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10010 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10012 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10013 tcg_temp_free_i64(tcg_tmp1
);
10014 tcg_temp_free_i64(tcg_tmp2
);
10017 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10018 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10019 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10020 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10022 case 9: /* SQDMLAL, SQDMLAL2 */
10023 case 11: /* SQDMLSL, SQDMLSL2 */
10024 case 13: /* SQDMULL, SQDMULL2 */
10025 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10026 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10027 tcg_passres
, tcg_passres
);
10030 g_assert_not_reached();
10033 if (opcode
== 9 || opcode
== 11) {
10034 /* saturating accumulate ops */
10036 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10038 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10039 tcg_res
[pass
], tcg_passres
);
10040 } else if (accop
> 0) {
10041 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10042 } else if (accop
< 0) {
10043 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10047 tcg_temp_free_i64(tcg_passres
);
10050 tcg_temp_free_i64(tcg_op1
);
10051 tcg_temp_free_i64(tcg_op2
);
10054 /* size 0 or 1, generally helper functions */
10055 for (pass
= 0; pass
< 2; pass
++) {
10056 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10057 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10058 TCGv_i64 tcg_passres
;
10059 int elt
= pass
+ is_q
* 2;
10061 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10062 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10065 tcg_passres
= tcg_res
[pass
];
10067 tcg_passres
= tcg_temp_new_i64();
10071 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10072 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10074 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10075 static NeonGenWidenFn
* const widenfns
[2][2] = {
10076 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10077 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10079 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10081 widenfn(tcg_op2_64
, tcg_op2
);
10082 widenfn(tcg_passres
, tcg_op1
);
10083 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10084 tcg_passres
, tcg_op2_64
);
10085 tcg_temp_free_i64(tcg_op2_64
);
10088 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10089 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10092 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10094 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10098 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10100 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10104 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10105 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10106 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10109 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10111 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10115 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10117 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10121 case 9: /* SQDMLAL, SQDMLAL2 */
10122 case 11: /* SQDMLSL, SQDMLSL2 */
10123 case 13: /* SQDMULL, SQDMULL2 */
10125 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10126 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10127 tcg_passres
, tcg_passres
);
10129 case 14: /* PMULL */
10131 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10134 g_assert_not_reached();
10136 tcg_temp_free_i32(tcg_op1
);
10137 tcg_temp_free_i32(tcg_op2
);
10140 if (opcode
== 9 || opcode
== 11) {
10141 /* saturating accumulate ops */
10143 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10145 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10149 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10150 tcg_res
[pass
], tcg_passres
);
10152 tcg_temp_free_i64(tcg_passres
);
10157 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10158 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10159 tcg_temp_free_i64(tcg_res
[0]);
10160 tcg_temp_free_i64(tcg_res
[1]);
10163 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10164 int opcode
, int rd
, int rn
, int rm
)
10166 TCGv_i64 tcg_res
[2];
10167 int part
= is_q
? 2 : 0;
10170 for (pass
= 0; pass
< 2; pass
++) {
10171 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10172 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10173 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10174 static NeonGenWidenFn
* const widenfns
[3][2] = {
10175 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10176 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10177 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10179 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10181 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10182 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10183 widenfn(tcg_op2_wide
, tcg_op2
);
10184 tcg_temp_free_i32(tcg_op2
);
10185 tcg_res
[pass
] = tcg_temp_new_i64();
10186 gen_neon_addl(size
, (opcode
== 3),
10187 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10188 tcg_temp_free_i64(tcg_op1
);
10189 tcg_temp_free_i64(tcg_op2_wide
);
10192 for (pass
= 0; pass
< 2; pass
++) {
10193 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10194 tcg_temp_free_i64(tcg_res
[pass
]);
10198 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10200 tcg_gen_addi_i64(in
, in
, 1U << 31);
10201 tcg_gen_extrh_i64_i32(res
, in
);
10204 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10205 int opcode
, int rd
, int rn
, int rm
)
10207 TCGv_i32 tcg_res
[2];
10208 int part
= is_q
? 2 : 0;
10211 for (pass
= 0; pass
< 2; pass
++) {
10212 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10213 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10214 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10215 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10216 { gen_helper_neon_narrow_high_u8
,
10217 gen_helper_neon_narrow_round_high_u8
},
10218 { gen_helper_neon_narrow_high_u16
,
10219 gen_helper_neon_narrow_round_high_u16
},
10220 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10222 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10224 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10225 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10227 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10229 tcg_temp_free_i64(tcg_op1
);
10230 tcg_temp_free_i64(tcg_op2
);
10232 tcg_res
[pass
] = tcg_temp_new_i32();
10233 gennarrow(tcg_res
[pass
], tcg_wideres
);
10234 tcg_temp_free_i64(tcg_wideres
);
10237 for (pass
= 0; pass
< 2; pass
++) {
10238 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10239 tcg_temp_free_i32(tcg_res
[pass
]);
10241 clear_vec_high(s
, is_q
, rd
);
10244 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10246 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10247 * is the only three-reg-diff instruction which produces a
10248 * 128-bit wide result from a single operation. However since
10249 * it's possible to calculate the two halves more or less
10250 * separately we just use two helper calls.
10252 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10253 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10254 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10256 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10257 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10258 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10259 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10260 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10261 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10263 tcg_temp_free_i64(tcg_op1
);
10264 tcg_temp_free_i64(tcg_op2
);
10265 tcg_temp_free_i64(tcg_res
);
10268 /* AdvSIMD three different
10269 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10270 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10271 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10272 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10274 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10276 /* Instructions in this group fall into three basic classes
10277 * (in each case with the operation working on each element in
10278 * the input vectors):
10279 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10281 * (2) wide 64 x 128 -> 128
10282 * (3) narrowing 128 x 128 -> 64
10283 * Here we do initial decode, catch unallocated cases and
10284 * dispatch to separate functions for each class.
10286 int is_q
= extract32(insn
, 30, 1);
10287 int is_u
= extract32(insn
, 29, 1);
10288 int size
= extract32(insn
, 22, 2);
10289 int opcode
= extract32(insn
, 12, 4);
10290 int rm
= extract32(insn
, 16, 5);
10291 int rn
= extract32(insn
, 5, 5);
10292 int rd
= extract32(insn
, 0, 5);
10295 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10296 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10297 /* 64 x 128 -> 128 */
10299 unallocated_encoding(s
);
10302 if (!fp_access_check(s
)) {
10305 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10307 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10308 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10309 /* 128 x 128 -> 64 */
10311 unallocated_encoding(s
);
10314 if (!fp_access_check(s
)) {
10317 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10319 case 14: /* PMULL, PMULL2 */
10320 if (is_u
|| size
== 1 || size
== 2) {
10321 unallocated_encoding(s
);
10325 if (!arm_dc_feature(s
, ARM_FEATURE_V8_PMULL
)) {
10326 unallocated_encoding(s
);
10329 if (!fp_access_check(s
)) {
10332 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10336 case 9: /* SQDMLAL, SQDMLAL2 */
10337 case 11: /* SQDMLSL, SQDMLSL2 */
10338 case 13: /* SQDMULL, SQDMULL2 */
10339 if (is_u
|| size
== 0) {
10340 unallocated_encoding(s
);
10344 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10345 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10346 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10347 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10348 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10349 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10350 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10351 /* 64 x 64 -> 128 */
10353 unallocated_encoding(s
);
10357 if (!fp_access_check(s
)) {
10361 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10364 /* opcode 15 not allocated */
10365 unallocated_encoding(s
);
10370 static void gen_bsl_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
10372 tcg_gen_xor_i64(rn
, rn
, rm
);
10373 tcg_gen_and_i64(rn
, rn
, rd
);
10374 tcg_gen_xor_i64(rd
, rm
, rn
);
10377 static void gen_bit_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
10379 tcg_gen_xor_i64(rn
, rn
, rd
);
10380 tcg_gen_and_i64(rn
, rn
, rm
);
10381 tcg_gen_xor_i64(rd
, rd
, rn
);
10384 static void gen_bif_i64(TCGv_i64 rd
, TCGv_i64 rn
, TCGv_i64 rm
)
10386 tcg_gen_xor_i64(rn
, rn
, rd
);
10387 tcg_gen_andc_i64(rn
, rn
, rm
);
10388 tcg_gen_xor_i64(rd
, rd
, rn
);
10391 static void gen_bsl_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
10393 tcg_gen_xor_vec(vece
, rn
, rn
, rm
);
10394 tcg_gen_and_vec(vece
, rn
, rn
, rd
);
10395 tcg_gen_xor_vec(vece
, rd
, rm
, rn
);
10398 static void gen_bit_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
10400 tcg_gen_xor_vec(vece
, rn
, rn
, rd
);
10401 tcg_gen_and_vec(vece
, rn
, rn
, rm
);
10402 tcg_gen_xor_vec(vece
, rd
, rd
, rn
);
10405 static void gen_bif_vec(unsigned vece
, TCGv_vec rd
, TCGv_vec rn
, TCGv_vec rm
)
10407 tcg_gen_xor_vec(vece
, rn
, rn
, rd
);
10408 tcg_gen_andc_vec(vece
, rn
, rn
, rm
);
10409 tcg_gen_xor_vec(vece
, rd
, rd
, rn
);
10412 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10413 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10415 static const GVecGen3 bsl_op
= {
10416 .fni8
= gen_bsl_i64
,
10417 .fniv
= gen_bsl_vec
,
10418 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10421 static const GVecGen3 bit_op
= {
10422 .fni8
= gen_bit_i64
,
10423 .fniv
= gen_bit_vec
,
10424 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10427 static const GVecGen3 bif_op
= {
10428 .fni8
= gen_bif_i64
,
10429 .fniv
= gen_bif_vec
,
10430 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10434 int rd
= extract32(insn
, 0, 5);
10435 int rn
= extract32(insn
, 5, 5);
10436 int rm
= extract32(insn
, 16, 5);
10437 int size
= extract32(insn
, 22, 2);
10438 bool is_u
= extract32(insn
, 29, 1);
10439 bool is_q
= extract32(insn
, 30, 1);
10441 if (!fp_access_check(s
)) {
10445 switch (size
+ 4 * is_u
) {
10447 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10450 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10453 if (rn
== rm
) { /* MOV */
10454 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_mov
, 0);
10456 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10460 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10463 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10466 case 5: /* BSL bitwise select */
10467 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10469 case 6: /* BIT, bitwise insert if true */
10470 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10472 case 7: /* BIF, bitwise insert if false */
10473 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10477 g_assert_not_reached();
10481 /* Pairwise op subgroup of C3.6.16.
10483 * This is called directly or via the handle_3same_float for float pairwise
10484 * operations where the opcode and size are calculated differently.
10486 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10487 int size
, int rn
, int rm
, int rd
)
10492 /* Floating point operations need fpst */
10493 if (opcode
>= 0x58) {
10494 fpst
= get_fpstatus_ptr(false);
10499 if (!fp_access_check(s
)) {
10503 /* These operations work on the concatenated rm:rn, with each pair of
10504 * adjacent elements being operated on to produce an element in the result.
10507 TCGv_i64 tcg_res
[2];
10509 for (pass
= 0; pass
< 2; pass
++) {
10510 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10511 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10512 int passreg
= (pass
== 0) ? rn
: rm
;
10514 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10515 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10516 tcg_res
[pass
] = tcg_temp_new_i64();
10519 case 0x17: /* ADDP */
10520 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10522 case 0x58: /* FMAXNMP */
10523 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10525 case 0x5a: /* FADDP */
10526 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10528 case 0x5e: /* FMAXP */
10529 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10531 case 0x78: /* FMINNMP */
10532 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10534 case 0x7e: /* FMINP */
10535 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10538 g_assert_not_reached();
10541 tcg_temp_free_i64(tcg_op1
);
10542 tcg_temp_free_i64(tcg_op2
);
10545 for (pass
= 0; pass
< 2; pass
++) {
10546 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10547 tcg_temp_free_i64(tcg_res
[pass
]);
10550 int maxpass
= is_q
? 4 : 2;
10551 TCGv_i32 tcg_res
[4];
10553 for (pass
= 0; pass
< maxpass
; pass
++) {
10554 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10555 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10556 NeonGenTwoOpFn
*genfn
= NULL
;
10557 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10558 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10560 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10561 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10562 tcg_res
[pass
] = tcg_temp_new_i32();
10565 case 0x17: /* ADDP */
10567 static NeonGenTwoOpFn
* const fns
[3] = {
10568 gen_helper_neon_padd_u8
,
10569 gen_helper_neon_padd_u16
,
10575 case 0x14: /* SMAXP, UMAXP */
10577 static NeonGenTwoOpFn
* const fns
[3][2] = {
10578 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10579 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10580 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10582 genfn
= fns
[size
][u
];
10585 case 0x15: /* SMINP, UMINP */
10587 static NeonGenTwoOpFn
* const fns
[3][2] = {
10588 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10589 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10590 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10592 genfn
= fns
[size
][u
];
10595 /* The FP operations are all on single floats (32 bit) */
10596 case 0x58: /* FMAXNMP */
10597 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10599 case 0x5a: /* FADDP */
10600 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10602 case 0x5e: /* FMAXP */
10603 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10605 case 0x78: /* FMINNMP */
10606 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10608 case 0x7e: /* FMINP */
10609 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10612 g_assert_not_reached();
10615 /* FP ops called directly, otherwise call now */
10617 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10620 tcg_temp_free_i32(tcg_op1
);
10621 tcg_temp_free_i32(tcg_op2
);
10624 for (pass
= 0; pass
< maxpass
; pass
++) {
10625 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10626 tcg_temp_free_i32(tcg_res
[pass
]);
10628 clear_vec_high(s
, is_q
, rd
);
10632 tcg_temp_free_ptr(fpst
);
10636 /* Floating point op subgroup of C3.6.16. */
10637 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10639 /* For floating point ops, the U, size[1] and opcode bits
10640 * together indicate the operation. size[0] indicates single
10643 int fpopcode
= extract32(insn
, 11, 5)
10644 | (extract32(insn
, 23, 1) << 5)
10645 | (extract32(insn
, 29, 1) << 6);
10646 int is_q
= extract32(insn
, 30, 1);
10647 int size
= extract32(insn
, 22, 1);
10648 int rm
= extract32(insn
, 16, 5);
10649 int rn
= extract32(insn
, 5, 5);
10650 int rd
= extract32(insn
, 0, 5);
10652 int datasize
= is_q
? 128 : 64;
10653 int esize
= 32 << size
;
10654 int elements
= datasize
/ esize
;
10656 if (size
== 1 && !is_q
) {
10657 unallocated_encoding(s
);
10661 switch (fpopcode
) {
10662 case 0x58: /* FMAXNMP */
10663 case 0x5a: /* FADDP */
10664 case 0x5e: /* FMAXP */
10665 case 0x78: /* FMINNMP */
10666 case 0x7e: /* FMINP */
10667 if (size
&& !is_q
) {
10668 unallocated_encoding(s
);
10671 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10674 case 0x1b: /* FMULX */
10675 case 0x1f: /* FRECPS */
10676 case 0x3f: /* FRSQRTS */
10677 case 0x5d: /* FACGE */
10678 case 0x7d: /* FACGT */
10679 case 0x19: /* FMLA */
10680 case 0x39: /* FMLS */
10681 case 0x18: /* FMAXNM */
10682 case 0x1a: /* FADD */
10683 case 0x1c: /* FCMEQ */
10684 case 0x1e: /* FMAX */
10685 case 0x38: /* FMINNM */
10686 case 0x3a: /* FSUB */
10687 case 0x3e: /* FMIN */
10688 case 0x5b: /* FMUL */
10689 case 0x5c: /* FCMGE */
10690 case 0x5f: /* FDIV */
10691 case 0x7a: /* FABD */
10692 case 0x7c: /* FCMGT */
10693 if (!fp_access_check(s
)) {
10697 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10700 unallocated_encoding(s
);
10705 static void gen_mla8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10707 gen_helper_neon_mul_u8(a
, a
, b
);
10708 gen_helper_neon_add_u8(d
, d
, a
);
10711 static void gen_mla16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10713 gen_helper_neon_mul_u16(a
, a
, b
);
10714 gen_helper_neon_add_u16(d
, d
, a
);
10717 static void gen_mla32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10719 tcg_gen_mul_i32(a
, a
, b
);
10720 tcg_gen_add_i32(d
, d
, a
);
10723 static void gen_mla64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
10725 tcg_gen_mul_i64(a
, a
, b
);
10726 tcg_gen_add_i64(d
, d
, a
);
10729 static void gen_mla_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
10731 tcg_gen_mul_vec(vece
, a
, a
, b
);
10732 tcg_gen_add_vec(vece
, d
, d
, a
);
10735 static void gen_mls8_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10737 gen_helper_neon_mul_u8(a
, a
, b
);
10738 gen_helper_neon_sub_u8(d
, d
, a
);
10741 static void gen_mls16_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10743 gen_helper_neon_mul_u16(a
, a
, b
);
10744 gen_helper_neon_sub_u16(d
, d
, a
);
10747 static void gen_mls32_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
)
10749 tcg_gen_mul_i32(a
, a
, b
);
10750 tcg_gen_sub_i32(d
, d
, a
);
10753 static void gen_mls64_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
)
10755 tcg_gen_mul_i64(a
, a
, b
);
10756 tcg_gen_sub_i64(d
, d
, a
);
10759 static void gen_mls_vec(unsigned vece
, TCGv_vec d
, TCGv_vec a
, TCGv_vec b
)
10761 tcg_gen_mul_vec(vece
, a
, a
, b
);
10762 tcg_gen_sub_vec(vece
, d
, d
, a
);
10765 /* Integer op subgroup of C3.6.16. */
10766 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
10768 static const GVecGen3 cmtst_op
[4] = {
10769 { .fni4
= gen_helper_neon_tst_u8
,
10770 .fniv
= gen_cmtst_vec
,
10772 { .fni4
= gen_helper_neon_tst_u16
,
10773 .fniv
= gen_cmtst_vec
,
10775 { .fni4
= gen_cmtst_i32
,
10776 .fniv
= gen_cmtst_vec
,
10778 { .fni8
= gen_cmtst_i64
,
10779 .fniv
= gen_cmtst_vec
,
10780 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10783 static const GVecGen3 mla_op
[4] = {
10784 { .fni4
= gen_mla8_i32
,
10785 .fniv
= gen_mla_vec
,
10786 .opc
= INDEX_op_mul_vec
,
10789 { .fni4
= gen_mla16_i32
,
10790 .fniv
= gen_mla_vec
,
10791 .opc
= INDEX_op_mul_vec
,
10794 { .fni4
= gen_mla32_i32
,
10795 .fniv
= gen_mla_vec
,
10796 .opc
= INDEX_op_mul_vec
,
10799 { .fni8
= gen_mla64_i64
,
10800 .fniv
= gen_mla_vec
,
10801 .opc
= INDEX_op_mul_vec
,
10802 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10806 static const GVecGen3 mls_op
[4] = {
10807 { .fni4
= gen_mls8_i32
,
10808 .fniv
= gen_mls_vec
,
10809 .opc
= INDEX_op_mul_vec
,
10812 { .fni4
= gen_mls16_i32
,
10813 .fniv
= gen_mls_vec
,
10814 .opc
= INDEX_op_mul_vec
,
10817 { .fni4
= gen_mls32_i32
,
10818 .fniv
= gen_mls_vec
,
10819 .opc
= INDEX_op_mul_vec
,
10822 { .fni8
= gen_mls64_i64
,
10823 .fniv
= gen_mls_vec
,
10824 .opc
= INDEX_op_mul_vec
,
10825 .prefer_i64
= TCG_TARGET_REG_BITS
== 64,
10830 int is_q
= extract32(insn
, 30, 1);
10831 int u
= extract32(insn
, 29, 1);
10832 int size
= extract32(insn
, 22, 2);
10833 int opcode
= extract32(insn
, 11, 5);
10834 int rm
= extract32(insn
, 16, 5);
10835 int rn
= extract32(insn
, 5, 5);
10836 int rd
= extract32(insn
, 0, 5);
10841 case 0x13: /* MUL, PMUL */
10842 if (u
&& size
!= 0) {
10843 unallocated_encoding(s
);
10847 case 0x0: /* SHADD, UHADD */
10848 case 0x2: /* SRHADD, URHADD */
10849 case 0x4: /* SHSUB, UHSUB */
10850 case 0xc: /* SMAX, UMAX */
10851 case 0xd: /* SMIN, UMIN */
10852 case 0xe: /* SABD, UABD */
10853 case 0xf: /* SABA, UABA */
10854 case 0x12: /* MLA, MLS */
10856 unallocated_encoding(s
);
10860 case 0x16: /* SQDMULH, SQRDMULH */
10861 if (size
== 0 || size
== 3) {
10862 unallocated_encoding(s
);
10867 if (size
== 3 && !is_q
) {
10868 unallocated_encoding(s
);
10874 if (!fp_access_check(s
)) {
10879 case 0x10: /* ADD, SUB */
10881 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
10883 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
10886 case 0x13: /* MUL, PMUL */
10887 if (!u
) { /* MUL */
10888 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
10892 case 0x12: /* MLA, MLS */
10894 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
10896 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
10900 if (!u
) { /* CMTST */
10901 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
10905 cond
= TCG_COND_EQ
;
10907 case 0x06: /* CMGT, CMHI */
10908 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
10910 case 0x07: /* CMGE, CMHS */
10911 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
10913 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
10914 vec_full_reg_offset(s
, rn
),
10915 vec_full_reg_offset(s
, rm
),
10916 is_q
? 16 : 8, vec_full_reg_size(s
));
10922 for (pass
= 0; pass
< 2; pass
++) {
10923 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10924 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10925 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10927 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10928 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10930 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
10932 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10934 tcg_temp_free_i64(tcg_res
);
10935 tcg_temp_free_i64(tcg_op1
);
10936 tcg_temp_free_i64(tcg_op2
);
10939 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
10940 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10941 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10942 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10943 NeonGenTwoOpFn
*genfn
= NULL
;
10944 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
10946 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
10947 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
10950 case 0x0: /* SHADD, UHADD */
10952 static NeonGenTwoOpFn
* const fns
[3][2] = {
10953 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
10954 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
10955 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
10957 genfn
= fns
[size
][u
];
10960 case 0x1: /* SQADD, UQADD */
10962 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10963 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
10964 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
10965 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
10967 genenvfn
= fns
[size
][u
];
10970 case 0x2: /* SRHADD, URHADD */
10972 static NeonGenTwoOpFn
* const fns
[3][2] = {
10973 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
10974 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
10975 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
10977 genfn
= fns
[size
][u
];
10980 case 0x4: /* SHSUB, UHSUB */
10982 static NeonGenTwoOpFn
* const fns
[3][2] = {
10983 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
10984 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
10985 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
10987 genfn
= fns
[size
][u
];
10990 case 0x5: /* SQSUB, UQSUB */
10992 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
10993 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
10994 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
10995 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
10997 genenvfn
= fns
[size
][u
];
11000 case 0x8: /* SSHL, USHL */
11002 static NeonGenTwoOpFn
* const fns
[3][2] = {
11003 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11004 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11005 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11007 genfn
= fns
[size
][u
];
11010 case 0x9: /* SQSHL, UQSHL */
11012 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11013 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11014 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11015 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11017 genenvfn
= fns
[size
][u
];
11020 case 0xa: /* SRSHL, URSHL */
11022 static NeonGenTwoOpFn
* const fns
[3][2] = {
11023 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11024 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11025 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11027 genfn
= fns
[size
][u
];
11030 case 0xb: /* SQRSHL, UQRSHL */
11032 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11033 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11034 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11035 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11037 genenvfn
= fns
[size
][u
];
11040 case 0xc: /* SMAX, UMAX */
11042 static NeonGenTwoOpFn
* const fns
[3][2] = {
11043 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
11044 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
11045 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11047 genfn
= fns
[size
][u
];
11051 case 0xd: /* SMIN, UMIN */
11053 static NeonGenTwoOpFn
* const fns
[3][2] = {
11054 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
11055 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
11056 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11058 genfn
= fns
[size
][u
];
11061 case 0xe: /* SABD, UABD */
11062 case 0xf: /* SABA, UABA */
11064 static NeonGenTwoOpFn
* const fns
[3][2] = {
11065 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11066 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11067 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11069 genfn
= fns
[size
][u
];
11072 case 0x13: /* MUL, PMUL */
11073 assert(u
); /* PMUL */
11075 genfn
= gen_helper_neon_mul_p8
;
11077 case 0x16: /* SQDMULH, SQRDMULH */
11079 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11080 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11081 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11083 assert(size
== 1 || size
== 2);
11084 genenvfn
= fns
[size
- 1][u
];
11088 g_assert_not_reached();
11092 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11094 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11097 if (opcode
== 0xf) {
11098 /* SABA, UABA: accumulating ops */
11099 static NeonGenTwoOpFn
* const fns
[3] = {
11100 gen_helper_neon_add_u8
,
11101 gen_helper_neon_add_u16
,
11105 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11106 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11109 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11111 tcg_temp_free_i32(tcg_res
);
11112 tcg_temp_free_i32(tcg_op1
);
11113 tcg_temp_free_i32(tcg_op2
);
11116 clear_vec_high(s
, is_q
, rd
);
11119 /* AdvSIMD three same
11120 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11121 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11122 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11123 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11125 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11127 int opcode
= extract32(insn
, 11, 5);
11130 case 0x3: /* logic ops */
11131 disas_simd_3same_logic(s
, insn
);
11133 case 0x17: /* ADDP */
11134 case 0x14: /* SMAXP, UMAXP */
11135 case 0x15: /* SMINP, UMINP */
11137 /* Pairwise operations */
11138 int is_q
= extract32(insn
, 30, 1);
11139 int u
= extract32(insn
, 29, 1);
11140 int size
= extract32(insn
, 22, 2);
11141 int rm
= extract32(insn
, 16, 5);
11142 int rn
= extract32(insn
, 5, 5);
11143 int rd
= extract32(insn
, 0, 5);
11144 if (opcode
== 0x17) {
11145 if (u
|| (size
== 3 && !is_q
)) {
11146 unallocated_encoding(s
);
11151 unallocated_encoding(s
);
11155 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11158 case 0x18 ... 0x31:
11159 /* floating point ops, sz[1] and U are part of opcode */
11160 disas_simd_3same_float(s
, insn
);
11163 disas_simd_3same_int(s
, insn
);
11169 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11171 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11172 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11173 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11174 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11176 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11177 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11180 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11182 int opcode
, fpopcode
;
11183 int is_q
, u
, a
, rm
, rn
, rd
;
11184 int datasize
, elements
;
11187 bool pairwise
= false;
11189 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
11190 unallocated_encoding(s
);
11194 if (!fp_access_check(s
)) {
11198 /* For these floating point ops, the U, a and opcode bits
11199 * together indicate the operation.
11201 opcode
= extract32(insn
, 11, 3);
11202 u
= extract32(insn
, 29, 1);
11203 a
= extract32(insn
, 23, 1);
11204 is_q
= extract32(insn
, 30, 1);
11205 rm
= extract32(insn
, 16, 5);
11206 rn
= extract32(insn
, 5, 5);
11207 rd
= extract32(insn
, 0, 5);
11209 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11210 datasize
= is_q
? 128 : 64;
11211 elements
= datasize
/ 16;
11213 switch (fpopcode
) {
11214 case 0x10: /* FMAXNMP */
11215 case 0x12: /* FADDP */
11216 case 0x16: /* FMAXP */
11217 case 0x18: /* FMINNMP */
11218 case 0x1e: /* FMINP */
11223 fpst
= get_fpstatus_ptr(true);
11226 int maxpass
= is_q
? 8 : 4;
11227 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11228 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11229 TCGv_i32 tcg_res
[8];
11231 for (pass
= 0; pass
< maxpass
; pass
++) {
11232 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11233 int passelt
= (pass
<< 1) & (maxpass
- 1);
11235 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11236 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11237 tcg_res
[pass
] = tcg_temp_new_i32();
11239 switch (fpopcode
) {
11240 case 0x10: /* FMAXNMP */
11241 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11244 case 0x12: /* FADDP */
11245 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11247 case 0x16: /* FMAXP */
11248 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11250 case 0x18: /* FMINNMP */
11251 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11254 case 0x1e: /* FMINP */
11255 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11258 g_assert_not_reached();
11262 for (pass
= 0; pass
< maxpass
; pass
++) {
11263 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11264 tcg_temp_free_i32(tcg_res
[pass
]);
11267 tcg_temp_free_i32(tcg_op1
);
11268 tcg_temp_free_i32(tcg_op2
);
11271 for (pass
= 0; pass
< elements
; pass
++) {
11272 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11273 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11274 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11276 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11277 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11279 switch (fpopcode
) {
11280 case 0x0: /* FMAXNM */
11281 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11283 case 0x1: /* FMLA */
11284 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11285 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11288 case 0x2: /* FADD */
11289 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11291 case 0x3: /* FMULX */
11292 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11294 case 0x4: /* FCMEQ */
11295 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11297 case 0x6: /* FMAX */
11298 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11300 case 0x7: /* FRECPS */
11301 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11303 case 0x8: /* FMINNM */
11304 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11306 case 0x9: /* FMLS */
11307 /* As usual for ARM, separate negation for fused multiply-add */
11308 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11309 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11310 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11313 case 0xa: /* FSUB */
11314 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11316 case 0xe: /* FMIN */
11317 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11319 case 0xf: /* FRSQRTS */
11320 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11322 case 0x13: /* FMUL */
11323 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11325 case 0x14: /* FCMGE */
11326 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11328 case 0x15: /* FACGE */
11329 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11331 case 0x17: /* FDIV */
11332 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11334 case 0x1a: /* FABD */
11335 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11336 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11338 case 0x1c: /* FCMGT */
11339 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11341 case 0x1d: /* FACGT */
11342 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11345 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11346 __func__
, insn
, fpopcode
, s
->pc
);
11347 g_assert_not_reached();
11350 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11351 tcg_temp_free_i32(tcg_res
);
11352 tcg_temp_free_i32(tcg_op1
);
11353 tcg_temp_free_i32(tcg_op2
);
11357 tcg_temp_free_ptr(fpst
);
11359 clear_vec_high(s
, is_q
, rd
);
11362 /* AdvSIMD three same extra
11363 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11364 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11365 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11366 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11368 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11370 int rd
= extract32(insn
, 0, 5);
11371 int rn
= extract32(insn
, 5, 5);
11372 int opcode
= extract32(insn
, 11, 4);
11373 int rm
= extract32(insn
, 16, 5);
11374 int size
= extract32(insn
, 22, 2);
11375 bool u
= extract32(insn
, 29, 1);
11376 bool is_q
= extract32(insn
, 30, 1);
11379 switch (u
* 16 + opcode
) {
11380 case 0x10: /* SQRDMLAH (vector) */
11381 case 0x11: /* SQRDMLSH (vector) */
11382 if (size
!= 1 && size
!= 2) {
11383 unallocated_encoding(s
);
11386 feature
= ARM_FEATURE_V8_RDM
;
11388 case 0x8: /* FCMLA, #0 */
11389 case 0x9: /* FCMLA, #90 */
11390 case 0xa: /* FCMLA, #180 */
11391 case 0xb: /* FCMLA, #270 */
11392 case 0xc: /* FCADD, #90 */
11393 case 0xe: /* FCADD, #270 */
11395 || (size
== 1 && !arm_dc_feature(s
, ARM_FEATURE_V8_FP16
))
11396 || (size
== 3 && !is_q
)) {
11397 unallocated_encoding(s
);
11400 feature
= ARM_FEATURE_V8_FCMA
;
11403 unallocated_encoding(s
);
11406 if (!arm_dc_feature(s
, feature
)) {
11407 unallocated_encoding(s
);
11410 if (!fp_access_check(s
)) {
11415 case 0x0: /* SQRDMLAH (vector) */
11418 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11421 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11424 g_assert_not_reached();
11428 case 0x1: /* SQRDMLSH (vector) */
11431 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11434 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11437 g_assert_not_reached();
11441 case 0x8: /* FCMLA, #0 */
11442 case 0x9: /* FCMLA, #90 */
11443 case 0xa: /* FCMLA, #180 */
11444 case 0xb: /* FCMLA, #270 */
11445 rot
= extract32(opcode
, 0, 2);
11448 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11449 gen_helper_gvec_fcmlah
);
11452 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11453 gen_helper_gvec_fcmlas
);
11456 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11457 gen_helper_gvec_fcmlad
);
11460 g_assert_not_reached();
11464 case 0xc: /* FCADD, #90 */
11465 case 0xe: /* FCADD, #270 */
11466 rot
= extract32(opcode
, 1, 1);
11469 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11470 gen_helper_gvec_fcaddh
);
11473 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11474 gen_helper_gvec_fcadds
);
11477 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11478 gen_helper_gvec_fcaddd
);
11481 g_assert_not_reached();
11486 g_assert_not_reached();
11490 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11491 int size
, int rn
, int rd
)
11493 /* Handle 2-reg-misc ops which are widening (so each size element
11494 * in the source becomes a 2*size element in the destination.
11495 * The only instruction like this is FCVTL.
11500 /* 32 -> 64 bit fp conversion */
11501 TCGv_i64 tcg_res
[2];
11502 int srcelt
= is_q
? 2 : 0;
11504 for (pass
= 0; pass
< 2; pass
++) {
11505 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11506 tcg_res
[pass
] = tcg_temp_new_i64();
11508 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11509 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11510 tcg_temp_free_i32(tcg_op
);
11512 for (pass
= 0; pass
< 2; pass
++) {
11513 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11514 tcg_temp_free_i64(tcg_res
[pass
]);
11517 /* 16 -> 32 bit fp conversion */
11518 int srcelt
= is_q
? 4 : 0;
11519 TCGv_i32 tcg_res
[4];
11521 for (pass
= 0; pass
< 4; pass
++) {
11522 tcg_res
[pass
] = tcg_temp_new_i32();
11524 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11525 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11528 for (pass
= 0; pass
< 4; pass
++) {
11529 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11530 tcg_temp_free_i32(tcg_res
[pass
]);
11535 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11536 bool is_q
, int size
, int rn
, int rd
)
11538 int op
= (opcode
<< 1) | u
;
11539 int opsz
= op
+ size
;
11540 int grp_size
= 3 - opsz
;
11541 int dsize
= is_q
? 128 : 64;
11545 unallocated_encoding(s
);
11549 if (!fp_access_check(s
)) {
11554 /* Special case bytes, use bswap op on each group of elements */
11555 int groups
= dsize
/ (8 << grp_size
);
11557 for (i
= 0; i
< groups
; i
++) {
11558 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11560 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11561 switch (grp_size
) {
11563 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11566 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11569 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11572 g_assert_not_reached();
11574 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11575 tcg_temp_free_i64(tcg_tmp
);
11577 clear_vec_high(s
, is_q
, rd
);
11579 int revmask
= (1 << grp_size
) - 1;
11580 int esize
= 8 << size
;
11581 int elements
= dsize
/ esize
;
11582 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11583 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11584 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11586 for (i
= 0; i
< elements
; i
++) {
11587 int e_rev
= (i
& 0xf) ^ revmask
;
11588 int off
= e_rev
* esize
;
11589 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11591 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11592 tcg_rn
, off
- 64, esize
);
11594 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11597 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11598 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11600 tcg_temp_free_i64(tcg_rd_hi
);
11601 tcg_temp_free_i64(tcg_rd
);
11602 tcg_temp_free_i64(tcg_rn
);
11606 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11607 bool is_q
, int size
, int rn
, int rd
)
11609 /* Implement the pairwise operations from 2-misc:
11610 * SADDLP, UADDLP, SADALP, UADALP.
11611 * These all add pairs of elements in the input to produce a
11612 * double-width result element in the output (possibly accumulating).
11614 bool accum
= (opcode
== 0x6);
11615 int maxpass
= is_q
? 2 : 1;
11617 TCGv_i64 tcg_res
[2];
11620 /* 32 + 32 -> 64 op */
11621 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11623 for (pass
= 0; pass
< maxpass
; pass
++) {
11624 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11625 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11627 tcg_res
[pass
] = tcg_temp_new_i64();
11629 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11630 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11631 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11633 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11634 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11637 tcg_temp_free_i64(tcg_op1
);
11638 tcg_temp_free_i64(tcg_op2
);
11641 for (pass
= 0; pass
< maxpass
; pass
++) {
11642 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11643 NeonGenOneOpFn
*genfn
;
11644 static NeonGenOneOpFn
* const fns
[2][2] = {
11645 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11646 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11649 genfn
= fns
[size
][u
];
11651 tcg_res
[pass
] = tcg_temp_new_i64();
11653 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11654 genfn(tcg_res
[pass
], tcg_op
);
11657 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11659 gen_helper_neon_addl_u16(tcg_res
[pass
],
11660 tcg_res
[pass
], tcg_op
);
11662 gen_helper_neon_addl_u32(tcg_res
[pass
],
11663 tcg_res
[pass
], tcg_op
);
11666 tcg_temp_free_i64(tcg_op
);
11670 tcg_res
[1] = tcg_const_i64(0);
11672 for (pass
= 0; pass
< 2; pass
++) {
11673 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11674 tcg_temp_free_i64(tcg_res
[pass
]);
11678 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11680 /* Implement SHLL and SHLL2 */
11682 int part
= is_q
? 2 : 0;
11683 TCGv_i64 tcg_res
[2];
11685 for (pass
= 0; pass
< 2; pass
++) {
11686 static NeonGenWidenFn
* const widenfns
[3] = {
11687 gen_helper_neon_widen_u8
,
11688 gen_helper_neon_widen_u16
,
11689 tcg_gen_extu_i32_i64
,
11691 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11692 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11694 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11695 tcg_res
[pass
] = tcg_temp_new_i64();
11696 widenfn(tcg_res
[pass
], tcg_op
);
11697 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11699 tcg_temp_free_i32(tcg_op
);
11702 for (pass
= 0; pass
< 2; pass
++) {
11703 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11704 tcg_temp_free_i64(tcg_res
[pass
]);
11708 /* AdvSIMD two reg misc
11709 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11710 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11711 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11712 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11714 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11716 int size
= extract32(insn
, 22, 2);
11717 int opcode
= extract32(insn
, 12, 5);
11718 bool u
= extract32(insn
, 29, 1);
11719 bool is_q
= extract32(insn
, 30, 1);
11720 int rn
= extract32(insn
, 5, 5);
11721 int rd
= extract32(insn
, 0, 5);
11722 bool need_fpstatus
= false;
11723 bool need_rmode
= false;
11725 TCGv_i32 tcg_rmode
;
11726 TCGv_ptr tcg_fpstatus
;
11729 case 0x0: /* REV64, REV32 */
11730 case 0x1: /* REV16 */
11731 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11733 case 0x5: /* CNT, NOT, RBIT */
11734 if (u
&& size
== 0) {
11737 } else if (u
&& size
== 1) {
11740 } else if (!u
&& size
== 0) {
11744 unallocated_encoding(s
);
11746 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11747 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11749 unallocated_encoding(s
);
11752 if (!fp_access_check(s
)) {
11756 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11758 case 0x4: /* CLS, CLZ */
11760 unallocated_encoding(s
);
11764 case 0x2: /* SADDLP, UADDLP */
11765 case 0x6: /* SADALP, UADALP */
11767 unallocated_encoding(s
);
11770 if (!fp_access_check(s
)) {
11773 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11775 case 0x13: /* SHLL, SHLL2 */
11776 if (u
== 0 || size
== 3) {
11777 unallocated_encoding(s
);
11780 if (!fp_access_check(s
)) {
11783 handle_shll(s
, is_q
, size
, rn
, rd
);
11785 case 0xa: /* CMLT */
11787 unallocated_encoding(s
);
11791 case 0x8: /* CMGT, CMGE */
11792 case 0x9: /* CMEQ, CMLE */
11793 case 0xb: /* ABS, NEG */
11794 if (size
== 3 && !is_q
) {
11795 unallocated_encoding(s
);
11799 case 0x3: /* SUQADD, USQADD */
11800 if (size
== 3 && !is_q
) {
11801 unallocated_encoding(s
);
11804 if (!fp_access_check(s
)) {
11807 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11809 case 0x7: /* SQABS, SQNEG */
11810 if (size
== 3 && !is_q
) {
11811 unallocated_encoding(s
);
11816 case 0x16 ... 0x1d:
11819 /* Floating point: U, size[1] and opcode indicate operation;
11820 * size[0] indicates single or double precision.
11822 int is_double
= extract32(size
, 0, 1);
11823 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
11824 size
= is_double
? 3 : 2;
11826 case 0x2f: /* FABS */
11827 case 0x6f: /* FNEG */
11828 if (size
== 3 && !is_q
) {
11829 unallocated_encoding(s
);
11833 case 0x1d: /* SCVTF */
11834 case 0x5d: /* UCVTF */
11836 bool is_signed
= (opcode
== 0x1d) ? true : false;
11837 int elements
= is_double
? 2 : is_q
? 4 : 2;
11838 if (is_double
&& !is_q
) {
11839 unallocated_encoding(s
);
11842 if (!fp_access_check(s
)) {
11845 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
11848 case 0x2c: /* FCMGT (zero) */
11849 case 0x2d: /* FCMEQ (zero) */
11850 case 0x2e: /* FCMLT (zero) */
11851 case 0x6c: /* FCMGE (zero) */
11852 case 0x6d: /* FCMLE (zero) */
11853 if (size
== 3 && !is_q
) {
11854 unallocated_encoding(s
);
11857 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11859 case 0x7f: /* FSQRT */
11860 if (size
== 3 && !is_q
) {
11861 unallocated_encoding(s
);
11865 case 0x1a: /* FCVTNS */
11866 case 0x1b: /* FCVTMS */
11867 case 0x3a: /* FCVTPS */
11868 case 0x3b: /* FCVTZS */
11869 case 0x5a: /* FCVTNU */
11870 case 0x5b: /* FCVTMU */
11871 case 0x7a: /* FCVTPU */
11872 case 0x7b: /* FCVTZU */
11873 need_fpstatus
= true;
11875 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11876 if (size
== 3 && !is_q
) {
11877 unallocated_encoding(s
);
11881 case 0x5c: /* FCVTAU */
11882 case 0x1c: /* FCVTAS */
11883 need_fpstatus
= true;
11885 rmode
= FPROUNDING_TIEAWAY
;
11886 if (size
== 3 && !is_q
) {
11887 unallocated_encoding(s
);
11891 case 0x3c: /* URECPE */
11893 unallocated_encoding(s
);
11897 case 0x3d: /* FRECPE */
11898 case 0x7d: /* FRSQRTE */
11899 if (size
== 3 && !is_q
) {
11900 unallocated_encoding(s
);
11903 if (!fp_access_check(s
)) {
11906 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11908 case 0x56: /* FCVTXN, FCVTXN2 */
11910 unallocated_encoding(s
);
11914 case 0x16: /* FCVTN, FCVTN2 */
11915 /* handle_2misc_narrow does a 2*size -> size operation, but these
11916 * instructions encode the source size rather than dest size.
11918 if (!fp_access_check(s
)) {
11921 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
11923 case 0x17: /* FCVTL, FCVTL2 */
11924 if (!fp_access_check(s
)) {
11927 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
11929 case 0x18: /* FRINTN */
11930 case 0x19: /* FRINTM */
11931 case 0x38: /* FRINTP */
11932 case 0x39: /* FRINTZ */
11934 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11936 case 0x59: /* FRINTX */
11937 case 0x79: /* FRINTI */
11938 need_fpstatus
= true;
11939 if (size
== 3 && !is_q
) {
11940 unallocated_encoding(s
);
11944 case 0x58: /* FRINTA */
11946 rmode
= FPROUNDING_TIEAWAY
;
11947 need_fpstatus
= true;
11948 if (size
== 3 && !is_q
) {
11949 unallocated_encoding(s
);
11953 case 0x7c: /* URSQRTE */
11955 unallocated_encoding(s
);
11958 need_fpstatus
= true;
11961 unallocated_encoding(s
);
11967 unallocated_encoding(s
);
11971 if (!fp_access_check(s
)) {
11975 if (need_fpstatus
|| need_rmode
) {
11976 tcg_fpstatus
= get_fpstatus_ptr(false);
11978 tcg_fpstatus
= NULL
;
11981 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
11982 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
11989 if (u
&& size
== 0) { /* NOT */
11990 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
11996 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12003 /* All 64-bit element operations can be shared with scalar 2misc */
12006 /* Coverity claims (size == 3 && !is_q) has been eliminated
12007 * from all paths leading to here.
12009 tcg_debug_assert(is_q
);
12010 for (pass
= 0; pass
< 2; pass
++) {
12011 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12012 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12014 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12016 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12017 tcg_rmode
, tcg_fpstatus
);
12019 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12021 tcg_temp_free_i64(tcg_res
);
12022 tcg_temp_free_i64(tcg_op
);
12027 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12028 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12029 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12032 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12035 /* Special cases for 32 bit elements */
12037 case 0xa: /* CMLT */
12038 /* 32 bit integer comparison against zero, result is
12039 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12042 cond
= TCG_COND_LT
;
12044 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12045 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12047 case 0x8: /* CMGT, CMGE */
12048 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12050 case 0x9: /* CMEQ, CMLE */
12051 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12053 case 0x4: /* CLS */
12055 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12057 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12060 case 0x7: /* SQABS, SQNEG */
12062 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12064 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12067 case 0xb: /* ABS, NEG */
12069 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12071 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12072 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12073 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
12074 tcg_zero
, tcg_op
, tcg_res
);
12075 tcg_temp_free_i32(tcg_zero
);
12078 case 0x2f: /* FABS */
12079 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12081 case 0x6f: /* FNEG */
12082 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12084 case 0x7f: /* FSQRT */
12085 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12087 case 0x1a: /* FCVTNS */
12088 case 0x1b: /* FCVTMS */
12089 case 0x1c: /* FCVTAS */
12090 case 0x3a: /* FCVTPS */
12091 case 0x3b: /* FCVTZS */
12093 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12094 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12095 tcg_shift
, tcg_fpstatus
);
12096 tcg_temp_free_i32(tcg_shift
);
12099 case 0x5a: /* FCVTNU */
12100 case 0x5b: /* FCVTMU */
12101 case 0x5c: /* FCVTAU */
12102 case 0x7a: /* FCVTPU */
12103 case 0x7b: /* FCVTZU */
12105 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12106 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12107 tcg_shift
, tcg_fpstatus
);
12108 tcg_temp_free_i32(tcg_shift
);
12111 case 0x18: /* FRINTN */
12112 case 0x19: /* FRINTM */
12113 case 0x38: /* FRINTP */
12114 case 0x39: /* FRINTZ */
12115 case 0x58: /* FRINTA */
12116 case 0x79: /* FRINTI */
12117 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12119 case 0x59: /* FRINTX */
12120 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12122 case 0x7c: /* URSQRTE */
12123 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12126 g_assert_not_reached();
12129 /* Use helpers for 8 and 16 bit elements */
12131 case 0x5: /* CNT, RBIT */
12132 /* For these two insns size is part of the opcode specifier
12133 * (handled earlier); they always operate on byte elements.
12136 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12138 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12141 case 0x7: /* SQABS, SQNEG */
12143 NeonGenOneOpEnvFn
*genfn
;
12144 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12145 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12146 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12148 genfn
= fns
[size
][u
];
12149 genfn(tcg_res
, cpu_env
, tcg_op
);
12152 case 0x8: /* CMGT, CMGE */
12153 case 0x9: /* CMEQ, CMLE */
12154 case 0xa: /* CMLT */
12156 static NeonGenTwoOpFn
* const fns
[3][2] = {
12157 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12158 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12159 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12161 NeonGenTwoOpFn
*genfn
;
12164 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12166 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12167 comp
= (opcode
- 0x8) * 2 + u
;
12168 /* ...but LE, LT are implemented as reverse GE, GT */
12169 reverse
= (comp
> 2);
12173 genfn
= fns
[comp
][size
];
12175 genfn(tcg_res
, tcg_zero
, tcg_op
);
12177 genfn(tcg_res
, tcg_op
, tcg_zero
);
12179 tcg_temp_free_i32(tcg_zero
);
12182 case 0xb: /* ABS, NEG */
12184 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12186 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
12188 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
12190 tcg_temp_free_i32(tcg_zero
);
12193 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
12195 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
12199 case 0x4: /* CLS, CLZ */
12202 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12204 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12208 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12210 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12215 g_assert_not_reached();
12219 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12221 tcg_temp_free_i32(tcg_res
);
12222 tcg_temp_free_i32(tcg_op
);
12225 clear_vec_high(s
, is_q
, rd
);
12228 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12229 tcg_temp_free_i32(tcg_rmode
);
12231 if (need_fpstatus
) {
12232 tcg_temp_free_ptr(tcg_fpstatus
);
12236 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12238 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12239 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12240 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12241 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12242 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12243 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12245 * This actually covers two groups where scalar access is governed by
12246 * bit 28. A bunch of the instructions (float to integral) only exist
12247 * in the vector form and are un-allocated for the scalar decode. Also
12248 * in the scalar decode Q is always 1.
12250 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12252 int fpop
, opcode
, a
, u
;
12256 bool only_in_vector
= false;
12259 TCGv_i32 tcg_rmode
= NULL
;
12260 TCGv_ptr tcg_fpstatus
= NULL
;
12261 bool need_rmode
= false;
12262 bool need_fpst
= true;
12265 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
12266 unallocated_encoding(s
);
12270 rd
= extract32(insn
, 0, 5);
12271 rn
= extract32(insn
, 5, 5);
12273 a
= extract32(insn
, 23, 1);
12274 u
= extract32(insn
, 29, 1);
12275 is_scalar
= extract32(insn
, 28, 1);
12276 is_q
= extract32(insn
, 30, 1);
12278 opcode
= extract32(insn
, 12, 5);
12279 fpop
= deposit32(opcode
, 5, 1, a
);
12280 fpop
= deposit32(fpop
, 6, 1, u
);
12282 rd
= extract32(insn
, 0, 5);
12283 rn
= extract32(insn
, 5, 5);
12286 case 0x1d: /* SCVTF */
12287 case 0x5d: /* UCVTF */
12294 elements
= (is_q
? 8 : 4);
12297 if (!fp_access_check(s
)) {
12300 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12304 case 0x2c: /* FCMGT (zero) */
12305 case 0x2d: /* FCMEQ (zero) */
12306 case 0x2e: /* FCMLT (zero) */
12307 case 0x6c: /* FCMGE (zero) */
12308 case 0x6d: /* FCMLE (zero) */
12309 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12311 case 0x3d: /* FRECPE */
12312 case 0x3f: /* FRECPX */
12314 case 0x18: /* FRINTN */
12316 only_in_vector
= true;
12317 rmode
= FPROUNDING_TIEEVEN
;
12319 case 0x19: /* FRINTM */
12321 only_in_vector
= true;
12322 rmode
= FPROUNDING_NEGINF
;
12324 case 0x38: /* FRINTP */
12326 only_in_vector
= true;
12327 rmode
= FPROUNDING_POSINF
;
12329 case 0x39: /* FRINTZ */
12331 only_in_vector
= true;
12332 rmode
= FPROUNDING_ZERO
;
12334 case 0x58: /* FRINTA */
12336 only_in_vector
= true;
12337 rmode
= FPROUNDING_TIEAWAY
;
12339 case 0x59: /* FRINTX */
12340 case 0x79: /* FRINTI */
12341 only_in_vector
= true;
12342 /* current rounding mode */
12344 case 0x1a: /* FCVTNS */
12346 rmode
= FPROUNDING_TIEEVEN
;
12348 case 0x1b: /* FCVTMS */
12350 rmode
= FPROUNDING_NEGINF
;
12352 case 0x1c: /* FCVTAS */
12354 rmode
= FPROUNDING_TIEAWAY
;
12356 case 0x3a: /* FCVTPS */
12358 rmode
= FPROUNDING_POSINF
;
12360 case 0x3b: /* FCVTZS */
12362 rmode
= FPROUNDING_ZERO
;
12364 case 0x5a: /* FCVTNU */
12366 rmode
= FPROUNDING_TIEEVEN
;
12368 case 0x5b: /* FCVTMU */
12370 rmode
= FPROUNDING_NEGINF
;
12372 case 0x5c: /* FCVTAU */
12374 rmode
= FPROUNDING_TIEAWAY
;
12376 case 0x7a: /* FCVTPU */
12378 rmode
= FPROUNDING_POSINF
;
12380 case 0x7b: /* FCVTZU */
12382 rmode
= FPROUNDING_ZERO
;
12384 case 0x2f: /* FABS */
12385 case 0x6f: /* FNEG */
12388 case 0x7d: /* FRSQRTE */
12389 case 0x7f: /* FSQRT (vector) */
12392 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12393 g_assert_not_reached();
12397 /* Check additional constraints for the scalar encoding */
12400 unallocated_encoding(s
);
12403 /* FRINTxx is only in the vector form */
12404 if (only_in_vector
) {
12405 unallocated_encoding(s
);
12410 if (!fp_access_check(s
)) {
12414 if (need_rmode
|| need_fpst
) {
12415 tcg_fpstatus
= get_fpstatus_ptr(true);
12419 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12420 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12424 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12425 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12428 case 0x1a: /* FCVTNS */
12429 case 0x1b: /* FCVTMS */
12430 case 0x1c: /* FCVTAS */
12431 case 0x3a: /* FCVTPS */
12432 case 0x3b: /* FCVTZS */
12433 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12435 case 0x3d: /* FRECPE */
12436 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12438 case 0x3f: /* FRECPX */
12439 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12441 case 0x5a: /* FCVTNU */
12442 case 0x5b: /* FCVTMU */
12443 case 0x5c: /* FCVTAU */
12444 case 0x7a: /* FCVTPU */
12445 case 0x7b: /* FCVTZU */
12446 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12448 case 0x6f: /* FNEG */
12449 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12451 case 0x7d: /* FRSQRTE */
12452 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12455 g_assert_not_reached();
12458 /* limit any sign extension going on */
12459 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12460 write_fp_sreg(s
, rd
, tcg_res
);
12462 tcg_temp_free_i32(tcg_res
);
12463 tcg_temp_free_i32(tcg_op
);
12465 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12466 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12467 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12469 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12472 case 0x1a: /* FCVTNS */
12473 case 0x1b: /* FCVTMS */
12474 case 0x1c: /* FCVTAS */
12475 case 0x3a: /* FCVTPS */
12476 case 0x3b: /* FCVTZS */
12477 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12479 case 0x3d: /* FRECPE */
12480 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12482 case 0x5a: /* FCVTNU */
12483 case 0x5b: /* FCVTMU */
12484 case 0x5c: /* FCVTAU */
12485 case 0x7a: /* FCVTPU */
12486 case 0x7b: /* FCVTZU */
12487 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12489 case 0x18: /* FRINTN */
12490 case 0x19: /* FRINTM */
12491 case 0x38: /* FRINTP */
12492 case 0x39: /* FRINTZ */
12493 case 0x58: /* FRINTA */
12494 case 0x79: /* FRINTI */
12495 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12497 case 0x59: /* FRINTX */
12498 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12500 case 0x2f: /* FABS */
12501 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12503 case 0x6f: /* FNEG */
12504 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12506 case 0x7d: /* FRSQRTE */
12507 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12509 case 0x7f: /* FSQRT */
12510 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12513 g_assert_not_reached();
12516 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12518 tcg_temp_free_i32(tcg_res
);
12519 tcg_temp_free_i32(tcg_op
);
12522 clear_vec_high(s
, is_q
, rd
);
12526 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12527 tcg_temp_free_i32(tcg_rmode
);
12530 if (tcg_fpstatus
) {
12531 tcg_temp_free_ptr(tcg_fpstatus
);
12535 /* AdvSIMD scalar x indexed element
12536 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12537 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12538 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12539 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12540 * AdvSIMD vector x indexed element
12541 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12542 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12543 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12544 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12546 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12548 /* This encoding has two kinds of instruction:
12549 * normal, where we perform elt x idxelt => elt for each
12550 * element in the vector
12551 * long, where we perform elt x idxelt and generate a result of
12552 * double the width of the input element
12553 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12555 bool is_scalar
= extract32(insn
, 28, 1);
12556 bool is_q
= extract32(insn
, 30, 1);
12557 bool u
= extract32(insn
, 29, 1);
12558 int size
= extract32(insn
, 22, 2);
12559 int l
= extract32(insn
, 21, 1);
12560 int m
= extract32(insn
, 20, 1);
12561 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12562 int rm
= extract32(insn
, 16, 4);
12563 int opcode
= extract32(insn
, 12, 4);
12564 int h
= extract32(insn
, 11, 1);
12565 int rn
= extract32(insn
, 5, 5);
12566 int rd
= extract32(insn
, 0, 5);
12567 bool is_long
= false;
12569 bool is_fp16
= false;
12573 switch (16 * u
+ opcode
) {
12574 case 0x08: /* MUL */
12575 case 0x10: /* MLA */
12576 case 0x14: /* MLS */
12578 unallocated_encoding(s
);
12582 case 0x02: /* SMLAL, SMLAL2 */
12583 case 0x12: /* UMLAL, UMLAL2 */
12584 case 0x06: /* SMLSL, SMLSL2 */
12585 case 0x16: /* UMLSL, UMLSL2 */
12586 case 0x0a: /* SMULL, SMULL2 */
12587 case 0x1a: /* UMULL, UMULL2 */
12589 unallocated_encoding(s
);
12594 case 0x03: /* SQDMLAL, SQDMLAL2 */
12595 case 0x07: /* SQDMLSL, SQDMLSL2 */
12596 case 0x0b: /* SQDMULL, SQDMULL2 */
12599 case 0x0c: /* SQDMULH */
12600 case 0x0d: /* SQRDMULH */
12602 case 0x01: /* FMLA */
12603 case 0x05: /* FMLS */
12604 case 0x09: /* FMUL */
12605 case 0x19: /* FMULX */
12608 case 0x1d: /* SQRDMLAH */
12609 case 0x1f: /* SQRDMLSH */
12610 if (!arm_dc_feature(s
, ARM_FEATURE_V8_RDM
)) {
12611 unallocated_encoding(s
);
12615 case 0x11: /* FCMLA #0 */
12616 case 0x13: /* FCMLA #90 */
12617 case 0x15: /* FCMLA #180 */
12618 case 0x17: /* FCMLA #270 */
12619 if (!arm_dc_feature(s
, ARM_FEATURE_V8_FCMA
)) {
12620 unallocated_encoding(s
);
12626 unallocated_encoding(s
);
12631 case 1: /* normal fp */
12632 /* convert insn encoded size to TCGMemOp size */
12634 case 0: /* half-precision */
12638 case MO_32
: /* single precision */
12639 case MO_64
: /* double precision */
12642 unallocated_encoding(s
);
12647 case 2: /* complex fp */
12648 /* Each indexable element is a complex pair. */
12653 unallocated_encoding(s
);
12661 unallocated_encoding(s
);
12666 default: /* integer */
12670 unallocated_encoding(s
);
12675 if (is_fp16
&& !arm_dc_feature(s
, ARM_FEATURE_V8_FP16
)) {
12676 unallocated_encoding(s
);
12680 /* Given TCGMemOp size, adjust register and indexing. */
12683 index
= h
<< 2 | l
<< 1 | m
;
12686 index
= h
<< 1 | l
;
12691 unallocated_encoding(s
);
12698 g_assert_not_reached();
12701 if (!fp_access_check(s
)) {
12706 fpst
= get_fpstatus_ptr(is_fp16
);
12711 switch (16 * u
+ opcode
) {
12712 case 0x11: /* FCMLA #0 */
12713 case 0x13: /* FCMLA #90 */
12714 case 0x15: /* FCMLA #180 */
12715 case 0x17: /* FCMLA #270 */
12716 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12717 vec_full_reg_offset(s
, rn
),
12718 vec_reg_offset(s
, rm
, index
, size
), fpst
,
12719 is_q
? 16 : 8, vec_full_reg_size(s
),
12720 extract32(insn
, 13, 2), /* rot */
12722 ? gen_helper_gvec_fcmlas_idx
12723 : gen_helper_gvec_fcmlah_idx
);
12724 tcg_temp_free_ptr(fpst
);
12729 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12732 assert(is_fp
&& is_q
&& !is_long
);
12734 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12736 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12737 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12738 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12740 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12742 switch (16 * u
+ opcode
) {
12743 case 0x05: /* FMLS */
12744 /* As usual for ARM, separate negation for fused multiply-add */
12745 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12747 case 0x01: /* FMLA */
12748 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12749 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12751 case 0x09: /* FMUL */
12752 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12754 case 0x19: /* FMULX */
12755 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12758 g_assert_not_reached();
12761 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12762 tcg_temp_free_i64(tcg_op
);
12763 tcg_temp_free_i64(tcg_res
);
12766 tcg_temp_free_i64(tcg_idx
);
12767 clear_vec_high(s
, !is_scalar
, rd
);
12768 } else if (!is_long
) {
12769 /* 32 bit floating point, or 16 or 32 bit integer.
12770 * For the 16 bit scalar case we use the usual Neon helpers and
12771 * rely on the fact that 0 op 0 == 0 with no side effects.
12773 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12774 int pass
, maxpasses
;
12779 maxpasses
= is_q
? 4 : 2;
12782 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12784 if (size
== 1 && !is_scalar
) {
12785 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12786 * the index into both halves of the 32 bit tcg_idx and then use
12787 * the usual Neon helpers.
12789 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12792 for (pass
= 0; pass
< maxpasses
; pass
++) {
12793 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12794 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12796 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
12798 switch (16 * u
+ opcode
) {
12799 case 0x08: /* MUL */
12800 case 0x10: /* MLA */
12801 case 0x14: /* MLS */
12803 static NeonGenTwoOpFn
* const fns
[2][2] = {
12804 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
12805 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
12807 NeonGenTwoOpFn
*genfn
;
12808 bool is_sub
= opcode
== 0x4;
12811 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
12813 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
12815 if (opcode
== 0x8) {
12818 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
12819 genfn
= fns
[size
- 1][is_sub
];
12820 genfn(tcg_res
, tcg_op
, tcg_res
);
12823 case 0x05: /* FMLS */
12824 case 0x01: /* FMLA */
12825 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12826 is_scalar
? size
: MO_32
);
12829 if (opcode
== 0x5) {
12830 /* As usual for ARM, separate negation for fused
12832 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
12835 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
12838 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
12843 if (opcode
== 0x5) {
12844 /* As usual for ARM, separate negation for
12845 * fused multiply-add */
12846 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
12848 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
12852 g_assert_not_reached();
12855 case 0x09: /* FMUL */
12859 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
12862 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
12867 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12870 g_assert_not_reached();
12873 case 0x19: /* FMULX */
12877 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
12880 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
12885 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12888 g_assert_not_reached();
12891 case 0x0c: /* SQDMULH */
12893 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
12896 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
12900 case 0x0d: /* SQRDMULH */
12902 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
12905 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
12909 case 0x1d: /* SQRDMLAH */
12910 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12911 is_scalar
? size
: MO_32
);
12913 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
12914 tcg_op
, tcg_idx
, tcg_res
);
12916 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
12917 tcg_op
, tcg_idx
, tcg_res
);
12920 case 0x1f: /* SQRDMLSH */
12921 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12922 is_scalar
? size
: MO_32
);
12924 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
12925 tcg_op
, tcg_idx
, tcg_res
);
12927 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
12928 tcg_op
, tcg_idx
, tcg_res
);
12932 g_assert_not_reached();
12936 write_fp_sreg(s
, rd
, tcg_res
);
12938 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12941 tcg_temp_free_i32(tcg_op
);
12942 tcg_temp_free_i32(tcg_res
);
12945 tcg_temp_free_i32(tcg_idx
);
12946 clear_vec_high(s
, is_q
, rd
);
12948 /* long ops: 16x16->32 or 32x32->64 */
12949 TCGv_i64 tcg_res
[2];
12951 bool satop
= extract32(opcode
, 0, 1);
12952 TCGMemOp memop
= MO_32
;
12959 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12961 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
12963 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12964 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12965 TCGv_i64 tcg_passres
;
12971 passelt
= pass
+ (is_q
* 2);
12974 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
12976 tcg_res
[pass
] = tcg_temp_new_i64();
12978 if (opcode
== 0xa || opcode
== 0xb) {
12979 /* Non-accumulating ops */
12980 tcg_passres
= tcg_res
[pass
];
12982 tcg_passres
= tcg_temp_new_i64();
12985 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
12986 tcg_temp_free_i64(tcg_op
);
12989 /* saturating, doubling */
12990 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
12991 tcg_passres
, tcg_passres
);
12994 if (opcode
== 0xa || opcode
== 0xb) {
12998 /* Accumulating op: handle accumulate step */
12999 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13002 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13003 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13005 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13006 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13008 case 0x7: /* SQDMLSL, SQDMLSL2 */
13009 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13011 case 0x3: /* SQDMLAL, SQDMLAL2 */
13012 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13017 g_assert_not_reached();
13019 tcg_temp_free_i64(tcg_passres
);
13021 tcg_temp_free_i64(tcg_idx
);
13023 clear_vec_high(s
, !is_scalar
, rd
);
13025 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13028 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13031 /* The simplest way to handle the 16x16 indexed ops is to
13032 * duplicate the index into both halves of the 32 bit tcg_idx
13033 * and then use the usual Neon helpers.
13035 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13038 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13039 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13040 TCGv_i64 tcg_passres
;
13043 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13045 read_vec_element_i32(s
, tcg_op
, rn
,
13046 pass
+ (is_q
* 2), MO_32
);
13049 tcg_res
[pass
] = tcg_temp_new_i64();
13051 if (opcode
== 0xa || opcode
== 0xb) {
13052 /* Non-accumulating ops */
13053 tcg_passres
= tcg_res
[pass
];
13055 tcg_passres
= tcg_temp_new_i64();
13058 if (memop
& MO_SIGN
) {
13059 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13061 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13064 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13065 tcg_passres
, tcg_passres
);
13067 tcg_temp_free_i32(tcg_op
);
13069 if (opcode
== 0xa || opcode
== 0xb) {
13073 /* Accumulating op: handle accumulate step */
13074 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13077 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13078 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13081 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13082 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13085 case 0x7: /* SQDMLSL, SQDMLSL2 */
13086 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13088 case 0x3: /* SQDMLAL, SQDMLAL2 */
13089 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13094 g_assert_not_reached();
13096 tcg_temp_free_i64(tcg_passres
);
13098 tcg_temp_free_i32(tcg_idx
);
13101 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13106 tcg_res
[1] = tcg_const_i64(0);
13109 for (pass
= 0; pass
< 2; pass
++) {
13110 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13111 tcg_temp_free_i64(tcg_res
[pass
]);
13116 tcg_temp_free_ptr(fpst
);
13121 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13122 * +-----------------+------+-----------+--------+-----+------+------+
13123 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13124 * +-----------------+------+-----------+--------+-----+------+------+
13126 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13128 int size
= extract32(insn
, 22, 2);
13129 int opcode
= extract32(insn
, 12, 5);
13130 int rn
= extract32(insn
, 5, 5);
13131 int rd
= extract32(insn
, 0, 5);
13133 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13134 TCGv_i32 tcg_decrypt
;
13135 CryptoThreeOpIntFn
*genfn
;
13137 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)
13139 unallocated_encoding(s
);
13144 case 0x4: /* AESE */
13146 genfn
= gen_helper_crypto_aese
;
13148 case 0x6: /* AESMC */
13150 genfn
= gen_helper_crypto_aesmc
;
13152 case 0x5: /* AESD */
13154 genfn
= gen_helper_crypto_aese
;
13156 case 0x7: /* AESIMC */
13158 genfn
= gen_helper_crypto_aesmc
;
13161 unallocated_encoding(s
);
13165 if (!fp_access_check(s
)) {
13169 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13170 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13171 tcg_decrypt
= tcg_const_i32(decrypt
);
13173 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13175 tcg_temp_free_ptr(tcg_rd_ptr
);
13176 tcg_temp_free_ptr(tcg_rn_ptr
);
13177 tcg_temp_free_i32(tcg_decrypt
);
13180 /* Crypto three-reg SHA
13181 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13182 * +-----------------+------+---+------+---+--------+-----+------+------+
13183 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13184 * +-----------------+------+---+------+---+--------+-----+------+------+
13186 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13188 int size
= extract32(insn
, 22, 2);
13189 int opcode
= extract32(insn
, 12, 3);
13190 int rm
= extract32(insn
, 16, 5);
13191 int rn
= extract32(insn
, 5, 5);
13192 int rd
= extract32(insn
, 0, 5);
13193 CryptoThreeOpFn
*genfn
;
13194 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13195 int feature
= ARM_FEATURE_V8_SHA256
;
13198 unallocated_encoding(s
);
13203 case 0: /* SHA1C */
13204 case 1: /* SHA1P */
13205 case 2: /* SHA1M */
13206 case 3: /* SHA1SU0 */
13208 feature
= ARM_FEATURE_V8_SHA1
;
13210 case 4: /* SHA256H */
13211 genfn
= gen_helper_crypto_sha256h
;
13213 case 5: /* SHA256H2 */
13214 genfn
= gen_helper_crypto_sha256h2
;
13216 case 6: /* SHA256SU1 */
13217 genfn
= gen_helper_crypto_sha256su1
;
13220 unallocated_encoding(s
);
13224 if (!arm_dc_feature(s
, feature
)) {
13225 unallocated_encoding(s
);
13229 if (!fp_access_check(s
)) {
13233 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13234 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13235 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13238 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13240 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13242 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13243 tcg_rm_ptr
, tcg_opcode
);
13244 tcg_temp_free_i32(tcg_opcode
);
13247 tcg_temp_free_ptr(tcg_rd_ptr
);
13248 tcg_temp_free_ptr(tcg_rn_ptr
);
13249 tcg_temp_free_ptr(tcg_rm_ptr
);
13252 /* Crypto two-reg SHA
13253 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13254 * +-----------------+------+-----------+--------+-----+------+------+
13255 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13256 * +-----------------+------+-----------+--------+-----+------+------+
13258 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13260 int size
= extract32(insn
, 22, 2);
13261 int opcode
= extract32(insn
, 12, 5);
13262 int rn
= extract32(insn
, 5, 5);
13263 int rd
= extract32(insn
, 0, 5);
13264 CryptoTwoOpFn
*genfn
;
13266 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13269 unallocated_encoding(s
);
13274 case 0: /* SHA1H */
13275 feature
= ARM_FEATURE_V8_SHA1
;
13276 genfn
= gen_helper_crypto_sha1h
;
13278 case 1: /* SHA1SU1 */
13279 feature
= ARM_FEATURE_V8_SHA1
;
13280 genfn
= gen_helper_crypto_sha1su1
;
13282 case 2: /* SHA256SU0 */
13283 feature
= ARM_FEATURE_V8_SHA256
;
13284 genfn
= gen_helper_crypto_sha256su0
;
13287 unallocated_encoding(s
);
13291 if (!arm_dc_feature(s
, feature
)) {
13292 unallocated_encoding(s
);
13296 if (!fp_access_check(s
)) {
13300 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13301 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13303 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13305 tcg_temp_free_ptr(tcg_rd_ptr
);
13306 tcg_temp_free_ptr(tcg_rn_ptr
);
13309 /* Crypto three-reg SHA512
13310 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13311 * +-----------------------+------+---+---+-----+--------+------+------+
13312 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13313 * +-----------------------+------+---+---+-----+--------+------+------+
13315 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13317 int opcode
= extract32(insn
, 10, 2);
13318 int o
= extract32(insn
, 14, 1);
13319 int rm
= extract32(insn
, 16, 5);
13320 int rn
= extract32(insn
, 5, 5);
13321 int rd
= extract32(insn
, 0, 5);
13323 CryptoThreeOpFn
*genfn
;
13327 case 0: /* SHA512H */
13328 feature
= ARM_FEATURE_V8_SHA512
;
13329 genfn
= gen_helper_crypto_sha512h
;
13331 case 1: /* SHA512H2 */
13332 feature
= ARM_FEATURE_V8_SHA512
;
13333 genfn
= gen_helper_crypto_sha512h2
;
13335 case 2: /* SHA512SU1 */
13336 feature
= ARM_FEATURE_V8_SHA512
;
13337 genfn
= gen_helper_crypto_sha512su1
;
13340 feature
= ARM_FEATURE_V8_SHA3
;
13346 case 0: /* SM3PARTW1 */
13347 feature
= ARM_FEATURE_V8_SM3
;
13348 genfn
= gen_helper_crypto_sm3partw1
;
13350 case 1: /* SM3PARTW2 */
13351 feature
= ARM_FEATURE_V8_SM3
;
13352 genfn
= gen_helper_crypto_sm3partw2
;
13354 case 2: /* SM4EKEY */
13355 feature
= ARM_FEATURE_V8_SM4
;
13356 genfn
= gen_helper_crypto_sm4ekey
;
13359 unallocated_encoding(s
);
13364 if (!arm_dc_feature(s
, feature
)) {
13365 unallocated_encoding(s
);
13369 if (!fp_access_check(s
)) {
13374 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13376 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13377 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13378 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13380 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13382 tcg_temp_free_ptr(tcg_rd_ptr
);
13383 tcg_temp_free_ptr(tcg_rn_ptr
);
13384 tcg_temp_free_ptr(tcg_rm_ptr
);
13386 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13389 tcg_op1
= tcg_temp_new_i64();
13390 tcg_op2
= tcg_temp_new_i64();
13391 tcg_res
[0] = tcg_temp_new_i64();
13392 tcg_res
[1] = tcg_temp_new_i64();
13394 for (pass
= 0; pass
< 2; pass
++) {
13395 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13396 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13398 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13399 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13401 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13402 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13404 tcg_temp_free_i64(tcg_op1
);
13405 tcg_temp_free_i64(tcg_op2
);
13406 tcg_temp_free_i64(tcg_res
[0]);
13407 tcg_temp_free_i64(tcg_res
[1]);
13411 /* Crypto two-reg SHA512
13412 * 31 12 11 10 9 5 4 0
13413 * +-----------------------------------------+--------+------+------+
13414 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13415 * +-----------------------------------------+--------+------+------+
13417 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13419 int opcode
= extract32(insn
, 10, 2);
13420 int rn
= extract32(insn
, 5, 5);
13421 int rd
= extract32(insn
, 0, 5);
13422 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13424 CryptoTwoOpFn
*genfn
;
13427 case 0: /* SHA512SU0 */
13428 feature
= ARM_FEATURE_V8_SHA512
;
13429 genfn
= gen_helper_crypto_sha512su0
;
13432 feature
= ARM_FEATURE_V8_SM4
;
13433 genfn
= gen_helper_crypto_sm4e
;
13436 unallocated_encoding(s
);
13440 if (!arm_dc_feature(s
, feature
)) {
13441 unallocated_encoding(s
);
13445 if (!fp_access_check(s
)) {
13449 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13450 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13452 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13454 tcg_temp_free_ptr(tcg_rd_ptr
);
13455 tcg_temp_free_ptr(tcg_rn_ptr
);
13458 /* Crypto four-register
13459 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13460 * +-------------------+-----+------+---+------+------+------+
13461 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13462 * +-------------------+-----+------+---+------+------+------+
13464 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13466 int op0
= extract32(insn
, 21, 2);
13467 int rm
= extract32(insn
, 16, 5);
13468 int ra
= extract32(insn
, 10, 5);
13469 int rn
= extract32(insn
, 5, 5);
13470 int rd
= extract32(insn
, 0, 5);
13476 feature
= ARM_FEATURE_V8_SHA3
;
13478 case 2: /* SM3SS1 */
13479 feature
= ARM_FEATURE_V8_SM3
;
13482 unallocated_encoding(s
);
13486 if (!arm_dc_feature(s
, feature
)) {
13487 unallocated_encoding(s
);
13491 if (!fp_access_check(s
)) {
13496 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13499 tcg_op1
= tcg_temp_new_i64();
13500 tcg_op2
= tcg_temp_new_i64();
13501 tcg_op3
= tcg_temp_new_i64();
13502 tcg_res
[0] = tcg_temp_new_i64();
13503 tcg_res
[1] = tcg_temp_new_i64();
13505 for (pass
= 0; pass
< 2; pass
++) {
13506 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13507 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13508 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13512 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13515 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13517 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13519 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13520 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13522 tcg_temp_free_i64(tcg_op1
);
13523 tcg_temp_free_i64(tcg_op2
);
13524 tcg_temp_free_i64(tcg_op3
);
13525 tcg_temp_free_i64(tcg_res
[0]);
13526 tcg_temp_free_i64(tcg_res
[1]);
13528 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13530 tcg_op1
= tcg_temp_new_i32();
13531 tcg_op2
= tcg_temp_new_i32();
13532 tcg_op3
= tcg_temp_new_i32();
13533 tcg_res
= tcg_temp_new_i32();
13534 tcg_zero
= tcg_const_i32(0);
13536 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13537 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13538 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13540 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13541 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13542 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13543 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13545 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13546 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13547 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13548 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13550 tcg_temp_free_i32(tcg_op1
);
13551 tcg_temp_free_i32(tcg_op2
);
13552 tcg_temp_free_i32(tcg_op3
);
13553 tcg_temp_free_i32(tcg_res
);
13554 tcg_temp_free_i32(tcg_zero
);
13559 * 31 21 20 16 15 10 9 5 4 0
13560 * +-----------------------+------+--------+------+------+
13561 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13562 * +-----------------------+------+--------+------+------+
13564 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13566 int rm
= extract32(insn
, 16, 5);
13567 int imm6
= extract32(insn
, 10, 6);
13568 int rn
= extract32(insn
, 5, 5);
13569 int rd
= extract32(insn
, 0, 5);
13570 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13573 if (!arm_dc_feature(s
, ARM_FEATURE_V8_SHA3
)) {
13574 unallocated_encoding(s
);
13578 if (!fp_access_check(s
)) {
13582 tcg_op1
= tcg_temp_new_i64();
13583 tcg_op2
= tcg_temp_new_i64();
13584 tcg_res
[0] = tcg_temp_new_i64();
13585 tcg_res
[1] = tcg_temp_new_i64();
13587 for (pass
= 0; pass
< 2; pass
++) {
13588 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13589 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13591 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13592 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13594 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13595 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13597 tcg_temp_free_i64(tcg_op1
);
13598 tcg_temp_free_i64(tcg_op2
);
13599 tcg_temp_free_i64(tcg_res
[0]);
13600 tcg_temp_free_i64(tcg_res
[1]);
13603 /* Crypto three-reg imm2
13604 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13605 * +-----------------------+------+-----+------+--------+------+------+
13606 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13607 * +-----------------------+------+-----+------+--------+------+------+
13609 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13611 int opcode
= extract32(insn
, 10, 2);
13612 int imm2
= extract32(insn
, 12, 2);
13613 int rm
= extract32(insn
, 16, 5);
13614 int rn
= extract32(insn
, 5, 5);
13615 int rd
= extract32(insn
, 0, 5);
13616 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13617 TCGv_i32 tcg_imm2
, tcg_opcode
;
13619 if (!arm_dc_feature(s
, ARM_FEATURE_V8_SM3
)) {
13620 unallocated_encoding(s
);
13624 if (!fp_access_check(s
)) {
13628 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13629 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13630 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13631 tcg_imm2
= tcg_const_i32(imm2
);
13632 tcg_opcode
= tcg_const_i32(opcode
);
13634 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13637 tcg_temp_free_ptr(tcg_rd_ptr
);
13638 tcg_temp_free_ptr(tcg_rn_ptr
);
13639 tcg_temp_free_ptr(tcg_rm_ptr
);
13640 tcg_temp_free_i32(tcg_imm2
);
13641 tcg_temp_free_i32(tcg_opcode
);
13644 /* C3.6 Data processing - SIMD, inc Crypto
13646 * As the decode gets a little complex we are using a table based
13647 * approach for this part of the decode.
13649 static const AArch64DecodeTable data_proc_simd
[] = {
13650 /* pattern , mask , fn */
13651 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13652 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13653 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13654 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13655 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13656 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13657 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13658 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13659 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13660 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13661 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13662 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13663 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13664 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13665 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13666 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13667 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13668 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13669 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13670 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13671 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13672 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13673 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13674 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13675 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13676 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13677 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13678 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13679 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13680 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13681 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13682 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13683 { 0x00000000, 0x00000000, NULL
}
13686 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13688 /* Note that this is called with all non-FP cases from
13689 * table C3-6 so it must UNDEF for entries not specifically
13690 * allocated to instructions in that table.
13692 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13696 unallocated_encoding(s
);
13700 /* C3.6 Data processing - SIMD and floating point */
13701 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13703 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13704 disas_data_proc_fp(s
, insn
);
13706 /* SIMD, including crypto */
13707 disas_data_proc_simd(s
, insn
);
13711 /* C3.1 A64 instruction index by encoding */
13712 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
13716 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
13720 s
->fp_access_checked
= false;
13722 switch (extract32(insn
, 25, 4)) {
13723 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
13724 unallocated_encoding(s
);
13726 case 0x8: case 0x9: /* Data processing - immediate */
13727 disas_data_proc_imm(s
, insn
);
13729 case 0xa: case 0xb: /* Branch, exception generation and system insns */
13730 disas_b_exc_sys(s
, insn
);
13735 case 0xe: /* Loads and stores */
13736 disas_ldst(s
, insn
);
13739 case 0xd: /* Data processing - register */
13740 disas_data_proc_reg(s
, insn
);
13743 case 0xf: /* Data processing - SIMD and floating point */
13744 disas_data_proc_simd_fp(s
, insn
);
13747 assert(FALSE
); /* all 15 cases should be handled above */
13751 /* if we allocated any temporaries, free them here */
13755 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
13758 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13759 CPUARMState
*env
= cpu
->env_ptr
;
13760 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
13763 dc
->pc
= dc
->base
.pc_first
;
13767 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
13768 * there is no secure EL1, so we route exceptions to EL3.
13770 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
13771 !arm_el_is_aa64(env
, 3);
13774 dc
->be_data
= ARM_TBFLAG_BE_DATA(dc
->base
.tb
->flags
) ? MO_BE
: MO_LE
;
13775 dc
->condexec_mask
= 0;
13776 dc
->condexec_cond
= 0;
13777 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, ARM_TBFLAG_MMUIDX(dc
->base
.tb
->flags
));
13778 dc
->tbi0
= ARM_TBFLAG_TBI0(dc
->base
.tb
->flags
);
13779 dc
->tbi1
= ARM_TBFLAG_TBI1(dc
->base
.tb
->flags
);
13780 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
13781 #if !defined(CONFIG_USER_ONLY)
13782 dc
->user
= (dc
->current_el
== 0);
13784 dc
->fp_excp_el
= ARM_TBFLAG_FPEXC_EL(dc
->base
.tb
->flags
);
13785 dc
->sve_excp_el
= ARM_TBFLAG_SVEEXC_EL(dc
->base
.tb
->flags
);
13786 dc
->sve_len
= (ARM_TBFLAG_ZCR_LEN(dc
->base
.tb
->flags
) + 1) * 16;
13788 dc
->vec_stride
= 0;
13789 dc
->cp_regs
= arm_cpu
->cp_regs
;
13790 dc
->features
= env
->features
;
13792 /* Single step state. The code-generation logic here is:
13794 * generate code with no special handling for single-stepping (except
13795 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
13796 * this happens anyway because those changes are all system register or
13798 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
13799 * emit code for one insn
13800 * emit code to clear PSTATE.SS
13801 * emit code to generate software step exception for completed step
13802 * end TB (as usual for having generated an exception)
13803 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
13804 * emit code to generate a software step exception
13807 dc
->ss_active
= ARM_TBFLAG_SS_ACTIVE(dc
->base
.tb
->flags
);
13808 dc
->pstate_ss
= ARM_TBFLAG_PSTATE_SS(dc
->base
.tb
->flags
);
13809 dc
->is_ldex
= false;
13810 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
13812 /* Bound the number of insns to execute to those left on the page. */
13813 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
13815 /* If architectural single step active, limit to 1. */
13816 if (dc
->ss_active
) {
13819 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
13821 init_tmp_a64_array(dc
);
13824 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
13826 tcg_clear_temp_count();
13829 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
13831 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13833 tcg_gen_insn_start(dc
->pc
, 0, 0);
13834 dc
->insn_start
= tcg_last_op();
13837 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
13838 const CPUBreakpoint
*bp
)
13840 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13842 if (bp
->flags
& BP_CPU
) {
13843 gen_a64_set_pc_im(dc
->pc
);
13844 gen_helper_check_breakpoints(cpu_env
);
13845 /* End the TB early; it likely won't be executed */
13846 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
13848 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
13849 /* The address covered by the breakpoint must be
13850 included in [tb->pc, tb->pc + tb->size) in order
13851 to for it to be properly cleared -- thus we
13852 increment the PC here so that the logic setting
13853 tb->size below does the right thing. */
13855 dc
->base
.is_jmp
= DISAS_NORETURN
;
13861 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
13863 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13864 CPUARMState
*env
= cpu
->env_ptr
;
13866 if (dc
->ss_active
&& !dc
->pstate_ss
) {
13867 /* Singlestep state is Active-pending.
13868 * If we're in this state at the start of a TB then either
13869 * a) we just took an exception to an EL which is being debugged
13870 * and this is the first insn in the exception handler
13871 * b) debug exceptions were masked and we just unmasked them
13872 * without changing EL (eg by clearing PSTATE.D)
13873 * In either case we're going to take a swstep exception in the
13874 * "did not step an insn" case, and so the syndrome ISV and EX
13875 * bits should be zero.
13877 assert(dc
->base
.num_insns
== 1);
13878 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
13879 default_exception_el(dc
));
13880 dc
->base
.is_jmp
= DISAS_NORETURN
;
13882 disas_a64_insn(env
, dc
);
13885 dc
->base
.pc_next
= dc
->pc
;
13886 translator_loop_temp_check(&dc
->base
);
13889 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
13891 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13893 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
13894 /* Note that this means single stepping WFI doesn't halt the CPU.
13895 * For conditional branch insns this is harmless unreachable code as
13896 * gen_goto_tb() has already handled emitting the debug exception
13897 * (and thus a tb-jump is not possible when singlestepping).
13899 switch (dc
->base
.is_jmp
) {
13901 gen_a64_set_pc_im(dc
->pc
);
13905 if (dc
->base
.singlestep_enabled
) {
13906 gen_exception_internal(EXCP_DEBUG
);
13908 gen_step_complete_exception(dc
);
13911 case DISAS_NORETURN
:
13915 switch (dc
->base
.is_jmp
) {
13917 case DISAS_TOO_MANY
:
13918 gen_goto_tb(dc
, 1, dc
->pc
);
13922 gen_a64_set_pc_im(dc
->pc
);
13925 tcg_gen_exit_tb(0);
13928 tcg_gen_lookup_and_goto_ptr();
13930 case DISAS_NORETURN
:
13934 gen_a64_set_pc_im(dc
->pc
);
13935 gen_helper_wfe(cpu_env
);
13938 gen_a64_set_pc_im(dc
->pc
);
13939 gen_helper_yield(cpu_env
);
13943 /* This is a special case because we don't want to just halt the CPU
13944 * if trying to debug across a WFI.
13946 TCGv_i32 tmp
= tcg_const_i32(4);
13948 gen_a64_set_pc_im(dc
->pc
);
13949 gen_helper_wfi(cpu_env
, tmp
);
13950 tcg_temp_free_i32(tmp
);
13951 /* The helper doesn't necessarily throw an exception, but we
13952 * must go back to the main loop to check for interrupts anyway.
13954 tcg_gen_exit_tb(0);
13960 /* Functions above can change dc->pc, so re-align db->pc_next */
13961 dc
->base
.pc_next
= dc
->pc
;
13964 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
13967 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13969 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
13970 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
13973 const TranslatorOps aarch64_translator_ops
= {
13974 .init_disas_context
= aarch64_tr_init_disas_context
,
13975 .tb_start
= aarch64_tr_tb_start
,
13976 .insn_start
= aarch64_tr_insn_start
,
13977 .breakpoint_check
= aarch64_tr_breakpoint_check
,
13978 .translate_insn
= aarch64_tr_translate_insn
,
13979 .tb_stop
= aarch64_tr_tb_stop
,
13980 .disas_log
= aarch64_tr_disas_log
,