2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Gerd Hoffmann <kraxel@redhat.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-timer.h"
25 #include "intel-hda.h"
26 #include "intel-hda-defs.h"
28 /* --------------------------------------------------------------------- */
31 static struct BusInfo hda_codec_bus_info
= {
33 .size
= sizeof(HDACodecBus
),
34 .props
= (Property
[]) {
35 DEFINE_PROP_UINT32("cad", HDACodecDevice
, cad
, -1),
36 DEFINE_PROP_END_OF_LIST()
40 void hda_codec_bus_init(DeviceState
*dev
, HDACodecBus
*bus
,
41 hda_codec_response_func response
,
42 hda_codec_xfer_func xfer
)
44 qbus_create_inplace(&bus
->qbus
, &hda_codec_bus_info
, dev
, NULL
);
45 bus
->response
= response
;
49 static int hda_codec_dev_init(DeviceState
*qdev
, DeviceInfo
*base
)
51 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, qdev
->parent_bus
);
52 HDACodecDevice
*dev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
53 HDACodecDeviceInfo
*info
= DO_UPCAST(HDACodecDeviceInfo
, qdev
, base
);
57 dev
->cad
= bus
->next_cad
;
61 bus
->next_cad
= dev
->cad
+ 1;
62 return info
->init(dev
);
65 static int hda_codec_dev_exit(DeviceState
*qdev
)
67 HDACodecDevice
*dev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
69 if (dev
->info
->exit
) {
75 void hda_codec_register(HDACodecDeviceInfo
*info
)
77 info
->qdev
.init
= hda_codec_dev_init
;
78 info
->qdev
.exit
= hda_codec_dev_exit
;
79 info
->qdev
.bus_info
= &hda_codec_bus_info
;
80 qdev_register(&info
->qdev
);
83 HDACodecDevice
*hda_codec_find(HDACodecBus
*bus
, uint32_t cad
)
88 QLIST_FOREACH(qdev
, &bus
->qbus
.children
, sibling
) {
89 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
90 if (cdev
->cad
== cad
) {
97 void hda_codec_response(HDACodecDevice
*dev
, bool solicited
, uint32_t response
)
99 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
100 bus
->response(dev
, solicited
, response
);
103 bool hda_codec_xfer(HDACodecDevice
*dev
, uint32_t stnr
, bool output
,
104 uint8_t *buf
, uint32_t len
)
106 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
107 return bus
->xfer(dev
, stnr
, output
, buf
, len
);
110 /* --------------------------------------------------------------------- */
111 /* intel hda emulation */
113 typedef struct IntelHDAStream IntelHDAStream
;
114 typedef struct IntelHDAState IntelHDAState
;
115 typedef struct IntelHDAReg IntelHDAReg
;
123 struct IntelHDAStream
{
136 uint32_t bsize
, be
, bp
;
139 struct IntelHDAState
{
176 IntelHDAStream st
[8];
181 int64_t wall_base_ns
;
184 const IntelHDAReg
*last_reg
;
188 uint32_t repeat_count
;
196 const char *name
; /* register name */
197 uint32_t size
; /* size in bytes */
198 uint32_t reset
; /* reset value */
199 uint32_t wmask
; /* write mask */
200 uint32_t wclear
; /* write 1 to clear bits */
201 uint32_t offset
; /* location in IntelHDAState */
202 uint32_t shift
; /* byte access entries for dwords */
204 void (*whandler
)(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
);
205 void (*rhandler
)(IntelHDAState
*d
, const IntelHDAReg
*reg
);
208 static void intel_hda_reset(DeviceState
*dev
);
210 /* --------------------------------------------------------------------- */
212 static target_phys_addr_t
intel_hda_addr(uint32_t lbase
, uint32_t ubase
)
214 target_phys_addr_t addr
;
216 #if TARGET_PHYS_ADDR_BITS == 32
226 static void stl_phys_le(target_phys_addr_t addr
, uint32_t value
)
228 uint32_t value_le
= cpu_to_le32(value
);
229 cpu_physical_memory_write(addr
, (uint8_t*)(&value_le
), sizeof(value_le
));
232 static uint32_t ldl_phys_le(target_phys_addr_t addr
)
235 cpu_physical_memory_read(addr
, (uint8_t*)(&value_le
), sizeof(value_le
));
236 return le32_to_cpu(value_le
);
239 static void intel_hda_update_int_sts(IntelHDAState
*d
)
244 /* update controller status */
245 if (d
->rirb_sts
& ICH6_RBSTS_IRQ
) {
248 if (d
->rirb_sts
& ICH6_RBSTS_OVERRUN
) {
251 if (d
->state_sts
& d
->wake_en
) {
255 /* update stream status */
256 for (i
= 0; i
< 8; i
++) {
257 /* buffer completion interrupt */
258 if (d
->st
[i
].ctl
& (1 << 26)) {
263 /* update global status */
264 if (sts
& d
->int_ctl
) {
271 static void intel_hda_update_irq(IntelHDAState
*d
)
273 int msi
= d
->msi
&& msi_enabled(&d
->pci
);
276 intel_hda_update_int_sts(d
);
277 if (d
->int_sts
& (1 << 31) && d
->int_ctl
& (1 << 31)) {
282 dprint(d
, 2, "%s: level %d [%s]\n", __FUNCTION__
,
283 level
, msi
? "msi" : "intx");
286 msi_notify(&d
->pci
, 0);
289 qemu_set_irq(d
->pci
.irq
[0], level
);
293 static int intel_hda_send_command(IntelHDAState
*d
, uint32_t verb
)
295 uint32_t cad
, nid
, data
;
296 HDACodecDevice
*codec
;
298 cad
= (verb
>> 28) & 0x0f;
299 if (verb
& (1 << 27)) {
300 /* indirect node addressing, not specified in HDA 1.0 */
301 dprint(d
, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__
);
304 nid
= (verb
>> 20) & 0x7f;
305 data
= verb
& 0xfffff;
307 codec
= hda_codec_find(&d
->codecs
, cad
);
309 dprint(d
, 1, "%s: addressed non-existing codec\n", __FUNCTION__
);
312 codec
->info
->command(codec
, nid
, data
);
316 static void intel_hda_corb_run(IntelHDAState
*d
)
318 target_phys_addr_t addr
;
321 if (d
->ics
& ICH6_IRS_BUSY
) {
322 dprint(d
, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__
, d
->icw
);
323 intel_hda_send_command(d
, d
->icw
);
328 if (!(d
->corb_ctl
& ICH6_CORBCTL_RUN
)) {
329 dprint(d
, 2, "%s: !run\n", __FUNCTION__
);
332 if ((d
->corb_rp
& 0xff) == d
->corb_wp
) {
333 dprint(d
, 2, "%s: corb ring empty\n", __FUNCTION__
);
336 if (d
->rirb_count
== d
->rirb_cnt
) {
337 dprint(d
, 2, "%s: rirb count reached\n", __FUNCTION__
);
341 rp
= (d
->corb_rp
+ 1) & 0xff;
342 addr
= intel_hda_addr(d
->corb_lbase
, d
->corb_ubase
);
343 verb
= ldl_phys_le(addr
+ 4*rp
);
346 dprint(d
, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__
, rp
, verb
);
347 intel_hda_send_command(d
, verb
);
351 static void intel_hda_response(HDACodecDevice
*dev
, bool solicited
, uint32_t response
)
353 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
354 IntelHDAState
*d
= container_of(bus
, IntelHDAState
, codecs
);
355 target_phys_addr_t addr
;
358 if (d
->ics
& ICH6_IRS_BUSY
) {
359 dprint(d
, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
360 __FUNCTION__
, response
, dev
->cad
);
362 d
->ics
&= ~(ICH6_IRS_BUSY
| 0xf0);
363 d
->ics
|= (ICH6_IRS_VALID
| (dev
->cad
<< 4));
367 if (!(d
->rirb_ctl
& ICH6_RBCTL_DMA_EN
)) {
368 dprint(d
, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__
);
372 ex
= (solicited
? 0 : (1 << 4)) | dev
->cad
;
373 wp
= (d
->rirb_wp
+ 1) & 0xff;
374 addr
= intel_hda_addr(d
->rirb_lbase
, d
->rirb_ubase
);
375 stl_phys_le(addr
+ 8*wp
, response
);
376 stl_phys_le(addr
+ 8*wp
+ 4, ex
);
379 dprint(d
, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
380 __FUNCTION__
, wp
, response
, ex
);
383 if (d
->rirb_count
== d
->rirb_cnt
) {
384 dprint(d
, 2, "%s: rirb count reached (%d)\n", __FUNCTION__
, d
->rirb_count
);
385 if (d
->rirb_ctl
& ICH6_RBCTL_IRQ_EN
) {
386 d
->rirb_sts
|= ICH6_RBSTS_IRQ
;
387 intel_hda_update_irq(d
);
389 } else if ((d
->corb_rp
& 0xff) == d
->corb_wp
) {
390 dprint(d
, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__
,
391 d
->rirb_count
, d
->rirb_cnt
);
392 if (d
->rirb_ctl
& ICH6_RBCTL_IRQ_EN
) {
393 d
->rirb_sts
|= ICH6_RBSTS_IRQ
;
394 intel_hda_update_irq(d
);
399 static bool intel_hda_xfer(HDACodecDevice
*dev
, uint32_t stnr
, bool output
,
400 uint8_t *buf
, uint32_t len
)
402 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
403 IntelHDAState
*d
= container_of(bus
, IntelHDAState
, codecs
);
404 IntelHDAStream
*st
= NULL
;
405 target_phys_addr_t addr
;
406 uint32_t s
, copy
, left
;
409 for (s
= 0; s
< ARRAY_SIZE(d
->st
); s
++) {
410 if (stnr
== ((d
->st
[s
].ctl
>> 20) & 0x0f)) {
418 if (st
->bpl
== NULL
) {
421 if (st
->ctl
& (1 << 26)) {
423 * Wait with the next DMA xfer until the guest
424 * has acked the buffer completion interrupt
432 if (copy
> st
->bsize
- st
->lpib
)
433 copy
= st
->bsize
- st
->lpib
;
434 if (copy
> st
->bpl
[st
->be
].len
- st
->bp
)
435 copy
= st
->bpl
[st
->be
].len
- st
->bp
;
437 dprint(d
, 3, "dma: entry %d, pos %d/%d, copy %d\n",
438 st
->be
, st
->bp
, st
->bpl
[st
->be
].len
, copy
);
440 cpu_physical_memory_rw(st
->bpl
[st
->be
].addr
+ st
->bp
,
447 if (st
->bpl
[st
->be
].len
== st
->bp
) {
448 /* bpl entry filled */
449 if (st
->bpl
[st
->be
].flags
& 0x01) {
454 if (st
->be
== st
->bentries
) {
455 /* bpl wrap around */
461 if (d
->dp_lbase
& 0x01) {
462 addr
= intel_hda_addr(d
->dp_lbase
& ~0x01, d
->dp_ubase
);
463 stl_phys_le(addr
+ 8*s
, st
->lpib
);
465 dprint(d
, 3, "dma: --\n");
468 st
->ctl
|= (1 << 26); /* buffer completion interrupt */
469 intel_hda_update_irq(d
);
474 static void intel_hda_parse_bdl(IntelHDAState
*d
, IntelHDAStream
*st
)
476 target_phys_addr_t addr
;
480 addr
= intel_hda_addr(st
->bdlp_lbase
, st
->bdlp_ubase
);
481 st
->bentries
= st
->lvi
+1;
483 st
->bpl
= qemu_malloc(sizeof(bpl
) * st
->bentries
);
484 for (i
= 0; i
< st
->bentries
; i
++, addr
+= 16) {
485 cpu_physical_memory_read(addr
, buf
, 16);
486 st
->bpl
[i
].addr
= le64_to_cpu(*(uint64_t *)buf
);
487 st
->bpl
[i
].len
= le32_to_cpu(*(uint32_t *)(buf
+ 8));
488 st
->bpl
[i
].flags
= le32_to_cpu(*(uint32_t *)(buf
+ 12));
489 dprint(d
, 1, "bdl/%d: 0x%" PRIx64
" +0x%x, 0x%x\n",
490 i
, st
->bpl
[i
].addr
, st
->bpl
[i
].len
, st
->bpl
[i
].flags
);
499 static void intel_hda_notify_codecs(IntelHDAState
*d
, uint32_t stream
, bool running
)
502 HDACodecDevice
*cdev
;
504 QLIST_FOREACH(qdev
, &d
->codecs
.qbus
.children
, sibling
) {
505 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
506 if (cdev
->info
->stream
) {
507 cdev
->info
->stream(cdev
, stream
, running
);
512 /* --------------------------------------------------------------------- */
514 static void intel_hda_set_g_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
516 if ((d
->g_ctl
& ICH6_GCTL_RESET
) == 0) {
517 intel_hda_reset(&d
->pci
.qdev
);
521 static void intel_hda_set_wake_en(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
523 intel_hda_update_irq(d
);
526 static void intel_hda_set_state_sts(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
528 intel_hda_update_irq(d
);
531 static void intel_hda_set_int_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
533 intel_hda_update_irq(d
);
536 static void intel_hda_get_wall_clk(IntelHDAState
*d
, const IntelHDAReg
*reg
)
540 ns
= qemu_get_clock_ns(vm_clock
) - d
->wall_base_ns
;
541 d
->wall_clk
= (uint32_t)(ns
* 24 / 1000); /* 24 MHz */
544 static void intel_hda_set_corb_wp(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
546 intel_hda_corb_run(d
);
549 static void intel_hda_set_corb_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
551 intel_hda_corb_run(d
);
554 static void intel_hda_set_rirb_wp(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
556 if (d
->rirb_wp
& ICH6_RIRBWP_RST
) {
561 static void intel_hda_set_rirb_sts(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
563 intel_hda_update_irq(d
);
565 if ((old
& ICH6_RBSTS_IRQ
) && !(d
->rirb_sts
& ICH6_RBSTS_IRQ
)) {
566 /* cleared ICH6_RBSTS_IRQ */
568 intel_hda_corb_run(d
);
572 static void intel_hda_set_ics(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
574 if (d
->ics
& ICH6_IRS_BUSY
) {
575 intel_hda_corb_run(d
);
579 static void intel_hda_set_st_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
581 IntelHDAStream
*st
= d
->st
+ reg
->stream
;
583 if (st
->ctl
& 0x01) {
585 dprint(d
, 1, "st #%d: reset\n", reg
->stream
);
588 if ((st
->ctl
& 0x02) != (old
& 0x02)) {
589 uint32_t stnr
= (st
->ctl
>> 20) & 0x0f;
590 /* run bit flipped */
591 if (st
->ctl
& 0x02) {
593 dprint(d
, 1, "st #%d: start %d (ring buf %d bytes)\n",
594 reg
->stream
, stnr
, st
->cbl
);
595 intel_hda_parse_bdl(d
, st
);
596 intel_hda_notify_codecs(d
, stnr
, true);
599 dprint(d
, 1, "st #%d: stop %d\n", reg
->stream
, stnr
);
600 intel_hda_notify_codecs(d
, stnr
, false);
603 intel_hda_update_irq(d
);
606 /* --------------------------------------------------------------------- */
608 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
610 static const struct IntelHDAReg regtab
[] = {
612 [ ICH6_REG_GCAP
] = {
617 [ ICH6_REG_VMIN
] = {
621 [ ICH6_REG_VMAJ
] = {
626 [ ICH6_REG_OUTPAY
] = {
631 [ ICH6_REG_INPAY
] = {
636 [ ICH6_REG_GCTL
] = {
640 .offset
= offsetof(IntelHDAState
, g_ctl
),
641 .whandler
= intel_hda_set_g_ctl
,
643 [ ICH6_REG_WAKEEN
] = {
647 .offset
= offsetof(IntelHDAState
, wake_en
),
648 .whandler
= intel_hda_set_wake_en
,
650 [ ICH6_REG_STATESTS
] = {
655 .offset
= offsetof(IntelHDAState
, state_sts
),
656 .whandler
= intel_hda_set_state_sts
,
660 [ ICH6_REG_INTCTL
] = {
664 .offset
= offsetof(IntelHDAState
, int_ctl
),
665 .whandler
= intel_hda_set_int_ctl
,
667 [ ICH6_REG_INTSTS
] = {
671 .wclear
= 0xc00000ff,
672 .offset
= offsetof(IntelHDAState
, int_sts
),
676 [ ICH6_REG_WALLCLK
] = {
679 .offset
= offsetof(IntelHDAState
, wall_clk
),
680 .rhandler
= intel_hda_get_wall_clk
,
682 [ ICH6_REG_WALLCLK
+ 0x2000 ] = {
683 .name
= "WALLCLK(alias)",
685 .offset
= offsetof(IntelHDAState
, wall_clk
),
686 .rhandler
= intel_hda_get_wall_clk
,
690 [ ICH6_REG_CORBLBASE
] = {
694 .offset
= offsetof(IntelHDAState
, corb_lbase
),
696 [ ICH6_REG_CORBUBASE
] = {
700 .offset
= offsetof(IntelHDAState
, corb_ubase
),
702 [ ICH6_REG_CORBWP
] = {
706 .offset
= offsetof(IntelHDAState
, corb_wp
),
707 .whandler
= intel_hda_set_corb_wp
,
709 [ ICH6_REG_CORBRP
] = {
713 .offset
= offsetof(IntelHDAState
, corb_rp
),
715 [ ICH6_REG_CORBCTL
] = {
719 .offset
= offsetof(IntelHDAState
, corb_ctl
),
720 .whandler
= intel_hda_set_corb_ctl
,
722 [ ICH6_REG_CORBSTS
] = {
727 .offset
= offsetof(IntelHDAState
, corb_sts
),
729 [ ICH6_REG_CORBSIZE
] = {
733 .offset
= offsetof(IntelHDAState
, corb_size
),
735 [ ICH6_REG_RIRBLBASE
] = {
739 .offset
= offsetof(IntelHDAState
, rirb_lbase
),
741 [ ICH6_REG_RIRBUBASE
] = {
745 .offset
= offsetof(IntelHDAState
, rirb_ubase
),
747 [ ICH6_REG_RIRBWP
] = {
751 .offset
= offsetof(IntelHDAState
, rirb_wp
),
752 .whandler
= intel_hda_set_rirb_wp
,
754 [ ICH6_REG_RINTCNT
] = {
758 .offset
= offsetof(IntelHDAState
, rirb_cnt
),
760 [ ICH6_REG_RIRBCTL
] = {
764 .offset
= offsetof(IntelHDAState
, rirb_ctl
),
766 [ ICH6_REG_RIRBSTS
] = {
771 .offset
= offsetof(IntelHDAState
, rirb_sts
),
772 .whandler
= intel_hda_set_rirb_sts
,
774 [ ICH6_REG_RIRBSIZE
] = {
778 .offset
= offsetof(IntelHDAState
, rirb_size
),
781 [ ICH6_REG_DPLBASE
] = {
785 .offset
= offsetof(IntelHDAState
, dp_lbase
),
787 [ ICH6_REG_DPUBASE
] = {
791 .offset
= offsetof(IntelHDAState
, dp_ubase
),
798 .offset
= offsetof(IntelHDAState
, icw
),
803 .offset
= offsetof(IntelHDAState
, irr
),
810 .offset
= offsetof(IntelHDAState
, ics
),
811 .whandler
= intel_hda_set_ics
,
814 #define HDA_STREAM(_t, _i) \
815 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
817 .name = _t stringify(_i) " CTL", \
819 .wmask = 0x1cff001f, \
820 .offset = offsetof(IntelHDAState, st[_i].ctl), \
821 .whandler = intel_hda_set_st_ctl, \
823 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
825 .name = _t stringify(_i) " CTL(stnr)", \
828 .wmask = 0x00ff0000, \
829 .offset = offsetof(IntelHDAState, st[_i].ctl), \
830 .whandler = intel_hda_set_st_ctl, \
832 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
834 .name = _t stringify(_i) " CTL(sts)", \
837 .wmask = 0x1c000000, \
838 .wclear = 0x1c000000, \
839 .offset = offsetof(IntelHDAState, st[_i].ctl), \
840 .whandler = intel_hda_set_st_ctl, \
842 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
844 .name = _t stringify(_i) " LPIB", \
846 .offset = offsetof(IntelHDAState, st[_i].lpib), \
848 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
850 .name = _t stringify(_i) " LPIB(alias)", \
852 .offset = offsetof(IntelHDAState, st[_i].lpib), \
854 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
856 .name = _t stringify(_i) " CBL", \
858 .wmask = 0xffffffff, \
859 .offset = offsetof(IntelHDAState, st[_i].cbl), \
861 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
863 .name = _t stringify(_i) " LVI", \
866 .offset = offsetof(IntelHDAState, st[_i].lvi), \
868 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
870 .name = _t stringify(_i) " FIFOS", \
872 .reset = HDA_BUFFER_SIZE, \
874 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
876 .name = _t stringify(_i) " FMT", \
879 .offset = offsetof(IntelHDAState, st[_i].fmt), \
881 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
883 .name = _t stringify(_i) " BDLPL", \
885 .wmask = 0xffffff80, \
886 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
888 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
890 .name = _t stringify(_i) " BDLPU", \
892 .wmask = 0xffffffff, \
893 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
908 static const IntelHDAReg
*intel_hda_reg_find(IntelHDAState
*d
, target_phys_addr_t addr
)
910 const IntelHDAReg
*reg
;
912 if (addr
>= sizeof(regtab
)/sizeof(regtab
[0])) {
916 if (reg
->name
== NULL
) {
922 dprint(d
, 1, "unknown register, addr 0x%x\n", (int) addr
);
926 static uint32_t *intel_hda_reg_addr(IntelHDAState
*d
, const IntelHDAReg
*reg
)
928 uint8_t *addr
= (void*)d
;
931 return (uint32_t*)addr
;
934 static void intel_hda_reg_write(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t val
,
945 time_t now
= time(NULL
);
946 if (d
->last_write
&& d
->last_reg
== reg
&& d
->last_val
== val
) {
948 if (d
->last_sec
!= now
) {
949 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
954 if (d
->repeat_count
) {
955 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
957 dprint(d
, 2, "write %-16s: 0x%x (%x)\n", reg
->name
, val
, wmask
);
965 assert(reg
->offset
!= 0);
967 addr
= intel_hda_reg_addr(d
, reg
);
972 wmask
<<= reg
->shift
;
976 *addr
|= wmask
& val
;
977 *addr
&= ~(val
& reg
->wclear
);
980 reg
->whandler(d
, reg
, old
);
984 static uint32_t intel_hda_reg_read(IntelHDAState
*d
, const IntelHDAReg
*reg
,
994 reg
->rhandler(d
, reg
);
997 if (reg
->offset
== 0) {
998 /* constant read-only register */
1001 addr
= intel_hda_reg_addr(d
, reg
);
1009 time_t now
= time(NULL
);
1010 if (!d
->last_write
&& d
->last_reg
== reg
&& d
->last_val
== ret
) {
1012 if (d
->last_sec
!= now
) {
1013 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
1015 d
->repeat_count
= 0;
1018 if (d
->repeat_count
) {
1019 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
1021 dprint(d
, 2, "read %-16s: 0x%x (%x)\n", reg
->name
, ret
, rmask
);
1026 d
->repeat_count
= 0;
1032 static void intel_hda_regs_reset(IntelHDAState
*d
)
1037 for (i
= 0; i
< sizeof(regtab
)/sizeof(regtab
[0]); i
++) {
1038 if (regtab
[i
].name
== NULL
) {
1041 if (regtab
[i
].offset
== 0) {
1044 addr
= intel_hda_reg_addr(d
, regtab
+ i
);
1045 *addr
= regtab
[i
].reset
;
1049 /* --------------------------------------------------------------------- */
1051 static void intel_hda_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1053 IntelHDAState
*d
= opaque
;
1054 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1056 intel_hda_reg_write(d
, reg
, val
, 0xff);
1059 static void intel_hda_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1061 IntelHDAState
*d
= opaque
;
1062 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1064 intel_hda_reg_write(d
, reg
, val
, 0xffff);
1067 static void intel_hda_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1069 IntelHDAState
*d
= opaque
;
1070 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1072 intel_hda_reg_write(d
, reg
, val
, 0xffffffff);
1075 static uint32_t intel_hda_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1077 IntelHDAState
*d
= opaque
;
1078 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1080 return intel_hda_reg_read(d
, reg
, 0xff);
1083 static uint32_t intel_hda_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1085 IntelHDAState
*d
= opaque
;
1086 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1088 return intel_hda_reg_read(d
, reg
, 0xffff);
1091 static uint32_t intel_hda_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1093 IntelHDAState
*d
= opaque
;
1094 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1096 return intel_hda_reg_read(d
, reg
, 0xffffffff);
1099 static CPUReadMemoryFunc
* const intel_hda_mmio_read
[3] = {
1100 intel_hda_mmio_readb
,
1101 intel_hda_mmio_readw
,
1102 intel_hda_mmio_readl
,
1105 static CPUWriteMemoryFunc
* const intel_hda_mmio_write
[3] = {
1106 intel_hda_mmio_writeb
,
1107 intel_hda_mmio_writew
,
1108 intel_hda_mmio_writel
,
1111 static void intel_hda_map(PCIDevice
*pci
, int region_num
,
1112 pcibus_t addr
, pcibus_t size
, int type
)
1114 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1116 cpu_register_physical_memory(addr
, 0x4000, d
->mmio_addr
);
1119 /* --------------------------------------------------------------------- */
1121 static void intel_hda_reset(DeviceState
*dev
)
1123 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
.qdev
, dev
);
1125 HDACodecDevice
*cdev
;
1127 intel_hda_regs_reset(d
);
1128 d
->wall_base_ns
= qemu_get_clock(vm_clock
);
1131 QLIST_FOREACH(qdev
, &d
->codecs
.qbus
.children
, sibling
) {
1132 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
1133 if (qdev
->info
->reset
) {
1134 qdev
->info
->reset(qdev
);
1136 d
->state_sts
|= (1 << cdev
->cad
);
1138 intel_hda_update_irq(d
);
1141 static int intel_hda_init(PCIDevice
*pci
)
1143 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1144 uint8_t *conf
= d
->pci
.config
;
1146 d
->name
= d
->pci
.qdev
.info
->name
;
1148 pci_config_set_vendor_id(conf
, PCI_VENDOR_ID_INTEL
);
1149 pci_config_set_device_id(conf
, 0x2668);
1150 pci_config_set_revision(conf
, 1);
1151 pci_config_set_class(conf
, PCI_CLASS_MULTIMEDIA_HD_AUDIO
);
1152 pci_config_set_interrupt_pin(conf
, 1);
1154 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1157 d
->mmio_addr
= cpu_register_io_memory(intel_hda_mmio_read
,
1158 intel_hda_mmio_write
, d
);
1159 pci_register_bar(&d
->pci
, 0, 0x4000, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1162 msi_init(&d
->pci
, 0x50, 1, true, false);
1165 hda_codec_bus_init(&d
->pci
.qdev
, &d
->codecs
,
1166 intel_hda_response
, intel_hda_xfer
);
1171 static int intel_hda_exit(PCIDevice
*pci
)
1173 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1176 msi_uninit(&d
->pci
);
1178 cpu_unregister_io_memory(d
->mmio_addr
);
1182 static void intel_hda_write_config(PCIDevice
*pci
, uint32_t addr
,
1183 uint32_t val
, int len
)
1185 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1187 pci_default_write_config(pci
, addr
, val
, len
);
1189 msi_write_config(pci
, addr
, val
, len
);
1193 static int intel_hda_post_load(void *opaque
, int version
)
1195 IntelHDAState
* d
= opaque
;
1198 dprint(d
, 1, "%s\n", __FUNCTION__
);
1199 for (i
= 0; i
< ARRAY_SIZE(d
->st
); i
++) {
1200 if (d
->st
[i
].ctl
& 0x02) {
1201 intel_hda_parse_bdl(d
, &d
->st
[i
]);
1204 intel_hda_update_irq(d
);
1208 static const VMStateDescription vmstate_intel_hda_stream
= {
1209 .name
= "intel-hda-stream",
1211 .fields
= (VMStateField
[]) {
1212 VMSTATE_UINT32(ctl
, IntelHDAStream
),
1213 VMSTATE_UINT32(lpib
, IntelHDAStream
),
1214 VMSTATE_UINT32(cbl
, IntelHDAStream
),
1215 VMSTATE_UINT32(lvi
, IntelHDAStream
),
1216 VMSTATE_UINT32(fmt
, IntelHDAStream
),
1217 VMSTATE_UINT32(bdlp_lbase
, IntelHDAStream
),
1218 VMSTATE_UINT32(bdlp_ubase
, IntelHDAStream
),
1219 VMSTATE_END_OF_LIST()
1223 static const VMStateDescription vmstate_intel_hda
= {
1224 .name
= "intel-hda",
1226 .post_load
= intel_hda_post_load
,
1227 .fields
= (VMStateField
[]) {
1228 VMSTATE_PCI_DEVICE(pci
, IntelHDAState
),
1231 VMSTATE_UINT32(g_ctl
, IntelHDAState
),
1232 VMSTATE_UINT32(wake_en
, IntelHDAState
),
1233 VMSTATE_UINT32(state_sts
, IntelHDAState
),
1234 VMSTATE_UINT32(int_ctl
, IntelHDAState
),
1235 VMSTATE_UINT32(int_sts
, IntelHDAState
),
1236 VMSTATE_UINT32(wall_clk
, IntelHDAState
),
1237 VMSTATE_UINT32(corb_lbase
, IntelHDAState
),
1238 VMSTATE_UINT32(corb_ubase
, IntelHDAState
),
1239 VMSTATE_UINT32(corb_rp
, IntelHDAState
),
1240 VMSTATE_UINT32(corb_wp
, IntelHDAState
),
1241 VMSTATE_UINT32(corb_ctl
, IntelHDAState
),
1242 VMSTATE_UINT32(corb_sts
, IntelHDAState
),
1243 VMSTATE_UINT32(corb_size
, IntelHDAState
),
1244 VMSTATE_UINT32(rirb_lbase
, IntelHDAState
),
1245 VMSTATE_UINT32(rirb_ubase
, IntelHDAState
),
1246 VMSTATE_UINT32(rirb_wp
, IntelHDAState
),
1247 VMSTATE_UINT32(rirb_cnt
, IntelHDAState
),
1248 VMSTATE_UINT32(rirb_ctl
, IntelHDAState
),
1249 VMSTATE_UINT32(rirb_sts
, IntelHDAState
),
1250 VMSTATE_UINT32(rirb_size
, IntelHDAState
),
1251 VMSTATE_UINT32(dp_lbase
, IntelHDAState
),
1252 VMSTATE_UINT32(dp_ubase
, IntelHDAState
),
1253 VMSTATE_UINT32(icw
, IntelHDAState
),
1254 VMSTATE_UINT32(irr
, IntelHDAState
),
1255 VMSTATE_UINT32(ics
, IntelHDAState
),
1256 VMSTATE_STRUCT_ARRAY(st
, IntelHDAState
, 8, 0,
1257 vmstate_intel_hda_stream
,
1260 /* additional state info */
1261 VMSTATE_UINT32(rirb_count
, IntelHDAState
),
1262 VMSTATE_INT64(wall_base_ns
, IntelHDAState
),
1264 VMSTATE_END_OF_LIST()
1268 static PCIDeviceInfo intel_hda_info
= {
1269 .qdev
.name
= "intel-hda",
1270 .qdev
.desc
= "Intel HD Audio Controller",
1271 .qdev
.size
= sizeof(IntelHDAState
),
1272 .qdev
.vmsd
= &vmstate_intel_hda
,
1273 .qdev
.reset
= intel_hda_reset
,
1274 .init
= intel_hda_init
,
1275 .exit
= intel_hda_exit
,
1276 .config_write
= intel_hda_write_config
,
1277 .qdev
.props
= (Property
[]) {
1278 DEFINE_PROP_UINT32("debug", IntelHDAState
, debug
, 0),
1279 DEFINE_PROP_UINT32("msi", IntelHDAState
, msi
, 1),
1280 DEFINE_PROP_END_OF_LIST(),
1284 static void intel_hda_register(void)
1286 pci_qdev_register(&intel_hda_info
);
1288 device_init(intel_hda_register
);
1291 * create intel hda controller with codec attached to it,
1292 * so '-soundhw hda' works.
1294 int intel_hda_and_codec_init(PCIBus
*bus
)
1296 PCIDevice
*controller
;
1300 controller
= pci_create_simple(bus
, -1, "intel-hda");
1301 hdabus
= QLIST_FIRST(&controller
->qdev
.child_bus
);
1302 codec
= qdev_create(hdabus
, "hda-duplex");
1303 qdev_init_nofail(codec
);