4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
28 #include "translate.h"
29 #include "internals.h"
30 #include "qemu/host-utils.h"
32 #include "exec/gen-icount.h"
38 static TCGv_i64 cpu_X
[32];
39 static TCGv_i64 cpu_pc
;
40 static TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
42 /* Load/store exclusive handling */
43 static TCGv_i64 cpu_exclusive_addr
;
44 static TCGv_i64 cpu_exclusive_val
;
45 static TCGv_i64 cpu_exclusive_high
;
46 #ifdef CONFIG_USER_ONLY
47 static TCGv_i64 cpu_exclusive_test
;
48 static TCGv_i32 cpu_exclusive_info
;
51 static const char *regnames
[] = {
52 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
53 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
54 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
55 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
59 A64_SHIFT_TYPE_LSL
= 0,
60 A64_SHIFT_TYPE_LSR
= 1,
61 A64_SHIFT_TYPE_ASR
= 2,
62 A64_SHIFT_TYPE_ROR
= 3
65 /* Table based decoder typedefs - used when the relevant bits for decode
66 * are too awkwardly scattered across the instruction (eg SIMD).
68 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
70 typedef struct AArch64DecodeTable
{
73 AArch64DecodeFn
*disas_fn
;
76 /* Function prototype for gen_ functions for calling Neon helpers */
77 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
78 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
79 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
80 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
81 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
82 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
83 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
84 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
85 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
86 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
87 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
89 /* initialize TCG globals. */
90 void a64_translate_init(void)
94 cpu_pc
= tcg_global_mem_new_i64(TCG_AREG0
,
95 offsetof(CPUARMState
, pc
),
97 for (i
= 0; i
< 32; i
++) {
98 cpu_X
[i
] = tcg_global_mem_new_i64(TCG_AREG0
,
99 offsetof(CPUARMState
, xregs
[i
]),
103 cpu_NF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, NF
), "NF");
104 cpu_ZF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, ZF
), "ZF");
105 cpu_CF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, CF
), "CF");
106 cpu_VF
= tcg_global_mem_new_i32(TCG_AREG0
, offsetof(CPUARMState
, VF
), "VF");
108 cpu_exclusive_addr
= tcg_global_mem_new_i64(TCG_AREG0
,
109 offsetof(CPUARMState
, exclusive_addr
), "exclusive_addr");
110 cpu_exclusive_val
= tcg_global_mem_new_i64(TCG_AREG0
,
111 offsetof(CPUARMState
, exclusive_val
), "exclusive_val");
112 cpu_exclusive_high
= tcg_global_mem_new_i64(TCG_AREG0
,
113 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
114 #ifdef CONFIG_USER_ONLY
115 cpu_exclusive_test
= tcg_global_mem_new_i64(TCG_AREG0
,
116 offsetof(CPUARMState
, exclusive_test
), "exclusive_test");
117 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
118 offsetof(CPUARMState
, exclusive_info
), "exclusive_info");
122 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
123 fprintf_function cpu_fprintf
, int flags
)
125 ARMCPU
*cpu
= ARM_CPU(cs
);
126 CPUARMState
*env
= &cpu
->env
;
127 uint32_t psr
= pstate_read(env
);
130 cpu_fprintf(f
, "PC=%016"PRIx64
" SP=%016"PRIx64
"\n",
131 env
->pc
, env
->xregs
[31]);
132 for (i
= 0; i
< 31; i
++) {
133 cpu_fprintf(f
, "X%02d=%016"PRIx64
, i
, env
->xregs
[i
]);
135 cpu_fprintf(f
, "\n");
140 cpu_fprintf(f
, "PSTATE=%08x (flags %c%c%c%c)\n",
142 psr
& PSTATE_N
? 'N' : '-',
143 psr
& PSTATE_Z
? 'Z' : '-',
144 psr
& PSTATE_C
? 'C' : '-',
145 psr
& PSTATE_V
? 'V' : '-');
146 cpu_fprintf(f
, "\n");
148 if (flags
& CPU_DUMP_FPU
) {
150 for (i
= 0; i
< numvfpregs
; i
+= 2) {
151 uint64_t vlo
= float64_val(env
->vfp
.regs
[i
* 2]);
152 uint64_t vhi
= float64_val(env
->vfp
.regs
[(i
* 2) + 1]);
153 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
" ",
155 vlo
= float64_val(env
->vfp
.regs
[(i
+ 1) * 2]);
156 vhi
= float64_val(env
->vfp
.regs
[((i
+ 1) * 2) + 1]);
157 cpu_fprintf(f
, "q%02d=%016" PRIx64
":%016" PRIx64
"\n",
160 cpu_fprintf(f
, "FPCR: %08x FPSR: %08x\n",
161 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
165 static int get_mem_index(DisasContext
*s
)
167 #ifdef CONFIG_USER_ONLY
174 void gen_a64_set_pc_im(uint64_t val
)
176 tcg_gen_movi_i64(cpu_pc
, val
);
179 static void gen_exception_internal(int excp
)
181 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
183 assert(excp_is_internal(excp
));
184 gen_helper_exception_internal(cpu_env
, tcg_excp
);
185 tcg_temp_free_i32(tcg_excp
);
188 static void gen_exception(int excp
, uint32_t syndrome
)
190 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
191 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
193 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
, tcg_syn
);
194 tcg_temp_free_i32(tcg_syn
);
195 tcg_temp_free_i32(tcg_excp
);
198 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
200 gen_a64_set_pc_im(s
->pc
- offset
);
201 gen_exception_internal(excp
);
202 s
->is_jmp
= DISAS_EXC
;
205 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
208 gen_a64_set_pc_im(s
->pc
- offset
);
209 gen_exception(excp
, syndrome
);
210 s
->is_jmp
= DISAS_EXC
;
213 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
215 /* No direct tb linking with singlestep or deterministic io */
216 if (s
->singlestep_enabled
|| (s
->tb
->cflags
& CF_LAST_IO
)) {
220 /* Only link tbs from inside the same guest page */
221 if ((s
->tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
228 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
230 TranslationBlock
*tb
;
233 if (use_goto_tb(s
, n
, dest
)) {
235 gen_a64_set_pc_im(dest
);
236 tcg_gen_exit_tb((intptr_t)tb
+ n
);
237 s
->is_jmp
= DISAS_TB_JUMP
;
239 gen_a64_set_pc_im(dest
);
240 if (s
->singlestep_enabled
) {
241 gen_exception_internal(EXCP_DEBUG
);
244 s
->is_jmp
= DISAS_JUMP
;
248 static void unallocated_encoding(DisasContext
*s
)
250 /* Unallocated and reserved encodings are uncategorized */
251 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized());
254 #define unsupported_encoding(s, insn) \
256 qemu_log_mask(LOG_UNIMP, \
257 "%s:%d: unsupported instruction encoding 0x%08x " \
258 "at pc=%016" PRIx64 "\n", \
259 __FILE__, __LINE__, insn, s->pc - 4); \
260 unallocated_encoding(s); \
263 static void init_tmp_a64_array(DisasContext
*s
)
265 #ifdef CONFIG_DEBUG_TCG
267 for (i
= 0; i
< ARRAY_SIZE(s
->tmp_a64
); i
++) {
268 TCGV_UNUSED_I64(s
->tmp_a64
[i
]);
271 s
->tmp_a64_count
= 0;
274 static void free_tmp_a64(DisasContext
*s
)
277 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
278 tcg_temp_free_i64(s
->tmp_a64
[i
]);
280 init_tmp_a64_array(s
);
283 static TCGv_i64
new_tmp_a64(DisasContext
*s
)
285 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
286 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
289 static TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
291 TCGv_i64 t
= new_tmp_a64(s
);
292 tcg_gen_movi_i64(t
, 0);
297 * Register access functions
299 * These functions are used for directly accessing a register in where
300 * changes to the final register value are likely to be made. If you
301 * need to use a register for temporary calculation (e.g. index type
302 * operations) use the read_* form.
304 * B1.2.1 Register mappings
306 * In instruction register encoding 31 can refer to ZR (zero register) or
307 * the SP (stack pointer) depending on context. In QEMU's case we map SP
308 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
309 * This is the point of the _sp forms.
311 static TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
314 return new_tmp_a64_zero(s
);
320 /* register access for when 31 == SP */
321 static TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
326 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
327 * representing the register contents. This TCGv is an auto-freed
328 * temporary so it need not be explicitly freed, and may be modified.
330 static TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
332 TCGv_i64 v
= new_tmp_a64(s
);
335 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
337 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
340 tcg_gen_movi_i64(v
, 0);
345 static TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
347 TCGv_i64 v
= new_tmp_a64(s
);
349 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
351 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
356 /* We should have at some point before trying to access an FP register
357 * done the necessary access check, so assert that
358 * (a) we did the check and
359 * (b) we didn't then just plough ahead anyway if it failed.
360 * Print the instruction pattern in the abort message so we can figure
361 * out what we need to fix if a user encounters this problem in the wild.
363 static inline void assert_fp_access_checked(DisasContext
*s
)
365 #ifdef CONFIG_DEBUG_TCG
366 if (unlikely(!s
->fp_access_checked
|| !s
->cpacr_fpen
)) {
367 fprintf(stderr
, "target-arm: FP access check missing for "
368 "instruction 0x%08x\n", s
->insn
);
374 /* Return the offset into CPUARMState of an element of specified
375 * size, 'element' places in from the least significant end of
376 * the FP/vector register Qn.
378 static inline int vec_reg_offset(DisasContext
*s
, int regno
,
379 int element
, TCGMemOp size
)
381 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
382 #ifdef HOST_WORDS_BIGENDIAN
383 /* This is complicated slightly because vfp.regs[2n] is
384 * still the low half and vfp.regs[2n+1] the high half
385 * of the 128 bit vector, even on big endian systems.
386 * Calculate the offset assuming a fully bigendian 128 bits,
387 * then XOR to account for the order of the two 64 bit halves.
389 offs
+= (16 - ((element
+ 1) * (1 << size
)));
392 offs
+= element
* (1 << size
);
394 assert_fp_access_checked(s
);
398 /* Return the offset into CPUARMState of a slice (from
399 * the least significant end) of FP register Qn (ie
401 * (Note that this is not the same mapping as for A32; see cpu.h)
403 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
405 int offs
= offsetof(CPUARMState
, vfp
.regs
[regno
* 2]);
406 #ifdef HOST_WORDS_BIGENDIAN
407 offs
+= (8 - (1 << size
));
409 assert_fp_access_checked(s
);
413 /* Offset of the high half of the 128 bit vector Qn */
414 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
416 assert_fp_access_checked(s
);
417 return offsetof(CPUARMState
, vfp
.regs
[regno
* 2 + 1]);
420 /* Convenience accessors for reading and writing single and double
421 * FP registers. Writing clears the upper parts of the associated
422 * 128 bit vector register, as required by the architecture.
423 * Note that unlike the GP register accessors, the values returned
424 * by the read functions must be manually freed.
426 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
428 TCGv_i64 v
= tcg_temp_new_i64();
430 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
434 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
436 TCGv_i32 v
= tcg_temp_new_i32();
438 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
442 static void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
444 TCGv_i64 tcg_zero
= tcg_const_i64(0);
446 tcg_gen_st_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
447 tcg_gen_st_i64(tcg_zero
, cpu_env
, fp_reg_hi_offset(s
, reg
));
448 tcg_temp_free_i64(tcg_zero
);
451 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
453 TCGv_i64 tmp
= tcg_temp_new_i64();
455 tcg_gen_extu_i32_i64(tmp
, v
);
456 write_fp_dreg(s
, reg
, tmp
);
457 tcg_temp_free_i64(tmp
);
460 static TCGv_ptr
get_fpstatus_ptr(void)
462 TCGv_ptr statusptr
= tcg_temp_new_ptr();
465 /* In A64 all instructions (both FP and Neon) use the FPCR;
466 * there is no equivalent of the A32 Neon "standard FPSCR value"
467 * and all operations use vfp.fp_status.
469 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
470 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
474 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
475 * than the 32 bit equivalent.
477 static inline void gen_set_NZ64(TCGv_i64 result
)
479 TCGv_i64 flag
= tcg_temp_new_i64();
481 tcg_gen_setcondi_i64(TCG_COND_NE
, flag
, result
, 0);
482 tcg_gen_trunc_i64_i32(cpu_ZF
, flag
);
483 tcg_gen_shri_i64(flag
, result
, 32);
484 tcg_gen_trunc_i64_i32(cpu_NF
, flag
);
485 tcg_temp_free_i64(flag
);
488 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
489 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
492 gen_set_NZ64(result
);
494 tcg_gen_trunc_i64_i32(cpu_ZF
, result
);
495 tcg_gen_trunc_i64_i32(cpu_NF
, result
);
497 tcg_gen_movi_i32(cpu_CF
, 0);
498 tcg_gen_movi_i32(cpu_VF
, 0);
501 /* dest = T0 + T1; compute C, N, V and Z flags */
502 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
505 TCGv_i64 result
, flag
, tmp
;
506 result
= tcg_temp_new_i64();
507 flag
= tcg_temp_new_i64();
508 tmp
= tcg_temp_new_i64();
510 tcg_gen_movi_i64(tmp
, 0);
511 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
513 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
515 gen_set_NZ64(result
);
517 tcg_gen_xor_i64(flag
, result
, t0
);
518 tcg_gen_xor_i64(tmp
, t0
, t1
);
519 tcg_gen_andc_i64(flag
, flag
, tmp
);
520 tcg_temp_free_i64(tmp
);
521 tcg_gen_shri_i64(flag
, flag
, 32);
522 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
524 tcg_gen_mov_i64(dest
, result
);
525 tcg_temp_free_i64(result
);
526 tcg_temp_free_i64(flag
);
528 /* 32 bit arithmetic */
529 TCGv_i32 t0_32
= tcg_temp_new_i32();
530 TCGv_i32 t1_32
= tcg_temp_new_i32();
531 TCGv_i32 tmp
= tcg_temp_new_i32();
533 tcg_gen_movi_i32(tmp
, 0);
534 tcg_gen_trunc_i64_i32(t0_32
, t0
);
535 tcg_gen_trunc_i64_i32(t1_32
, t1
);
536 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
537 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
538 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
539 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
540 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
541 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
543 tcg_temp_free_i32(tmp
);
544 tcg_temp_free_i32(t0_32
);
545 tcg_temp_free_i32(t1_32
);
549 /* dest = T0 - T1; compute C, N, V and Z flags */
550 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
553 /* 64 bit arithmetic */
554 TCGv_i64 result
, flag
, tmp
;
556 result
= tcg_temp_new_i64();
557 flag
= tcg_temp_new_i64();
558 tcg_gen_sub_i64(result
, t0
, t1
);
560 gen_set_NZ64(result
);
562 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
563 tcg_gen_trunc_i64_i32(cpu_CF
, flag
);
565 tcg_gen_xor_i64(flag
, result
, t0
);
566 tmp
= tcg_temp_new_i64();
567 tcg_gen_xor_i64(tmp
, t0
, t1
);
568 tcg_gen_and_i64(flag
, flag
, tmp
);
569 tcg_temp_free_i64(tmp
);
570 tcg_gen_shri_i64(flag
, flag
, 32);
571 tcg_gen_trunc_i64_i32(cpu_VF
, flag
);
572 tcg_gen_mov_i64(dest
, result
);
573 tcg_temp_free_i64(flag
);
574 tcg_temp_free_i64(result
);
576 /* 32 bit arithmetic */
577 TCGv_i32 t0_32
= tcg_temp_new_i32();
578 TCGv_i32 t1_32
= tcg_temp_new_i32();
581 tcg_gen_trunc_i64_i32(t0_32
, t0
);
582 tcg_gen_trunc_i64_i32(t1_32
, t1
);
583 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
584 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
585 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
586 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
587 tmp
= tcg_temp_new_i32();
588 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
589 tcg_temp_free_i32(t0_32
);
590 tcg_temp_free_i32(t1_32
);
591 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
592 tcg_temp_free_i32(tmp
);
593 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
597 /* dest = T0 + T1 + CF; do not compute flags. */
598 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
600 TCGv_i64 flag
= tcg_temp_new_i64();
601 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
602 tcg_gen_add_i64(dest
, t0
, t1
);
603 tcg_gen_add_i64(dest
, dest
, flag
);
604 tcg_temp_free_i64(flag
);
607 tcg_gen_ext32u_i64(dest
, dest
);
611 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
612 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
615 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
616 result
= tcg_temp_new_i64();
617 cf_64
= tcg_temp_new_i64();
618 vf_64
= tcg_temp_new_i64();
619 tmp
= tcg_const_i64(0);
621 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
622 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
623 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
624 tcg_gen_trunc_i64_i32(cpu_CF
, cf_64
);
625 gen_set_NZ64(result
);
627 tcg_gen_xor_i64(vf_64
, result
, t0
);
628 tcg_gen_xor_i64(tmp
, t0
, t1
);
629 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
630 tcg_gen_shri_i64(vf_64
, vf_64
, 32);
631 tcg_gen_trunc_i64_i32(cpu_VF
, vf_64
);
633 tcg_gen_mov_i64(dest
, result
);
635 tcg_temp_free_i64(tmp
);
636 tcg_temp_free_i64(vf_64
);
637 tcg_temp_free_i64(cf_64
);
638 tcg_temp_free_i64(result
);
640 TCGv_i32 t0_32
, t1_32
, tmp
;
641 t0_32
= tcg_temp_new_i32();
642 t1_32
= tcg_temp_new_i32();
643 tmp
= tcg_const_i32(0);
645 tcg_gen_trunc_i64_i32(t0_32
, t0
);
646 tcg_gen_trunc_i64_i32(t1_32
, t1
);
647 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
648 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
650 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
651 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
652 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
653 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
654 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
656 tcg_temp_free_i32(tmp
);
657 tcg_temp_free_i32(t1_32
);
658 tcg_temp_free_i32(t0_32
);
663 * Load/Store generators
667 * Store from GPR register to memory.
669 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
670 TCGv_i64 tcg_addr
, int size
, int memidx
)
673 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, MO_TE
+ size
);
676 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
677 TCGv_i64 tcg_addr
, int size
)
679 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
));
683 * Load from memory to GPR register
685 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
686 int size
, bool is_signed
, bool extend
, int memidx
)
688 TCGMemOp memop
= MO_TE
+ size
;
696 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
698 if (extend
&& is_signed
) {
700 tcg_gen_ext32u_i64(dest
, dest
);
704 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
705 int size
, bool is_signed
, bool extend
)
707 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
712 * Store from FP register to memory
714 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
716 /* This writes the bottom N bits of a 128 bit wide vector to memory */
717 TCGv_i64 tmp
= tcg_temp_new_i64();
718 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
720 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TE
+ size
);
722 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
723 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
724 tcg_gen_qemu_st64(tmp
, tcg_addr
, get_mem_index(s
));
725 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
726 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
727 tcg_gen_qemu_st_i64(tmp
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
728 tcg_temp_free_i64(tcg_hiaddr
);
731 tcg_temp_free_i64(tmp
);
735 * Load from memory to FP register
737 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
739 /* This always zero-extends and writes to a full 128 bit wide vector */
740 TCGv_i64 tmplo
= tcg_temp_new_i64();
744 TCGMemOp memop
= MO_TE
+ size
;
745 tmphi
= tcg_const_i64(0);
746 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
749 tmphi
= tcg_temp_new_i64();
750 tcg_hiaddr
= tcg_temp_new_i64();
752 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), MO_TEQ
);
753 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
754 tcg_gen_qemu_ld_i64(tmphi
, tcg_hiaddr
, get_mem_index(s
), MO_TEQ
);
755 tcg_temp_free_i64(tcg_hiaddr
);
758 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
759 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
761 tcg_temp_free_i64(tmplo
);
762 tcg_temp_free_i64(tmphi
);
766 * Vector load/store helpers.
768 * The principal difference between this and a FP load is that we don't
769 * zero extend as we are filling a partial chunk of the vector register.
770 * These functions don't support 128 bit loads/stores, which would be
771 * normal load/store operations.
773 * The _i32 versions are useful when operating on 32 bit quantities
774 * (eg for floating point single or using Neon helper functions).
777 /* Get value of an element within a vector register */
778 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
779 int element
, TCGMemOp memop
)
781 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
784 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
787 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
790 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
793 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
796 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
799 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
803 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
806 g_assert_not_reached();
810 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
811 int element
, TCGMemOp memop
)
813 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
816 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
819 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
822 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
825 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
829 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
832 g_assert_not_reached();
836 /* Set value of an element within a vector register */
837 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
838 int element
, TCGMemOp memop
)
840 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
843 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
846 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
849 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
852 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
855 g_assert_not_reached();
859 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
860 int destidx
, int element
, TCGMemOp memop
)
862 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
865 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
868 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
871 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
874 g_assert_not_reached();
878 /* Clear the high 64 bits of a 128 bit vector (in general non-quad
879 * vector ops all need to do this).
881 static void clear_vec_high(DisasContext
*s
, int rd
)
883 TCGv_i64 tcg_zero
= tcg_const_i64(0);
885 write_vec_element(s
, tcg_zero
, rd
, 1, MO_64
);
886 tcg_temp_free_i64(tcg_zero
);
889 /* Store from vector register to memory */
890 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
891 TCGv_i64 tcg_addr
, int size
)
893 TCGMemOp memop
= MO_TE
+ size
;
894 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
896 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
897 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
899 tcg_temp_free_i64(tcg_tmp
);
902 /* Load from memory to vector register */
903 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
904 TCGv_i64 tcg_addr
, int size
)
906 TCGMemOp memop
= MO_TE
+ size
;
907 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
909 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), memop
);
910 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
912 tcg_temp_free_i64(tcg_tmp
);
915 /* Check that FP/Neon access is enabled. If it is, return
916 * true. If not, emit code to generate an appropriate exception,
917 * and return false; the caller should not emit any code for
918 * the instruction. Note that this check must happen after all
919 * unallocated-encoding checks (otherwise the syndrome information
920 * for the resulting exception will be incorrect).
922 static inline bool fp_access_check(DisasContext
*s
)
924 assert(!s
->fp_access_checked
);
925 s
->fp_access_checked
= true;
931 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false));
936 * This utility function is for doing register extension with an
937 * optional shift. You will likely want to pass a temporary for the
938 * destination register. See DecodeRegExtend() in the ARM ARM.
940 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
941 int option
, unsigned int shift
)
943 int extsize
= extract32(option
, 0, 2);
944 bool is_signed
= extract32(option
, 2, 1);
949 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
952 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
955 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
958 tcg_gen_mov_i64(tcg_out
, tcg_in
);
964 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
967 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
970 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
973 tcg_gen_mov_i64(tcg_out
, tcg_in
);
979 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
983 static inline void gen_check_sp_alignment(DisasContext
*s
)
985 /* The AArch64 architecture mandates that (if enabled via PSTATE
986 * or SCTLR bits) there is a check that SP is 16-aligned on every
987 * SP-relative load or store (with an exception generated if it is not).
988 * In line with general QEMU practice regarding misaligned accesses,
989 * we omit these checks for the sake of guest program performance.
990 * This function is provided as a hook so we can more easily add these
991 * checks in future (possibly as a "favour catching guest program bugs
992 * over speed" user selectable option).
997 * This provides a simple table based table lookup decoder. It is
998 * intended to be used when the relevant bits for decode are too
999 * awkwardly placed and switch/if based logic would be confusing and
1000 * deeply nested. Since it's a linear search through the table, tables
1001 * should be kept small.
1003 * It returns the first handler where insn & mask == pattern, or
1004 * NULL if there is no match.
1005 * The table is terminated by an empty mask (i.e. 0)
1007 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1010 const AArch64DecodeTable
*tptr
= table
;
1012 while (tptr
->mask
) {
1013 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1014 return tptr
->disas_fn
;
1022 * the instruction disassembly implemented here matches
1023 * the instruction encoding classifications in chapter 3 (C3)
1024 * of the ARM Architecture Reference Manual (DDI0487A_a)
1027 /* C3.2.7 Unconditional branch (immediate)
1029 * +----+-----------+-------------------------------------+
1030 * | op | 0 0 1 0 1 | imm26 |
1031 * +----+-----------+-------------------------------------+
1033 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1035 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1037 if (insn
& (1 << 31)) {
1038 /* C5.6.26 BL Branch with link */
1039 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1042 /* C5.6.20 B Branch / C5.6.26 BL Branch with link */
1043 gen_goto_tb(s
, 0, addr
);
1046 /* C3.2.1 Compare & branch (immediate)
1047 * 31 30 25 24 23 5 4 0
1048 * +----+-------------+----+---------------------+--------+
1049 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1050 * +----+-------------+----+---------------------+--------+
1052 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1054 unsigned int sf
, op
, rt
;
1059 sf
= extract32(insn
, 31, 1);
1060 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1061 rt
= extract32(insn
, 0, 5);
1062 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1064 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1065 label_match
= gen_new_label();
1067 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1068 tcg_cmp
, 0, label_match
);
1070 gen_goto_tb(s
, 0, s
->pc
);
1071 gen_set_label(label_match
);
1072 gen_goto_tb(s
, 1, addr
);
1075 /* C3.2.5 Test & branch (immediate)
1076 * 31 30 25 24 23 19 18 5 4 0
1077 * +----+-------------+----+-------+-------------+------+
1078 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1079 * +----+-------------+----+-------+-------------+------+
1081 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1083 unsigned int bit_pos
, op
, rt
;
1088 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1089 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1090 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1091 rt
= extract32(insn
, 0, 5);
1093 tcg_cmp
= tcg_temp_new_i64();
1094 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1095 label_match
= gen_new_label();
1096 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1097 tcg_cmp
, 0, label_match
);
1098 tcg_temp_free_i64(tcg_cmp
);
1099 gen_goto_tb(s
, 0, s
->pc
);
1100 gen_set_label(label_match
);
1101 gen_goto_tb(s
, 1, addr
);
1104 /* C3.2.2 / C5.6.19 Conditional branch (immediate)
1105 * 31 25 24 23 5 4 3 0
1106 * +---------------+----+---------------------+----+------+
1107 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1108 * +---------------+----+---------------------+----+------+
1110 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1115 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1116 unallocated_encoding(s
);
1119 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1120 cond
= extract32(insn
, 0, 4);
1123 /* genuinely conditional branches */
1124 int label_match
= gen_new_label();
1125 arm_gen_test_cc(cond
, label_match
);
1126 gen_goto_tb(s
, 0, s
->pc
);
1127 gen_set_label(label_match
);
1128 gen_goto_tb(s
, 1, addr
);
1130 /* 0xe and 0xf are both "always" conditions */
1131 gen_goto_tb(s
, 0, addr
);
1136 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1137 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1139 unsigned int selector
= crm
<< 3 | op2
;
1142 unallocated_encoding(s
);
1150 s
->is_jmp
= DISAS_WFI
;
1156 /* we treat all as NOP at least for now */
1159 /* default specified as NOP equivalent */
1164 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1166 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1169 /* CLREX, DSB, DMB, ISB */
1170 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1171 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1174 unallocated_encoding(s
);
1185 /* We don't emulate caches so barriers are no-ops */
1188 unallocated_encoding(s
);
1193 /* C5.6.130 MSR (immediate) - move immediate to processor state field */
1194 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1195 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1197 int op
= op1
<< 3 | op2
;
1199 case 0x05: /* SPSel */
1200 if (s
->current_pl
== 0) {
1201 unallocated_encoding(s
);
1205 case 0x1e: /* DAIFSet */
1206 case 0x1f: /* DAIFClear */
1208 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1209 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1210 gen_a64_set_pc_im(s
->pc
- 4);
1211 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1212 tcg_temp_free_i32(tcg_imm
);
1213 tcg_temp_free_i32(tcg_op
);
1214 s
->is_jmp
= DISAS_UPDATE
;
1218 unallocated_encoding(s
);
1223 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1225 TCGv_i32 tmp
= tcg_temp_new_i32();
1226 TCGv_i32 nzcv
= tcg_temp_new_i32();
1228 /* build bit 31, N */
1229 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1 << 31));
1230 /* build bit 30, Z */
1231 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1232 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1233 /* build bit 29, C */
1234 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1235 /* build bit 28, V */
1236 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1237 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1238 /* generate result */
1239 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1241 tcg_temp_free_i32(nzcv
);
1242 tcg_temp_free_i32(tmp
);
1245 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1248 TCGv_i32 nzcv
= tcg_temp_new_i32();
1250 /* take NZCV from R[t] */
1251 tcg_gen_trunc_i64_i32(nzcv
, tcg_rt
);
1254 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1 << 31));
1256 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1257 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1259 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1260 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1262 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1263 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1264 tcg_temp_free_i32(nzcv
);
1267 /* C5.6.129 MRS - move from system register
1268 * C5.6.131 MSR (register) - move to system register
1271 * These are all essentially the same insn in 'read' and 'write'
1272 * versions, with varying op0 fields.
1274 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1275 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1276 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1278 const ARMCPRegInfo
*ri
;
1281 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1282 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1283 crn
, crm
, op0
, op1
, op2
));
1286 /* Unknown register; this might be a guest error or a QEMU
1287 * unimplemented feature.
1289 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1290 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1291 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1292 unallocated_encoding(s
);
1296 /* Check access permissions */
1297 if (!cp_access_ok(s
->current_pl
, ri
, isread
)) {
1298 unallocated_encoding(s
);
1303 /* Emit code to perform further access permissions checks at
1304 * runtime; this may result in an exception.
1310 gen_a64_set_pc_im(s
->pc
- 4);
1311 tmpptr
= tcg_const_ptr(ri
);
1312 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1313 tcg_syn
= tcg_const_i32(syndrome
);
1314 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
);
1315 tcg_temp_free_ptr(tmpptr
);
1316 tcg_temp_free_i32(tcg_syn
);
1319 /* Handle special cases first */
1320 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1324 tcg_rt
= cpu_reg(s
, rt
);
1326 gen_get_nzcv(tcg_rt
);
1328 gen_set_nzcv(tcg_rt
);
1331 case ARM_CP_CURRENTEL
:
1332 /* Reads as current EL value from pstate, which is
1333 * guaranteed to be constant by the tb flags.
1335 tcg_rt
= cpu_reg(s
, rt
);
1336 tcg_gen_movi_i64(tcg_rt
, s
->current_pl
<< 2);
1339 /* Writes clear the aligned block of memory which rt points into. */
1340 tcg_rt
= cpu_reg(s
, rt
);
1341 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1347 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1351 tcg_rt
= cpu_reg(s
, rt
);
1354 if (ri
->type
& ARM_CP_CONST
) {
1355 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1356 } else if (ri
->readfn
) {
1358 tmpptr
= tcg_const_ptr(ri
);
1359 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1360 tcg_temp_free_ptr(tmpptr
);
1362 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1365 if (ri
->type
& ARM_CP_CONST
) {
1366 /* If not forbidden by access permissions, treat as WI */
1368 } else if (ri
->writefn
) {
1370 tmpptr
= tcg_const_ptr(ri
);
1371 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1372 tcg_temp_free_ptr(tmpptr
);
1374 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1378 if (use_icount
&& (ri
->type
& ARM_CP_IO
)) {
1379 /* I/O operations must end the TB here (whether read or write) */
1381 s
->is_jmp
= DISAS_UPDATE
;
1382 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1383 /* We default to ending the TB on a coprocessor register write,
1384 * but allow this to be suppressed by the register definition
1385 * (usually only necessary to work around guest bugs).
1387 s
->is_jmp
= DISAS_UPDATE
;
1392 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1393 * +---------------------+---+-----+-----+-------+-------+-----+------+
1394 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1395 * +---------------------+---+-----+-----+-------+-------+-----+------+
1397 static void disas_system(DisasContext
*s
, uint32_t insn
)
1399 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1400 l
= extract32(insn
, 21, 1);
1401 op0
= extract32(insn
, 19, 2);
1402 op1
= extract32(insn
, 16, 3);
1403 crn
= extract32(insn
, 12, 4);
1404 crm
= extract32(insn
, 8, 4);
1405 op2
= extract32(insn
, 5, 3);
1406 rt
= extract32(insn
, 0, 5);
1409 if (l
|| rt
!= 31) {
1410 unallocated_encoding(s
);
1414 case 2: /* C5.6.68 HINT */
1415 handle_hint(s
, insn
, op1
, op2
, crm
);
1417 case 3: /* CLREX, DSB, DMB, ISB */
1418 handle_sync(s
, insn
, op1
, op2
, crm
);
1420 case 4: /* C5.6.130 MSR (immediate) */
1421 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1424 unallocated_encoding(s
);
1429 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1432 /* C3.2.3 Exception generation
1434 * 31 24 23 21 20 5 4 2 1 0
1435 * +-----------------+-----+------------------------+-----+----+
1436 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1437 * +-----------------------+------------------------+----------+
1439 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1441 int opc
= extract32(insn
, 21, 3);
1442 int op2_ll
= extract32(insn
, 0, 5);
1443 int imm16
= extract32(insn
, 5, 16);
1447 /* SVC, HVC, SMC; since we don't support the Virtualization
1448 * or TrustZone extensions these all UNDEF except SVC.
1451 unallocated_encoding(s
);
1454 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
));
1458 unallocated_encoding(s
);
1462 gen_exception_insn(s
, 0, EXCP_BKPT
, syn_aa64_bkpt(imm16
));
1466 unallocated_encoding(s
);
1470 unsupported_encoding(s
, insn
);
1473 if (op2_ll
< 1 || op2_ll
> 3) {
1474 unallocated_encoding(s
);
1477 /* DCPS1, DCPS2, DCPS3 */
1478 unsupported_encoding(s
, insn
);
1481 unallocated_encoding(s
);
1486 /* C3.2.7 Unconditional branch (register)
1487 * 31 25 24 21 20 16 15 10 9 5 4 0
1488 * +---------------+-------+-------+-------+------+-------+
1489 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1490 * +---------------+-------+-------+-------+------+-------+
1492 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1494 unsigned int opc
, op2
, op3
, rn
, op4
;
1496 opc
= extract32(insn
, 21, 4);
1497 op2
= extract32(insn
, 16, 5);
1498 op3
= extract32(insn
, 10, 6);
1499 rn
= extract32(insn
, 5, 5);
1500 op4
= extract32(insn
, 0, 5);
1502 if (op4
!= 0x0 || op3
!= 0x0 || op2
!= 0x1f) {
1503 unallocated_encoding(s
);
1512 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1517 unallocated_encoding(s
);
1519 unsupported_encoding(s
, insn
);
1523 unallocated_encoding(s
);
1527 tcg_gen_mov_i64(cpu_pc
, cpu_reg(s
, rn
));
1528 s
->is_jmp
= DISAS_JUMP
;
1531 /* C3.2 Branches, exception generating and system instructions */
1532 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
1534 switch (extract32(insn
, 25, 7)) {
1535 case 0x0a: case 0x0b:
1536 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1537 disas_uncond_b_imm(s
, insn
);
1539 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1540 disas_comp_b_imm(s
, insn
);
1542 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1543 disas_test_b_imm(s
, insn
);
1545 case 0x2a: /* Conditional branch (immediate) */
1546 disas_cond_b_imm(s
, insn
);
1548 case 0x6a: /* Exception generation / System */
1549 if (insn
& (1 << 24)) {
1550 disas_system(s
, insn
);
1555 case 0x6b: /* Unconditional branch (register) */
1556 disas_uncond_b_reg(s
, insn
);
1559 unallocated_encoding(s
);
1565 * Load/Store exclusive instructions are implemented by remembering
1566 * the value/address loaded, and seeing if these are the same
1567 * when the store is performed. This is not actually the architecturally
1568 * mandated semantics, but it works for typical guest code sequences
1569 * and avoids having to monitor regular stores.
1571 * In system emulation mode only one CPU will be running at once, so
1572 * this sequence is effectively atomic. In user emulation mode we
1573 * throw an exception and handle the atomic operation elsewhere.
1575 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
1576 TCGv_i64 addr
, int size
, bool is_pair
)
1578 TCGv_i64 tmp
= tcg_temp_new_i64();
1579 TCGMemOp memop
= MO_TE
+ size
;
1581 g_assert(size
<= 3);
1582 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), memop
);
1585 TCGv_i64 addr2
= tcg_temp_new_i64();
1586 TCGv_i64 hitmp
= tcg_temp_new_i64();
1588 g_assert(size
>= 2);
1589 tcg_gen_addi_i64(addr2
, addr
, 1 << size
);
1590 tcg_gen_qemu_ld_i64(hitmp
, addr2
, get_mem_index(s
), memop
);
1591 tcg_temp_free_i64(addr2
);
1592 tcg_gen_mov_i64(cpu_exclusive_high
, hitmp
);
1593 tcg_gen_mov_i64(cpu_reg(s
, rt2
), hitmp
);
1594 tcg_temp_free_i64(hitmp
);
1597 tcg_gen_mov_i64(cpu_exclusive_val
, tmp
);
1598 tcg_gen_mov_i64(cpu_reg(s
, rt
), tmp
);
1600 tcg_temp_free_i64(tmp
);
1601 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
1604 #ifdef CONFIG_USER_ONLY
1605 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1606 TCGv_i64 addr
, int size
, int is_pair
)
1608 tcg_gen_mov_i64(cpu_exclusive_test
, addr
);
1609 tcg_gen_movi_i32(cpu_exclusive_info
,
1610 size
| is_pair
<< 2 | (rd
<< 4) | (rt
<< 9) | (rt2
<< 14));
1611 gen_exception_internal_insn(s
, 4, EXCP_STREX
);
1614 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
1615 TCGv_i64 inaddr
, int size
, int is_pair
)
1617 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1618 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1621 * [addr + datasize] = {Rt2};
1627 * env->exclusive_addr = -1;
1629 int fail_label
= gen_new_label();
1630 int done_label
= gen_new_label();
1631 TCGv_i64 addr
= tcg_temp_local_new_i64();
1634 /* Copy input into a local temp so it is not trashed when the
1635 * basic block ends at the branch insn.
1637 tcg_gen_mov_i64(addr
, inaddr
);
1638 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
1640 tmp
= tcg_temp_new_i64();
1641 tcg_gen_qemu_ld_i64(tmp
, addr
, get_mem_index(s
), MO_TE
+ size
);
1642 tcg_gen_brcond_i64(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
1643 tcg_temp_free_i64(tmp
);
1646 TCGv_i64 addrhi
= tcg_temp_new_i64();
1647 TCGv_i64 tmphi
= tcg_temp_new_i64();
1649 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1650 tcg_gen_qemu_ld_i64(tmphi
, addrhi
, get_mem_index(s
), MO_TE
+ size
);
1651 tcg_gen_brcond_i64(TCG_COND_NE
, tmphi
, cpu_exclusive_high
, fail_label
);
1653 tcg_temp_free_i64(tmphi
);
1654 tcg_temp_free_i64(addrhi
);
1657 /* We seem to still have the exclusive monitor, so do the store */
1658 tcg_gen_qemu_st_i64(cpu_reg(s
, rt
), addr
, get_mem_index(s
), MO_TE
+ size
);
1660 TCGv_i64 addrhi
= tcg_temp_new_i64();
1662 tcg_gen_addi_i64(addrhi
, addr
, 1 << size
);
1663 tcg_gen_qemu_st_i64(cpu_reg(s
, rt2
), addrhi
,
1664 get_mem_index(s
), MO_TE
+ size
);
1665 tcg_temp_free_i64(addrhi
);
1668 tcg_temp_free_i64(addr
);
1670 tcg_gen_movi_i64(cpu_reg(s
, rd
), 0);
1671 tcg_gen_br(done_label
);
1672 gen_set_label(fail_label
);
1673 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
1674 gen_set_label(done_label
);
1675 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1680 /* C3.3.6 Load/store exclusive
1682 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
1683 * +-----+-------------+----+---+----+------+----+-------+------+------+
1684 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
1685 * +-----+-------------+----+---+----+------+----+-------+------+------+
1687 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
1688 * L: 0 -> store, 1 -> load
1689 * o2: 0 -> exclusive, 1 -> not
1690 * o1: 0 -> single register, 1 -> register pair
1691 * o0: 1 -> load-acquire/store-release, 0 -> not
1693 * o0 == 0 AND o2 == 1 is un-allocated
1694 * o1 == 1 is un-allocated except for 32 and 64 bit sizes
1696 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
1698 int rt
= extract32(insn
, 0, 5);
1699 int rn
= extract32(insn
, 5, 5);
1700 int rt2
= extract32(insn
, 10, 5);
1701 int is_lasr
= extract32(insn
, 15, 1);
1702 int rs
= extract32(insn
, 16, 5);
1703 int is_pair
= extract32(insn
, 21, 1);
1704 int is_store
= !extract32(insn
, 22, 1);
1705 int is_excl
= !extract32(insn
, 23, 1);
1706 int size
= extract32(insn
, 30, 2);
1709 if ((!is_excl
&& !is_lasr
) ||
1710 (is_pair
&& size
< 2)) {
1711 unallocated_encoding(s
);
1716 gen_check_sp_alignment(s
);
1718 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1720 /* Note that since TCG is single threaded load-acquire/store-release
1721 * semantics require no extra if (is_lasr) { ... } handling.
1726 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1728 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, is_pair
);
1731 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1733 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1735 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, false, false);
1738 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt
);
1739 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1741 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1743 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, false, false);
1750 * C3.3.5 Load register (literal)
1752 * 31 30 29 27 26 25 24 23 5 4 0
1753 * +-----+-------+---+-----+-------------------+-------+
1754 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
1755 * +-----+-------+---+-----+-------------------+-------+
1757 * V: 1 -> vector (simd/fp)
1758 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
1759 * 10-> 32 bit signed, 11 -> prefetch
1760 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
1762 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
1764 int rt
= extract32(insn
, 0, 5);
1765 int64_t imm
= sextract32(insn
, 5, 19) << 2;
1766 bool is_vector
= extract32(insn
, 26, 1);
1767 int opc
= extract32(insn
, 30, 2);
1768 bool is_signed
= false;
1770 TCGv_i64 tcg_rt
, tcg_addr
;
1774 unallocated_encoding(s
);
1778 if (!fp_access_check(s
)) {
1783 /* PRFM (literal) : prefetch */
1786 size
= 2 + extract32(opc
, 0, 1);
1787 is_signed
= extract32(opc
, 1, 1);
1790 tcg_rt
= cpu_reg(s
, rt
);
1792 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
1794 do_fp_ld(s
, rt
, tcg_addr
, size
);
1796 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1798 tcg_temp_free_i64(tcg_addr
);
1802 * C5.6.80 LDNP (Load Pair - non-temporal hint)
1803 * C5.6.81 LDP (Load Pair - non vector)
1804 * C5.6.82 LDPSW (Load Pair Signed Word - non vector)
1805 * C5.6.176 STNP (Store Pair - non-temporal hint)
1806 * C5.6.177 STP (Store Pair - non vector)
1807 * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint)
1808 * C6.3.165 LDP (Load Pair of SIMD&FP)
1809 * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint)
1810 * C6.3.284 STP (Store Pair of SIMD&FP)
1812 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
1813 * +-----+-------+---+---+-------+---+-----------------------------+
1814 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
1815 * +-----+-------+---+---+-------+---+-------+-------+------+------+
1817 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
1819 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
1820 * V: 0 -> GPR, 1 -> Vector
1821 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
1822 * 10 -> signed offset, 11 -> pre-index
1823 * L: 0 -> Store 1 -> Load
1825 * Rt, Rt2 = GPR or SIMD registers to be stored
1826 * Rn = general purpose register containing address
1827 * imm7 = signed offset (multiple of 4 or 8 depending on size)
1829 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
1831 int rt
= extract32(insn
, 0, 5);
1832 int rn
= extract32(insn
, 5, 5);
1833 int rt2
= extract32(insn
, 10, 5);
1834 int64_t offset
= sextract32(insn
, 15, 7);
1835 int index
= extract32(insn
, 23, 2);
1836 bool is_vector
= extract32(insn
, 26, 1);
1837 bool is_load
= extract32(insn
, 22, 1);
1838 int opc
= extract32(insn
, 30, 2);
1840 bool is_signed
= false;
1841 bool postindex
= false;
1844 TCGv_i64 tcg_addr
; /* calculated address */
1848 unallocated_encoding(s
);
1855 size
= 2 + extract32(opc
, 1, 1);
1856 is_signed
= extract32(opc
, 0, 1);
1857 if (!is_load
&& is_signed
) {
1858 unallocated_encoding(s
);
1864 case 1: /* post-index */
1869 /* signed offset with "non-temporal" hint. Since we don't emulate
1870 * caches we don't care about hints to the cache system about
1871 * data access patterns, and handle this identically to plain
1875 /* There is no non-temporal-hint version of LDPSW */
1876 unallocated_encoding(s
);
1881 case 2: /* signed offset, rn not updated */
1884 case 3: /* pre-index */
1890 if (is_vector
&& !fp_access_check(s
)) {
1897 gen_check_sp_alignment(s
);
1900 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
1903 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
1908 do_fp_ld(s
, rt
, tcg_addr
, size
);
1910 do_fp_st(s
, rt
, tcg_addr
, size
);
1913 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
1915 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false);
1917 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
1920 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1923 do_fp_ld(s
, rt2
, tcg_addr
, size
);
1925 do_fp_st(s
, rt2
, tcg_addr
, size
);
1928 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
1930 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false);
1932 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
);
1938 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
1940 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
1942 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
1947 * C3.3.8 Load/store (immediate post-indexed)
1948 * C3.3.9 Load/store (immediate pre-indexed)
1949 * C3.3.12 Load/store (unscaled immediate)
1951 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
1952 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1953 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
1954 * +----+-------+---+-----+-----+---+--------+-----+------+------+
1956 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
1958 * V = 0 -> non-vector
1959 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
1960 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
1962 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
)
1964 int rt
= extract32(insn
, 0, 5);
1965 int rn
= extract32(insn
, 5, 5);
1966 int imm9
= sextract32(insn
, 12, 9);
1967 int opc
= extract32(insn
, 22, 2);
1968 int size
= extract32(insn
, 30, 2);
1969 int idx
= extract32(insn
, 10, 2);
1970 bool is_signed
= false;
1971 bool is_store
= false;
1972 bool is_extended
= false;
1973 bool is_unpriv
= (idx
== 2);
1974 bool is_vector
= extract32(insn
, 26, 1);
1981 size
|= (opc
& 2) << 1;
1982 if (size
> 4 || is_unpriv
) {
1983 unallocated_encoding(s
);
1986 is_store
= ((opc
& 1) == 0);
1987 if (!fp_access_check(s
)) {
1991 if (size
== 3 && opc
== 2) {
1992 /* PRFM - prefetch */
1994 unallocated_encoding(s
);
1999 if (opc
== 3 && size
> 1) {
2000 unallocated_encoding(s
);
2003 is_store
= (opc
== 0);
2004 is_signed
= opc
& (1<<1);
2005 is_extended
= (size
< 3) && (opc
& 1);
2025 gen_check_sp_alignment(s
);
2027 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2030 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2035 do_fp_st(s
, rt
, tcg_addr
, size
);
2037 do_fp_ld(s
, rt
, tcg_addr
, size
);
2040 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2041 int memidx
= is_unpriv
? 1 : get_mem_index(s
);
2044 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
);
2046 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2047 is_signed
, is_extended
, memidx
);
2052 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2054 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2056 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2061 * C3.3.10 Load/store (register offset)
2063 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2064 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2065 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2066 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2069 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2070 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2072 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2073 * opc<0>: 0 -> store, 1 -> load
2074 * V: 1 -> vector/simd
2075 * opt: extend encoding (see DecodeRegExtend)
2076 * S: if S=1 then scale (essentially index by sizeof(size))
2077 * Rt: register to transfer into/out of
2078 * Rn: address register or SP for base
2079 * Rm: offset register or ZR for offset
2081 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
)
2083 int rt
= extract32(insn
, 0, 5);
2084 int rn
= extract32(insn
, 5, 5);
2085 int shift
= extract32(insn
, 12, 1);
2086 int rm
= extract32(insn
, 16, 5);
2087 int opc
= extract32(insn
, 22, 2);
2088 int opt
= extract32(insn
, 13, 3);
2089 int size
= extract32(insn
, 30, 2);
2090 bool is_signed
= false;
2091 bool is_store
= false;
2092 bool is_extended
= false;
2093 bool is_vector
= extract32(insn
, 26, 1);
2098 if (extract32(opt
, 1, 1) == 0) {
2099 unallocated_encoding(s
);
2104 size
|= (opc
& 2) << 1;
2106 unallocated_encoding(s
);
2109 is_store
= !extract32(opc
, 0, 1);
2110 if (!fp_access_check(s
)) {
2114 if (size
== 3 && opc
== 2) {
2115 /* PRFM - prefetch */
2118 if (opc
== 3 && size
> 1) {
2119 unallocated_encoding(s
);
2122 is_store
= (opc
== 0);
2123 is_signed
= extract32(opc
, 1, 1);
2124 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2128 gen_check_sp_alignment(s
);
2130 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2132 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2133 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2135 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
2139 do_fp_st(s
, rt
, tcg_addr
, size
);
2141 do_fp_ld(s
, rt
, tcg_addr
, size
);
2144 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2146 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2148 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2154 * C3.3.13 Load/store (unsigned immediate)
2156 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2157 * +----+-------+---+-----+-----+------------+-------+------+
2158 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2159 * +----+-------+---+-----+-----+------------+-------+------+
2162 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2163 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2165 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2166 * opc<0>: 0 -> store, 1 -> load
2167 * Rn: base address register (inc SP)
2168 * Rt: target register
2170 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
)
2172 int rt
= extract32(insn
, 0, 5);
2173 int rn
= extract32(insn
, 5, 5);
2174 unsigned int imm12
= extract32(insn
, 10, 12);
2175 bool is_vector
= extract32(insn
, 26, 1);
2176 int size
= extract32(insn
, 30, 2);
2177 int opc
= extract32(insn
, 22, 2);
2178 unsigned int offset
;
2183 bool is_signed
= false;
2184 bool is_extended
= false;
2187 size
|= (opc
& 2) << 1;
2189 unallocated_encoding(s
);
2192 is_store
= !extract32(opc
, 0, 1);
2193 if (!fp_access_check(s
)) {
2197 if (size
== 3 && opc
== 2) {
2198 /* PRFM - prefetch */
2201 if (opc
== 3 && size
> 1) {
2202 unallocated_encoding(s
);
2205 is_store
= (opc
== 0);
2206 is_signed
= extract32(opc
, 1, 1);
2207 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2211 gen_check_sp_alignment(s
);
2213 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2214 offset
= imm12
<< size
;
2215 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2219 do_fp_st(s
, rt
, tcg_addr
, size
);
2221 do_fp_ld(s
, rt
, tcg_addr
, size
);
2224 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2226 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
);
2228 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
);
2233 /* Load/store register (all forms) */
2234 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
2236 switch (extract32(insn
, 24, 2)) {
2238 if (extract32(insn
, 21, 1) == 1 && extract32(insn
, 10, 2) == 2) {
2239 disas_ldst_reg_roffset(s
, insn
);
2241 /* Load/store register (unscaled immediate)
2242 * Load/store immediate pre/post-indexed
2243 * Load/store register unprivileged
2245 disas_ldst_reg_imm9(s
, insn
);
2249 disas_ldst_reg_unsigned_imm(s
, insn
);
2252 unallocated_encoding(s
);
2257 /* C3.3.1 AdvSIMD load/store multiple structures
2259 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2260 * +---+---+---------------+---+-------------+--------+------+------+------+
2261 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2262 * +---+---+---------------+---+-------------+--------+------+------+------+
2264 * C3.3.2 AdvSIMD load/store multiple structures (post-indexed)
2266 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2267 * +---+---+---------------+---+---+---------+--------+------+------+------+
2268 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2269 * +---+---+---------------+---+---+---------+--------+------+------+------+
2271 * Rt: first (or only) SIMD&FP register to be transferred
2272 * Rn: base address or SP
2273 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2275 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
2277 int rt
= extract32(insn
, 0, 5);
2278 int rn
= extract32(insn
, 5, 5);
2279 int size
= extract32(insn
, 10, 2);
2280 int opcode
= extract32(insn
, 12, 4);
2281 bool is_store
= !extract32(insn
, 22, 1);
2282 bool is_postidx
= extract32(insn
, 23, 1);
2283 bool is_q
= extract32(insn
, 30, 1);
2284 TCGv_i64 tcg_addr
, tcg_rn
;
2286 int ebytes
= 1 << size
;
2287 int elements
= (is_q
? 128 : 64) / (8 << size
);
2288 int rpt
; /* num iterations */
2289 int selem
; /* structure elements */
2292 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
2293 unallocated_encoding(s
);
2297 /* From the shared decode logic */
2328 unallocated_encoding(s
);
2332 if (size
== 3 && !is_q
&& selem
!= 1) {
2334 unallocated_encoding(s
);
2338 if (!fp_access_check(s
)) {
2343 gen_check_sp_alignment(s
);
2346 tcg_rn
= cpu_reg_sp(s
, rn
);
2347 tcg_addr
= tcg_temp_new_i64();
2348 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2350 for (r
= 0; r
< rpt
; r
++) {
2352 for (e
= 0; e
< elements
; e
++) {
2353 int tt
= (rt
+ r
) % 32;
2355 for (xs
= 0; xs
< selem
; xs
++) {
2357 do_vec_st(s
, tt
, e
, tcg_addr
, size
);
2359 do_vec_ld(s
, tt
, e
, tcg_addr
, size
);
2361 /* For non-quad operations, setting a slice of the low
2362 * 64 bits of the register clears the high 64 bits (in
2363 * the ARM ARM pseudocode this is implicit in the fact
2364 * that 'rval' is a 64 bit wide variable). We optimize
2365 * by noticing that we only need to do this the first
2366 * time we touch a register.
2368 if (!is_q
&& e
== 0 && (r
== 0 || xs
== selem
- 1)) {
2369 clear_vec_high(s
, tt
);
2372 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2379 int rm
= extract32(insn
, 16, 5);
2381 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2383 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2386 tcg_temp_free_i64(tcg_addr
);
2389 /* C3.3.3 AdvSIMD load/store single structure
2391 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2392 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2393 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
2394 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2396 * C3.3.4 AdvSIMD load/store single structure (post-indexed)
2398 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2399 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2400 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
2401 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
2403 * Rt: first (or only) SIMD&FP register to be transferred
2404 * Rn: base address or SP
2405 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2406 * index = encoded in Q:S:size dependent on size
2408 * lane_size = encoded in R, opc
2409 * transfer width = encoded in opc, S, size
2411 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
2413 int rt
= extract32(insn
, 0, 5);
2414 int rn
= extract32(insn
, 5, 5);
2415 int size
= extract32(insn
, 10, 2);
2416 int S
= extract32(insn
, 12, 1);
2417 int opc
= extract32(insn
, 13, 3);
2418 int R
= extract32(insn
, 21, 1);
2419 int is_load
= extract32(insn
, 22, 1);
2420 int is_postidx
= extract32(insn
, 23, 1);
2421 int is_q
= extract32(insn
, 30, 1);
2423 int scale
= extract32(opc
, 1, 2);
2424 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
2425 bool replicate
= false;
2426 int index
= is_q
<< 3 | S
<< 2 | size
;
2428 TCGv_i64 tcg_addr
, tcg_rn
;
2432 if (!is_load
|| S
) {
2433 unallocated_encoding(s
);
2442 if (extract32(size
, 0, 1)) {
2443 unallocated_encoding(s
);
2449 if (extract32(size
, 1, 1)) {
2450 unallocated_encoding(s
);
2453 if (!extract32(size
, 0, 1)) {
2457 unallocated_encoding(s
);
2465 g_assert_not_reached();
2468 if (!fp_access_check(s
)) {
2472 ebytes
= 1 << scale
;
2475 gen_check_sp_alignment(s
);
2478 tcg_rn
= cpu_reg_sp(s
, rn
);
2479 tcg_addr
= tcg_temp_new_i64();
2480 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
2482 for (xs
= 0; xs
< selem
; xs
++) {
2484 /* Load and replicate to all elements */
2486 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
2488 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
2489 get_mem_index(s
), MO_TE
+ scale
);
2492 mulconst
= 0x0101010101010101ULL
;
2495 mulconst
= 0x0001000100010001ULL
;
2498 mulconst
= 0x0000000100000001ULL
;
2504 g_assert_not_reached();
2507 tcg_gen_muli_i64(tcg_tmp
, tcg_tmp
, mulconst
);
2509 write_vec_element(s
, tcg_tmp
, rt
, 0, MO_64
);
2511 write_vec_element(s
, tcg_tmp
, rt
, 1, MO_64
);
2513 clear_vec_high(s
, rt
);
2515 tcg_temp_free_i64(tcg_tmp
);
2517 /* Load/store one element per register */
2519 do_vec_ld(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2521 do_vec_st(s
, rt
, index
, tcg_addr
, MO_TE
+ scale
);
2524 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, ebytes
);
2529 int rm
= extract32(insn
, 16, 5);
2531 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2533 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
2536 tcg_temp_free_i64(tcg_addr
);
2539 /* C3.3 Loads and stores */
2540 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
2542 switch (extract32(insn
, 24, 6)) {
2543 case 0x08: /* Load/store exclusive */
2544 disas_ldst_excl(s
, insn
);
2546 case 0x18: case 0x1c: /* Load register (literal) */
2547 disas_ld_lit(s
, insn
);
2549 case 0x28: case 0x29:
2550 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
2551 disas_ldst_pair(s
, insn
);
2553 case 0x38: case 0x39:
2554 case 0x3c: case 0x3d: /* Load/store register (all forms) */
2555 disas_ldst_reg(s
, insn
);
2557 case 0x0c: /* AdvSIMD load/store multiple structures */
2558 disas_ldst_multiple_struct(s
, insn
);
2560 case 0x0d: /* AdvSIMD load/store single structure */
2561 disas_ldst_single_struct(s
, insn
);
2564 unallocated_encoding(s
);
2569 /* C3.4.6 PC-rel. addressing
2570 * 31 30 29 28 24 23 5 4 0
2571 * +----+-------+-----------+-------------------+------+
2572 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
2573 * +----+-------+-----------+-------------------+------+
2575 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
2577 unsigned int page
, rd
;
2581 page
= extract32(insn
, 31, 1);
2582 /* SignExtend(immhi:immlo) -> offset */
2583 offset
= ((int64_t)sextract32(insn
, 5, 19) << 2) | extract32(insn
, 29, 2);
2584 rd
= extract32(insn
, 0, 5);
2588 /* ADRP (page based) */
2593 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
2597 * C3.4.1 Add/subtract (immediate)
2599 * 31 30 29 28 24 23 22 21 10 9 5 4 0
2600 * +--+--+--+-----------+-----+-------------+-----+-----+
2601 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
2602 * +--+--+--+-----------+-----+-------------+-----+-----+
2604 * sf: 0 -> 32bit, 1 -> 64bit
2605 * op: 0 -> add , 1 -> sub
2607 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
2609 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
2611 int rd
= extract32(insn
, 0, 5);
2612 int rn
= extract32(insn
, 5, 5);
2613 uint64_t imm
= extract32(insn
, 10, 12);
2614 int shift
= extract32(insn
, 22, 2);
2615 bool setflags
= extract32(insn
, 29, 1);
2616 bool sub_op
= extract32(insn
, 30, 1);
2617 bool is_64bit
= extract32(insn
, 31, 1);
2619 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2620 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
2621 TCGv_i64 tcg_result
;
2630 unallocated_encoding(s
);
2634 tcg_result
= tcg_temp_new_i64();
2637 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
2639 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
2642 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
2644 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2646 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
2648 tcg_temp_free_i64(tcg_imm
);
2652 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
2654 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
2657 tcg_temp_free_i64(tcg_result
);
2660 /* The input should be a value in the bottom e bits (with higher
2661 * bits zero); returns that value replicated into every element
2662 * of size e in a 64 bit integer.
2664 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
2674 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
2675 static inline uint64_t bitmask64(unsigned int length
)
2677 assert(length
> 0 && length
<= 64);
2678 return ~0ULL >> (64 - length
);
2681 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
2682 * only require the wmask. Returns false if the imms/immr/immn are a reserved
2683 * value (ie should cause a guest UNDEF exception), and true if they are
2684 * valid, in which case the decoded bit pattern is written to result.
2686 static bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
2687 unsigned int imms
, unsigned int immr
)
2690 unsigned e
, levels
, s
, r
;
2693 assert(immn
< 2 && imms
< 64 && immr
< 64);
2695 /* The bit patterns we create here are 64 bit patterns which
2696 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
2697 * 64 bits each. Each element contains the same value: a run
2698 * of between 1 and e-1 non-zero bits, rotated within the
2699 * element by between 0 and e-1 bits.
2701 * The element size and run length are encoded into immn (1 bit)
2702 * and imms (6 bits) as follows:
2703 * 64 bit elements: immn = 1, imms = <length of run - 1>
2704 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
2705 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
2706 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
2707 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
2708 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
2709 * Notice that immn = 0, imms = 11111x is the only combination
2710 * not covered by one of the above options; this is reserved.
2711 * Further, <length of run - 1> all-ones is a reserved pattern.
2713 * In all cases the rotation is by immr % e (and immr is 6 bits).
2716 /* First determine the element size */
2717 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
2719 /* This is the immn == 0, imms == 0x11111x case */
2729 /* <length of run - 1> mustn't be all-ones. */
2733 /* Create the value of one element: s+1 set bits rotated
2734 * by r within the element (which is e bits wide)...
2736 mask
= bitmask64(s
+ 1);
2737 mask
= (mask
>> r
) | (mask
<< (e
- r
));
2738 /* ...then replicate the element over the whole 64 bit value */
2739 mask
= bitfield_replicate(mask
, e
);
2744 /* C3.4.4 Logical (immediate)
2745 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2746 * +----+-----+-------------+---+------+------+------+------+
2747 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
2748 * +----+-----+-------------+---+------+------+------+------+
2750 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
2752 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
2753 TCGv_i64 tcg_rd
, tcg_rn
;
2755 bool is_and
= false;
2757 sf
= extract32(insn
, 31, 1);
2758 opc
= extract32(insn
, 29, 2);
2759 is_n
= extract32(insn
, 22, 1);
2760 immr
= extract32(insn
, 16, 6);
2761 imms
= extract32(insn
, 10, 6);
2762 rn
= extract32(insn
, 5, 5);
2763 rd
= extract32(insn
, 0, 5);
2766 unallocated_encoding(s
);
2770 if (opc
== 0x3) { /* ANDS */
2771 tcg_rd
= cpu_reg(s
, rd
);
2773 tcg_rd
= cpu_reg_sp(s
, rd
);
2775 tcg_rn
= cpu_reg(s
, rn
);
2777 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
2778 /* some immediate field values are reserved */
2779 unallocated_encoding(s
);
2784 wmask
&= 0xffffffff;
2788 case 0x3: /* ANDS */
2790 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
2794 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
2797 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
2800 assert(FALSE
); /* must handle all above */
2804 if (!sf
&& !is_and
) {
2805 /* zero extend final result; we know we can skip this for AND
2806 * since the immediate had the high 32 bits clear.
2808 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2811 if (opc
== 3) { /* ANDS */
2812 gen_logic_CC(sf
, tcg_rd
);
2817 * C3.4.5 Move wide (immediate)
2819 * 31 30 29 28 23 22 21 20 5 4 0
2820 * +--+-----+-------------+-----+----------------+------+
2821 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
2822 * +--+-----+-------------+-----+----------------+------+
2824 * sf: 0 -> 32 bit, 1 -> 64 bit
2825 * opc: 00 -> N, 10 -> Z, 11 -> K
2826 * hw: shift/16 (0,16, and sf only 32, 48)
2828 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
2830 int rd
= extract32(insn
, 0, 5);
2831 uint64_t imm
= extract32(insn
, 5, 16);
2832 int sf
= extract32(insn
, 31, 1);
2833 int opc
= extract32(insn
, 29, 2);
2834 int pos
= extract32(insn
, 21, 2) << 4;
2835 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
2838 if (!sf
&& (pos
>= 32)) {
2839 unallocated_encoding(s
);
2853 tcg_gen_movi_i64(tcg_rd
, imm
);
2856 tcg_imm
= tcg_const_i64(imm
);
2857 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
2858 tcg_temp_free_i64(tcg_imm
);
2860 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2864 unallocated_encoding(s
);
2870 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
2871 * +----+-----+-------------+---+------+------+------+------+
2872 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
2873 * +----+-----+-------------+---+------+------+------+------+
2875 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
2877 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
2878 TCGv_i64 tcg_rd
, tcg_tmp
;
2880 sf
= extract32(insn
, 31, 1);
2881 opc
= extract32(insn
, 29, 2);
2882 n
= extract32(insn
, 22, 1);
2883 ri
= extract32(insn
, 16, 6);
2884 si
= extract32(insn
, 10, 6);
2885 rn
= extract32(insn
, 5, 5);
2886 rd
= extract32(insn
, 0, 5);
2887 bitsize
= sf
? 64 : 32;
2889 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
2890 unallocated_encoding(s
);
2894 tcg_rd
= cpu_reg(s
, rd
);
2895 tcg_tmp
= read_cpu_reg(s
, rn
, sf
);
2897 /* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
2899 if (opc
!= 1) { /* SBFM or UBFM */
2900 tcg_gen_movi_i64(tcg_rd
, 0);
2903 /* do the bit move operation */
2905 /* Wd<s-r:0> = Wn<s:r> */
2906 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
2908 len
= (si
- ri
) + 1;
2910 /* Wd<32+s-r,32-r> = Wn<s:0> */
2915 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
2917 if (opc
== 0) { /* SBFM - sign extend the destination field */
2918 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2919 tcg_gen_sari_i64(tcg_rd
, tcg_rd
, 64 - (pos
+ len
));
2922 if (!sf
) { /* zero extend final result */
2923 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2928 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
2929 * +----+------+-------------+---+----+------+--------+------+------+
2930 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
2931 * +----+------+-------------+---+----+------+--------+------+------+
2933 static void disas_extract(DisasContext
*s
, uint32_t insn
)
2935 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
2937 sf
= extract32(insn
, 31, 1);
2938 n
= extract32(insn
, 22, 1);
2939 rm
= extract32(insn
, 16, 5);
2940 imm
= extract32(insn
, 10, 6);
2941 rn
= extract32(insn
, 5, 5);
2942 rd
= extract32(insn
, 0, 5);
2943 op21
= extract32(insn
, 29, 2);
2944 op0
= extract32(insn
, 21, 1);
2945 bitsize
= sf
? 64 : 32;
2947 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
2948 unallocated_encoding(s
);
2950 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
2952 tcg_rd
= cpu_reg(s
, rd
);
2955 /* OPTME: we can special case rm==rn as a rotate */
2956 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
2957 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
2958 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
2959 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
2960 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
2962 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
2965 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
2966 * so an extract from bit 0 is a special case.
2969 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
2971 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
2978 /* C3.4 Data processing - immediate */
2979 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
2981 switch (extract32(insn
, 23, 6)) {
2982 case 0x20: case 0x21: /* PC-rel. addressing */
2983 disas_pc_rel_adr(s
, insn
);
2985 case 0x22: case 0x23: /* Add/subtract (immediate) */
2986 disas_add_sub_imm(s
, insn
);
2988 case 0x24: /* Logical (immediate) */
2989 disas_logic_imm(s
, insn
);
2991 case 0x25: /* Move wide (immediate) */
2992 disas_movw_imm(s
, insn
);
2994 case 0x26: /* Bitfield */
2995 disas_bitfield(s
, insn
);
2997 case 0x27: /* Extract */
2998 disas_extract(s
, insn
);
3001 unallocated_encoding(s
);
3006 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3007 * Note that it is the caller's responsibility to ensure that the
3008 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3009 * mandated semantics for out of range shifts.
3011 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3012 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
3014 switch (shift_type
) {
3015 case A64_SHIFT_TYPE_LSL
:
3016 tcg_gen_shl_i64(dst
, src
, shift_amount
);
3018 case A64_SHIFT_TYPE_LSR
:
3019 tcg_gen_shr_i64(dst
, src
, shift_amount
);
3021 case A64_SHIFT_TYPE_ASR
:
3023 tcg_gen_ext32s_i64(dst
, src
);
3025 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
3027 case A64_SHIFT_TYPE_ROR
:
3029 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
3032 t0
= tcg_temp_new_i32();
3033 t1
= tcg_temp_new_i32();
3034 tcg_gen_trunc_i64_i32(t0
, src
);
3035 tcg_gen_trunc_i64_i32(t1
, shift_amount
);
3036 tcg_gen_rotr_i32(t0
, t0
, t1
);
3037 tcg_gen_extu_i32_i64(dst
, t0
);
3038 tcg_temp_free_i32(t0
);
3039 tcg_temp_free_i32(t1
);
3043 assert(FALSE
); /* all shift types should be handled */
3047 if (!sf
) { /* zero extend final result */
3048 tcg_gen_ext32u_i64(dst
, dst
);
3052 /* Shift a TCGv src by immediate, put result in dst.
3053 * The shift amount must be in range (this should always be true as the
3054 * relevant instructions will UNDEF on bad shift immediates).
3056 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
3057 enum a64_shift_type shift_type
, unsigned int shift_i
)
3059 assert(shift_i
< (sf
? 64 : 32));
3062 tcg_gen_mov_i64(dst
, src
);
3064 TCGv_i64 shift_const
;
3066 shift_const
= tcg_const_i64(shift_i
);
3067 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
3068 tcg_temp_free_i64(shift_const
);
3072 /* C3.5.10 Logical (shifted register)
3073 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3074 * +----+-----+-----------+-------+---+------+--------+------+------+
3075 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3076 * +----+-----+-----------+-------+---+------+--------+------+------+
3078 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
3080 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
3081 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
3083 sf
= extract32(insn
, 31, 1);
3084 opc
= extract32(insn
, 29, 2);
3085 shift_type
= extract32(insn
, 22, 2);
3086 invert
= extract32(insn
, 21, 1);
3087 rm
= extract32(insn
, 16, 5);
3088 shift_amount
= extract32(insn
, 10, 6);
3089 rn
= extract32(insn
, 5, 5);
3090 rd
= extract32(insn
, 0, 5);
3092 if (!sf
&& (shift_amount
& (1 << 5))) {
3093 unallocated_encoding(s
);
3097 tcg_rd
= cpu_reg(s
, rd
);
3099 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
3100 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3101 * register-register MOV and MVN, so it is worth special casing.
3103 tcg_rm
= cpu_reg(s
, rm
);
3105 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
3107 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3111 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
3113 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
3119 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3122 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
3125 tcg_rn
= cpu_reg(s
, rn
);
3127 switch (opc
| (invert
<< 2)) {
3130 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3133 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3136 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3140 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3143 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3146 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
3154 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3158 gen_logic_CC(sf
, tcg_rd
);
3163 * C3.5.1 Add/subtract (extended register)
3165 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3166 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3167 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3168 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3170 * sf: 0 -> 32bit, 1 -> 64bit
3171 * op: 0 -> add , 1 -> sub
3174 * option: extension type (see DecodeRegExtend)
3175 * imm3: optional shift to Rm
3177 * Rd = Rn + LSL(extend(Rm), amount)
3179 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
3181 int rd
= extract32(insn
, 0, 5);
3182 int rn
= extract32(insn
, 5, 5);
3183 int imm3
= extract32(insn
, 10, 3);
3184 int option
= extract32(insn
, 13, 3);
3185 int rm
= extract32(insn
, 16, 5);
3186 bool setflags
= extract32(insn
, 29, 1);
3187 bool sub_op
= extract32(insn
, 30, 1);
3188 bool sf
= extract32(insn
, 31, 1);
3190 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
3192 TCGv_i64 tcg_result
;
3195 unallocated_encoding(s
);
3199 /* non-flag setting ops may use SP */
3201 tcg_rd
= cpu_reg_sp(s
, rd
);
3203 tcg_rd
= cpu_reg(s
, rd
);
3205 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
3207 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3208 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
3210 tcg_result
= tcg_temp_new_i64();
3214 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3216 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3220 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3222 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3227 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3229 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3232 tcg_temp_free_i64(tcg_result
);
3236 * C3.5.2 Add/subtract (shifted register)
3238 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3239 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3240 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3241 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3243 * sf: 0 -> 32bit, 1 -> 64bit
3244 * op: 0 -> add , 1 -> sub
3246 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3247 * imm6: Shift amount to apply to Rm before the add/sub
3249 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
3251 int rd
= extract32(insn
, 0, 5);
3252 int rn
= extract32(insn
, 5, 5);
3253 int imm6
= extract32(insn
, 10, 6);
3254 int rm
= extract32(insn
, 16, 5);
3255 int shift_type
= extract32(insn
, 22, 2);
3256 bool setflags
= extract32(insn
, 29, 1);
3257 bool sub_op
= extract32(insn
, 30, 1);
3258 bool sf
= extract32(insn
, 31, 1);
3260 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3261 TCGv_i64 tcg_rn
, tcg_rm
;
3262 TCGv_i64 tcg_result
;
3264 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
3265 unallocated_encoding(s
);
3269 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3270 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
3272 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
3274 tcg_result
= tcg_temp_new_i64();
3278 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
3280 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
3284 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3286 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
3291 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3293 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3296 tcg_temp_free_i64(tcg_result
);
3299 /* C3.5.9 Data-processing (3 source)
3301 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3302 +--+------+-----------+------+------+----+------+------+------+
3303 |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3304 +--+------+-----------+------+------+----+------+------+------+
3307 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
3309 int rd
= extract32(insn
, 0, 5);
3310 int rn
= extract32(insn
, 5, 5);
3311 int ra
= extract32(insn
, 10, 5);
3312 int rm
= extract32(insn
, 16, 5);
3313 int op_id
= (extract32(insn
, 29, 3) << 4) |
3314 (extract32(insn
, 21, 3) << 1) |
3315 extract32(insn
, 15, 1);
3316 bool sf
= extract32(insn
, 31, 1);
3317 bool is_sub
= extract32(op_id
, 0, 1);
3318 bool is_high
= extract32(op_id
, 2, 1);
3319 bool is_signed
= false;
3324 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
3326 case 0x42: /* SMADDL */
3327 case 0x43: /* SMSUBL */
3328 case 0x44: /* SMULH */
3331 case 0x0: /* MADD (32bit) */
3332 case 0x1: /* MSUB (32bit) */
3333 case 0x40: /* MADD (64bit) */
3334 case 0x41: /* MSUB (64bit) */
3335 case 0x4a: /* UMADDL */
3336 case 0x4b: /* UMSUBL */
3337 case 0x4c: /* UMULH */
3340 unallocated_encoding(s
);
3345 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
3346 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3347 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
3348 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
3351 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3353 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
3356 tcg_temp_free_i64(low_bits
);
3360 tcg_op1
= tcg_temp_new_i64();
3361 tcg_op2
= tcg_temp_new_i64();
3362 tcg_tmp
= tcg_temp_new_i64();
3365 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
3366 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
3369 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
3370 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
3372 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
3373 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
3377 if (ra
== 31 && !is_sub
) {
3378 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
3379 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
3381 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
3383 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3385 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
3390 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
3393 tcg_temp_free_i64(tcg_op1
);
3394 tcg_temp_free_i64(tcg_op2
);
3395 tcg_temp_free_i64(tcg_tmp
);
3398 /* C3.5.3 - Add/subtract (with carry)
3399 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
3400 * +--+--+--+------------------------+------+---------+------+-----+
3401 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
3402 * +--+--+--+------------------------+------+---------+------+-----+
3406 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
3408 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
3409 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
3411 if (extract32(insn
, 10, 6) != 0) {
3412 unallocated_encoding(s
);
3416 sf
= extract32(insn
, 31, 1);
3417 op
= extract32(insn
, 30, 1);
3418 setflags
= extract32(insn
, 29, 1);
3419 rm
= extract32(insn
, 16, 5);
3420 rn
= extract32(insn
, 5, 5);
3421 rd
= extract32(insn
, 0, 5);
3423 tcg_rd
= cpu_reg(s
, rd
);
3424 tcg_rn
= cpu_reg(s
, rn
);
3427 tcg_y
= new_tmp_a64(s
);
3428 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
3430 tcg_y
= cpu_reg(s
, rm
);
3434 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3436 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
3440 /* C3.5.4 - C3.5.5 Conditional compare (immediate / register)
3441 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3442 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3443 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
3444 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
3447 static void disas_cc(DisasContext
*s
, uint32_t insn
)
3449 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
3450 int label_continue
= -1;
3451 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
3453 if (!extract32(insn
, 29, 1)) {
3454 unallocated_encoding(s
);
3457 if (insn
& (1 << 10 | 1 << 4)) {
3458 unallocated_encoding(s
);
3461 sf
= extract32(insn
, 31, 1);
3462 op
= extract32(insn
, 30, 1);
3463 is_imm
= extract32(insn
, 11, 1);
3464 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
3465 cond
= extract32(insn
, 12, 4);
3466 rn
= extract32(insn
, 5, 5);
3467 nzcv
= extract32(insn
, 0, 4);
3469 if (cond
< 0x0e) { /* not always */
3470 int label_match
= gen_new_label();
3471 label_continue
= gen_new_label();
3472 arm_gen_test_cc(cond
, label_match
);
3474 tcg_tmp
= tcg_temp_new_i64();
3475 tcg_gen_movi_i64(tcg_tmp
, nzcv
<< 28);
3476 gen_set_nzcv(tcg_tmp
);
3477 tcg_temp_free_i64(tcg_tmp
);
3478 tcg_gen_br(label_continue
);
3479 gen_set_label(label_match
);
3481 /* match, or condition is always */
3483 tcg_y
= new_tmp_a64(s
);
3484 tcg_gen_movi_i64(tcg_y
, y
);
3486 tcg_y
= cpu_reg(s
, y
);
3488 tcg_rn
= cpu_reg(s
, rn
);
3490 tcg_tmp
= tcg_temp_new_i64();
3492 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3494 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
3496 tcg_temp_free_i64(tcg_tmp
);
3498 if (cond
< 0x0e) { /* continue */
3499 gen_set_label(label_continue
);
3503 /* C3.5.6 Conditional select
3504 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
3505 * +----+----+---+-----------------+------+------+-----+------+------+
3506 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
3507 * +----+----+---+-----------------+------+------+-----+------+------+
3509 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
3511 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
3512 TCGv_i64 tcg_rd
, tcg_src
;
3514 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
3515 /* S == 1 or op2<1> == 1 */
3516 unallocated_encoding(s
);
3519 sf
= extract32(insn
, 31, 1);
3520 else_inv
= extract32(insn
, 30, 1);
3521 rm
= extract32(insn
, 16, 5);
3522 cond
= extract32(insn
, 12, 4);
3523 else_inc
= extract32(insn
, 10, 1);
3524 rn
= extract32(insn
, 5, 5);
3525 rd
= extract32(insn
, 0, 5);
3528 /* silly no-op write; until we use movcond we must special-case
3529 * this to avoid a dead temporary across basic blocks.
3534 tcg_rd
= cpu_reg(s
, rd
);
3536 if (cond
>= 0x0e) { /* condition "always" */
3537 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3538 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3540 /* OPTME: we could use movcond here, at the cost of duplicating
3541 * a lot of the arm_gen_test_cc() logic.
3543 int label_match
= gen_new_label();
3544 int label_continue
= gen_new_label();
3546 arm_gen_test_cc(cond
, label_match
);
3548 tcg_src
= cpu_reg(s
, rm
);
3550 if (else_inv
&& else_inc
) {
3551 tcg_gen_neg_i64(tcg_rd
, tcg_src
);
3552 } else if (else_inv
) {
3553 tcg_gen_not_i64(tcg_rd
, tcg_src
);
3554 } else if (else_inc
) {
3555 tcg_gen_addi_i64(tcg_rd
, tcg_src
, 1);
3557 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3560 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3562 tcg_gen_br(label_continue
);
3564 gen_set_label(label_match
);
3565 tcg_src
= read_cpu_reg(s
, rn
, sf
);
3566 tcg_gen_mov_i64(tcg_rd
, tcg_src
);
3568 gen_set_label(label_continue
);
3572 static void handle_clz(DisasContext
*s
, unsigned int sf
,
3573 unsigned int rn
, unsigned int rd
)
3575 TCGv_i64 tcg_rd
, tcg_rn
;
3576 tcg_rd
= cpu_reg(s
, rd
);
3577 tcg_rn
= cpu_reg(s
, rn
);
3580 gen_helper_clz64(tcg_rd
, tcg_rn
);
3582 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3583 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3584 gen_helper_clz(tcg_tmp32
, tcg_tmp32
);
3585 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3586 tcg_temp_free_i32(tcg_tmp32
);
3590 static void handle_cls(DisasContext
*s
, unsigned int sf
,
3591 unsigned int rn
, unsigned int rd
)
3593 TCGv_i64 tcg_rd
, tcg_rn
;
3594 tcg_rd
= cpu_reg(s
, rd
);
3595 tcg_rn
= cpu_reg(s
, rn
);
3598 gen_helper_cls64(tcg_rd
, tcg_rn
);
3600 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3601 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3602 gen_helper_cls32(tcg_tmp32
, tcg_tmp32
);
3603 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3604 tcg_temp_free_i32(tcg_tmp32
);
3608 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
3609 unsigned int rn
, unsigned int rd
)
3611 TCGv_i64 tcg_rd
, tcg_rn
;
3612 tcg_rd
= cpu_reg(s
, rd
);
3613 tcg_rn
= cpu_reg(s
, rn
);
3616 gen_helper_rbit64(tcg_rd
, tcg_rn
);
3618 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
3619 tcg_gen_trunc_i64_i32(tcg_tmp32
, tcg_rn
);
3620 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
3621 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
3622 tcg_temp_free_i32(tcg_tmp32
);
3626 /* C5.6.149 REV with sf==1, opcode==3 ("REV64") */
3627 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
3628 unsigned int rn
, unsigned int rd
)
3631 unallocated_encoding(s
);
3634 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
3637 /* C5.6.149 REV with sf==0, opcode==2
3638 * C5.6.151 REV32 (sf==1, opcode==2)
3640 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
3641 unsigned int rn
, unsigned int rd
)
3643 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3646 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3647 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3649 /* bswap32_i64 requires zero high word */
3650 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
3651 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
3652 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3653 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
3654 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
3656 tcg_temp_free_i64(tcg_tmp
);
3658 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
3659 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
3663 /* C5.6.150 REV16 (opcode==1) */
3664 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
3665 unsigned int rn
, unsigned int rd
)
3667 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3668 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3669 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3671 tcg_gen_andi_i64(tcg_tmp
, tcg_rn
, 0xffff);
3672 tcg_gen_bswap16_i64(tcg_rd
, tcg_tmp
);
3674 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 16);
3675 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3676 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3677 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 16, 16);
3680 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
3681 tcg_gen_andi_i64(tcg_tmp
, tcg_tmp
, 0xffff);
3682 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3683 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 32, 16);
3685 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 48);
3686 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
3687 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, 48, 16);
3690 tcg_temp_free_i64(tcg_tmp
);
3693 /* C3.5.7 Data-processing (1 source)
3694 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3695 * +----+---+---+-----------------+---------+--------+------+------+
3696 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
3697 * +----+---+---+-----------------+---------+--------+------+------+
3699 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
3701 unsigned int sf
, opcode
, rn
, rd
;
3703 if (extract32(insn
, 29, 1) || extract32(insn
, 16, 5)) {
3704 unallocated_encoding(s
);
3708 sf
= extract32(insn
, 31, 1);
3709 opcode
= extract32(insn
, 10, 6);
3710 rn
= extract32(insn
, 5, 5);
3711 rd
= extract32(insn
, 0, 5);
3715 handle_rbit(s
, sf
, rn
, rd
);
3718 handle_rev16(s
, sf
, rn
, rd
);
3721 handle_rev32(s
, sf
, rn
, rd
);
3724 handle_rev64(s
, sf
, rn
, rd
);
3727 handle_clz(s
, sf
, rn
, rd
);
3730 handle_cls(s
, sf
, rn
, rd
);
3735 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
3736 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3738 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
3739 tcg_rd
= cpu_reg(s
, rd
);
3741 if (!sf
&& is_signed
) {
3742 tcg_n
= new_tmp_a64(s
);
3743 tcg_m
= new_tmp_a64(s
);
3744 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
3745 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
3747 tcg_n
= read_cpu_reg(s
, rn
, sf
);
3748 tcg_m
= read_cpu_reg(s
, rm
, sf
);
3752 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
3754 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
3757 if (!sf
) { /* zero extend final result */
3758 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3762 /* C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV */
3763 static void handle_shift_reg(DisasContext
*s
,
3764 enum a64_shift_type shift_type
, unsigned int sf
,
3765 unsigned int rm
, unsigned int rn
, unsigned int rd
)
3767 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
3768 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3769 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
3771 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
3772 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
3773 tcg_temp_free_i64(tcg_shift
);
3776 /* C3.5.8 Data-processing (2 source)
3777 * 31 30 29 28 21 20 16 15 10 9 5 4 0
3778 * +----+---+---+-----------------+------+--------+------+------+
3779 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
3780 * +----+---+---+-----------------+------+--------+------+------+
3782 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
3784 unsigned int sf
, rm
, opcode
, rn
, rd
;
3785 sf
= extract32(insn
, 31, 1);
3786 rm
= extract32(insn
, 16, 5);
3787 opcode
= extract32(insn
, 10, 6);
3788 rn
= extract32(insn
, 5, 5);
3789 rd
= extract32(insn
, 0, 5);
3791 if (extract32(insn
, 29, 1)) {
3792 unallocated_encoding(s
);
3798 handle_div(s
, false, sf
, rm
, rn
, rd
);
3801 handle_div(s
, true, sf
, rm
, rn
, rd
);
3804 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
3807 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
3810 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
3813 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
3822 case 23: /* CRC32 */
3823 unsupported_encoding(s
, insn
);
3826 unallocated_encoding(s
);
3831 /* C3.5 Data processing - register */
3832 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
3834 switch (extract32(insn
, 24, 5)) {
3835 case 0x0a: /* Logical (shifted register) */
3836 disas_logic_reg(s
, insn
);
3838 case 0x0b: /* Add/subtract */
3839 if (insn
& (1 << 21)) { /* (extended register) */
3840 disas_add_sub_ext_reg(s
, insn
);
3842 disas_add_sub_reg(s
, insn
);
3845 case 0x1b: /* Data-processing (3 source) */
3846 disas_data_proc_3src(s
, insn
);
3849 switch (extract32(insn
, 21, 3)) {
3850 case 0x0: /* Add/subtract (with carry) */
3851 disas_adc_sbc(s
, insn
);
3853 case 0x2: /* Conditional compare */
3854 disas_cc(s
, insn
); /* both imm and reg forms */
3856 case 0x4: /* Conditional select */
3857 disas_cond_select(s
, insn
);
3859 case 0x6: /* Data-processing */
3860 if (insn
& (1 << 30)) { /* (1 source) */
3861 disas_data_proc_1src(s
, insn
);
3862 } else { /* (2 source) */
3863 disas_data_proc_2src(s
, insn
);
3867 unallocated_encoding(s
);
3872 unallocated_encoding(s
);
3877 static void handle_fp_compare(DisasContext
*s
, bool is_double
,
3878 unsigned int rn
, unsigned int rm
,
3879 bool cmp_with_zero
, bool signal_all_nans
)
3881 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
3882 TCGv_ptr fpst
= get_fpstatus_ptr();
3885 TCGv_i64 tcg_vn
, tcg_vm
;
3887 tcg_vn
= read_fp_dreg(s
, rn
);
3888 if (cmp_with_zero
) {
3889 tcg_vm
= tcg_const_i64(0);
3891 tcg_vm
= read_fp_dreg(s
, rm
);
3893 if (signal_all_nans
) {
3894 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3896 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3898 tcg_temp_free_i64(tcg_vn
);
3899 tcg_temp_free_i64(tcg_vm
);
3901 TCGv_i32 tcg_vn
, tcg_vm
;
3903 tcg_vn
= read_fp_sreg(s
, rn
);
3904 if (cmp_with_zero
) {
3905 tcg_vm
= tcg_const_i32(0);
3907 tcg_vm
= read_fp_sreg(s
, rm
);
3909 if (signal_all_nans
) {
3910 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3912 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
3914 tcg_temp_free_i32(tcg_vn
);
3915 tcg_temp_free_i32(tcg_vm
);
3918 tcg_temp_free_ptr(fpst
);
3920 gen_set_nzcv(tcg_flags
);
3922 tcg_temp_free_i64(tcg_flags
);
3925 /* C3.6.22 Floating point compare
3926 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
3927 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3928 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
3929 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
3931 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
3933 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
3935 mos
= extract32(insn
, 29, 3);
3936 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3937 rm
= extract32(insn
, 16, 5);
3938 op
= extract32(insn
, 14, 2);
3939 rn
= extract32(insn
, 5, 5);
3940 opc
= extract32(insn
, 3, 2);
3941 op2r
= extract32(insn
, 0, 3);
3943 if (mos
|| op
|| op2r
|| type
> 1) {
3944 unallocated_encoding(s
);
3948 if (!fp_access_check(s
)) {
3952 handle_fp_compare(s
, type
, rn
, rm
, opc
& 1, opc
& 2);
3955 /* C3.6.23 Floating point conditional compare
3956 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
3957 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3958 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
3959 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
3961 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
3963 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
3965 int label_continue
= -1;
3967 mos
= extract32(insn
, 29, 3);
3968 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
3969 rm
= extract32(insn
, 16, 5);
3970 cond
= extract32(insn
, 12, 4);
3971 rn
= extract32(insn
, 5, 5);
3972 op
= extract32(insn
, 4, 1);
3973 nzcv
= extract32(insn
, 0, 4);
3975 if (mos
|| type
> 1) {
3976 unallocated_encoding(s
);
3980 if (!fp_access_check(s
)) {
3984 if (cond
< 0x0e) { /* not always */
3985 int label_match
= gen_new_label();
3986 label_continue
= gen_new_label();
3987 arm_gen_test_cc(cond
, label_match
);
3989 tcg_flags
= tcg_const_i64(nzcv
<< 28);
3990 gen_set_nzcv(tcg_flags
);
3991 tcg_temp_free_i64(tcg_flags
);
3992 tcg_gen_br(label_continue
);
3993 gen_set_label(label_match
);
3996 handle_fp_compare(s
, type
, rn
, rm
, false, op
);
3999 gen_set_label(label_continue
);
4003 /* copy src FP register to dst FP register; type specifies single or double */
4004 static void gen_mov_fp2fp(DisasContext
*s
, int type
, int dst
, int src
)
4007 TCGv_i64 v
= read_fp_dreg(s
, src
);
4008 write_fp_dreg(s
, dst
, v
);
4009 tcg_temp_free_i64(v
);
4011 TCGv_i32 v
= read_fp_sreg(s
, src
);
4012 write_fp_sreg(s
, dst
, v
);
4013 tcg_temp_free_i32(v
);
4017 /* C3.6.24 Floating point conditional select
4018 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4019 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4020 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4021 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4023 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
4025 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
4026 int label_continue
= -1;
4028 mos
= extract32(insn
, 29, 3);
4029 type
= extract32(insn
, 22, 2); /* 0 = single, 1 = double */
4030 rm
= extract32(insn
, 16, 5);
4031 cond
= extract32(insn
, 12, 4);
4032 rn
= extract32(insn
, 5, 5);
4033 rd
= extract32(insn
, 0, 5);
4035 if (mos
|| type
> 1) {
4036 unallocated_encoding(s
);
4040 if (!fp_access_check(s
)) {
4044 if (cond
< 0x0e) { /* not always */
4045 int label_match
= gen_new_label();
4046 label_continue
= gen_new_label();
4047 arm_gen_test_cc(cond
, label_match
);
4049 gen_mov_fp2fp(s
, type
, rd
, rm
);
4050 tcg_gen_br(label_continue
);
4051 gen_set_label(label_match
);
4054 gen_mov_fp2fp(s
, type
, rd
, rn
);
4056 if (cond
< 0x0e) { /* continue */
4057 gen_set_label(label_continue
);
4061 /* C3.6.25 Floating-point data-processing (1 source) - single precision */
4062 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
4068 fpst
= get_fpstatus_ptr();
4069 tcg_op
= read_fp_sreg(s
, rn
);
4070 tcg_res
= tcg_temp_new_i32();
4073 case 0x0: /* FMOV */
4074 tcg_gen_mov_i32(tcg_res
, tcg_op
);
4076 case 0x1: /* FABS */
4077 gen_helper_vfp_abss(tcg_res
, tcg_op
);
4079 case 0x2: /* FNEG */
4080 gen_helper_vfp_negs(tcg_res
, tcg_op
);
4082 case 0x3: /* FSQRT */
4083 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
4085 case 0x8: /* FRINTN */
4086 case 0x9: /* FRINTP */
4087 case 0xa: /* FRINTM */
4088 case 0xb: /* FRINTZ */
4089 case 0xc: /* FRINTA */
4091 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4093 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4094 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4096 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4097 tcg_temp_free_i32(tcg_rmode
);
4100 case 0xe: /* FRINTX */
4101 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
4103 case 0xf: /* FRINTI */
4104 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
4110 write_fp_sreg(s
, rd
, tcg_res
);
4112 tcg_temp_free_ptr(fpst
);
4113 tcg_temp_free_i32(tcg_op
);
4114 tcg_temp_free_i32(tcg_res
);
4117 /* C3.6.25 Floating-point data-processing (1 source) - double precision */
4118 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
4124 fpst
= get_fpstatus_ptr();
4125 tcg_op
= read_fp_dreg(s
, rn
);
4126 tcg_res
= tcg_temp_new_i64();
4129 case 0x0: /* FMOV */
4130 tcg_gen_mov_i64(tcg_res
, tcg_op
);
4132 case 0x1: /* FABS */
4133 gen_helper_vfp_absd(tcg_res
, tcg_op
);
4135 case 0x2: /* FNEG */
4136 gen_helper_vfp_negd(tcg_res
, tcg_op
);
4138 case 0x3: /* FSQRT */
4139 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
4141 case 0x8: /* FRINTN */
4142 case 0x9: /* FRINTP */
4143 case 0xa: /* FRINTM */
4144 case 0xb: /* FRINTZ */
4145 case 0xc: /* FRINTA */
4147 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
4149 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4150 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4152 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4153 tcg_temp_free_i32(tcg_rmode
);
4156 case 0xe: /* FRINTX */
4157 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
4159 case 0xf: /* FRINTI */
4160 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
4166 write_fp_dreg(s
, rd
, tcg_res
);
4168 tcg_temp_free_ptr(fpst
);
4169 tcg_temp_free_i64(tcg_op
);
4170 tcg_temp_free_i64(tcg_res
);
4173 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
4174 int rd
, int rn
, int dtype
, int ntype
)
4179 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4181 /* Single to double */
4182 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4183 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
4184 write_fp_dreg(s
, rd
, tcg_rd
);
4185 tcg_temp_free_i64(tcg_rd
);
4187 /* Single to half */
4188 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4189 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4190 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4191 write_fp_sreg(s
, rd
, tcg_rd
);
4192 tcg_temp_free_i32(tcg_rd
);
4194 tcg_temp_free_i32(tcg_rn
);
4199 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
4200 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4202 /* Double to single */
4203 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
4205 /* Double to half */
4206 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, cpu_env
);
4207 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
4209 write_fp_sreg(s
, rd
, tcg_rd
);
4210 tcg_temp_free_i32(tcg_rd
);
4211 tcg_temp_free_i64(tcg_rn
);
4216 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
4217 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
4219 /* Half to single */
4220 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
4221 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, cpu_env
);
4222 write_fp_sreg(s
, rd
, tcg_rd
);
4223 tcg_temp_free_i32(tcg_rd
);
4225 /* Half to double */
4226 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
4227 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, cpu_env
);
4228 write_fp_dreg(s
, rd
, tcg_rd
);
4229 tcg_temp_free_i64(tcg_rd
);
4231 tcg_temp_free_i32(tcg_rn
);
4239 /* C3.6.25 Floating point data-processing (1 source)
4240 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
4241 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4242 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
4243 * +---+---+---+-----------+------+---+--------+-----------+------+------+
4245 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
4247 int type
= extract32(insn
, 22, 2);
4248 int opcode
= extract32(insn
, 15, 6);
4249 int rn
= extract32(insn
, 5, 5);
4250 int rd
= extract32(insn
, 0, 5);
4253 case 0x4: case 0x5: case 0x7:
4255 /* FCVT between half, single and double precision */
4256 int dtype
= extract32(opcode
, 0, 2);
4257 if (type
== 2 || dtype
== type
) {
4258 unallocated_encoding(s
);
4261 if (!fp_access_check(s
)) {
4265 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
4271 /* 32-to-32 and 64-to-64 ops */
4274 if (!fp_access_check(s
)) {
4278 handle_fp_1src_single(s
, opcode
, rd
, rn
);
4281 if (!fp_access_check(s
)) {
4285 handle_fp_1src_double(s
, opcode
, rd
, rn
);
4288 unallocated_encoding(s
);
4292 unallocated_encoding(s
);
4297 /* C3.6.26 Floating-point data-processing (2 source) - single precision */
4298 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
4299 int rd
, int rn
, int rm
)
4306 tcg_res
= tcg_temp_new_i32();
4307 fpst
= get_fpstatus_ptr();
4308 tcg_op1
= read_fp_sreg(s
, rn
);
4309 tcg_op2
= read_fp_sreg(s
, rm
);
4312 case 0x0: /* FMUL */
4313 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4315 case 0x1: /* FDIV */
4316 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4318 case 0x2: /* FADD */
4319 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4321 case 0x3: /* FSUB */
4322 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4324 case 0x4: /* FMAX */
4325 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4327 case 0x5: /* FMIN */
4328 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4330 case 0x6: /* FMAXNM */
4331 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4333 case 0x7: /* FMINNM */
4334 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4336 case 0x8: /* FNMUL */
4337 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4338 gen_helper_vfp_negs(tcg_res
, tcg_res
);
4342 write_fp_sreg(s
, rd
, tcg_res
);
4344 tcg_temp_free_ptr(fpst
);
4345 tcg_temp_free_i32(tcg_op1
);
4346 tcg_temp_free_i32(tcg_op2
);
4347 tcg_temp_free_i32(tcg_res
);
4350 /* C3.6.26 Floating-point data-processing (2 source) - double precision */
4351 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
4352 int rd
, int rn
, int rm
)
4359 tcg_res
= tcg_temp_new_i64();
4360 fpst
= get_fpstatus_ptr();
4361 tcg_op1
= read_fp_dreg(s
, rn
);
4362 tcg_op2
= read_fp_dreg(s
, rm
);
4365 case 0x0: /* FMUL */
4366 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4368 case 0x1: /* FDIV */
4369 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4371 case 0x2: /* FADD */
4372 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4374 case 0x3: /* FSUB */
4375 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4377 case 0x4: /* FMAX */
4378 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4380 case 0x5: /* FMIN */
4381 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4383 case 0x6: /* FMAXNM */
4384 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4386 case 0x7: /* FMINNM */
4387 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4389 case 0x8: /* FNMUL */
4390 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
4391 gen_helper_vfp_negd(tcg_res
, tcg_res
);
4395 write_fp_dreg(s
, rd
, tcg_res
);
4397 tcg_temp_free_ptr(fpst
);
4398 tcg_temp_free_i64(tcg_op1
);
4399 tcg_temp_free_i64(tcg_op2
);
4400 tcg_temp_free_i64(tcg_res
);
4403 /* C3.6.26 Floating point data-processing (2 source)
4404 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4405 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4406 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
4407 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
4409 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
4411 int type
= extract32(insn
, 22, 2);
4412 int rd
= extract32(insn
, 0, 5);
4413 int rn
= extract32(insn
, 5, 5);
4414 int rm
= extract32(insn
, 16, 5);
4415 int opcode
= extract32(insn
, 12, 4);
4418 unallocated_encoding(s
);
4424 if (!fp_access_check(s
)) {
4427 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
4430 if (!fp_access_check(s
)) {
4433 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
4436 unallocated_encoding(s
);
4440 /* C3.6.27 Floating-point data-processing (3 source) - single precision */
4441 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
4442 int rd
, int rn
, int rm
, int ra
)
4444 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
4445 TCGv_i32 tcg_res
= tcg_temp_new_i32();
4446 TCGv_ptr fpst
= get_fpstatus_ptr();
4448 tcg_op1
= read_fp_sreg(s
, rn
);
4449 tcg_op2
= read_fp_sreg(s
, rm
);
4450 tcg_op3
= read_fp_sreg(s
, ra
);
4452 /* These are fused multiply-add, and must be done as one
4453 * floating point operation with no rounding between the
4454 * multiplication and addition steps.
4455 * NB that doing the negations here as separate steps is
4456 * correct : an input NaN should come out with its sign bit
4457 * flipped if it is a negated-input.
4460 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
4464 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
4467 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4469 write_fp_sreg(s
, rd
, tcg_res
);
4471 tcg_temp_free_ptr(fpst
);
4472 tcg_temp_free_i32(tcg_op1
);
4473 tcg_temp_free_i32(tcg_op2
);
4474 tcg_temp_free_i32(tcg_op3
);
4475 tcg_temp_free_i32(tcg_res
);
4478 /* C3.6.27 Floating-point data-processing (3 source) - double precision */
4479 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
4480 int rd
, int rn
, int rm
, int ra
)
4482 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
4483 TCGv_i64 tcg_res
= tcg_temp_new_i64();
4484 TCGv_ptr fpst
= get_fpstatus_ptr();
4486 tcg_op1
= read_fp_dreg(s
, rn
);
4487 tcg_op2
= read_fp_dreg(s
, rm
);
4488 tcg_op3
= read_fp_dreg(s
, ra
);
4490 /* These are fused multiply-add, and must be done as one
4491 * floating point operation with no rounding between the
4492 * multiplication and addition steps.
4493 * NB that doing the negations here as separate steps is
4494 * correct : an input NaN should come out with its sign bit
4495 * flipped if it is a negated-input.
4498 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
4502 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
4505 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
4507 write_fp_dreg(s
, rd
, tcg_res
);
4509 tcg_temp_free_ptr(fpst
);
4510 tcg_temp_free_i64(tcg_op1
);
4511 tcg_temp_free_i64(tcg_op2
);
4512 tcg_temp_free_i64(tcg_op3
);
4513 tcg_temp_free_i64(tcg_res
);
4516 /* C3.6.27 Floating point data-processing (3 source)
4517 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
4518 * +---+---+---+-----------+------+----+------+----+------+------+------+
4519 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
4520 * +---+---+---+-----------+------+----+------+----+------+------+------+
4522 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
4524 int type
= extract32(insn
, 22, 2);
4525 int rd
= extract32(insn
, 0, 5);
4526 int rn
= extract32(insn
, 5, 5);
4527 int ra
= extract32(insn
, 10, 5);
4528 int rm
= extract32(insn
, 16, 5);
4529 bool o0
= extract32(insn
, 15, 1);
4530 bool o1
= extract32(insn
, 21, 1);
4534 if (!fp_access_check(s
)) {
4537 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4540 if (!fp_access_check(s
)) {
4543 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
4546 unallocated_encoding(s
);
4550 /* C3.6.28 Floating point immediate
4551 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
4552 * +---+---+---+-----------+------+---+------------+-------+------+------+
4553 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
4554 * +---+---+---+-----------+------+---+------------+-------+------+------+
4556 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
4558 int rd
= extract32(insn
, 0, 5);
4559 int imm8
= extract32(insn
, 13, 8);
4560 int is_double
= extract32(insn
, 22, 2);
4564 if (is_double
> 1) {
4565 unallocated_encoding(s
);
4569 if (!fp_access_check(s
)) {
4573 /* The imm8 encodes the sign bit, enough bits to represent
4574 * an exponent in the range 01....1xx to 10....0xx,
4575 * and the most significant 4 bits of the mantissa; see
4576 * VFPExpandImm() in the v8 ARM ARM.
4579 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4580 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
4581 extract32(imm8
, 0, 6);
4584 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
4585 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
4586 (extract32(imm8
, 0, 6) << 3);
4590 tcg_res
= tcg_const_i64(imm
);
4591 write_fp_dreg(s
, rd
, tcg_res
);
4592 tcg_temp_free_i64(tcg_res
);
4595 /* Handle floating point <=> fixed point conversions. Note that we can
4596 * also deal with fp <=> integer conversions as a special case (scale == 64)
4597 * OPTME: consider handling that special case specially or at least skipping
4598 * the call to scalbn in the helpers for zero shifts.
4600 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
4601 bool itof
, int rmode
, int scale
, int sf
, int type
)
4603 bool is_signed
= !(opcode
& 1);
4604 bool is_double
= type
;
4605 TCGv_ptr tcg_fpstatus
;
4608 tcg_fpstatus
= get_fpstatus_ptr();
4610 tcg_shift
= tcg_const_i32(64 - scale
);
4613 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
4615 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
4618 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
4620 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
4623 tcg_int
= tcg_extend
;
4627 TCGv_i64 tcg_double
= tcg_temp_new_i64();
4629 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
4630 tcg_shift
, tcg_fpstatus
);
4632 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
4633 tcg_shift
, tcg_fpstatus
);
4635 write_fp_dreg(s
, rd
, tcg_double
);
4636 tcg_temp_free_i64(tcg_double
);
4638 TCGv_i32 tcg_single
= tcg_temp_new_i32();
4640 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
4641 tcg_shift
, tcg_fpstatus
);
4643 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
4644 tcg_shift
, tcg_fpstatus
);
4646 write_fp_sreg(s
, rd
, tcg_single
);
4647 tcg_temp_free_i32(tcg_single
);
4650 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
4653 if (extract32(opcode
, 2, 1)) {
4654 /* There are too many rounding modes to all fit into rmode,
4655 * so FCVTA[US] is a special case.
4657 rmode
= FPROUNDING_TIEAWAY
;
4660 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
4662 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4665 TCGv_i64 tcg_double
= read_fp_dreg(s
, rn
);
4668 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
4669 tcg_shift
, tcg_fpstatus
);
4671 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
4672 tcg_shift
, tcg_fpstatus
);
4676 gen_helper_vfp_tould(tcg_int
, tcg_double
,
4677 tcg_shift
, tcg_fpstatus
);
4679 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
4680 tcg_shift
, tcg_fpstatus
);
4683 tcg_temp_free_i64(tcg_double
);
4685 TCGv_i32 tcg_single
= read_fp_sreg(s
, rn
);
4688 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
4689 tcg_shift
, tcg_fpstatus
);
4691 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
4692 tcg_shift
, tcg_fpstatus
);
4695 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
4697 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
4698 tcg_shift
, tcg_fpstatus
);
4700 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
4701 tcg_shift
, tcg_fpstatus
);
4703 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
4704 tcg_temp_free_i32(tcg_dest
);
4706 tcg_temp_free_i32(tcg_single
);
4709 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
4710 tcg_temp_free_i32(tcg_rmode
);
4713 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
4717 tcg_temp_free_ptr(tcg_fpstatus
);
4718 tcg_temp_free_i32(tcg_shift
);
4721 /* C3.6.29 Floating point <-> fixed point conversions
4722 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4723 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4724 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
4725 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
4727 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
4729 int rd
= extract32(insn
, 0, 5);
4730 int rn
= extract32(insn
, 5, 5);
4731 int scale
= extract32(insn
, 10, 6);
4732 int opcode
= extract32(insn
, 16, 3);
4733 int rmode
= extract32(insn
, 19, 2);
4734 int type
= extract32(insn
, 22, 2);
4735 bool sbit
= extract32(insn
, 29, 1);
4736 bool sf
= extract32(insn
, 31, 1);
4739 if (sbit
|| (type
> 1)
4740 || (!sf
&& scale
< 32)) {
4741 unallocated_encoding(s
);
4745 switch ((rmode
<< 3) | opcode
) {
4746 case 0x2: /* SCVTF */
4747 case 0x3: /* UCVTF */
4750 case 0x18: /* FCVTZS */
4751 case 0x19: /* FCVTZU */
4755 unallocated_encoding(s
);
4759 if (!fp_access_check(s
)) {
4763 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
4766 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
4768 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
4769 * without conversion.
4773 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4779 TCGv_i64 tmp
= tcg_temp_new_i64();
4780 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
4781 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4782 tcg_gen_movi_i64(tmp
, 0);
4783 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4784 tcg_temp_free_i64(tmp
);
4790 TCGv_i64 tmp
= tcg_const_i64(0);
4791 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_offset(s
, rd
, MO_64
));
4792 tcg_gen_st_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4793 tcg_temp_free_i64(tmp
);
4797 /* 64 bit to top half. */
4798 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
4802 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4807 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
4811 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
4814 /* 64 bits from top half */
4815 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
4821 /* C3.6.30 Floating point <-> integer conversions
4822 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
4823 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4824 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
4825 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
4827 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
4829 int rd
= extract32(insn
, 0, 5);
4830 int rn
= extract32(insn
, 5, 5);
4831 int opcode
= extract32(insn
, 16, 3);
4832 int rmode
= extract32(insn
, 19, 2);
4833 int type
= extract32(insn
, 22, 2);
4834 bool sbit
= extract32(insn
, 29, 1);
4835 bool sf
= extract32(insn
, 31, 1);
4838 unallocated_encoding(s
);
4844 bool itof
= opcode
& 1;
4847 unallocated_encoding(s
);
4851 switch (sf
<< 3 | type
<< 1 | rmode
) {
4852 case 0x0: /* 32 bit */
4853 case 0xa: /* 64 bit */
4854 case 0xd: /* 64 bit to top half of quad */
4857 /* all other sf/type/rmode combinations are invalid */
4858 unallocated_encoding(s
);
4862 if (!fp_access_check(s
)) {
4865 handle_fmov(s
, rd
, rn
, type
, itof
);
4867 /* actual FP conversions */
4868 bool itof
= extract32(opcode
, 1, 1);
4870 if (type
> 1 || (rmode
!= 0 && opcode
> 1)) {
4871 unallocated_encoding(s
);
4875 if (!fp_access_check(s
)) {
4878 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
4882 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
4883 * 31 30 29 28 25 24 0
4884 * +---+---+---+---------+-----------------------------+
4885 * | | 0 | | 1 1 1 1 | |
4886 * +---+---+---+---------+-----------------------------+
4888 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
4890 if (extract32(insn
, 24, 1)) {
4891 /* Floating point data-processing (3 source) */
4892 disas_fp_3src(s
, insn
);
4893 } else if (extract32(insn
, 21, 1) == 0) {
4894 /* Floating point to fixed point conversions */
4895 disas_fp_fixed_conv(s
, insn
);
4897 switch (extract32(insn
, 10, 2)) {
4899 /* Floating point conditional compare */
4900 disas_fp_ccomp(s
, insn
);
4903 /* Floating point data-processing (2 source) */
4904 disas_fp_2src(s
, insn
);
4907 /* Floating point conditional select */
4908 disas_fp_csel(s
, insn
);
4911 switch (ctz32(extract32(insn
, 12, 4))) {
4912 case 0: /* [15:12] == xxx1 */
4913 /* Floating point immediate */
4914 disas_fp_imm(s
, insn
);
4916 case 1: /* [15:12] == xx10 */
4917 /* Floating point compare */
4918 disas_fp_compare(s
, insn
);
4920 case 2: /* [15:12] == x100 */
4921 /* Floating point data-processing (1 source) */
4922 disas_fp_1src(s
, insn
);
4924 case 3: /* [15:12] == 1000 */
4925 unallocated_encoding(s
);
4927 default: /* [15:12] == 0000 */
4928 /* Floating point <-> integer conversions */
4929 disas_fp_int_conv(s
, insn
);
4937 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
4940 /* Extract 64 bits from the middle of two concatenated 64 bit
4941 * vector register slices left:right. The extracted bits start
4942 * at 'pos' bits into the right (least significant) side.
4943 * We return the result in tcg_right, and guarantee not to
4946 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4947 assert(pos
> 0 && pos
< 64);
4949 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
4950 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
4951 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
4953 tcg_temp_free_i64(tcg_tmp
);
4957 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
4958 * +---+---+-------------+-----+---+------+---+------+---+------+------+
4959 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
4960 * +---+---+-------------+-----+---+------+---+------+---+------+------+
4962 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
4964 int is_q
= extract32(insn
, 30, 1);
4965 int op2
= extract32(insn
, 22, 2);
4966 int imm4
= extract32(insn
, 11, 4);
4967 int rm
= extract32(insn
, 16, 5);
4968 int rn
= extract32(insn
, 5, 5);
4969 int rd
= extract32(insn
, 0, 5);
4970 int pos
= imm4
<< 3;
4971 TCGv_i64 tcg_resl
, tcg_resh
;
4973 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
4974 unallocated_encoding(s
);
4978 if (!fp_access_check(s
)) {
4982 tcg_resh
= tcg_temp_new_i64();
4983 tcg_resl
= tcg_temp_new_i64();
4985 /* Vd gets bits starting at pos bits into Vm:Vn. This is
4986 * either extracting 128 bits from a 128:128 concatenation, or
4987 * extracting 64 bits from a 64:64 concatenation.
4990 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
4992 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
4993 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
4995 tcg_gen_movi_i64(tcg_resh
, 0);
5002 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
5003 EltPosns
*elt
= eltposns
;
5010 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
5012 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
5015 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
5016 tcg_hh
= tcg_temp_new_i64();
5017 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
5018 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
5019 tcg_temp_free_i64(tcg_hh
);
5023 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5024 tcg_temp_free_i64(tcg_resl
);
5025 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5026 tcg_temp_free_i64(tcg_resh
);
5030 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
5031 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5032 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
5033 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
5035 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
5037 int op2
= extract32(insn
, 22, 2);
5038 int is_q
= extract32(insn
, 30, 1);
5039 int rm
= extract32(insn
, 16, 5);
5040 int rn
= extract32(insn
, 5, 5);
5041 int rd
= extract32(insn
, 0, 5);
5042 int is_tblx
= extract32(insn
, 12, 1);
5043 int len
= extract32(insn
, 13, 2);
5044 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
5045 TCGv_i32 tcg_regno
, tcg_numregs
;
5048 unallocated_encoding(s
);
5052 if (!fp_access_check(s
)) {
5056 /* This does a table lookup: for every byte element in the input
5057 * we index into a table formed from up to four vector registers,
5058 * and then the output is the result of the lookups. Our helper
5059 * function does the lookup operation for a single 64 bit part of
5062 tcg_resl
= tcg_temp_new_i64();
5063 tcg_resh
= tcg_temp_new_i64();
5066 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5068 tcg_gen_movi_i64(tcg_resl
, 0);
5070 if (is_tblx
&& is_q
) {
5071 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5073 tcg_gen_movi_i64(tcg_resh
, 0);
5076 tcg_idx
= tcg_temp_new_i64();
5077 tcg_regno
= tcg_const_i32(rn
);
5078 tcg_numregs
= tcg_const_i32(len
+ 1);
5079 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
5080 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
5081 tcg_regno
, tcg_numregs
);
5083 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
5084 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
5085 tcg_regno
, tcg_numregs
);
5087 tcg_temp_free_i64(tcg_idx
);
5088 tcg_temp_free_i32(tcg_regno
);
5089 tcg_temp_free_i32(tcg_numregs
);
5091 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5092 tcg_temp_free_i64(tcg_resl
);
5093 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5094 tcg_temp_free_i64(tcg_resh
);
5097 /* C3.6.3 ZIP/UZP/TRN
5098 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
5099 * +---+---+-------------+------+---+------+---+------------------+------+
5100 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
5101 * +---+---+-------------+------+---+------+---+------------------+------+
5103 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
5105 int rd
= extract32(insn
, 0, 5);
5106 int rn
= extract32(insn
, 5, 5);
5107 int rm
= extract32(insn
, 16, 5);
5108 int size
= extract32(insn
, 22, 2);
5109 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
5110 * bit 2 indicates 1 vs 2 variant of the insn.
5112 int opcode
= extract32(insn
, 12, 2);
5113 bool part
= extract32(insn
, 14, 1);
5114 bool is_q
= extract32(insn
, 30, 1);
5115 int esize
= 8 << size
;
5117 int datasize
= is_q
? 128 : 64;
5118 int elements
= datasize
/ esize
;
5119 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
5121 if (opcode
== 0 || (size
== 3 && !is_q
)) {
5122 unallocated_encoding(s
);
5126 if (!fp_access_check(s
)) {
5130 tcg_resl
= tcg_const_i64(0);
5131 tcg_resh
= tcg_const_i64(0);
5132 tcg_res
= tcg_temp_new_i64();
5134 for (i
= 0; i
< elements
; i
++) {
5136 case 1: /* UZP1/2 */
5138 int midpoint
= elements
/ 2;
5140 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
5142 read_vec_element(s
, tcg_res
, rm
,
5143 2 * (i
- midpoint
) + part
, size
);
5147 case 2: /* TRN1/2 */
5149 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
5151 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
5154 case 3: /* ZIP1/2 */
5156 int base
= part
* elements
/ 2;
5158 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
5160 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
5165 g_assert_not_reached();
5170 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
5171 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
5173 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
5174 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
5178 tcg_temp_free_i64(tcg_res
);
5180 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
5181 tcg_temp_free_i64(tcg_resl
);
5182 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
5183 tcg_temp_free_i64(tcg_resh
);
5186 static void do_minmaxop(DisasContext
*s
, TCGv_i32 tcg_elt1
, TCGv_i32 tcg_elt2
,
5187 int opc
, bool is_min
, TCGv_ptr fpst
)
5189 /* Helper function for disas_simd_across_lanes: do a single precision
5190 * min/max operation on the specified two inputs,
5191 * and return the result in tcg_elt1.
5195 gen_helper_vfp_minnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5197 gen_helper_vfp_maxnums(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5202 gen_helper_vfp_mins(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5204 gen_helper_vfp_maxs(tcg_elt1
, tcg_elt1
, tcg_elt2
, fpst
);
5209 /* C3.6.4 AdvSIMD across lanes
5210 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5211 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5212 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5213 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
5215 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
5217 int rd
= extract32(insn
, 0, 5);
5218 int rn
= extract32(insn
, 5, 5);
5219 int size
= extract32(insn
, 22, 2);
5220 int opcode
= extract32(insn
, 12, 5);
5221 bool is_q
= extract32(insn
, 30, 1);
5222 bool is_u
= extract32(insn
, 29, 1);
5224 bool is_min
= false;
5228 TCGv_i64 tcg_res
, tcg_elt
;
5231 case 0x1b: /* ADDV */
5233 unallocated_encoding(s
);
5237 case 0x3: /* SADDLV, UADDLV */
5238 case 0xa: /* SMAXV, UMAXV */
5239 case 0x1a: /* SMINV, UMINV */
5240 if (size
== 3 || (size
== 2 && !is_q
)) {
5241 unallocated_encoding(s
);
5245 case 0xc: /* FMAXNMV, FMINNMV */
5246 case 0xf: /* FMAXV, FMINV */
5247 if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
5248 unallocated_encoding(s
);
5251 /* Bit 1 of size field encodes min vs max, and actual size is always
5252 * 32 bits: adjust the size variable so following code can rely on it
5254 is_min
= extract32(size
, 1, 1);
5259 unallocated_encoding(s
);
5263 if (!fp_access_check(s
)) {
5268 elements
= (is_q
? 128 : 64) / esize
;
5270 tcg_res
= tcg_temp_new_i64();
5271 tcg_elt
= tcg_temp_new_i64();
5273 /* These instructions operate across all lanes of a vector
5274 * to produce a single result. We can guarantee that a 64
5275 * bit intermediate is sufficient:
5276 * + for [US]ADDLV the maximum element size is 32 bits, and
5277 * the result type is 64 bits
5278 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
5279 * same as the element size, which is 32 bits at most
5280 * For the integer operations we can choose to work at 64
5281 * or 32 bits and truncate at the end; for simplicity
5282 * we use 64 bits always. The floating point
5283 * ops do require 32 bit intermediates, though.
5286 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
5288 for (i
= 1; i
< elements
; i
++) {
5289 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
5292 case 0x03: /* SADDLV / UADDLV */
5293 case 0x1b: /* ADDV */
5294 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
5296 case 0x0a: /* SMAXV / UMAXV */
5297 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
5299 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5301 case 0x1a: /* SMINV / UMINV */
5302 tcg_gen_movcond_i64(is_u
? TCG_COND_LEU
: TCG_COND_LE
,
5304 tcg_res
, tcg_elt
, tcg_res
, tcg_elt
);
5308 g_assert_not_reached();
5313 /* Floating point ops which work on 32 bit (single) intermediates.
5314 * Note that correct NaN propagation requires that we do these
5315 * operations in exactly the order specified by the pseudocode.
5317 TCGv_i32 tcg_elt1
= tcg_temp_new_i32();
5318 TCGv_i32 tcg_elt2
= tcg_temp_new_i32();
5319 TCGv_i32 tcg_elt3
= tcg_temp_new_i32();
5320 TCGv_ptr fpst
= get_fpstatus_ptr();
5322 assert(esize
== 32);
5323 assert(elements
== 4);
5325 read_vec_element(s
, tcg_elt
, rn
, 0, MO_32
);
5326 tcg_gen_trunc_i64_i32(tcg_elt1
, tcg_elt
);
5327 read_vec_element(s
, tcg_elt
, rn
, 1, MO_32
);
5328 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5330 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5332 read_vec_element(s
, tcg_elt
, rn
, 2, MO_32
);
5333 tcg_gen_trunc_i64_i32(tcg_elt2
, tcg_elt
);
5334 read_vec_element(s
, tcg_elt
, rn
, 3, MO_32
);
5335 tcg_gen_trunc_i64_i32(tcg_elt3
, tcg_elt
);
5337 do_minmaxop(s
, tcg_elt2
, tcg_elt3
, opcode
, is_min
, fpst
);
5339 do_minmaxop(s
, tcg_elt1
, tcg_elt2
, opcode
, is_min
, fpst
);
5341 tcg_gen_extu_i32_i64(tcg_res
, tcg_elt1
);
5342 tcg_temp_free_i32(tcg_elt1
);
5343 tcg_temp_free_i32(tcg_elt2
);
5344 tcg_temp_free_i32(tcg_elt3
);
5345 tcg_temp_free_ptr(fpst
);
5348 tcg_temp_free_i64(tcg_elt
);
5350 /* Now truncate the result to the width required for the final output */
5351 if (opcode
== 0x03) {
5352 /* SADDLV, UADDLV: result is 2*esize */
5358 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
5361 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
5364 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
5369 g_assert_not_reached();
5372 write_fp_dreg(s
, rd
, tcg_res
);
5373 tcg_temp_free_i64(tcg_res
);
5376 /* C6.3.31 DUP (Element, Vector)
5378 * 31 30 29 21 20 16 15 10 9 5 4 0
5379 * +---+---+-------------------+--------+-------------+------+------+
5380 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5381 * +---+---+-------------------+--------+-------------+------+------+
5383 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5385 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
5388 int size
= ctz32(imm5
);
5389 int esize
= 8 << size
;
5390 int elements
= (is_q
? 128 : 64) / esize
;
5394 if (size
> 3 || (size
== 3 && !is_q
)) {
5395 unallocated_encoding(s
);
5399 if (!fp_access_check(s
)) {
5403 index
= imm5
>> (size
+ 1);
5405 tmp
= tcg_temp_new_i64();
5406 read_vec_element(s
, tmp
, rn
, index
, size
);
5408 for (i
= 0; i
< elements
; i
++) {
5409 write_vec_element(s
, tmp
, rd
, i
, size
);
5413 clear_vec_high(s
, rd
);
5416 tcg_temp_free_i64(tmp
);
5419 /* C6.3.31 DUP (element, scalar)
5420 * 31 21 20 16 15 10 9 5 4 0
5421 * +-----------------------+--------+-------------+------+------+
5422 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
5423 * +-----------------------+--------+-------------+------+------+
5425 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
5428 int size
= ctz32(imm5
);
5433 unallocated_encoding(s
);
5437 if (!fp_access_check(s
)) {
5441 index
= imm5
>> (size
+ 1);
5443 /* This instruction just extracts the specified element and
5444 * zero-extends it into the bottom of the destination register.
5446 tmp
= tcg_temp_new_i64();
5447 read_vec_element(s
, tmp
, rn
, index
, size
);
5448 write_fp_dreg(s
, rd
, tmp
);
5449 tcg_temp_free_i64(tmp
);
5452 /* C6.3.32 DUP (General)
5454 * 31 30 29 21 20 16 15 10 9 5 4 0
5455 * +---+---+-------------------+--------+-------------+------+------+
5456 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
5457 * +---+---+-------------------+--------+-------------+------+------+
5459 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5461 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
5464 int size
= ctz32(imm5
);
5465 int esize
= 8 << size
;
5466 int elements
= (is_q
? 128 : 64)/esize
;
5469 if (size
> 3 || ((size
== 3) && !is_q
)) {
5470 unallocated_encoding(s
);
5474 if (!fp_access_check(s
)) {
5478 for (i
= 0; i
< elements
; i
++) {
5479 write_vec_element(s
, cpu_reg(s
, rn
), rd
, i
, size
);
5482 clear_vec_high(s
, rd
);
5486 /* C6.3.150 INS (Element)
5488 * 31 21 20 16 15 14 11 10 9 5 4 0
5489 * +-----------------------+--------+------------+---+------+------+
5490 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5491 * +-----------------------+--------+------------+---+------+------+
5493 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5494 * index: encoded in imm5<4:size+1>
5496 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
5499 int size
= ctz32(imm5
);
5500 int src_index
, dst_index
;
5504 unallocated_encoding(s
);
5508 if (!fp_access_check(s
)) {
5512 dst_index
= extract32(imm5
, 1+size
, 5);
5513 src_index
= extract32(imm4
, size
, 4);
5515 tmp
= tcg_temp_new_i64();
5517 read_vec_element(s
, tmp
, rn
, src_index
, size
);
5518 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
5520 tcg_temp_free_i64(tmp
);
5524 /* C6.3.151 INS (General)
5526 * 31 21 20 16 15 10 9 5 4 0
5527 * +-----------------------+--------+-------------+------+------+
5528 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
5529 * +-----------------------+--------+-------------+------+------+
5531 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5532 * index: encoded in imm5<4:size+1>
5534 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
5536 int size
= ctz32(imm5
);
5540 unallocated_encoding(s
);
5544 if (!fp_access_check(s
)) {
5548 idx
= extract32(imm5
, 1 + size
, 4 - size
);
5549 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
5553 * C6.3.321 UMOV (General)
5554 * C6.3.237 SMOV (General)
5556 * 31 30 29 21 20 16 15 12 10 9 5 4 0
5557 * +---+---+-------------------+--------+-------------+------+------+
5558 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
5559 * +---+---+-------------------+--------+-------------+------+------+
5561 * U: unsigned when set
5562 * size: encoded in imm5 (see ARM ARM LowestSetBit())
5564 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
5565 int rn
, int rd
, int imm5
)
5567 int size
= ctz32(imm5
);
5571 /* Check for UnallocatedEncodings */
5573 if (size
> 2 || (size
== 2 && !is_q
)) {
5574 unallocated_encoding(s
);
5579 || (size
< 3 && is_q
)
5580 || (size
== 3 && !is_q
)) {
5581 unallocated_encoding(s
);
5586 if (!fp_access_check(s
)) {
5590 element
= extract32(imm5
, 1+size
, 4);
5592 tcg_rd
= cpu_reg(s
, rd
);
5593 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
5594 if (is_signed
&& !is_q
) {
5595 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5599 /* C3.6.5 AdvSIMD copy
5600 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5601 * +---+---+----+-----------------+------+---+------+---+------+------+
5602 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5603 * +---+---+----+-----------------+------+---+------+---+------+------+
5605 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
5607 int rd
= extract32(insn
, 0, 5);
5608 int rn
= extract32(insn
, 5, 5);
5609 int imm4
= extract32(insn
, 11, 4);
5610 int op
= extract32(insn
, 29, 1);
5611 int is_q
= extract32(insn
, 30, 1);
5612 int imm5
= extract32(insn
, 16, 5);
5617 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
5619 unallocated_encoding(s
);
5624 /* DUP (element - vector) */
5625 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
5629 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
5634 handle_simd_insg(s
, rd
, rn
, imm5
);
5636 unallocated_encoding(s
);
5641 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
5642 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
5645 unallocated_encoding(s
);
5651 /* C3.6.6 AdvSIMD modified immediate
5652 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
5653 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5654 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
5655 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
5657 * There are a number of operations that can be carried out here:
5658 * MOVI - move (shifted) imm into register
5659 * MVNI - move inverted (shifted) imm into register
5660 * ORR - bitwise OR of (shifted) imm with register
5661 * BIC - bitwise clear of (shifted) imm with register
5663 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
5665 int rd
= extract32(insn
, 0, 5);
5666 int cmode
= extract32(insn
, 12, 4);
5667 int cmode_3_1
= extract32(cmode
, 1, 3);
5668 int cmode_0
= extract32(cmode
, 0, 1);
5669 int o2
= extract32(insn
, 11, 1);
5670 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
5671 bool is_neg
= extract32(insn
, 29, 1);
5672 bool is_q
= extract32(insn
, 30, 1);
5674 TCGv_i64 tcg_rd
, tcg_imm
;
5677 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
5678 unallocated_encoding(s
);
5682 if (!fp_access_check(s
)) {
5686 /* See AdvSIMDExpandImm() in ARM ARM */
5687 switch (cmode_3_1
) {
5688 case 0: /* Replicate(Zeros(24):imm8, 2) */
5689 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
5690 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
5691 case 3: /* Replicate(imm8:Zeros(24), 2) */
5693 int shift
= cmode_3_1
* 8;
5694 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
5697 case 4: /* Replicate(Zeros(8):imm8, 4) */
5698 case 5: /* Replicate(imm8:Zeros(8), 4) */
5700 int shift
= (cmode_3_1
& 0x1) * 8;
5701 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
5706 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
5707 imm
= (abcdefgh
<< 16) | 0xffff;
5709 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
5710 imm
= (abcdefgh
<< 8) | 0xff;
5712 imm
= bitfield_replicate(imm
, 32);
5715 if (!cmode_0
&& !is_neg
) {
5716 imm
= bitfield_replicate(abcdefgh
, 8);
5717 } else if (!cmode_0
&& is_neg
) {
5720 for (i
= 0; i
< 8; i
++) {
5721 if ((abcdefgh
) & (1 << i
)) {
5722 imm
|= 0xffULL
<< (i
* 8);
5725 } else if (cmode_0
) {
5727 imm
= (abcdefgh
& 0x3f) << 48;
5728 if (abcdefgh
& 0x80) {
5729 imm
|= 0x8000000000000000ULL
;
5731 if (abcdefgh
& 0x40) {
5732 imm
|= 0x3fc0000000000000ULL
;
5734 imm
|= 0x4000000000000000ULL
;
5737 imm
= (abcdefgh
& 0x3f) << 19;
5738 if (abcdefgh
& 0x80) {
5741 if (abcdefgh
& 0x40) {
5752 if (cmode_3_1
!= 7 && is_neg
) {
5756 tcg_imm
= tcg_const_i64(imm
);
5757 tcg_rd
= new_tmp_a64(s
);
5759 for (i
= 0; i
< 2; i
++) {
5760 int foffs
= i
? fp_reg_hi_offset(s
, rd
) : fp_reg_offset(s
, rd
, MO_64
);
5762 if (i
== 1 && !is_q
) {
5763 /* non-quad ops clear high half of vector */
5764 tcg_gen_movi_i64(tcg_rd
, 0);
5765 } else if ((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9) {
5766 tcg_gen_ld_i64(tcg_rd
, cpu_env
, foffs
);
5769 tcg_gen_and_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5772 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_imm
);
5776 tcg_gen_mov_i64(tcg_rd
, tcg_imm
);
5778 tcg_gen_st_i64(tcg_rd
, cpu_env
, foffs
);
5781 tcg_temp_free_i64(tcg_imm
);
5784 /* C3.6.7 AdvSIMD scalar copy
5785 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
5786 * +-----+----+-----------------+------+---+------+---+------+------+
5787 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
5788 * +-----+----+-----------------+------+---+------+---+------+------+
5790 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
5792 int rd
= extract32(insn
, 0, 5);
5793 int rn
= extract32(insn
, 5, 5);
5794 int imm4
= extract32(insn
, 11, 4);
5795 int imm5
= extract32(insn
, 16, 5);
5796 int op
= extract32(insn
, 29, 1);
5798 if (op
!= 0 || imm4
!= 0) {
5799 unallocated_encoding(s
);
5803 /* DUP (element, scalar) */
5804 handle_simd_dupes(s
, rd
, rn
, imm5
);
5807 /* C3.6.8 AdvSIMD scalar pairwise
5808 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
5809 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5810 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
5811 * +-----+---+-----------+------+-----------+--------+-----+------+------+
5813 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
5815 int u
= extract32(insn
, 29, 1);
5816 int size
= extract32(insn
, 22, 2);
5817 int opcode
= extract32(insn
, 12, 5);
5818 int rn
= extract32(insn
, 5, 5);
5819 int rd
= extract32(insn
, 0, 5);
5822 /* For some ops (the FP ones), size[1] is part of the encoding.
5823 * For ADDP strictly it is not but size[1] is always 1 for valid
5826 opcode
|= (extract32(size
, 1, 1) << 5);
5829 case 0x3b: /* ADDP */
5830 if (u
|| size
!= 3) {
5831 unallocated_encoding(s
);
5834 if (!fp_access_check(s
)) {
5838 TCGV_UNUSED_PTR(fpst
);
5840 case 0xc: /* FMAXNMP */
5841 case 0xd: /* FADDP */
5842 case 0xf: /* FMAXP */
5843 case 0x2c: /* FMINNMP */
5844 case 0x2f: /* FMINP */
5845 /* FP op, size[0] is 32 or 64 bit */
5847 unallocated_encoding(s
);
5850 if (!fp_access_check(s
)) {
5854 size
= extract32(size
, 0, 1) ? 3 : 2;
5855 fpst
= get_fpstatus_ptr();
5858 unallocated_encoding(s
);
5863 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
5864 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
5865 TCGv_i64 tcg_res
= tcg_temp_new_i64();
5867 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
5868 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
5871 case 0x3b: /* ADDP */
5872 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
5874 case 0xc: /* FMAXNMP */
5875 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5877 case 0xd: /* FADDP */
5878 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5880 case 0xf: /* FMAXP */
5881 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5883 case 0x2c: /* FMINNMP */
5884 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5886 case 0x2f: /* FMINP */
5887 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5890 g_assert_not_reached();
5893 write_fp_dreg(s
, rd
, tcg_res
);
5895 tcg_temp_free_i64(tcg_op1
);
5896 tcg_temp_free_i64(tcg_op2
);
5897 tcg_temp_free_i64(tcg_res
);
5899 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
5900 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
5901 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5903 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_32
);
5904 read_vec_element_i32(s
, tcg_op2
, rn
, 1, MO_32
);
5907 case 0xc: /* FMAXNMP */
5908 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5910 case 0xd: /* FADDP */
5911 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5913 case 0xf: /* FMAXP */
5914 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5916 case 0x2c: /* FMINNMP */
5917 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5919 case 0x2f: /* FMINP */
5920 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5923 g_assert_not_reached();
5926 write_fp_sreg(s
, rd
, tcg_res
);
5928 tcg_temp_free_i32(tcg_op1
);
5929 tcg_temp_free_i32(tcg_op2
);
5930 tcg_temp_free_i32(tcg_res
);
5933 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
5934 tcg_temp_free_ptr(fpst
);
5939 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
5941 * This code is handles the common shifting code and is used by both
5942 * the vector and scalar code.
5944 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
5945 TCGv_i64 tcg_rnd
, bool accumulate
,
5946 bool is_u
, int size
, int shift
)
5948 bool extended_result
= false;
5949 bool round
= !TCGV_IS_UNUSED_I64(tcg_rnd
);
5951 TCGv_i64 tcg_src_hi
;
5953 if (round
&& size
== 3) {
5954 extended_result
= true;
5955 ext_lshift
= 64 - shift
;
5956 tcg_src_hi
= tcg_temp_new_i64();
5957 } else if (shift
== 64) {
5958 if (!accumulate
&& is_u
) {
5959 /* result is zero */
5960 tcg_gen_movi_i64(tcg_res
, 0);
5965 /* Deal with the rounding step */
5967 if (extended_result
) {
5968 TCGv_i64 tcg_zero
= tcg_const_i64(0);
5970 /* take care of sign extending tcg_res */
5971 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
5972 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
5973 tcg_src
, tcg_src_hi
,
5976 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
5980 tcg_temp_free_i64(tcg_zero
);
5982 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
5986 /* Now do the shift right */
5987 if (round
&& extended_result
) {
5988 /* extended case, >64 bit precision required */
5989 if (ext_lshift
== 0) {
5990 /* special case, only high bits matter */
5991 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
5993 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
5994 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
5995 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
6000 /* essentially shifting in 64 zeros */
6001 tcg_gen_movi_i64(tcg_src
, 0);
6003 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6007 /* effectively extending the sign-bit */
6008 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
6010 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
6016 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
6018 tcg_gen_mov_i64(tcg_res
, tcg_src
);
6021 if (extended_result
) {
6022 tcg_temp_free_i64(tcg_src_hi
);
6026 /* Common SHL/SLI - Shift left with an optional insert */
6027 static void handle_shli_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6028 bool insert
, int shift
)
6030 if (insert
) { /* SLI */
6031 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, shift
, 64 - shift
);
6033 tcg_gen_shli_i64(tcg_res
, tcg_src
, shift
);
6037 /* SRI: shift right with insert */
6038 static void handle_shri_with_ins(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
6039 int size
, int shift
)
6041 int esize
= 8 << size
;
6043 /* shift count same as element size is valid but does nothing;
6044 * special case to avoid potential shift by 64.
6046 if (shift
!= esize
) {
6047 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
6048 tcg_gen_deposit_i64(tcg_res
, tcg_res
, tcg_src
, 0, esize
- shift
);
6052 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
6053 static void handle_scalar_simd_shri(DisasContext
*s
,
6054 bool is_u
, int immh
, int immb
,
6055 int opcode
, int rn
, int rd
)
6058 int immhb
= immh
<< 3 | immb
;
6059 int shift
= 2 * (8 << size
) - immhb
;
6060 bool accumulate
= false;
6062 bool insert
= false;
6067 if (!extract32(immh
, 3, 1)) {
6068 unallocated_encoding(s
);
6072 if (!fp_access_check(s
)) {
6077 case 0x02: /* SSRA / USRA (accumulate) */
6080 case 0x04: /* SRSHR / URSHR (rounding) */
6083 case 0x06: /* SRSRA / URSRA (accum + rounding) */
6084 accumulate
= round
= true;
6086 case 0x08: /* SRI */
6092 uint64_t round_const
= 1ULL << (shift
- 1);
6093 tcg_round
= tcg_const_i64(round_const
);
6095 TCGV_UNUSED_I64(tcg_round
);
6098 tcg_rn
= read_fp_dreg(s
, rn
);
6099 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6102 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
6104 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6105 accumulate
, is_u
, size
, shift
);
6108 write_fp_dreg(s
, rd
, tcg_rd
);
6110 tcg_temp_free_i64(tcg_rn
);
6111 tcg_temp_free_i64(tcg_rd
);
6113 tcg_temp_free_i64(tcg_round
);
6117 /* SHL/SLI - Scalar shift left */
6118 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
6119 int immh
, int immb
, int opcode
,
6122 int size
= 32 - clz32(immh
) - 1;
6123 int immhb
= immh
<< 3 | immb
;
6124 int shift
= immhb
- (8 << size
);
6125 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
6126 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
6128 if (!extract32(immh
, 3, 1)) {
6129 unallocated_encoding(s
);
6133 if (!fp_access_check(s
)) {
6137 tcg_rn
= read_fp_dreg(s
, rn
);
6138 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
6140 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
6142 write_fp_dreg(s
, rd
, tcg_rd
);
6144 tcg_temp_free_i64(tcg_rn
);
6145 tcg_temp_free_i64(tcg_rd
);
6148 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
6149 * (signed/unsigned) narrowing */
6150 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
6151 bool is_u_shift
, bool is_u_narrow
,
6152 int immh
, int immb
, int opcode
,
6155 int immhb
= immh
<< 3 | immb
;
6156 int size
= 32 - clz32(immh
) - 1;
6157 int esize
= 8 << size
;
6158 int shift
= (2 * esize
) - immhb
;
6159 int elements
= is_scalar
? 1 : (64 / esize
);
6160 bool round
= extract32(opcode
, 0, 1);
6161 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
6162 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
6163 TCGv_i32 tcg_rd_narrowed
;
6166 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
6167 { gen_helper_neon_narrow_sat_s8
,
6168 gen_helper_neon_unarrow_sat8
},
6169 { gen_helper_neon_narrow_sat_s16
,
6170 gen_helper_neon_unarrow_sat16
},
6171 { gen_helper_neon_narrow_sat_s32
,
6172 gen_helper_neon_unarrow_sat32
},
6175 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
6176 gen_helper_neon_narrow_sat_u8
,
6177 gen_helper_neon_narrow_sat_u16
,
6178 gen_helper_neon_narrow_sat_u32
,
6181 NeonGenNarrowEnvFn
*narrowfn
;
6187 if (extract32(immh
, 3, 1)) {
6188 unallocated_encoding(s
);
6192 if (!fp_access_check(s
)) {
6197 narrowfn
= unsigned_narrow_fns
[size
];
6199 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
6202 tcg_rn
= tcg_temp_new_i64();
6203 tcg_rd
= tcg_temp_new_i64();
6204 tcg_rd_narrowed
= tcg_temp_new_i32();
6205 tcg_final
= tcg_const_i64(0);
6208 uint64_t round_const
= 1ULL << (shift
- 1);
6209 tcg_round
= tcg_const_i64(round_const
);
6211 TCGV_UNUSED_I64(tcg_round
);
6214 for (i
= 0; i
< elements
; i
++) {
6215 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
6216 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
6217 false, is_u_shift
, size
+1, shift
);
6218 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
6219 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
6220 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
6224 clear_vec_high(s
, rd
);
6225 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
6227 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
6231 tcg_temp_free_i64(tcg_round
);
6233 tcg_temp_free_i64(tcg_rn
);
6234 tcg_temp_free_i64(tcg_rd
);
6235 tcg_temp_free_i32(tcg_rd_narrowed
);
6236 tcg_temp_free_i64(tcg_final
);
6240 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
6241 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
6242 bool src_unsigned
, bool dst_unsigned
,
6243 int immh
, int immb
, int rn
, int rd
)
6245 int immhb
= immh
<< 3 | immb
;
6246 int size
= 32 - clz32(immh
) - 1;
6247 int shift
= immhb
- (8 << size
);
6251 assert(!(scalar
&& is_q
));
6254 if (!is_q
&& extract32(immh
, 3, 1)) {
6255 unallocated_encoding(s
);
6259 /* Since we use the variable-shift helpers we must
6260 * replicate the shift count into each element of
6261 * the tcg_shift value.
6265 shift
|= shift
<< 8;
6268 shift
|= shift
<< 16;
6274 g_assert_not_reached();
6278 if (!fp_access_check(s
)) {
6283 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
6284 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
6285 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
6286 { NULL
, gen_helper_neon_qshl_u64
},
6288 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
6289 int maxpass
= is_q
? 2 : 1;
6291 for (pass
= 0; pass
< maxpass
; pass
++) {
6292 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6294 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6295 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6296 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6298 tcg_temp_free_i64(tcg_op
);
6300 tcg_temp_free_i64(tcg_shift
);
6303 clear_vec_high(s
, rd
);
6306 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
6307 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
6309 { gen_helper_neon_qshl_s8
,
6310 gen_helper_neon_qshl_s16
,
6311 gen_helper_neon_qshl_s32
},
6312 { gen_helper_neon_qshlu_s8
,
6313 gen_helper_neon_qshlu_s16
,
6314 gen_helper_neon_qshlu_s32
}
6316 { NULL
, NULL
, NULL
},
6317 { gen_helper_neon_qshl_u8
,
6318 gen_helper_neon_qshl_u16
,
6319 gen_helper_neon_qshl_u32
}
6322 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
6323 TCGMemOp memop
= scalar
? size
: MO_32
;
6324 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
6326 for (pass
= 0; pass
< maxpass
; pass
++) {
6327 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6329 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
6330 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
6334 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
6337 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
6342 g_assert_not_reached();
6344 write_fp_sreg(s
, rd
, tcg_op
);
6346 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6349 tcg_temp_free_i32(tcg_op
);
6351 tcg_temp_free_i32(tcg_shift
);
6353 if (!is_q
&& !scalar
) {
6354 clear_vec_high(s
, rd
);
6359 /* Common vector code for handling integer to FP conversion */
6360 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
6361 int elements
, int is_signed
,
6362 int fracbits
, int size
)
6364 bool is_double
= size
== 3 ? true : false;
6365 TCGv_ptr tcg_fpst
= get_fpstatus_ptr();
6366 TCGv_i32 tcg_shift
= tcg_const_i32(fracbits
);
6367 TCGv_i64 tcg_int
= tcg_temp_new_i64();
6368 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
6371 for (pass
= 0; pass
< elements
; pass
++) {
6372 read_vec_element(s
, tcg_int
, rn
, pass
, mop
);
6375 TCGv_i64 tcg_double
= tcg_temp_new_i64();
6377 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6378 tcg_shift
, tcg_fpst
);
6380 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6381 tcg_shift
, tcg_fpst
);
6383 if (elements
== 1) {
6384 write_fp_dreg(s
, rd
, tcg_double
);
6386 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
6388 tcg_temp_free_i64(tcg_double
);
6390 TCGv_i32 tcg_single
= tcg_temp_new_i32();
6392 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6393 tcg_shift
, tcg_fpst
);
6395 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6396 tcg_shift
, tcg_fpst
);
6398 if (elements
== 1) {
6399 write_fp_sreg(s
, rd
, tcg_single
);
6401 write_vec_element_i32(s
, tcg_single
, rd
, pass
, MO_32
);
6403 tcg_temp_free_i32(tcg_single
);
6407 if (!is_double
&& elements
== 2) {
6408 clear_vec_high(s
, rd
);
6411 tcg_temp_free_i64(tcg_int
);
6412 tcg_temp_free_ptr(tcg_fpst
);
6413 tcg_temp_free_i32(tcg_shift
);
6416 /* UCVTF/SCVTF - Integer to FP conversion */
6417 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
6418 bool is_q
, bool is_u
,
6419 int immh
, int immb
, int opcode
,
6422 bool is_double
= extract32(immh
, 3, 1);
6423 int size
= is_double
? MO_64
: MO_32
;
6425 int immhb
= immh
<< 3 | immb
;
6426 int fracbits
= (is_double
? 128 : 64) - immhb
;
6428 if (!extract32(immh
, 2, 2)) {
6429 unallocated_encoding(s
);
6436 elements
= is_double
? 2 : is_q
? 4 : 2;
6437 if (is_double
&& !is_q
) {
6438 unallocated_encoding(s
);
6443 if (!fp_access_check(s
)) {
6447 /* immh == 0 would be a failure of the decode logic */
6450 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
6453 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
6454 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
6455 bool is_q
, bool is_u
,
6456 int immh
, int immb
, int rn
, int rd
)
6458 bool is_double
= extract32(immh
, 3, 1);
6459 int immhb
= immh
<< 3 | immb
;
6460 int fracbits
= (is_double
? 128 : 64) - immhb
;
6462 TCGv_ptr tcg_fpstatus
;
6463 TCGv_i32 tcg_rmode
, tcg_shift
;
6465 if (!extract32(immh
, 2, 2)) {
6466 unallocated_encoding(s
);
6470 if (!is_scalar
&& !is_q
&& is_double
) {
6471 unallocated_encoding(s
);
6475 if (!fp_access_check(s
)) {
6479 assert(!(is_scalar
&& is_q
));
6481 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
6482 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6483 tcg_fpstatus
= get_fpstatus_ptr();
6484 tcg_shift
= tcg_const_i32(fracbits
);
6487 int maxpass
= is_scalar
? 1 : is_q
? 2 : 1;
6489 for (pass
= 0; pass
< maxpass
; pass
++) {
6490 TCGv_i64 tcg_op
= tcg_temp_new_i64();
6492 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
6494 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6496 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6498 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
6499 tcg_temp_free_i64(tcg_op
);
6502 clear_vec_high(s
, rd
);
6505 int maxpass
= is_scalar
? 1 : is_q
? 4 : 2;
6506 for (pass
= 0; pass
< maxpass
; pass
++) {
6507 TCGv_i32 tcg_op
= tcg_temp_new_i32();
6509 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
6511 gen_helper_vfp_touls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6513 gen_helper_vfp_tosls(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
6516 write_fp_sreg(s
, rd
, tcg_op
);
6518 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
6520 tcg_temp_free_i32(tcg_op
);
6522 if (!is_q
&& !is_scalar
) {
6523 clear_vec_high(s
, rd
);
6527 tcg_temp_free_ptr(tcg_fpstatus
);
6528 tcg_temp_free_i32(tcg_shift
);
6529 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
6530 tcg_temp_free_i32(tcg_rmode
);
6533 /* C3.6.9 AdvSIMD scalar shift by immediate
6534 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
6535 * +-----+---+-------------+------+------+--------+---+------+------+
6536 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
6537 * +-----+---+-------------+------+------+--------+---+------+------+
6539 * This is the scalar version so it works on a fixed sized registers
6541 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
6543 int rd
= extract32(insn
, 0, 5);
6544 int rn
= extract32(insn
, 5, 5);
6545 int opcode
= extract32(insn
, 11, 5);
6546 int immb
= extract32(insn
, 16, 3);
6547 int immh
= extract32(insn
, 19, 4);
6548 bool is_u
= extract32(insn
, 29, 1);
6551 unallocated_encoding(s
);
6556 case 0x08: /* SRI */
6558 unallocated_encoding(s
);
6562 case 0x00: /* SSHR / USHR */
6563 case 0x02: /* SSRA / USRA */
6564 case 0x04: /* SRSHR / URSHR */
6565 case 0x06: /* SRSRA / URSRA */
6566 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6568 case 0x0a: /* SHL / SLI */
6569 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
6571 case 0x1c: /* SCVTF, UCVTF */
6572 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
6575 case 0x10: /* SQSHRUN, SQSHRUN2 */
6576 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
6578 unallocated_encoding(s
);
6581 handle_vec_simd_sqshrn(s
, true, false, false, true,
6582 immh
, immb
, opcode
, rn
, rd
);
6584 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
6585 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
6586 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
6587 immh
, immb
, opcode
, rn
, rd
);
6589 case 0xc: /* SQSHLU */
6591 unallocated_encoding(s
);
6594 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
6596 case 0xe: /* SQSHL, UQSHL */
6597 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
6599 case 0x1f: /* FCVTZS, FCVTZU */
6600 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
6603 unallocated_encoding(s
);
6608 /* C3.6.10 AdvSIMD scalar three different
6609 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6610 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6611 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
6612 * +-----+---+-----------+------+---+------+--------+-----+------+------+
6614 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
6616 bool is_u
= extract32(insn
, 29, 1);
6617 int size
= extract32(insn
, 22, 2);
6618 int opcode
= extract32(insn
, 12, 4);
6619 int rm
= extract32(insn
, 16, 5);
6620 int rn
= extract32(insn
, 5, 5);
6621 int rd
= extract32(insn
, 0, 5);
6624 unallocated_encoding(s
);
6629 case 0x9: /* SQDMLAL, SQDMLAL2 */
6630 case 0xb: /* SQDMLSL, SQDMLSL2 */
6631 case 0xd: /* SQDMULL, SQDMULL2 */
6632 if (size
== 0 || size
== 3) {
6633 unallocated_encoding(s
);
6638 unallocated_encoding(s
);
6642 if (!fp_access_check(s
)) {
6647 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6648 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6649 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6651 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
6652 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
6654 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
6655 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6658 case 0xd: /* SQDMULL, SQDMULL2 */
6660 case 0xb: /* SQDMLSL, SQDMLSL2 */
6661 tcg_gen_neg_i64(tcg_res
, tcg_res
);
6663 case 0x9: /* SQDMLAL, SQDMLAL2 */
6664 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
6665 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
6669 g_assert_not_reached();
6672 write_fp_dreg(s
, rd
, tcg_res
);
6674 tcg_temp_free_i64(tcg_op1
);
6675 tcg_temp_free_i64(tcg_op2
);
6676 tcg_temp_free_i64(tcg_res
);
6678 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6679 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6680 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6682 read_vec_element_i32(s
, tcg_op1
, rn
, 0, MO_16
);
6683 read_vec_element_i32(s
, tcg_op2
, rm
, 0, MO_16
);
6685 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
6686 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
6689 case 0xd: /* SQDMULL, SQDMULL2 */
6691 case 0xb: /* SQDMLSL, SQDMLSL2 */
6692 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
6694 case 0x9: /* SQDMLAL, SQDMLAL2 */
6696 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
6697 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
6698 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
6700 tcg_temp_free_i64(tcg_op3
);
6704 g_assert_not_reached();
6707 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
6708 write_fp_dreg(s
, rd
, tcg_res
);
6710 tcg_temp_free_i32(tcg_op1
);
6711 tcg_temp_free_i32(tcg_op2
);
6712 tcg_temp_free_i64(tcg_res
);
6716 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
6717 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
6719 /* Handle 64x64->64 opcodes which are shared between the scalar
6720 * and vector 3-same groups. We cover every opcode where size == 3
6721 * is valid in either the three-reg-same (integer, not pairwise)
6722 * or scalar-three-reg-same groups. (Some opcodes are not yet
6728 case 0x1: /* SQADD */
6730 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6732 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6735 case 0x5: /* SQSUB */
6737 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6739 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6742 case 0x6: /* CMGT, CMHI */
6743 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
6744 * We implement this using setcond (test) and then negating.
6746 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
6748 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
6749 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6751 case 0x7: /* CMGE, CMHS */
6752 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
6754 case 0x11: /* CMTST, CMEQ */
6759 /* CMTST : test is "if (X & Y != 0)". */
6760 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6761 tcg_gen_setcondi_i64(TCG_COND_NE
, tcg_rd
, tcg_rd
, 0);
6762 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
6764 case 0x8: /* SSHL, USHL */
6766 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6768 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6771 case 0x9: /* SQSHL, UQSHL */
6773 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6775 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6778 case 0xa: /* SRSHL, URSHL */
6780 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
6782 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
6785 case 0xb: /* SQRSHL, UQRSHL */
6787 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6789 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
6792 case 0x10: /* ADD, SUB */
6794 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6796 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
6800 g_assert_not_reached();
6804 /* Handle the 3-same-operands float operations; shared by the scalar
6805 * and vector encodings. The caller must filter out any encodings
6806 * not allocated for the encoding it is dealing with.
6808 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
6809 int fpopcode
, int rd
, int rn
, int rm
)
6812 TCGv_ptr fpst
= get_fpstatus_ptr();
6814 for (pass
= 0; pass
< elements
; pass
++) {
6817 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
6818 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
6819 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6821 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
6822 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
6825 case 0x39: /* FMLS */
6826 /* As usual for ARM, separate negation for fused multiply-add */
6827 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6829 case 0x19: /* FMLA */
6830 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6831 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
6834 case 0x18: /* FMAXNM */
6835 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6837 case 0x1a: /* FADD */
6838 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6840 case 0x1b: /* FMULX */
6841 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6843 case 0x1c: /* FCMEQ */
6844 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6846 case 0x1e: /* FMAX */
6847 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6849 case 0x1f: /* FRECPS */
6850 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6852 case 0x38: /* FMINNM */
6853 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6855 case 0x3a: /* FSUB */
6856 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6858 case 0x3e: /* FMIN */
6859 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6861 case 0x3f: /* FRSQRTS */
6862 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6864 case 0x5b: /* FMUL */
6865 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6867 case 0x5c: /* FCMGE */
6868 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6870 case 0x5d: /* FACGE */
6871 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6873 case 0x5f: /* FDIV */
6874 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6876 case 0x7a: /* FABD */
6877 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6878 gen_helper_vfp_absd(tcg_res
, tcg_res
);
6880 case 0x7c: /* FCMGT */
6881 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6883 case 0x7d: /* FACGT */
6884 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6887 g_assert_not_reached();
6890 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
6892 tcg_temp_free_i64(tcg_res
);
6893 tcg_temp_free_i64(tcg_op1
);
6894 tcg_temp_free_i64(tcg_op2
);
6897 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
6898 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
6899 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6901 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
6902 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
6905 case 0x39: /* FMLS */
6906 /* As usual for ARM, separate negation for fused multiply-add */
6907 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6909 case 0x19: /* FMLA */
6910 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6911 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
6914 case 0x1a: /* FADD */
6915 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6917 case 0x1b: /* FMULX */
6918 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6920 case 0x1c: /* FCMEQ */
6921 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6923 case 0x1e: /* FMAX */
6924 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6926 case 0x1f: /* FRECPS */
6927 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6929 case 0x18: /* FMAXNM */
6930 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6932 case 0x38: /* FMINNM */
6933 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6935 case 0x3a: /* FSUB */
6936 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6938 case 0x3e: /* FMIN */
6939 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6941 case 0x3f: /* FRSQRTS */
6942 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6944 case 0x5b: /* FMUL */
6945 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6947 case 0x5c: /* FCMGE */
6948 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6950 case 0x5d: /* FACGE */
6951 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6953 case 0x5f: /* FDIV */
6954 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6956 case 0x7a: /* FABD */
6957 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6958 gen_helper_vfp_abss(tcg_res
, tcg_res
);
6960 case 0x7c: /* FCMGT */
6961 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6963 case 0x7d: /* FACGT */
6964 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6967 g_assert_not_reached();
6970 if (elements
== 1) {
6971 /* scalar single so clear high part */
6972 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6974 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
6975 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
6976 tcg_temp_free_i64(tcg_tmp
);
6978 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
6981 tcg_temp_free_i32(tcg_res
);
6982 tcg_temp_free_i32(tcg_op1
);
6983 tcg_temp_free_i32(tcg_op2
);
6987 tcg_temp_free_ptr(fpst
);
6989 if ((elements
<< size
) < 4) {
6990 /* scalar, or non-quad vector op */
6991 clear_vec_high(s
, rd
);
6995 /* C3.6.11 AdvSIMD scalar three same
6996 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
6997 * +-----+---+-----------+------+---+------+--------+---+------+------+
6998 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
6999 * +-----+---+-----------+------+---+------+--------+---+------+------+
7001 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
7003 int rd
= extract32(insn
, 0, 5);
7004 int rn
= extract32(insn
, 5, 5);
7005 int opcode
= extract32(insn
, 11, 5);
7006 int rm
= extract32(insn
, 16, 5);
7007 int size
= extract32(insn
, 22, 2);
7008 bool u
= extract32(insn
, 29, 1);
7011 if (opcode
>= 0x18) {
7012 /* Floating point: U, size[1] and opcode indicate operation */
7013 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
7015 case 0x1b: /* FMULX */
7016 case 0x1f: /* FRECPS */
7017 case 0x3f: /* FRSQRTS */
7018 case 0x5d: /* FACGE */
7019 case 0x7d: /* FACGT */
7020 case 0x1c: /* FCMEQ */
7021 case 0x5c: /* FCMGE */
7022 case 0x7c: /* FCMGT */
7023 case 0x7a: /* FABD */
7026 unallocated_encoding(s
);
7030 if (!fp_access_check(s
)) {
7034 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
7039 case 0x1: /* SQADD, UQADD */
7040 case 0x5: /* SQSUB, UQSUB */
7041 case 0x9: /* SQSHL, UQSHL */
7042 case 0xb: /* SQRSHL, UQRSHL */
7044 case 0x8: /* SSHL, USHL */
7045 case 0xa: /* SRSHL, URSHL */
7046 case 0x6: /* CMGT, CMHI */
7047 case 0x7: /* CMGE, CMHS */
7048 case 0x11: /* CMTST, CMEQ */
7049 case 0x10: /* ADD, SUB (vector) */
7051 unallocated_encoding(s
);
7055 case 0x16: /* SQDMULH, SQRDMULH (vector) */
7056 if (size
!= 1 && size
!= 2) {
7057 unallocated_encoding(s
);
7062 unallocated_encoding(s
);
7066 if (!fp_access_check(s
)) {
7070 tcg_rd
= tcg_temp_new_i64();
7073 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7074 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
7076 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
7077 tcg_temp_free_i64(tcg_rn
);
7078 tcg_temp_free_i64(tcg_rm
);
7080 /* Do a single operation on the lowest element in the vector.
7081 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
7082 * no side effects for all these operations.
7083 * OPTME: special-purpose helpers would avoid doing some
7084 * unnecessary work in the helper for the 8 and 16 bit cases.
7086 NeonGenTwoOpEnvFn
*genenvfn
;
7087 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7088 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
7089 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
7091 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7092 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
7095 case 0x1: /* SQADD, UQADD */
7097 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7098 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
7099 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
7100 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
7102 genenvfn
= fns
[size
][u
];
7105 case 0x5: /* SQSUB, UQSUB */
7107 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7108 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
7109 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
7110 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
7112 genenvfn
= fns
[size
][u
];
7115 case 0x9: /* SQSHL, UQSHL */
7117 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7118 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
7119 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
7120 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
7122 genenvfn
= fns
[size
][u
];
7125 case 0xb: /* SQRSHL, UQRSHL */
7127 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
7128 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
7129 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
7130 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
7132 genenvfn
= fns
[size
][u
];
7135 case 0x16: /* SQDMULH, SQRDMULH */
7137 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
7138 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
7139 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
7141 assert(size
== 1 || size
== 2);
7142 genenvfn
= fns
[size
- 1][u
];
7146 g_assert_not_reached();
7149 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
7150 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
7151 tcg_temp_free_i32(tcg_rd32
);
7152 tcg_temp_free_i32(tcg_rn
);
7153 tcg_temp_free_i32(tcg_rm
);
7156 write_fp_dreg(s
, rd
, tcg_rd
);
7158 tcg_temp_free_i64(tcg_rd
);
7161 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
7162 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
7163 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
7165 /* Handle 64->64 opcodes which are shared between the scalar and
7166 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
7167 * is valid in either group and also the double-precision fp ops.
7168 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
7174 case 0x4: /* CLS, CLZ */
7176 gen_helper_clz64(tcg_rd
, tcg_rn
);
7178 gen_helper_cls64(tcg_rd
, tcg_rn
);
7182 /* This opcode is shared with CNT and RBIT but we have earlier
7183 * enforced that size == 3 if and only if this is the NOT insn.
7185 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
7187 case 0x7: /* SQABS, SQNEG */
7189 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
7191 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
7194 case 0xa: /* CMLT */
7195 /* 64 bit integer comparison against zero, result is
7196 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
7201 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
7202 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
7204 case 0x8: /* CMGT, CMGE */
7205 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
7207 case 0x9: /* CMEQ, CMLE */
7208 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
7210 case 0xb: /* ABS, NEG */
7212 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7214 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7215 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
7216 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
7218 tcg_temp_free_i64(tcg_zero
);
7221 case 0x2f: /* FABS */
7222 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
7224 case 0x6f: /* FNEG */
7225 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
7227 case 0x7f: /* FSQRT */
7228 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
7230 case 0x1a: /* FCVTNS */
7231 case 0x1b: /* FCVTMS */
7232 case 0x1c: /* FCVTAS */
7233 case 0x3a: /* FCVTPS */
7234 case 0x3b: /* FCVTZS */
7236 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7237 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7238 tcg_temp_free_i32(tcg_shift
);
7241 case 0x5a: /* FCVTNU */
7242 case 0x5b: /* FCVTMU */
7243 case 0x5c: /* FCVTAU */
7244 case 0x7a: /* FCVTPU */
7245 case 0x7b: /* FCVTZU */
7247 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7248 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7249 tcg_temp_free_i32(tcg_shift
);
7252 case 0x18: /* FRINTN */
7253 case 0x19: /* FRINTM */
7254 case 0x38: /* FRINTP */
7255 case 0x39: /* FRINTZ */
7256 case 0x58: /* FRINTA */
7257 case 0x79: /* FRINTI */
7258 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7260 case 0x59: /* FRINTX */
7261 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
7264 g_assert_not_reached();
7268 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
7269 bool is_scalar
, bool is_u
, bool is_q
,
7270 int size
, int rn
, int rd
)
7272 bool is_double
= (size
== 3);
7275 if (!fp_access_check(s
)) {
7279 fpst
= get_fpstatus_ptr();
7282 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7283 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7284 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7285 NeonGenTwoDoubleOPFn
*genfn
;
7290 case 0x2e: /* FCMLT (zero) */
7293 case 0x2c: /* FCMGT (zero) */
7294 genfn
= gen_helper_neon_cgt_f64
;
7296 case 0x2d: /* FCMEQ (zero) */
7297 genfn
= gen_helper_neon_ceq_f64
;
7299 case 0x6d: /* FCMLE (zero) */
7302 case 0x6c: /* FCMGE (zero) */
7303 genfn
= gen_helper_neon_cge_f64
;
7306 g_assert_not_reached();
7309 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7310 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7312 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7314 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7316 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7319 clear_vec_high(s
, rd
);
7322 tcg_temp_free_i64(tcg_res
);
7323 tcg_temp_free_i64(tcg_zero
);
7324 tcg_temp_free_i64(tcg_op
);
7326 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7327 TCGv_i32 tcg_zero
= tcg_const_i32(0);
7328 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7329 NeonGenTwoSingleOPFn
*genfn
;
7331 int pass
, maxpasses
;
7334 case 0x2e: /* FCMLT (zero) */
7337 case 0x2c: /* FCMGT (zero) */
7338 genfn
= gen_helper_neon_cgt_f32
;
7340 case 0x2d: /* FCMEQ (zero) */
7341 genfn
= gen_helper_neon_ceq_f32
;
7343 case 0x6d: /* FCMLE (zero) */
7346 case 0x6c: /* FCMGE (zero) */
7347 genfn
= gen_helper_neon_cge_f32
;
7350 g_assert_not_reached();
7356 maxpasses
= is_q
? 4 : 2;
7359 for (pass
= 0; pass
< maxpasses
; pass
++) {
7360 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7362 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
7364 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
7367 write_fp_sreg(s
, rd
, tcg_res
);
7369 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7372 tcg_temp_free_i32(tcg_res
);
7373 tcg_temp_free_i32(tcg_zero
);
7374 tcg_temp_free_i32(tcg_op
);
7375 if (!is_q
&& !is_scalar
) {
7376 clear_vec_high(s
, rd
);
7380 tcg_temp_free_ptr(fpst
);
7383 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
7384 bool is_scalar
, bool is_u
, bool is_q
,
7385 int size
, int rn
, int rd
)
7387 bool is_double
= (size
== 3);
7388 TCGv_ptr fpst
= get_fpstatus_ptr();
7391 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7392 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7395 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7396 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7398 case 0x3d: /* FRECPE */
7399 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
7401 case 0x3f: /* FRECPX */
7402 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
7404 case 0x7d: /* FRSQRTE */
7405 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
7408 g_assert_not_reached();
7410 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
7413 clear_vec_high(s
, rd
);
7416 tcg_temp_free_i64(tcg_res
);
7417 tcg_temp_free_i64(tcg_op
);
7419 TCGv_i32 tcg_op
= tcg_temp_new_i32();
7420 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7421 int pass
, maxpasses
;
7426 maxpasses
= is_q
? 4 : 2;
7429 for (pass
= 0; pass
< maxpasses
; pass
++) {
7430 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
7433 case 0x3c: /* URECPE */
7434 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
7436 case 0x3d: /* FRECPE */
7437 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
7439 case 0x3f: /* FRECPX */
7440 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
7442 case 0x7d: /* FRSQRTE */
7443 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
7446 g_assert_not_reached();
7450 write_fp_sreg(s
, rd
, tcg_res
);
7452 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
7455 tcg_temp_free_i32(tcg_res
);
7456 tcg_temp_free_i32(tcg_op
);
7457 if (!is_q
&& !is_scalar
) {
7458 clear_vec_high(s
, rd
);
7461 tcg_temp_free_ptr(fpst
);
7464 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
7465 int opcode
, bool u
, bool is_q
,
7466 int size
, int rn
, int rd
)
7468 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
7469 * in the source becomes a size element in the destination).
7472 TCGv_i32 tcg_res
[2];
7473 int destelt
= is_q
? 2 : 0;
7474 int passes
= scalar
? 1 : 2;
7477 tcg_res
[1] = tcg_const_i32(0);
7480 for (pass
= 0; pass
< passes
; pass
++) {
7481 TCGv_i64 tcg_op
= tcg_temp_new_i64();
7482 NeonGenNarrowFn
*genfn
= NULL
;
7483 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
7486 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
7488 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
7490 tcg_res
[pass
] = tcg_temp_new_i32();
7493 case 0x12: /* XTN, SQXTUN */
7495 static NeonGenNarrowFn
* const xtnfns
[3] = {
7496 gen_helper_neon_narrow_u8
,
7497 gen_helper_neon_narrow_u16
,
7498 tcg_gen_trunc_i64_i32
,
7500 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
7501 gen_helper_neon_unarrow_sat8
,
7502 gen_helper_neon_unarrow_sat16
,
7503 gen_helper_neon_unarrow_sat32
,
7506 genenvfn
= sqxtunfns
[size
];
7508 genfn
= xtnfns
[size
];
7512 case 0x14: /* SQXTN, UQXTN */
7514 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
7515 { gen_helper_neon_narrow_sat_s8
,
7516 gen_helper_neon_narrow_sat_u8
},
7517 { gen_helper_neon_narrow_sat_s16
,
7518 gen_helper_neon_narrow_sat_u16
},
7519 { gen_helper_neon_narrow_sat_s32
,
7520 gen_helper_neon_narrow_sat_u32
},
7522 genenvfn
= fns
[size
][u
];
7525 case 0x16: /* FCVTN, FCVTN2 */
7526 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
7528 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
7530 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
7531 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
7532 tcg_gen_trunc_i64_i32(tcg_lo
, tcg_op
);
7533 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, cpu_env
);
7534 tcg_gen_shri_i64(tcg_op
, tcg_op
, 32);
7535 tcg_gen_trunc_i64_i32(tcg_hi
, tcg_op
);
7536 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, cpu_env
);
7537 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
7538 tcg_temp_free_i32(tcg_lo
);
7539 tcg_temp_free_i32(tcg_hi
);
7542 case 0x56: /* FCVTXN, FCVTXN2 */
7543 /* 64 bit to 32 bit float conversion
7544 * with von Neumann rounding (round to odd)
7547 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
7550 g_assert_not_reached();
7554 genfn(tcg_res
[pass
], tcg_op
);
7555 } else if (genenvfn
) {
7556 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
7559 tcg_temp_free_i64(tcg_op
);
7562 for (pass
= 0; pass
< 2; pass
++) {
7563 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
7564 tcg_temp_free_i32(tcg_res
[pass
]);
7567 clear_vec_high(s
, rd
);
7571 /* Remaining saturating accumulating ops */
7572 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
7573 bool is_q
, int size
, int rn
, int rd
)
7575 bool is_double
= (size
== 3);
7578 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
7579 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7582 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
7583 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
7584 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7586 if (is_u
) { /* USQADD */
7587 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7588 } else { /* SUQADD */
7589 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7591 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
7594 clear_vec_high(s
, rd
);
7597 tcg_temp_free_i64(tcg_rd
);
7598 tcg_temp_free_i64(tcg_rn
);
7600 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7601 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7602 int pass
, maxpasses
;
7607 maxpasses
= is_q
? 4 : 2;
7610 for (pass
= 0; pass
< maxpasses
; pass
++) {
7612 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
7613 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
7615 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
7616 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7619 if (is_u
) { /* USQADD */
7622 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7625 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7628 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7631 g_assert_not_reached();
7633 } else { /* SUQADD */
7636 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7639 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7642 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
7645 g_assert_not_reached();
7650 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7651 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
7652 tcg_temp_free_i64(tcg_zero
);
7654 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
7658 clear_vec_high(s
, rd
);
7661 tcg_temp_free_i32(tcg_rd
);
7662 tcg_temp_free_i32(tcg_rn
);
7666 /* C3.6.12 AdvSIMD scalar two reg misc
7667 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7668 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7669 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
7670 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7672 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
7674 int rd
= extract32(insn
, 0, 5);
7675 int rn
= extract32(insn
, 5, 5);
7676 int opcode
= extract32(insn
, 12, 5);
7677 int size
= extract32(insn
, 22, 2);
7678 bool u
= extract32(insn
, 29, 1);
7679 bool is_fcvt
= false;
7682 TCGv_ptr tcg_fpstatus
;
7685 case 0x3: /* USQADD / SUQADD*/
7686 if (!fp_access_check(s
)) {
7689 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
7691 case 0x7: /* SQABS / SQNEG */
7693 case 0xa: /* CMLT */
7695 unallocated_encoding(s
);
7699 case 0x8: /* CMGT, CMGE */
7700 case 0x9: /* CMEQ, CMLE */
7701 case 0xb: /* ABS, NEG */
7703 unallocated_encoding(s
);
7707 case 0x12: /* SQXTUN */
7709 unallocated_encoding(s
);
7713 case 0x14: /* SQXTN, UQXTN */
7715 unallocated_encoding(s
);
7718 if (!fp_access_check(s
)) {
7721 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
7726 /* Floating point: U, size[1] and opcode indicate operation;
7727 * size[0] indicates single or double precision.
7729 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
7730 size
= extract32(size
, 0, 1) ? 3 : 2;
7732 case 0x2c: /* FCMGT (zero) */
7733 case 0x2d: /* FCMEQ (zero) */
7734 case 0x2e: /* FCMLT (zero) */
7735 case 0x6c: /* FCMGE (zero) */
7736 case 0x6d: /* FCMLE (zero) */
7737 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
7739 case 0x1d: /* SCVTF */
7740 case 0x5d: /* UCVTF */
7742 bool is_signed
= (opcode
== 0x1d);
7743 if (!fp_access_check(s
)) {
7746 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
7749 case 0x3d: /* FRECPE */
7750 case 0x3f: /* FRECPX */
7751 case 0x7d: /* FRSQRTE */
7752 if (!fp_access_check(s
)) {
7755 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
7757 case 0x1a: /* FCVTNS */
7758 case 0x1b: /* FCVTMS */
7759 case 0x3a: /* FCVTPS */
7760 case 0x3b: /* FCVTZS */
7761 case 0x5a: /* FCVTNU */
7762 case 0x5b: /* FCVTMU */
7763 case 0x7a: /* FCVTPU */
7764 case 0x7b: /* FCVTZU */
7766 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
7768 case 0x1c: /* FCVTAS */
7769 case 0x5c: /* FCVTAU */
7770 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
7772 rmode
= FPROUNDING_TIEAWAY
;
7774 case 0x56: /* FCVTXN, FCVTXN2 */
7776 unallocated_encoding(s
);
7779 if (!fp_access_check(s
)) {
7782 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
7785 unallocated_encoding(s
);
7790 unallocated_encoding(s
);
7794 if (!fp_access_check(s
)) {
7799 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7800 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7801 tcg_fpstatus
= get_fpstatus_ptr();
7803 TCGV_UNUSED_I32(tcg_rmode
);
7804 TCGV_UNUSED_PTR(tcg_fpstatus
);
7808 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
7809 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
7811 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
7812 write_fp_dreg(s
, rd
, tcg_rd
);
7813 tcg_temp_free_i64(tcg_rd
);
7814 tcg_temp_free_i64(tcg_rn
);
7816 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
7817 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
7819 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
7822 case 0x7: /* SQABS, SQNEG */
7824 NeonGenOneOpEnvFn
*genfn
;
7825 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
7826 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
7827 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
7828 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
7830 genfn
= fns
[size
][u
];
7831 genfn(tcg_rd
, cpu_env
, tcg_rn
);
7834 case 0x1a: /* FCVTNS */
7835 case 0x1b: /* FCVTMS */
7836 case 0x1c: /* FCVTAS */
7837 case 0x3a: /* FCVTPS */
7838 case 0x3b: /* FCVTZS */
7840 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7841 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7842 tcg_temp_free_i32(tcg_shift
);
7845 case 0x5a: /* FCVTNU */
7846 case 0x5b: /* FCVTMU */
7847 case 0x5c: /* FCVTAU */
7848 case 0x7a: /* FCVTPU */
7849 case 0x7b: /* FCVTZU */
7851 TCGv_i32 tcg_shift
= tcg_const_i32(0);
7852 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
7853 tcg_temp_free_i32(tcg_shift
);
7857 g_assert_not_reached();
7860 write_fp_sreg(s
, rd
, tcg_rd
);
7861 tcg_temp_free_i32(tcg_rd
);
7862 tcg_temp_free_i32(tcg_rn
);
7866 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
7867 tcg_temp_free_i32(tcg_rmode
);
7868 tcg_temp_free_ptr(tcg_fpstatus
);
7872 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
7873 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
7874 int immh
, int immb
, int opcode
, int rn
, int rd
)
7876 int size
= 32 - clz32(immh
) - 1;
7877 int immhb
= immh
<< 3 | immb
;
7878 int shift
= 2 * (8 << size
) - immhb
;
7879 bool accumulate
= false;
7881 bool insert
= false;
7882 int dsize
= is_q
? 128 : 64;
7883 int esize
= 8 << size
;
7884 int elements
= dsize
/esize
;
7885 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
7886 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7887 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7891 if (extract32(immh
, 3, 1) && !is_q
) {
7892 unallocated_encoding(s
);
7896 if (size
> 3 && !is_q
) {
7897 unallocated_encoding(s
);
7901 if (!fp_access_check(s
)) {
7906 case 0x02: /* SSRA / USRA (accumulate) */
7909 case 0x04: /* SRSHR / URSHR (rounding) */
7912 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7913 accumulate
= round
= true;
7915 case 0x08: /* SRI */
7921 uint64_t round_const
= 1ULL << (shift
- 1);
7922 tcg_round
= tcg_const_i64(round_const
);
7924 TCGV_UNUSED_I64(tcg_round
);
7927 for (i
= 0; i
< elements
; i
++) {
7928 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
7929 if (accumulate
|| insert
) {
7930 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
7934 handle_shri_with_ins(tcg_rd
, tcg_rn
, size
, shift
);
7936 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7937 accumulate
, is_u
, size
, shift
);
7940 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
7944 clear_vec_high(s
, rd
);
7948 tcg_temp_free_i64(tcg_round
);
7952 /* SHL/SLI - Vector shift left */
7953 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
7954 int immh
, int immb
, int opcode
, int rn
, int rd
)
7956 int size
= 32 - clz32(immh
) - 1;
7957 int immhb
= immh
<< 3 | immb
;
7958 int shift
= immhb
- (8 << size
);
7959 int dsize
= is_q
? 128 : 64;
7960 int esize
= 8 << size
;
7961 int elements
= dsize
/esize
;
7962 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7963 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7966 if (extract32(immh
, 3, 1) && !is_q
) {
7967 unallocated_encoding(s
);
7971 if (size
> 3 && !is_q
) {
7972 unallocated_encoding(s
);
7976 if (!fp_access_check(s
)) {
7980 for (i
= 0; i
< elements
; i
++) {
7981 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
7983 read_vec_element(s
, tcg_rd
, rd
, i
, size
);
7986 handle_shli_with_ins(tcg_rd
, tcg_rn
, insert
, shift
);
7988 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
7992 clear_vec_high(s
, rd
);
7996 /* USHLL/SHLL - Vector shift left with widening */
7997 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
7998 int immh
, int immb
, int opcode
, int rn
, int rd
)
8000 int size
= 32 - clz32(immh
) - 1;
8001 int immhb
= immh
<< 3 | immb
;
8002 int shift
= immhb
- (8 << size
);
8004 int esize
= 8 << size
;
8005 int elements
= dsize
/esize
;
8006 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8007 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8011 unallocated_encoding(s
);
8015 if (!fp_access_check(s
)) {
8019 /* For the LL variants the store is larger than the load,
8020 * so if rd == rn we would overwrite parts of our input.
8021 * So load everything right now and use shifts in the main loop.
8023 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
8025 for (i
= 0; i
< elements
; i
++) {
8026 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
8027 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
8028 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
8029 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
8033 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
8034 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
8035 int immh
, int immb
, int opcode
, int rn
, int rd
)
8037 int immhb
= immh
<< 3 | immb
;
8038 int size
= 32 - clz32(immh
) - 1;
8040 int esize
= 8 << size
;
8041 int elements
= dsize
/esize
;
8042 int shift
= (2 * esize
) - immhb
;
8043 bool round
= extract32(opcode
, 0, 1);
8044 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
8048 if (extract32(immh
, 3, 1)) {
8049 unallocated_encoding(s
);
8053 if (!fp_access_check(s
)) {
8057 tcg_rn
= tcg_temp_new_i64();
8058 tcg_rd
= tcg_temp_new_i64();
8059 tcg_final
= tcg_temp_new_i64();
8060 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
8063 uint64_t round_const
= 1ULL << (shift
- 1);
8064 tcg_round
= tcg_const_i64(round_const
);
8066 TCGV_UNUSED_I64(tcg_round
);
8069 for (i
= 0; i
< elements
; i
++) {
8070 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
8071 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8072 false, true, size
+1, shift
);
8074 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8078 clear_vec_high(s
, rd
);
8079 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8081 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8085 tcg_temp_free_i64(tcg_round
);
8087 tcg_temp_free_i64(tcg_rn
);
8088 tcg_temp_free_i64(tcg_rd
);
8089 tcg_temp_free_i64(tcg_final
);
8094 /* C3.6.14 AdvSIMD shift by immediate
8095 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8096 * +---+---+---+-------------+------+------+--------+---+------+------+
8097 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8098 * +---+---+---+-------------+------+------+--------+---+------+------+
8100 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
8102 int rd
= extract32(insn
, 0, 5);
8103 int rn
= extract32(insn
, 5, 5);
8104 int opcode
= extract32(insn
, 11, 5);
8105 int immb
= extract32(insn
, 16, 3);
8106 int immh
= extract32(insn
, 19, 4);
8107 bool is_u
= extract32(insn
, 29, 1);
8108 bool is_q
= extract32(insn
, 30, 1);
8111 case 0x08: /* SRI */
8113 unallocated_encoding(s
);
8117 case 0x00: /* SSHR / USHR */
8118 case 0x02: /* SSRA / USRA (accumulate) */
8119 case 0x04: /* SRSHR / URSHR (rounding) */
8120 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8121 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8123 case 0x0a: /* SHL / SLI */
8124 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8126 case 0x10: /* SHRN */
8127 case 0x11: /* RSHRN / SQRSHRUN */
8129 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
8132 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
8135 case 0x12: /* SQSHRN / UQSHRN */
8136 case 0x13: /* SQRSHRN / UQRSHRN */
8137 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
8140 case 0x14: /* SSHLL / USHLL */
8141 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8143 case 0x1c: /* SCVTF / UCVTF */
8144 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
8147 case 0xc: /* SQSHLU */
8149 unallocated_encoding(s
);
8152 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
8154 case 0xe: /* SQSHL, UQSHL */
8155 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
8157 case 0x1f: /* FCVTZS/ FCVTZU */
8158 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
8161 unallocated_encoding(s
);
8166 /* Generate code to do a "long" addition or subtraction, ie one done in
8167 * TCGv_i64 on vector lanes twice the width specified by size.
8169 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
8170 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
8172 static NeonGenTwo64OpFn
* const fns
[3][2] = {
8173 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
8174 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
8175 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
8177 NeonGenTwo64OpFn
*genfn
;
8180 genfn
= fns
[size
][is_sub
];
8181 genfn(tcg_res
, tcg_op1
, tcg_op2
);
8184 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
8185 int opcode
, int rd
, int rn
, int rm
)
8187 /* 3-reg-different widening insns: 64 x 64 -> 128 */
8188 TCGv_i64 tcg_res
[2];
8191 tcg_res
[0] = tcg_temp_new_i64();
8192 tcg_res
[1] = tcg_temp_new_i64();
8194 /* Does this op do an adding accumulate, a subtracting accumulate,
8195 * or no accumulate at all?
8213 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8214 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8217 /* size == 2 means two 32x32->64 operations; this is worth special
8218 * casing because we can generally handle it inline.
8221 for (pass
= 0; pass
< 2; pass
++) {
8222 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8223 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8224 TCGv_i64 tcg_passres
;
8225 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
8227 int elt
= pass
+ is_q
* 2;
8229 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
8230 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
8233 tcg_passres
= tcg_res
[pass
];
8235 tcg_passres
= tcg_temp_new_i64();
8239 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8240 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8242 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8243 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8245 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8246 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8248 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
8249 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
8251 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
8252 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
8253 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
8255 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
8256 tcg_temp_free_i64(tcg_tmp1
);
8257 tcg_temp_free_i64(tcg_tmp2
);
8260 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8261 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8262 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8263 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8265 case 9: /* SQDMLAL, SQDMLAL2 */
8266 case 11: /* SQDMLSL, SQDMLSL2 */
8267 case 13: /* SQDMULL, SQDMULL2 */
8268 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
8269 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
8270 tcg_passres
, tcg_passres
);
8273 g_assert_not_reached();
8276 if (opcode
== 9 || opcode
== 11) {
8277 /* saturating accumulate ops */
8279 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
8281 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
8282 tcg_res
[pass
], tcg_passres
);
8283 } else if (accop
> 0) {
8284 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8285 } else if (accop
< 0) {
8286 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
8290 tcg_temp_free_i64(tcg_passres
);
8293 tcg_temp_free_i64(tcg_op1
);
8294 tcg_temp_free_i64(tcg_op2
);
8297 /* size 0 or 1, generally helper functions */
8298 for (pass
= 0; pass
< 2; pass
++) {
8299 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8300 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8301 TCGv_i64 tcg_passres
;
8302 int elt
= pass
+ is_q
* 2;
8304 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
8305 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
8308 tcg_passres
= tcg_res
[pass
];
8310 tcg_passres
= tcg_temp_new_i64();
8314 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8315 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8317 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
8318 static NeonGenWidenFn
* const widenfns
[2][2] = {
8319 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8320 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8322 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8324 widenfn(tcg_op2_64
, tcg_op2
);
8325 widenfn(tcg_passres
, tcg_op1
);
8326 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
8327 tcg_passres
, tcg_op2_64
);
8328 tcg_temp_free_i64(tcg_op2_64
);
8331 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8332 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8335 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8337 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8341 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
8343 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
8347 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8348 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8349 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
8352 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
8354 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
8358 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
8360 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8364 case 9: /* SQDMLAL, SQDMLAL2 */
8365 case 11: /* SQDMLSL, SQDMLSL2 */
8366 case 13: /* SQDMULL, SQDMULL2 */
8368 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
8369 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
8370 tcg_passres
, tcg_passres
);
8372 case 14: /* PMULL */
8374 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
8377 g_assert_not_reached();
8379 tcg_temp_free_i32(tcg_op1
);
8380 tcg_temp_free_i32(tcg_op2
);
8383 if (opcode
== 9 || opcode
== 11) {
8384 /* saturating accumulate ops */
8386 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
8388 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
8392 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
8393 tcg_res
[pass
], tcg_passres
);
8395 tcg_temp_free_i64(tcg_passres
);
8400 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8401 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8402 tcg_temp_free_i64(tcg_res
[0]);
8403 tcg_temp_free_i64(tcg_res
[1]);
8406 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
8407 int opcode
, int rd
, int rn
, int rm
)
8409 TCGv_i64 tcg_res
[2];
8410 int part
= is_q
? 2 : 0;
8413 for (pass
= 0; pass
< 2; pass
++) {
8414 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8415 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8416 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
8417 static NeonGenWidenFn
* const widenfns
[3][2] = {
8418 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
8419 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
8420 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
8422 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
8424 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8425 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
8426 widenfn(tcg_op2_wide
, tcg_op2
);
8427 tcg_temp_free_i32(tcg_op2
);
8428 tcg_res
[pass
] = tcg_temp_new_i64();
8429 gen_neon_addl(size
, (opcode
== 3),
8430 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
8431 tcg_temp_free_i64(tcg_op1
);
8432 tcg_temp_free_i64(tcg_op2_wide
);
8435 for (pass
= 0; pass
< 2; pass
++) {
8436 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8437 tcg_temp_free_i64(tcg_res
[pass
]);
8441 static void do_narrow_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8443 tcg_gen_shri_i64(in
, in
, 32);
8444 tcg_gen_trunc_i64_i32(res
, in
);
8447 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
8449 tcg_gen_addi_i64(in
, in
, 1U << 31);
8450 do_narrow_high_u32(res
, in
);
8453 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
8454 int opcode
, int rd
, int rn
, int rm
)
8456 TCGv_i32 tcg_res
[2];
8457 int part
= is_q
? 2 : 0;
8460 for (pass
= 0; pass
< 2; pass
++) {
8461 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8462 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8463 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
8464 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
8465 { gen_helper_neon_narrow_high_u8
,
8466 gen_helper_neon_narrow_round_high_u8
},
8467 { gen_helper_neon_narrow_high_u16
,
8468 gen_helper_neon_narrow_round_high_u16
},
8469 { do_narrow_high_u32
, do_narrow_round_high_u32
},
8471 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
8473 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8474 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8476 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
8478 tcg_temp_free_i64(tcg_op1
);
8479 tcg_temp_free_i64(tcg_op2
);
8481 tcg_res
[pass
] = tcg_temp_new_i32();
8482 gennarrow(tcg_res
[pass
], tcg_wideres
);
8483 tcg_temp_free_i64(tcg_wideres
);
8486 for (pass
= 0; pass
< 2; pass
++) {
8487 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
8488 tcg_temp_free_i32(tcg_res
[pass
]);
8491 clear_vec_high(s
, rd
);
8495 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
8497 /* PMULL of 64 x 64 -> 128 is an odd special case because it
8498 * is the only three-reg-diff instruction which produces a
8499 * 128-bit wide result from a single operation. However since
8500 * it's possible to calculate the two halves more or less
8501 * separately we just use two helper calls.
8503 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8504 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8505 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8507 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
8508 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
8509 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
8510 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
8511 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
8512 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
8514 tcg_temp_free_i64(tcg_op1
);
8515 tcg_temp_free_i64(tcg_op2
);
8516 tcg_temp_free_i64(tcg_res
);
8519 /* C3.6.15 AdvSIMD three different
8520 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8521 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8522 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8523 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
8525 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8527 /* Instructions in this group fall into three basic classes
8528 * (in each case with the operation working on each element in
8529 * the input vectors):
8530 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
8532 * (2) wide 64 x 128 -> 128
8533 * (3) narrowing 128 x 128 -> 64
8534 * Here we do initial decode, catch unallocated cases and
8535 * dispatch to separate functions for each class.
8537 int is_q
= extract32(insn
, 30, 1);
8538 int is_u
= extract32(insn
, 29, 1);
8539 int size
= extract32(insn
, 22, 2);
8540 int opcode
= extract32(insn
, 12, 4);
8541 int rm
= extract32(insn
, 16, 5);
8542 int rn
= extract32(insn
, 5, 5);
8543 int rd
= extract32(insn
, 0, 5);
8546 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
8547 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
8548 /* 64 x 128 -> 128 */
8550 unallocated_encoding(s
);
8553 if (!fp_access_check(s
)) {
8556 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8558 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
8559 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
8560 /* 128 x 128 -> 64 */
8562 unallocated_encoding(s
);
8565 if (!fp_access_check(s
)) {
8568 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8570 case 14: /* PMULL, PMULL2 */
8571 if (is_u
|| size
== 1 || size
== 2) {
8572 unallocated_encoding(s
);
8576 if (!arm_dc_feature(s
, ARM_FEATURE_V8_AES
)) {
8577 unallocated_encoding(s
);
8580 if (!fp_access_check(s
)) {
8583 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
8587 case 9: /* SQDMLAL, SQDMLAL2 */
8588 case 11: /* SQDMLSL, SQDMLSL2 */
8589 case 13: /* SQDMULL, SQDMULL2 */
8590 if (is_u
|| size
== 0) {
8591 unallocated_encoding(s
);
8595 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
8596 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
8597 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
8598 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
8599 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
8600 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
8601 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
8602 /* 64 x 64 -> 128 */
8604 unallocated_encoding(s
);
8608 if (!fp_access_check(s
)) {
8612 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
8615 /* opcode 15 not allocated */
8616 unallocated_encoding(s
);
8621 /* Logic op (opcode == 3) subgroup of C3.6.16. */
8622 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
8624 int rd
= extract32(insn
, 0, 5);
8625 int rn
= extract32(insn
, 5, 5);
8626 int rm
= extract32(insn
, 16, 5);
8627 int size
= extract32(insn
, 22, 2);
8628 bool is_u
= extract32(insn
, 29, 1);
8629 bool is_q
= extract32(insn
, 30, 1);
8630 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
8633 if (!fp_access_check(s
)) {
8637 tcg_op1
= tcg_temp_new_i64();
8638 tcg_op2
= tcg_temp_new_i64();
8639 tcg_res
[0] = tcg_temp_new_i64();
8640 tcg_res
[1] = tcg_temp_new_i64();
8642 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
8643 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8644 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8649 tcg_gen_and_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8652 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8655 tcg_gen_or_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8658 tcg_gen_orc_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8663 /* B* ops need res loaded to operate on */
8664 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8669 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8671 case 1: /* BSL bitwise select */
8672 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8673 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8674 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op1
);
8676 case 2: /* BIT, bitwise insert if true */
8677 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8678 tcg_gen_and_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8679 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8681 case 3: /* BIF, bitwise insert if false */
8682 tcg_gen_xor_i64(tcg_op1
, tcg_op1
, tcg_res
[pass
]);
8683 tcg_gen_andc_i64(tcg_op1
, tcg_op1
, tcg_op2
);
8684 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
8690 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
8692 tcg_gen_movi_i64(tcg_res
[1], 0);
8694 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
8696 tcg_temp_free_i64(tcg_op1
);
8697 tcg_temp_free_i64(tcg_op2
);
8698 tcg_temp_free_i64(tcg_res
[0]);
8699 tcg_temp_free_i64(tcg_res
[1]);
8702 /* Helper functions for 32 bit comparisons */
8703 static void gen_max_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8705 tcg_gen_movcond_i32(TCG_COND_GE
, res
, op1
, op2
, op1
, op2
);
8708 static void gen_max_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8710 tcg_gen_movcond_i32(TCG_COND_GEU
, res
, op1
, op2
, op1
, op2
);
8713 static void gen_min_s32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8715 tcg_gen_movcond_i32(TCG_COND_LE
, res
, op1
, op2
, op1
, op2
);
8718 static void gen_min_u32(TCGv_i32 res
, TCGv_i32 op1
, TCGv_i32 op2
)
8720 tcg_gen_movcond_i32(TCG_COND_LEU
, res
, op1
, op2
, op1
, op2
);
8723 /* Pairwise op subgroup of C3.6.16.
8725 * This is called directly or via the handle_3same_float for float pairwise
8726 * operations where the opcode and size are calculated differently.
8728 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
8729 int size
, int rn
, int rm
, int rd
)
8734 /* Floating point operations need fpst */
8735 if (opcode
>= 0x58) {
8736 fpst
= get_fpstatus_ptr();
8738 TCGV_UNUSED_PTR(fpst
);
8741 if (!fp_access_check(s
)) {
8745 /* These operations work on the concatenated rm:rn, with each pair of
8746 * adjacent elements being operated on to produce an element in the result.
8749 TCGv_i64 tcg_res
[2];
8751 for (pass
= 0; pass
< 2; pass
++) {
8752 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8753 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8754 int passreg
= (pass
== 0) ? rn
: rm
;
8756 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
8757 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
8758 tcg_res
[pass
] = tcg_temp_new_i64();
8761 case 0x17: /* ADDP */
8762 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8764 case 0x58: /* FMAXNMP */
8765 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8767 case 0x5a: /* FADDP */
8768 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8770 case 0x5e: /* FMAXP */
8771 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8773 case 0x78: /* FMINNMP */
8774 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8776 case 0x7e: /* FMINP */
8777 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8780 g_assert_not_reached();
8783 tcg_temp_free_i64(tcg_op1
);
8784 tcg_temp_free_i64(tcg_op2
);
8787 for (pass
= 0; pass
< 2; pass
++) {
8788 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
8789 tcg_temp_free_i64(tcg_res
[pass
]);
8792 int maxpass
= is_q
? 4 : 2;
8793 TCGv_i32 tcg_res
[4];
8795 for (pass
= 0; pass
< maxpass
; pass
++) {
8796 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8797 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8798 NeonGenTwoOpFn
*genfn
= NULL
;
8799 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
8800 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
8802 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
8803 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
8804 tcg_res
[pass
] = tcg_temp_new_i32();
8807 case 0x17: /* ADDP */
8809 static NeonGenTwoOpFn
* const fns
[3] = {
8810 gen_helper_neon_padd_u8
,
8811 gen_helper_neon_padd_u16
,
8817 case 0x14: /* SMAXP, UMAXP */
8819 static NeonGenTwoOpFn
* const fns
[3][2] = {
8820 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
8821 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
8822 { gen_max_s32
, gen_max_u32
},
8824 genfn
= fns
[size
][u
];
8827 case 0x15: /* SMINP, UMINP */
8829 static NeonGenTwoOpFn
* const fns
[3][2] = {
8830 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
8831 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
8832 { gen_min_s32
, gen_min_u32
},
8834 genfn
= fns
[size
][u
];
8837 /* The FP operations are all on single floats (32 bit) */
8838 case 0x58: /* FMAXNMP */
8839 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8841 case 0x5a: /* FADDP */
8842 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8844 case 0x5e: /* FMAXP */
8845 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8847 case 0x78: /* FMINNMP */
8848 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8850 case 0x7e: /* FMINP */
8851 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
8854 g_assert_not_reached();
8857 /* FP ops called directly, otherwise call now */
8859 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
8862 tcg_temp_free_i32(tcg_op1
);
8863 tcg_temp_free_i32(tcg_op2
);
8866 for (pass
= 0; pass
< maxpass
; pass
++) {
8867 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
8868 tcg_temp_free_i32(tcg_res
[pass
]);
8871 clear_vec_high(s
, rd
);
8875 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
8876 tcg_temp_free_ptr(fpst
);
8880 /* Floating point op subgroup of C3.6.16. */
8881 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
8883 /* For floating point ops, the U, size[1] and opcode bits
8884 * together indicate the operation. size[0] indicates single
8887 int fpopcode
= extract32(insn
, 11, 5)
8888 | (extract32(insn
, 23, 1) << 5)
8889 | (extract32(insn
, 29, 1) << 6);
8890 int is_q
= extract32(insn
, 30, 1);
8891 int size
= extract32(insn
, 22, 1);
8892 int rm
= extract32(insn
, 16, 5);
8893 int rn
= extract32(insn
, 5, 5);
8894 int rd
= extract32(insn
, 0, 5);
8896 int datasize
= is_q
? 128 : 64;
8897 int esize
= 32 << size
;
8898 int elements
= datasize
/ esize
;
8900 if (size
== 1 && !is_q
) {
8901 unallocated_encoding(s
);
8906 case 0x58: /* FMAXNMP */
8907 case 0x5a: /* FADDP */
8908 case 0x5e: /* FMAXP */
8909 case 0x78: /* FMINNMP */
8910 case 0x7e: /* FMINP */
8911 if (size
&& !is_q
) {
8912 unallocated_encoding(s
);
8915 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
8918 case 0x1b: /* FMULX */
8919 case 0x1f: /* FRECPS */
8920 case 0x3f: /* FRSQRTS */
8921 case 0x5d: /* FACGE */
8922 case 0x7d: /* FACGT */
8923 case 0x19: /* FMLA */
8924 case 0x39: /* FMLS */
8925 case 0x18: /* FMAXNM */
8926 case 0x1a: /* FADD */
8927 case 0x1c: /* FCMEQ */
8928 case 0x1e: /* FMAX */
8929 case 0x38: /* FMINNM */
8930 case 0x3a: /* FSUB */
8931 case 0x3e: /* FMIN */
8932 case 0x5b: /* FMUL */
8933 case 0x5c: /* FCMGE */
8934 case 0x5f: /* FDIV */
8935 case 0x7a: /* FABD */
8936 case 0x7c: /* FCMGT */
8937 if (!fp_access_check(s
)) {
8941 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
8944 unallocated_encoding(s
);
8949 /* Integer op subgroup of C3.6.16. */
8950 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
8952 int is_q
= extract32(insn
, 30, 1);
8953 int u
= extract32(insn
, 29, 1);
8954 int size
= extract32(insn
, 22, 2);
8955 int opcode
= extract32(insn
, 11, 5);
8956 int rm
= extract32(insn
, 16, 5);
8957 int rn
= extract32(insn
, 5, 5);
8958 int rd
= extract32(insn
, 0, 5);
8962 case 0x13: /* MUL, PMUL */
8963 if (u
&& size
!= 0) {
8964 unallocated_encoding(s
);
8968 case 0x0: /* SHADD, UHADD */
8969 case 0x2: /* SRHADD, URHADD */
8970 case 0x4: /* SHSUB, UHSUB */
8971 case 0xc: /* SMAX, UMAX */
8972 case 0xd: /* SMIN, UMIN */
8973 case 0xe: /* SABD, UABD */
8974 case 0xf: /* SABA, UABA */
8975 case 0x12: /* MLA, MLS */
8977 unallocated_encoding(s
);
8981 case 0x16: /* SQDMULH, SQRDMULH */
8982 if (size
== 0 || size
== 3) {
8983 unallocated_encoding(s
);
8988 if (size
== 3 && !is_q
) {
8989 unallocated_encoding(s
);
8995 if (!fp_access_check(s
)) {
9000 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9001 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9002 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9003 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9005 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9006 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9008 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
9010 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9012 tcg_temp_free_i64(tcg_res
);
9013 tcg_temp_free_i64(tcg_op1
);
9014 tcg_temp_free_i64(tcg_op2
);
9017 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9018 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9019 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9020 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9021 NeonGenTwoOpFn
*genfn
= NULL
;
9022 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
9024 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9025 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9028 case 0x0: /* SHADD, UHADD */
9030 static NeonGenTwoOpFn
* const fns
[3][2] = {
9031 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
9032 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
9033 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
9035 genfn
= fns
[size
][u
];
9038 case 0x1: /* SQADD, UQADD */
9040 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9041 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9042 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9043 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9045 genenvfn
= fns
[size
][u
];
9048 case 0x2: /* SRHADD, URHADD */
9050 static NeonGenTwoOpFn
* const fns
[3][2] = {
9051 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
9052 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
9053 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
9055 genfn
= fns
[size
][u
];
9058 case 0x4: /* SHSUB, UHSUB */
9060 static NeonGenTwoOpFn
* const fns
[3][2] = {
9061 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
9062 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
9063 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
9065 genfn
= fns
[size
][u
];
9068 case 0x5: /* SQSUB, UQSUB */
9070 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9071 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9072 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9073 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9075 genenvfn
= fns
[size
][u
];
9078 case 0x6: /* CMGT, CMHI */
9080 static NeonGenTwoOpFn
* const fns
[3][2] = {
9081 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_u8
},
9082 { gen_helper_neon_cgt_s16
, gen_helper_neon_cgt_u16
},
9083 { gen_helper_neon_cgt_s32
, gen_helper_neon_cgt_u32
},
9085 genfn
= fns
[size
][u
];
9088 case 0x7: /* CMGE, CMHS */
9090 static NeonGenTwoOpFn
* const fns
[3][2] = {
9091 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_u8
},
9092 { gen_helper_neon_cge_s16
, gen_helper_neon_cge_u16
},
9093 { gen_helper_neon_cge_s32
, gen_helper_neon_cge_u32
},
9095 genfn
= fns
[size
][u
];
9098 case 0x8: /* SSHL, USHL */
9100 static NeonGenTwoOpFn
* const fns
[3][2] = {
9101 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
9102 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
9103 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
9105 genfn
= fns
[size
][u
];
9108 case 0x9: /* SQSHL, UQSHL */
9110 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9111 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9112 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9113 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9115 genenvfn
= fns
[size
][u
];
9118 case 0xa: /* SRSHL, URSHL */
9120 static NeonGenTwoOpFn
* const fns
[3][2] = {
9121 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
9122 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
9123 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
9125 genfn
= fns
[size
][u
];
9128 case 0xb: /* SQRSHL, UQRSHL */
9130 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9131 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9132 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9133 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9135 genenvfn
= fns
[size
][u
];
9138 case 0xc: /* SMAX, UMAX */
9140 static NeonGenTwoOpFn
* const fns
[3][2] = {
9141 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
9142 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
9143 { gen_max_s32
, gen_max_u32
},
9145 genfn
= fns
[size
][u
];
9149 case 0xd: /* SMIN, UMIN */
9151 static NeonGenTwoOpFn
* const fns
[3][2] = {
9152 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
9153 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
9154 { gen_min_s32
, gen_min_u32
},
9156 genfn
= fns
[size
][u
];
9159 case 0xe: /* SABD, UABD */
9160 case 0xf: /* SABA, UABA */
9162 static NeonGenTwoOpFn
* const fns
[3][2] = {
9163 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
9164 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
9165 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
9167 genfn
= fns
[size
][u
];
9170 case 0x10: /* ADD, SUB */
9172 static NeonGenTwoOpFn
* const fns
[3][2] = {
9173 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9174 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9175 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9177 genfn
= fns
[size
][u
];
9180 case 0x11: /* CMTST, CMEQ */
9182 static NeonGenTwoOpFn
* const fns
[3][2] = {
9183 { gen_helper_neon_tst_u8
, gen_helper_neon_ceq_u8
},
9184 { gen_helper_neon_tst_u16
, gen_helper_neon_ceq_u16
},
9185 { gen_helper_neon_tst_u32
, gen_helper_neon_ceq_u32
},
9187 genfn
= fns
[size
][u
];
9190 case 0x13: /* MUL, PMUL */
9194 genfn
= gen_helper_neon_mul_p8
;
9197 /* fall through : MUL */
9198 case 0x12: /* MLA, MLS */
9200 static NeonGenTwoOpFn
* const fns
[3] = {
9201 gen_helper_neon_mul_u8
,
9202 gen_helper_neon_mul_u16
,
9208 case 0x16: /* SQDMULH, SQRDMULH */
9210 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9211 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9212 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9214 assert(size
== 1 || size
== 2);
9215 genenvfn
= fns
[size
- 1][u
];
9219 g_assert_not_reached();
9223 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
9225 genfn(tcg_res
, tcg_op1
, tcg_op2
);
9228 if (opcode
== 0xf || opcode
== 0x12) {
9229 /* SABA, UABA, MLA, MLS: accumulating ops */
9230 static NeonGenTwoOpFn
* const fns
[3][2] = {
9231 { gen_helper_neon_add_u8
, gen_helper_neon_sub_u8
},
9232 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
9233 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
9235 bool is_sub
= (opcode
== 0x12 && u
); /* MLS */
9237 genfn
= fns
[size
][is_sub
];
9238 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
9239 genfn(tcg_res
, tcg_op1
, tcg_res
);
9242 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9244 tcg_temp_free_i32(tcg_res
);
9245 tcg_temp_free_i32(tcg_op1
);
9246 tcg_temp_free_i32(tcg_op2
);
9251 clear_vec_high(s
, rd
);
9255 /* C3.6.16 AdvSIMD three same
9256 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9257 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9258 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9259 * +---+---+---+-----------+------+---+------+--------+---+------+------+
9261 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
9263 int opcode
= extract32(insn
, 11, 5);
9266 case 0x3: /* logic ops */
9267 disas_simd_3same_logic(s
, insn
);
9269 case 0x17: /* ADDP */
9270 case 0x14: /* SMAXP, UMAXP */
9271 case 0x15: /* SMINP, UMINP */
9273 /* Pairwise operations */
9274 int is_q
= extract32(insn
, 30, 1);
9275 int u
= extract32(insn
, 29, 1);
9276 int size
= extract32(insn
, 22, 2);
9277 int rm
= extract32(insn
, 16, 5);
9278 int rn
= extract32(insn
, 5, 5);
9279 int rd
= extract32(insn
, 0, 5);
9280 if (opcode
== 0x17) {
9281 if (u
|| (size
== 3 && !is_q
)) {
9282 unallocated_encoding(s
);
9287 unallocated_encoding(s
);
9291 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
9295 /* floating point ops, sz[1] and U are part of opcode */
9296 disas_simd_3same_float(s
, insn
);
9299 disas_simd_3same_int(s
, insn
);
9304 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
9305 int size
, int rn
, int rd
)
9307 /* Handle 2-reg-misc ops which are widening (so each size element
9308 * in the source becomes a 2*size element in the destination.
9309 * The only instruction like this is FCVTL.
9314 /* 32 -> 64 bit fp conversion */
9315 TCGv_i64 tcg_res
[2];
9316 int srcelt
= is_q
? 2 : 0;
9318 for (pass
= 0; pass
< 2; pass
++) {
9319 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9320 tcg_res
[pass
] = tcg_temp_new_i64();
9322 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
9323 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
9324 tcg_temp_free_i32(tcg_op
);
9326 for (pass
= 0; pass
< 2; pass
++) {
9327 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9328 tcg_temp_free_i64(tcg_res
[pass
]);
9331 /* 16 -> 32 bit fp conversion */
9332 int srcelt
= is_q
? 4 : 0;
9333 TCGv_i32 tcg_res
[4];
9335 for (pass
= 0; pass
< 4; pass
++) {
9336 tcg_res
[pass
] = tcg_temp_new_i32();
9338 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
9339 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
9342 for (pass
= 0; pass
< 4; pass
++) {
9343 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
9344 tcg_temp_free_i32(tcg_res
[pass
]);
9349 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
9350 bool is_q
, int size
, int rn
, int rd
)
9352 int op
= (opcode
<< 1) | u
;
9353 int opsz
= op
+ size
;
9354 int grp_size
= 3 - opsz
;
9355 int dsize
= is_q
? 128 : 64;
9359 unallocated_encoding(s
);
9363 if (!fp_access_check(s
)) {
9368 /* Special case bytes, use bswap op on each group of elements */
9369 int groups
= dsize
/ (8 << grp_size
);
9371 for (i
= 0; i
< groups
; i
++) {
9372 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9374 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
9377 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
9380 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
9383 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
9386 g_assert_not_reached();
9388 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
9389 tcg_temp_free_i64(tcg_tmp
);
9392 clear_vec_high(s
, rd
);
9395 int revmask
= (1 << grp_size
) - 1;
9396 int esize
= 8 << size
;
9397 int elements
= dsize
/ esize
;
9398 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9399 TCGv_i64 tcg_rd
= tcg_const_i64(0);
9400 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
9402 for (i
= 0; i
< elements
; i
++) {
9403 int e_rev
= (i
& 0xf) ^ revmask
;
9404 int off
= e_rev
* esize
;
9405 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
9407 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
9408 tcg_rn
, off
- 64, esize
);
9410 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
9413 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
9414 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
9416 tcg_temp_free_i64(tcg_rd_hi
);
9417 tcg_temp_free_i64(tcg_rd
);
9418 tcg_temp_free_i64(tcg_rn
);
9422 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
9423 bool is_q
, int size
, int rn
, int rd
)
9425 /* Implement the pairwise operations from 2-misc:
9426 * SADDLP, UADDLP, SADALP, UADALP.
9427 * These all add pairs of elements in the input to produce a
9428 * double-width result element in the output (possibly accumulating).
9430 bool accum
= (opcode
== 0x6);
9431 int maxpass
= is_q
? 2 : 1;
9433 TCGv_i64 tcg_res
[2];
9436 /* 32 + 32 -> 64 op */
9437 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
9439 for (pass
= 0; pass
< maxpass
; pass
++) {
9440 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9441 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9443 tcg_res
[pass
] = tcg_temp_new_i64();
9445 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
9446 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
9447 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
9449 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
9450 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
9453 tcg_temp_free_i64(tcg_op1
);
9454 tcg_temp_free_i64(tcg_op2
);
9457 for (pass
= 0; pass
< maxpass
; pass
++) {
9458 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9459 NeonGenOneOpFn
*genfn
;
9460 static NeonGenOneOpFn
* const fns
[2][2] = {
9461 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
9462 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
9465 genfn
= fns
[size
][u
];
9467 tcg_res
[pass
] = tcg_temp_new_i64();
9469 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9470 genfn(tcg_res
[pass
], tcg_op
);
9473 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9475 gen_helper_neon_addl_u16(tcg_res
[pass
],
9476 tcg_res
[pass
], tcg_op
);
9478 gen_helper_neon_addl_u32(tcg_res
[pass
],
9479 tcg_res
[pass
], tcg_op
);
9482 tcg_temp_free_i64(tcg_op
);
9486 tcg_res
[1] = tcg_const_i64(0);
9488 for (pass
= 0; pass
< 2; pass
++) {
9489 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9490 tcg_temp_free_i64(tcg_res
[pass
]);
9494 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
9496 /* Implement SHLL and SHLL2 */
9498 int part
= is_q
? 2 : 0;
9499 TCGv_i64 tcg_res
[2];
9501 for (pass
= 0; pass
< 2; pass
++) {
9502 static NeonGenWidenFn
* const widenfns
[3] = {
9503 gen_helper_neon_widen_u8
,
9504 gen_helper_neon_widen_u16
,
9505 tcg_gen_extu_i32_i64
,
9507 NeonGenWidenFn
*widenfn
= widenfns
[size
];
9508 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9510 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
9511 tcg_res
[pass
] = tcg_temp_new_i64();
9512 widenfn(tcg_res
[pass
], tcg_op
);
9513 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
9515 tcg_temp_free_i32(tcg_op
);
9518 for (pass
= 0; pass
< 2; pass
++) {
9519 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
9520 tcg_temp_free_i64(tcg_res
[pass
]);
9524 /* C3.6.17 AdvSIMD two reg misc
9525 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9526 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9527 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9528 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
9530 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9532 int size
= extract32(insn
, 22, 2);
9533 int opcode
= extract32(insn
, 12, 5);
9534 bool u
= extract32(insn
, 29, 1);
9535 bool is_q
= extract32(insn
, 30, 1);
9536 int rn
= extract32(insn
, 5, 5);
9537 int rd
= extract32(insn
, 0, 5);
9538 bool need_fpstatus
= false;
9539 bool need_rmode
= false;
9542 TCGv_ptr tcg_fpstatus
;
9545 case 0x0: /* REV64, REV32 */
9546 case 0x1: /* REV16 */
9547 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9549 case 0x5: /* CNT, NOT, RBIT */
9550 if (u
&& size
== 0) {
9551 /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
9554 } else if (u
&& size
== 1) {
9557 } else if (!u
&& size
== 0) {
9561 unallocated_encoding(s
);
9563 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
9564 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
9566 unallocated_encoding(s
);
9569 if (!fp_access_check(s
)) {
9573 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
9575 case 0x4: /* CLS, CLZ */
9577 unallocated_encoding(s
);
9581 case 0x2: /* SADDLP, UADDLP */
9582 case 0x6: /* SADALP, UADALP */
9584 unallocated_encoding(s
);
9587 if (!fp_access_check(s
)) {
9590 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
9592 case 0x13: /* SHLL, SHLL2 */
9593 if (u
== 0 || size
== 3) {
9594 unallocated_encoding(s
);
9597 if (!fp_access_check(s
)) {
9600 handle_shll(s
, is_q
, size
, rn
, rd
);
9602 case 0xa: /* CMLT */
9604 unallocated_encoding(s
);
9608 case 0x8: /* CMGT, CMGE */
9609 case 0x9: /* CMEQ, CMLE */
9610 case 0xb: /* ABS, NEG */
9611 if (size
== 3 && !is_q
) {
9612 unallocated_encoding(s
);
9616 case 0x3: /* SUQADD, USQADD */
9617 if (size
== 3 && !is_q
) {
9618 unallocated_encoding(s
);
9621 if (!fp_access_check(s
)) {
9624 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
9626 case 0x7: /* SQABS, SQNEG */
9627 if (size
== 3 && !is_q
) {
9628 unallocated_encoding(s
);
9636 /* Floating point: U, size[1] and opcode indicate operation;
9637 * size[0] indicates single or double precision.
9639 int is_double
= extract32(size
, 0, 1);
9640 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9641 size
= is_double
? 3 : 2;
9643 case 0x2f: /* FABS */
9644 case 0x6f: /* FNEG */
9645 if (size
== 3 && !is_q
) {
9646 unallocated_encoding(s
);
9650 case 0x1d: /* SCVTF */
9651 case 0x5d: /* UCVTF */
9653 bool is_signed
= (opcode
== 0x1d) ? true : false;
9654 int elements
= is_double
? 2 : is_q
? 4 : 2;
9655 if (is_double
&& !is_q
) {
9656 unallocated_encoding(s
);
9659 if (!fp_access_check(s
)) {
9662 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
9665 case 0x2c: /* FCMGT (zero) */
9666 case 0x2d: /* FCMEQ (zero) */
9667 case 0x2e: /* FCMLT (zero) */
9668 case 0x6c: /* FCMGE (zero) */
9669 case 0x6d: /* FCMLE (zero) */
9670 if (size
== 3 && !is_q
) {
9671 unallocated_encoding(s
);
9674 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9676 case 0x7f: /* FSQRT */
9677 if (size
== 3 && !is_q
) {
9678 unallocated_encoding(s
);
9682 case 0x1a: /* FCVTNS */
9683 case 0x1b: /* FCVTMS */
9684 case 0x3a: /* FCVTPS */
9685 case 0x3b: /* FCVTZS */
9686 case 0x5a: /* FCVTNU */
9687 case 0x5b: /* FCVTMU */
9688 case 0x7a: /* FCVTPU */
9689 case 0x7b: /* FCVTZU */
9690 need_fpstatus
= true;
9692 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9693 if (size
== 3 && !is_q
) {
9694 unallocated_encoding(s
);
9698 case 0x5c: /* FCVTAU */
9699 case 0x1c: /* FCVTAS */
9700 need_fpstatus
= true;
9702 rmode
= FPROUNDING_TIEAWAY
;
9703 if (size
== 3 && !is_q
) {
9704 unallocated_encoding(s
);
9708 case 0x3c: /* URECPE */
9710 unallocated_encoding(s
);
9714 case 0x3d: /* FRECPE */
9715 case 0x7d: /* FRSQRTE */
9716 if (size
== 3 && !is_q
) {
9717 unallocated_encoding(s
);
9720 if (!fp_access_check(s
)) {
9723 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
9725 case 0x56: /* FCVTXN, FCVTXN2 */
9727 unallocated_encoding(s
);
9731 case 0x16: /* FCVTN, FCVTN2 */
9732 /* handle_2misc_narrow does a 2*size -> size operation, but these
9733 * instructions encode the source size rather than dest size.
9735 if (!fp_access_check(s
)) {
9738 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
9740 case 0x17: /* FCVTL, FCVTL2 */
9741 if (!fp_access_check(s
)) {
9744 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
9746 case 0x18: /* FRINTN */
9747 case 0x19: /* FRINTM */
9748 case 0x38: /* FRINTP */
9749 case 0x39: /* FRINTZ */
9751 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9753 case 0x59: /* FRINTX */
9754 case 0x79: /* FRINTI */
9755 need_fpstatus
= true;
9756 if (size
== 3 && !is_q
) {
9757 unallocated_encoding(s
);
9761 case 0x58: /* FRINTA */
9763 rmode
= FPROUNDING_TIEAWAY
;
9764 need_fpstatus
= true;
9765 if (size
== 3 && !is_q
) {
9766 unallocated_encoding(s
);
9770 case 0x7c: /* URSQRTE */
9772 unallocated_encoding(s
);
9775 need_fpstatus
= true;
9778 unallocated_encoding(s
);
9784 unallocated_encoding(s
);
9788 if (!fp_access_check(s
)) {
9792 if (need_fpstatus
) {
9793 tcg_fpstatus
= get_fpstatus_ptr();
9795 TCGV_UNUSED_PTR(tcg_fpstatus
);
9798 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9799 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
9801 TCGV_UNUSED_I32(tcg_rmode
);
9805 /* All 64-bit element operations can be shared with scalar 2misc */
9808 for (pass
= 0; pass
< (is_q
? 2 : 1); pass
++) {
9809 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9810 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9812 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9814 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
9815 tcg_rmode
, tcg_fpstatus
);
9817 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9819 tcg_temp_free_i64(tcg_res
);
9820 tcg_temp_free_i64(tcg_op
);
9825 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
9826 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9827 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9830 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9833 /* Special cases for 32 bit elements */
9835 case 0xa: /* CMLT */
9836 /* 32 bit integer comparison against zero, result is
9837 * test ? (2^32 - 1) : 0. We implement via setcond(test)
9842 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
9843 tcg_gen_neg_i32(tcg_res
, tcg_res
);
9845 case 0x8: /* CMGT, CMGE */
9846 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9848 case 0x9: /* CMEQ, CMLE */
9849 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9853 gen_helper_clz32(tcg_res
, tcg_op
);
9855 gen_helper_cls32(tcg_res
, tcg_op
);
9858 case 0x7: /* SQABS, SQNEG */
9860 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
9862 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
9865 case 0xb: /* ABS, NEG */
9867 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9869 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9870 tcg_gen_neg_i32(tcg_res
, tcg_op
);
9871 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
9872 tcg_zero
, tcg_op
, tcg_res
);
9873 tcg_temp_free_i32(tcg_zero
);
9876 case 0x2f: /* FABS */
9877 gen_helper_vfp_abss(tcg_res
, tcg_op
);
9879 case 0x6f: /* FNEG */
9880 gen_helper_vfp_negs(tcg_res
, tcg_op
);
9882 case 0x7f: /* FSQRT */
9883 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
9885 case 0x1a: /* FCVTNS */
9886 case 0x1b: /* FCVTMS */
9887 case 0x1c: /* FCVTAS */
9888 case 0x3a: /* FCVTPS */
9889 case 0x3b: /* FCVTZS */
9891 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9892 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
9893 tcg_shift
, tcg_fpstatus
);
9894 tcg_temp_free_i32(tcg_shift
);
9897 case 0x5a: /* FCVTNU */
9898 case 0x5b: /* FCVTMU */
9899 case 0x5c: /* FCVTAU */
9900 case 0x7a: /* FCVTPU */
9901 case 0x7b: /* FCVTZU */
9903 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9904 gen_helper_vfp_touls(tcg_res
, tcg_op
,
9905 tcg_shift
, tcg_fpstatus
);
9906 tcg_temp_free_i32(tcg_shift
);
9909 case 0x18: /* FRINTN */
9910 case 0x19: /* FRINTM */
9911 case 0x38: /* FRINTP */
9912 case 0x39: /* FRINTZ */
9913 case 0x58: /* FRINTA */
9914 case 0x79: /* FRINTI */
9915 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
9917 case 0x59: /* FRINTX */
9918 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
9920 case 0x7c: /* URSQRTE */
9921 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
9924 g_assert_not_reached();
9927 /* Use helpers for 8 and 16 bit elements */
9929 case 0x5: /* CNT, RBIT */
9930 /* For these two insns size is part of the opcode specifier
9931 * (handled earlier); they always operate on byte elements.
9934 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
9936 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
9939 case 0x7: /* SQABS, SQNEG */
9941 NeonGenOneOpEnvFn
*genfn
;
9942 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
9943 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9944 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9946 genfn
= fns
[size
][u
];
9947 genfn(tcg_res
, cpu_env
, tcg_op
);
9950 case 0x8: /* CMGT, CMGE */
9951 case 0x9: /* CMEQ, CMLE */
9952 case 0xa: /* CMLT */
9954 static NeonGenTwoOpFn
* const fns
[3][2] = {
9955 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
9956 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
9957 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
9959 NeonGenTwoOpFn
*genfn
;
9962 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9964 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
9965 comp
= (opcode
- 0x8) * 2 + u
;
9966 /* ...but LE, LT are implemented as reverse GE, GT */
9967 reverse
= (comp
> 2);
9971 genfn
= fns
[comp
][size
];
9973 genfn(tcg_res
, tcg_zero
, tcg_op
);
9975 genfn(tcg_res
, tcg_op
, tcg_zero
);
9977 tcg_temp_free_i32(tcg_zero
);
9980 case 0xb: /* ABS, NEG */
9982 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9984 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
9986 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
9988 tcg_temp_free_i32(tcg_zero
);
9991 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
9993 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
9997 case 0x4: /* CLS, CLZ */
10000 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
10002 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
10006 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
10008 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
10013 g_assert_not_reached();
10017 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10019 tcg_temp_free_i32(tcg_res
);
10020 tcg_temp_free_i32(tcg_op
);
10024 clear_vec_high(s
, rd
);
10028 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, cpu_env
);
10029 tcg_temp_free_i32(tcg_rmode
);
10031 if (need_fpstatus
) {
10032 tcg_temp_free_ptr(tcg_fpstatus
);
10036 /* C3.6.13 AdvSIMD scalar x indexed element
10037 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10038 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10039 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10040 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
10041 * C3.6.18 AdvSIMD vector x indexed element
10042 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
10043 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10044 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
10045 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
10047 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
10049 /* This encoding has two kinds of instruction:
10050 * normal, where we perform elt x idxelt => elt for each
10051 * element in the vector
10052 * long, where we perform elt x idxelt and generate a result of
10053 * double the width of the input element
10054 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
10056 bool is_scalar
= extract32(insn
, 28, 1);
10057 bool is_q
= extract32(insn
, 30, 1);
10058 bool u
= extract32(insn
, 29, 1);
10059 int size
= extract32(insn
, 22, 2);
10060 int l
= extract32(insn
, 21, 1);
10061 int m
= extract32(insn
, 20, 1);
10062 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
10063 int rm
= extract32(insn
, 16, 4);
10064 int opcode
= extract32(insn
, 12, 4);
10065 int h
= extract32(insn
, 11, 1);
10066 int rn
= extract32(insn
, 5, 5);
10067 int rd
= extract32(insn
, 0, 5);
10068 bool is_long
= false;
10069 bool is_fp
= false;
10074 case 0x0: /* MLA */
10075 case 0x4: /* MLS */
10076 if (!u
|| is_scalar
) {
10077 unallocated_encoding(s
);
10081 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10082 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10083 case 0xa: /* SMULL, SMULL2, UMULL, UMULL2 */
10085 unallocated_encoding(s
);
10090 case 0x3: /* SQDMLAL, SQDMLAL2 */
10091 case 0x7: /* SQDMLSL, SQDMLSL2 */
10092 case 0xb: /* SQDMULL, SQDMULL2 */
10095 case 0xc: /* SQDMULH */
10096 case 0xd: /* SQRDMULH */
10098 unallocated_encoding(s
);
10102 case 0x8: /* MUL */
10103 if (u
|| is_scalar
) {
10104 unallocated_encoding(s
);
10108 case 0x1: /* FMLA */
10109 case 0x5: /* FMLS */
10111 unallocated_encoding(s
);
10115 case 0x9: /* FMUL, FMULX */
10116 if (!extract32(size
, 1, 1)) {
10117 unallocated_encoding(s
);
10123 unallocated_encoding(s
);
10128 /* low bit of size indicates single/double */
10129 size
= extract32(size
, 0, 1) ? 3 : 2;
10131 index
= h
<< 1 | l
;
10134 unallocated_encoding(s
);
10143 index
= h
<< 2 | l
<< 1 | m
;
10146 index
= h
<< 1 | l
;
10150 unallocated_encoding(s
);
10155 if (!fp_access_check(s
)) {
10160 fpst
= get_fpstatus_ptr();
10162 TCGV_UNUSED_PTR(fpst
);
10166 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10169 assert(is_fp
&& is_q
&& !is_long
);
10171 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
10173 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10174 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10175 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10177 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10180 case 0x5: /* FMLS */
10181 /* As usual for ARM, separate negation for fused multiply-add */
10182 gen_helper_vfp_negd(tcg_op
, tcg_op
);
10184 case 0x1: /* FMLA */
10185 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10186 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10188 case 0x9: /* FMUL, FMULX */
10190 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10192 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10196 g_assert_not_reached();
10199 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10200 tcg_temp_free_i64(tcg_op
);
10201 tcg_temp_free_i64(tcg_res
);
10205 clear_vec_high(s
, rd
);
10208 tcg_temp_free_i64(tcg_idx
);
10209 } else if (!is_long
) {
10210 /* 32 bit floating point, or 16 or 32 bit integer.
10211 * For the 16 bit scalar case we use the usual Neon helpers and
10212 * rely on the fact that 0 op 0 == 0 with no side effects.
10214 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10215 int pass
, maxpasses
;
10220 maxpasses
= is_q
? 4 : 2;
10223 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10225 if (size
== 1 && !is_scalar
) {
10226 /* The simplest way to handle the 16x16 indexed ops is to duplicate
10227 * the index into both halves of the 32 bit tcg_idx and then use
10228 * the usual Neon helpers.
10230 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10233 for (pass
= 0; pass
< maxpasses
; pass
++) {
10234 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10235 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10237 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
10240 case 0x0: /* MLA */
10241 case 0x4: /* MLS */
10242 case 0x8: /* MUL */
10244 static NeonGenTwoOpFn
* const fns
[2][2] = {
10245 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
10246 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
10248 NeonGenTwoOpFn
*genfn
;
10249 bool is_sub
= opcode
== 0x4;
10252 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
10254 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
10256 if (opcode
== 0x8) {
10259 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
10260 genfn
= fns
[size
- 1][is_sub
];
10261 genfn(tcg_res
, tcg_op
, tcg_res
);
10264 case 0x5: /* FMLS */
10265 /* As usual for ARM, separate negation for fused multiply-add */
10266 gen_helper_vfp_negs(tcg_op
, tcg_op
);
10268 case 0x1: /* FMLA */
10269 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10270 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
10272 case 0x9: /* FMUL, FMULX */
10274 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10276 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
10279 case 0xc: /* SQDMULH */
10281 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
10284 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
10288 case 0xd: /* SQRDMULH */
10290 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
10293 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
10298 g_assert_not_reached();
10302 write_fp_sreg(s
, rd
, tcg_res
);
10304 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10307 tcg_temp_free_i32(tcg_op
);
10308 tcg_temp_free_i32(tcg_res
);
10311 tcg_temp_free_i32(tcg_idx
);
10314 clear_vec_high(s
, rd
);
10317 /* long ops: 16x16->32 or 32x32->64 */
10318 TCGv_i64 tcg_res
[2];
10320 bool satop
= extract32(opcode
, 0, 1);
10321 TCGMemOp memop
= MO_32
;
10328 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
10330 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
10332 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10333 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10334 TCGv_i64 tcg_passres
;
10340 passelt
= pass
+ (is_q
* 2);
10343 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
10345 tcg_res
[pass
] = tcg_temp_new_i64();
10347 if (opcode
== 0xa || opcode
== 0xb) {
10348 /* Non-accumulating ops */
10349 tcg_passres
= tcg_res
[pass
];
10351 tcg_passres
= tcg_temp_new_i64();
10354 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
10355 tcg_temp_free_i64(tcg_op
);
10358 /* saturating, doubling */
10359 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10360 tcg_passres
, tcg_passres
);
10363 if (opcode
== 0xa || opcode
== 0xb) {
10367 /* Accumulating op: handle accumulate step */
10368 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10371 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10372 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10374 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10375 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10377 case 0x7: /* SQDMLSL, SQDMLSL2 */
10378 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10380 case 0x3: /* SQDMLAL, SQDMLAL2 */
10381 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10386 g_assert_not_reached();
10388 tcg_temp_free_i64(tcg_passres
);
10390 tcg_temp_free_i64(tcg_idx
);
10393 clear_vec_high(s
, rd
);
10396 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
10399 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
10402 /* The simplest way to handle the 16x16 indexed ops is to
10403 * duplicate the index into both halves of the 32 bit tcg_idx
10404 * and then use the usual Neon helpers.
10406 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
10409 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10410 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10411 TCGv_i64 tcg_passres
;
10414 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10416 read_vec_element_i32(s
, tcg_op
, rn
,
10417 pass
+ (is_q
* 2), MO_32
);
10420 tcg_res
[pass
] = tcg_temp_new_i64();
10422 if (opcode
== 0xa || opcode
== 0xb) {
10423 /* Non-accumulating ops */
10424 tcg_passres
= tcg_res
[pass
];
10426 tcg_passres
= tcg_temp_new_i64();
10429 if (memop
& MO_SIGN
) {
10430 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
10432 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
10435 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10436 tcg_passres
, tcg_passres
);
10438 tcg_temp_free_i32(tcg_op
);
10440 if (opcode
== 0xa || opcode
== 0xb) {
10444 /* Accumulating op: handle accumulate step */
10445 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10448 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10449 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
10452 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10453 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
10456 case 0x7: /* SQDMLSL, SQDMLSL2 */
10457 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10459 case 0x3: /* SQDMLAL, SQDMLAL2 */
10460 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10465 g_assert_not_reached();
10467 tcg_temp_free_i64(tcg_passres
);
10469 tcg_temp_free_i32(tcg_idx
);
10472 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
10477 tcg_res
[1] = tcg_const_i64(0);
10480 for (pass
= 0; pass
< 2; pass
++) {
10481 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10482 tcg_temp_free_i64(tcg_res
[pass
]);
10486 if (!TCGV_IS_UNUSED_PTR(fpst
)) {
10487 tcg_temp_free_ptr(fpst
);
10491 /* C3.6.19 Crypto AES
10492 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10493 * +-----------------+------+-----------+--------+-----+------+------+
10494 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10495 * +-----------------+------+-----------+--------+-----+------+------+
10497 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
10499 unsupported_encoding(s
, insn
);
10502 /* C3.6.20 Crypto three-reg SHA
10503 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
10504 * +-----------------+------+---+------+---+--------+-----+------+------+
10505 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
10506 * +-----------------+------+---+------+---+--------+-----+------+------+
10508 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
10510 unsupported_encoding(s
, insn
);
10513 /* C3.6.21 Crypto two-reg SHA
10514 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
10515 * +-----------------+------+-----------+--------+-----+------+------+
10516 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
10517 * +-----------------+------+-----------+--------+-----+------+------+
10519 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
10521 unsupported_encoding(s
, insn
);
10524 /* C3.6 Data processing - SIMD, inc Crypto
10526 * As the decode gets a little complex we are using a table based
10527 * approach for this part of the decode.
10529 static const AArch64DecodeTable data_proc_simd
[] = {
10530 /* pattern , mask , fn */
10531 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
10532 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
10533 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
10534 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
10535 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
10536 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
10537 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
10538 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
10539 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
10540 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
10541 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
10542 { 0x2e000000, 0xbf208400, disas_simd_ext
},
10543 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
10544 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
10545 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
10546 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
10547 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
10548 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
10549 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
10550 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
10551 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
10552 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
10553 { 0x00000000, 0x00000000, NULL
}
10556 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
10558 /* Note that this is called with all non-FP cases from
10559 * table C3-6 so it must UNDEF for entries not specifically
10560 * allocated to instructions in that table.
10562 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
10566 unallocated_encoding(s
);
10570 /* C3.6 Data processing - SIMD and floating point */
10571 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
10573 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
10574 disas_data_proc_fp(s
, insn
);
10576 /* SIMD, including crypto */
10577 disas_data_proc_simd(s
, insn
);
10581 /* C3.1 A64 instruction index by encoding */
10582 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
10586 insn
= arm_ldl_code(env
, s
->pc
, s
->bswap_code
);
10590 s
->fp_access_checked
= false;
10592 switch (extract32(insn
, 25, 4)) {
10593 case 0x0: case 0x1: case 0x2: case 0x3: /* UNALLOCATED */
10594 unallocated_encoding(s
);
10596 case 0x8: case 0x9: /* Data processing - immediate */
10597 disas_data_proc_imm(s
, insn
);
10599 case 0xa: case 0xb: /* Branch, exception generation and system insns */
10600 disas_b_exc_sys(s
, insn
);
10605 case 0xe: /* Loads and stores */
10606 disas_ldst(s
, insn
);
10609 case 0xd: /* Data processing - register */
10610 disas_data_proc_reg(s
, insn
);
10613 case 0xf: /* Data processing - SIMD and floating point */
10614 disas_data_proc_simd_fp(s
, insn
);
10617 assert(FALSE
); /* all 15 cases should be handled above */
10621 /* if we allocated any temporaries, free them here */
10625 void gen_intermediate_code_internal_a64(ARMCPU
*cpu
,
10626 TranslationBlock
*tb
,
10629 CPUState
*cs
= CPU(cpu
);
10630 CPUARMState
*env
= &cpu
->env
;
10631 DisasContext dc1
, *dc
= &dc1
;
10633 uint16_t *gen_opc_end
;
10635 target_ulong pc_start
;
10636 target_ulong next_page_start
;
10644 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
10646 dc
->is_jmp
= DISAS_NEXT
;
10648 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
10653 dc
->bswap_code
= 0;
10654 dc
->condexec_mask
= 0;
10655 dc
->condexec_cond
= 0;
10656 #if !defined(CONFIG_USER_ONLY)
10657 dc
->user
= (ARM_TBFLAG_AA64_EL(tb
->flags
) == 0);
10659 dc
->cpacr_fpen
= ARM_TBFLAG_AA64_FPEN(tb
->flags
);
10661 dc
->vec_stride
= 0;
10662 dc
->cp_regs
= cpu
->cp_regs
;
10663 dc
->current_pl
= arm_current_pl(env
);
10664 dc
->features
= env
->features
;
10666 init_tmp_a64_array(dc
);
10668 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
10671 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
10672 if (max_insns
== 0) {
10673 max_insns
= CF_COUNT_MASK
;
10678 tcg_clear_temp_count();
10681 if (unlikely(!QTAILQ_EMPTY(&cs
->breakpoints
))) {
10682 QTAILQ_FOREACH(bp
, &cs
->breakpoints
, entry
) {
10683 if (bp
->pc
== dc
->pc
) {
10684 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
10685 /* Advance PC so that clearing the breakpoint will
10686 invalidate this TB. */
10688 goto done_generating
;
10694 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10698 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10701 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
10702 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
10703 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
10706 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
10710 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
10711 tcg_gen_debug_insn_start(dc
->pc
);
10714 disas_a64_insn(env
, dc
);
10716 if (tcg_check_temp_count()) {
10717 fprintf(stderr
, "TCG temporary leak before "TARGET_FMT_lx
"\n",
10721 /* Translation stops when a conditional branch is encountered.
10722 * Otherwise the subsequent code could get translated several times.
10723 * Also stop translation when a page boundary is reached. This
10724 * ensures prefetch aborts occur at the right place.
10727 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
10728 !cs
->singlestep_enabled
&&
10730 dc
->pc
< next_page_start
&&
10731 num_insns
< max_insns
);
10733 if (tb
->cflags
& CF_LAST_IO
) {
10737 if (unlikely(cs
->singlestep_enabled
) && dc
->is_jmp
!= DISAS_EXC
) {
10738 /* Note that this means single stepping WFI doesn't halt the CPU.
10739 * For conditional branch insns this is harmless unreachable code as
10740 * gen_goto_tb() has already handled emitting the debug exception
10741 * (and thus a tb-jump is not possible when singlestepping).
10743 assert(dc
->is_jmp
!= DISAS_TB_JUMP
);
10744 if (dc
->is_jmp
!= DISAS_JUMP
) {
10745 gen_a64_set_pc_im(dc
->pc
);
10747 gen_exception_internal(EXCP_DEBUG
);
10749 switch (dc
->is_jmp
) {
10751 gen_goto_tb(dc
, 1, dc
->pc
);
10755 gen_a64_set_pc_im(dc
->pc
);
10758 /* indicate that the hash table must be used to find the next TB */
10759 tcg_gen_exit_tb(0);
10761 case DISAS_TB_JUMP
:
10766 /* This is a special case because we don't want to just halt the CPU
10767 * if trying to debug across a WFI.
10769 gen_a64_set_pc_im(dc
->pc
);
10770 gen_helper_wfi(cpu_env
);
10776 gen_tb_end(tb
, num_insns
);
10777 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
10780 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
10781 qemu_log("----------------\n");
10782 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
10783 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
,
10784 4 | (dc
->bswap_code
<< 1));
10789 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
10792 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
10795 tb
->size
= dc
->pc
- pc_start
;
10796 tb
->icount
= num_insns
;