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block: Use returned *file in bdrv_co_get_block_status
[qemu.git] / target-m68k / translate.c
blob342c0405593e268362b3a18e4210ae464d9a09b3
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "qemu/log.h"
26 #include "exec/cpu_ldst.h"
27
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
30
31 #include "trace-tcg.h"
32
33
34 //#define DEBUG_DISPATCH 1
35
36 /* Fake floating point. */
37 #define tcg_gen_mov_f64 tcg_gen_mov_i64
38 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
39 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
40
41 #define DEFO32(name, offset) static TCGv QREG_##name;
42 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
43 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
44 #include "qregs.def"
45 #undef DEFO32
46 #undef DEFO64
47 #undef DEFF64
48
49 static TCGv_i32 cpu_halted;
50 static TCGv_i32 cpu_exception_index;
51
52 static TCGv_ptr cpu_env;
53
54 static char cpu_reg_names[3*8*3 + 5*4];
55 static TCGv cpu_dregs[8];
56 static TCGv cpu_aregs[8];
57 static TCGv_i64 cpu_fregs[8];
58 static TCGv_i64 cpu_macc[4];
59
60 #define DREG(insn, pos) cpu_dregs[((insn) >> (pos)) & 7]
61 #define AREG(insn, pos) cpu_aregs[((insn) >> (pos)) & 7]
62 #define FREG(insn, pos) cpu_fregs[((insn) >> (pos)) & 7]
63 #define MACREG(acc) cpu_macc[acc]
64 #define QREG_SP cpu_aregs[7]
65
66 static TCGv NULL_QREG;
67 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
68 /* Used to distinguish stores from bad addressing modes. */
69 static TCGv store_dummy;
70
71 #include "exec/gen-icount.h"
72
73 void m68k_tcg_init(void)
74 {
75 char *p;
76 int i;
77
78 #define DEFO32(name, offset) QREG_##name = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
79 #define DEFO64(name, offset) QREG_##name = tcg_global_mem_new_i64(TCG_AREG0, offsetof(CPUM68KState, offset), #name);
80 #define DEFF64(name, offset) DEFO64(name, offset)
81 #include "qregs.def"
82 #undef DEFO32
83 #undef DEFO64
84 #undef DEFF64
85
86 cpu_halted = tcg_global_mem_new_i32(TCG_AREG0,
87 -offsetof(M68kCPU, env) +
88 offsetof(CPUState, halted), "HALTED");
89 cpu_exception_index = tcg_global_mem_new_i32(TCG_AREG0,
90 -offsetof(M68kCPU, env) +
91 offsetof(CPUState, exception_index),
92 "EXCEPTION");
93
94 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
95
96 p = cpu_reg_names;
97 for (i = 0; i < 8; i++) {
98 sprintf(p, "D%d", i);
99 cpu_dregs[i] = tcg_global_mem_new(TCG_AREG0,
100 offsetof(CPUM68KState, dregs[i]), p);
101 p += 3;
102 sprintf(p, "A%d", i);
103 cpu_aregs[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUM68KState, aregs[i]), p);
105 p += 3;
106 sprintf(p, "F%d", i);
107 cpu_fregs[i] = tcg_global_mem_new_i64(TCG_AREG0,
108 offsetof(CPUM68KState, fregs[i]), p);
109 p += 3;
110 }
111 for (i = 0; i < 4; i++) {
112 sprintf(p, "ACC%d", i);
113 cpu_macc[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUM68KState, macc[i]), p);
115 p += 5;
116 }
117
118 NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL");
119 store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL");
120 }
121
122 /* internal defines */
123 typedef struct DisasContext {
124 CPUM68KState *env;
125 target_ulong insn_pc; /* Start of the current instruction. */
126 target_ulong pc;
127 int is_jmp;
128 int cc_op;
129 int user;
130 uint32_t fpcr;
131 struct TranslationBlock *tb;
132 int singlestep_enabled;
133 TCGv_i64 mactmp;
134 int done_mac;
135 } DisasContext;
136
137 #define DISAS_JUMP_NEXT 4
138
139 #if defined(CONFIG_USER_ONLY)
140 #define IS_USER(s) 1
141 #else
142 #define IS_USER(s) s->user
143 #endif
144
145 /* XXX: move that elsewhere */
146 /* ??? Fix exceptions. */
147 static void *gen_throws_exception;
148 #define gen_last_qop NULL
149
150 #define OS_BYTE 0
151 #define OS_WORD 1
152 #define OS_LONG 2
153 #define OS_SINGLE 4
154 #define OS_DOUBLE 5
155
156 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
157
158 #ifdef DEBUG_DISPATCH
159 #define DISAS_INSN(name) \
160 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
161 uint16_t insn); \
162 static void disas_##name(CPUM68KState *env, DisasContext *s, \
163 uint16_t insn) \
164 { \
165 qemu_log("Dispatch " #name "\n"); \
166 real_disas_##name(s, env, insn); \
167 } \
168 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
169 uint16_t insn)
170 #else
171 #define DISAS_INSN(name) \
172 static void disas_##name(CPUM68KState *env, DisasContext *s, \
173 uint16_t insn)
174 #endif
175
176 /* Generate a load from the specified address. Narrow values are
177 sign extended to full register width. */
178 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
179 {
180 TCGv tmp;
181 int index = IS_USER(s);
182 tmp = tcg_temp_new_i32();
183 switch(opsize) {
184 case OS_BYTE:
185 if (sign)
186 tcg_gen_qemu_ld8s(tmp, addr, index);
187 else
188 tcg_gen_qemu_ld8u(tmp, addr, index);
189 break;
190 case OS_WORD:
191 if (sign)
192 tcg_gen_qemu_ld16s(tmp, addr, index);
193 else
194 tcg_gen_qemu_ld16u(tmp, addr, index);
195 break;
196 case OS_LONG:
197 case OS_SINGLE:
198 tcg_gen_qemu_ld32u(tmp, addr, index);
199 break;
200 default:
201 g_assert_not_reached();
202 }
203 gen_throws_exception = gen_last_qop;
204 return tmp;
205 }
206
207 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
208 {
209 TCGv_i64 tmp;
210 int index = IS_USER(s);
211 tmp = tcg_temp_new_i64();
212 tcg_gen_qemu_ldf64(tmp, addr, index);
213 gen_throws_exception = gen_last_qop;
214 return tmp;
215 }
216
217 /* Generate a store. */
218 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
219 {
220 int index = IS_USER(s);
221 switch(opsize) {
222 case OS_BYTE:
223 tcg_gen_qemu_st8(val, addr, index);
224 break;
225 case OS_WORD:
226 tcg_gen_qemu_st16(val, addr, index);
227 break;
228 case OS_LONG:
229 case OS_SINGLE:
230 tcg_gen_qemu_st32(val, addr, index);
231 break;
232 default:
233 g_assert_not_reached();
234 }
235 gen_throws_exception = gen_last_qop;
236 }
237
238 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
239 {
240 int index = IS_USER(s);
241 tcg_gen_qemu_stf64(val, addr, index);
242 gen_throws_exception = gen_last_qop;
243 }
244
245 typedef enum {
246 EA_STORE,
247 EA_LOADU,
248 EA_LOADS
249 } ea_what;
250
251 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
252 otherwise generate a store. */
253 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
254 ea_what what)
255 {
256 if (what == EA_STORE) {
257 gen_store(s, opsize, addr, val);
258 return store_dummy;
259 } else {
260 return gen_load(s, opsize, addr, what == EA_LOADS);
261 }
262 }
263
264 /* Read a 32-bit immediate constant. */
265 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
266 {
267 uint32_t im;
268 im = ((uint32_t)cpu_lduw_code(env, s->pc)) << 16;
269 s->pc += 2;
270 im |= cpu_lduw_code(env, s->pc);
271 s->pc += 2;
272 return im;
273 }
274
275 /* Calculate and address index. */
276 static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
277 {
278 TCGv add;
279 int scale;
280
281 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
282 if ((ext & 0x800) == 0) {
283 tcg_gen_ext16s_i32(tmp, add);
284 add = tmp;
285 }
286 scale = (ext >> 9) & 3;
287 if (scale != 0) {
288 tcg_gen_shli_i32(tmp, add, scale);
289 add = tmp;
290 }
291 return add;
292 }
293
294 /* Handle a base + index + displacement effective addresss.
295 A NULL_QREG base means pc-relative. */
296 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
297 {
298 uint32_t offset;
299 uint16_t ext;
300 TCGv add;
301 TCGv tmp;
302 uint32_t bd, od;
303
304 offset = s->pc;
305 ext = cpu_lduw_code(env, s->pc);
306 s->pc += 2;
307
308 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
309 return NULL_QREG;
310
311 if (ext & 0x100) {
312 /* full extension word format */
313 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
314 return NULL_QREG;
315
316 if ((ext & 0x30) > 0x10) {
317 /* base displacement */
318 if ((ext & 0x30) == 0x20) {
319 bd = (int16_t)cpu_lduw_code(env, s->pc);
320 s->pc += 2;
321 } else {
322 bd = read_im32(env, s);
323 }
324 } else {
325 bd = 0;
326 }
327 tmp = tcg_temp_new();
328 if ((ext & 0x44) == 0) {
329 /* pre-index */
330 add = gen_addr_index(ext, tmp);
331 } else {
332 add = NULL_QREG;
333 }
334 if ((ext & 0x80) == 0) {
335 /* base not suppressed */
336 if (IS_NULL_QREG(base)) {
337 base = tcg_const_i32(offset + bd);
338 bd = 0;
339 }
340 if (!IS_NULL_QREG(add)) {
341 tcg_gen_add_i32(tmp, add, base);
342 add = tmp;
343 } else {
344 add = base;
345 }
346 }
347 if (!IS_NULL_QREG(add)) {
348 if (bd != 0) {
349 tcg_gen_addi_i32(tmp, add, bd);
350 add = tmp;
351 }
352 } else {
353 add = tcg_const_i32(bd);
354 }
355 if ((ext & 3) != 0) {
356 /* memory indirect */
357 base = gen_load(s, OS_LONG, add, 0);
358 if ((ext & 0x44) == 4) {
359 add = gen_addr_index(ext, tmp);
360 tcg_gen_add_i32(tmp, add, base);
361 add = tmp;
362 } else {
363 add = base;
364 }
365 if ((ext & 3) > 1) {
366 /* outer displacement */
367 if ((ext & 3) == 2) {
368 od = (int16_t)cpu_lduw_code(env, s->pc);
369 s->pc += 2;
370 } else {
371 od = read_im32(env, s);
372 }
373 } else {
374 od = 0;
375 }
376 if (od != 0) {
377 tcg_gen_addi_i32(tmp, add, od);
378 add = tmp;
379 }
380 }
381 } else {
382 /* brief extension word format */
383 tmp = tcg_temp_new();
384 add = gen_addr_index(ext, tmp);
385 if (!IS_NULL_QREG(base)) {
386 tcg_gen_add_i32(tmp, add, base);
387 if ((int8_t)ext)
388 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
389 } else {
390 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
391 }
392 add = tmp;
393 }
394 return add;
395 }
396
397 /* Update the CPU env CC_OP state. */
398 static inline void gen_flush_cc_op(DisasContext *s)
399 {
400 if (s->cc_op != CC_OP_DYNAMIC)
401 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
402 }
403
404 /* Evaluate all the CC flags. */
405 static inline void gen_flush_flags(DisasContext *s)
406 {
407 if (s->cc_op == CC_OP_FLAGS)
408 return;
409 gen_flush_cc_op(s);
410 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
411 s->cc_op = CC_OP_FLAGS;
412 }
413
414 static void gen_logic_cc(DisasContext *s, TCGv val)
415 {
416 tcg_gen_mov_i32(QREG_CC_DEST, val);
417 s->cc_op = CC_OP_LOGIC;
418 }
419
420 static void gen_update_cc_add(TCGv dest, TCGv src)
421 {
422 tcg_gen_mov_i32(QREG_CC_DEST, dest);
423 tcg_gen_mov_i32(QREG_CC_SRC, src);
424 }
425
426 static inline int opsize_bytes(int opsize)
427 {
428 switch (opsize) {
429 case OS_BYTE: return 1;
430 case OS_WORD: return 2;
431 case OS_LONG: return 4;
432 case OS_SINGLE: return 4;
433 case OS_DOUBLE: return 8;
434 default:
435 g_assert_not_reached();
436 }
437 }
438
439 /* Assign value to a register. If the width is less than the register width
440 only the low part of the register is set. */
441 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
442 {
443 TCGv tmp;
444 switch (opsize) {
445 case OS_BYTE:
446 tcg_gen_andi_i32(reg, reg, 0xffffff00);
447 tmp = tcg_temp_new();
448 tcg_gen_ext8u_i32(tmp, val);
449 tcg_gen_or_i32(reg, reg, tmp);
450 break;
451 case OS_WORD:
452 tcg_gen_andi_i32(reg, reg, 0xffff0000);
453 tmp = tcg_temp_new();
454 tcg_gen_ext16u_i32(tmp, val);
455 tcg_gen_or_i32(reg, reg, tmp);
456 break;
457 case OS_LONG:
458 case OS_SINGLE:
459 tcg_gen_mov_i32(reg, val);
460 break;
461 default:
462 g_assert_not_reached();
463 }
464 }
465
466 /* Sign or zero extend a value. */
467 static inline TCGv gen_extend(TCGv val, int opsize, int sign)
468 {
469 TCGv tmp;
470
471 switch (opsize) {
472 case OS_BYTE:
473 tmp = tcg_temp_new();
474 if (sign)
475 tcg_gen_ext8s_i32(tmp, val);
476 else
477 tcg_gen_ext8u_i32(tmp, val);
478 break;
479 case OS_WORD:
480 tmp = tcg_temp_new();
481 if (sign)
482 tcg_gen_ext16s_i32(tmp, val);
483 else
484 tcg_gen_ext16u_i32(tmp, val);
485 break;
486 case OS_LONG:
487 case OS_SINGLE:
488 tmp = val;
489 break;
490 default:
491 g_assert_not_reached();
492 }
493 return tmp;
494 }
495
496 /* Generate code for an "effective address". Does not adjust the base
497 register for autoincrement addressing modes. */
498 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
499 int opsize)
500 {
501 TCGv reg;
502 TCGv tmp;
503 uint16_t ext;
504 uint32_t offset;
505
506 switch ((insn >> 3) & 7) {
507 case 0: /* Data register direct. */
508 case 1: /* Address register direct. */
509 return NULL_QREG;
510 case 2: /* Indirect register */
511 case 3: /* Indirect postincrement. */
512 return AREG(insn, 0);
513 case 4: /* Indirect predecrememnt. */
514 reg = AREG(insn, 0);
515 tmp = tcg_temp_new();
516 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
517 return tmp;
518 case 5: /* Indirect displacement. */
519 reg = AREG(insn, 0);
520 tmp = tcg_temp_new();
521 ext = cpu_lduw_code(env, s->pc);
522 s->pc += 2;
523 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
524 return tmp;
525 case 6: /* Indirect index + displacement. */
526 reg = AREG(insn, 0);
527 return gen_lea_indexed(env, s, reg);
528 case 7: /* Other */
529 switch (insn & 7) {
530 case 0: /* Absolute short. */
531 offset = cpu_ldsw_code(env, s->pc);
532 s->pc += 2;
533 return tcg_const_i32(offset);
534 case 1: /* Absolute long. */
535 offset = read_im32(env, s);
536 return tcg_const_i32(offset);
537 case 2: /* pc displacement */
538 offset = s->pc;
539 offset += cpu_ldsw_code(env, s->pc);
540 s->pc += 2;
541 return tcg_const_i32(offset);
542 case 3: /* pc index+displacement. */
543 return gen_lea_indexed(env, s, NULL_QREG);
544 case 4: /* Immediate. */
545 default:
546 return NULL_QREG;
547 }
548 }
549 /* Should never happen. */
550 return NULL_QREG;
551 }
552
553 /* Helper function for gen_ea. Reuse the computed address between the
554 for read/write operands. */
555 static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
556 uint16_t insn, int opsize, TCGv val,
557 TCGv *addrp, ea_what what)
558 {
559 TCGv tmp;
560
561 if (addrp && what == EA_STORE) {
562 tmp = *addrp;
563 } else {
564 tmp = gen_lea(env, s, insn, opsize);
565 if (IS_NULL_QREG(tmp))
566 return tmp;
567 if (addrp)
568 *addrp = tmp;
569 }
570 return gen_ldst(s, opsize, tmp, val, what);
571 }
572
573 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
574 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
575 ADDRP is non-null for readwrite operands. */
576 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
577 int opsize, TCGv val, TCGv *addrp, ea_what what)
578 {
579 TCGv reg;
580 TCGv result;
581 uint32_t offset;
582
583 switch ((insn >> 3) & 7) {
584 case 0: /* Data register direct. */
585 reg = DREG(insn, 0);
586 if (what == EA_STORE) {
587 gen_partset_reg(opsize, reg, val);
588 return store_dummy;
589 } else {
590 return gen_extend(reg, opsize, what == EA_LOADS);
591 }
592 case 1: /* Address register direct. */
593 reg = AREG(insn, 0);
594 if (what == EA_STORE) {
595 tcg_gen_mov_i32(reg, val);
596 return store_dummy;
597 } else {
598 return gen_extend(reg, opsize, what == EA_LOADS);
599 }
600 case 2: /* Indirect register */
601 reg = AREG(insn, 0);
602 return gen_ldst(s, opsize, reg, val, what);
603 case 3: /* Indirect postincrement. */
604 reg = AREG(insn, 0);
605 result = gen_ldst(s, opsize, reg, val, what);
606 /* ??? This is not exception safe. The instruction may still
607 fault after this point. */
608 if (what == EA_STORE || !addrp)
609 tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
610 return result;
611 case 4: /* Indirect predecrememnt. */
612 {
613 TCGv tmp;
614 if (addrp && what == EA_STORE) {
615 tmp = *addrp;
616 } else {
617 tmp = gen_lea(env, s, insn, opsize);
618 if (IS_NULL_QREG(tmp))
619 return tmp;
620 if (addrp)
621 *addrp = tmp;
622 }
623 result = gen_ldst(s, opsize, tmp, val, what);
624 /* ??? This is not exception safe. The instruction may still
625 fault after this point. */
626 if (what == EA_STORE || !addrp) {
627 reg = AREG(insn, 0);
628 tcg_gen_mov_i32(reg, tmp);
629 }
630 }
631 return result;
632 case 5: /* Indirect displacement. */
633 case 6: /* Indirect index + displacement. */
634 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
635 case 7: /* Other */
636 switch (insn & 7) {
637 case 0: /* Absolute short. */
638 case 1: /* Absolute long. */
639 case 2: /* pc displacement */
640 case 3: /* pc index+displacement. */
641 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
642 case 4: /* Immediate. */
643 /* Sign extend values for consistency. */
644 switch (opsize) {
645 case OS_BYTE:
646 if (what == EA_LOADS) {
647 offset = cpu_ldsb_code(env, s->pc + 1);
648 } else {
649 offset = cpu_ldub_code(env, s->pc + 1);
650 }
651 s->pc += 2;
652 break;
653 case OS_WORD:
654 if (what == EA_LOADS) {
655 offset = cpu_ldsw_code(env, s->pc);
656 } else {
657 offset = cpu_lduw_code(env, s->pc);
658 }
659 s->pc += 2;
660 break;
661 case OS_LONG:
662 offset = read_im32(env, s);
663 break;
664 default:
665 g_assert_not_reached();
666 }
667 return tcg_const_i32(offset);
668 default:
669 return NULL_QREG;
670 }
671 }
672 /* Should never happen. */
673 return NULL_QREG;
674 }
675
676 /* This generates a conditional branch, clobbering all temporaries. */
677 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
678 {
679 TCGv tmp;
680
681 /* TODO: Optimize compare/branch pairs rather than always flushing
682 flag state to CC_OP_FLAGS. */
683 gen_flush_flags(s);
684 switch (cond) {
685 case 0: /* T */
686 tcg_gen_br(l1);
687 break;
688 case 1: /* F */
689 break;
690 case 2: /* HI (!C && !Z) */
691 tmp = tcg_temp_new();
692 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
693 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
694 break;
695 case 3: /* LS (C || Z) */
696 tmp = tcg_temp_new();
697 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C | CCF_Z);
698 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
699 break;
700 case 4: /* CC (!C) */
701 tmp = tcg_temp_new();
702 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
703 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
704 break;
705 case 5: /* CS (C) */
706 tmp = tcg_temp_new();
707 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_C);
708 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
709 break;
710 case 6: /* NE (!Z) */
711 tmp = tcg_temp_new();
712 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
713 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
714 break;
715 case 7: /* EQ (Z) */
716 tmp = tcg_temp_new();
717 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_Z);
718 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
719 break;
720 case 8: /* VC (!V) */
721 tmp = tcg_temp_new();
722 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
723 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
724 break;
725 case 9: /* VS (V) */
726 tmp = tcg_temp_new();
727 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_V);
728 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
729 break;
730 case 10: /* PL (!N) */
731 tmp = tcg_temp_new();
732 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
733 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
734 break;
735 case 11: /* MI (N) */
736 tmp = tcg_temp_new();
737 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
738 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
739 break;
740 case 12: /* GE (!(N ^ V)) */
741 tmp = tcg_temp_new();
742 assert(CCF_V == (CCF_N >> 2));
743 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
744 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
745 tcg_gen_andi_i32(tmp, tmp, CCF_V);
746 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
747 break;
748 case 13: /* LT (N ^ V) */
749 tmp = tcg_temp_new();
750 assert(CCF_V == (CCF_N >> 2));
751 tcg_gen_shri_i32(tmp, QREG_CC_DEST, 2);
752 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
753 tcg_gen_andi_i32(tmp, tmp, CCF_V);
754 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
755 break;
756 case 14: /* GT (!(Z || (N ^ V))) */
757 tmp = tcg_temp_new();
758 assert(CCF_V == (CCF_N >> 2));
759 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
760 tcg_gen_shri_i32(tmp, tmp, 2);
761 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
762 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
763 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, l1);
764 break;
765 case 15: /* LE (Z || (N ^ V)) */
766 tmp = tcg_temp_new();
767 assert(CCF_V == (CCF_N >> 2));
768 tcg_gen_andi_i32(tmp, QREG_CC_DEST, CCF_N);
769 tcg_gen_shri_i32(tmp, tmp, 2);
770 tcg_gen_xor_i32(tmp, tmp, QREG_CC_DEST);
771 tcg_gen_andi_i32(tmp, tmp, CCF_V | CCF_Z);
772 tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, l1);
773 break;
774 default:
775 /* Should ever happen. */
776 abort();
777 }
778 }
779
780 DISAS_INSN(scc)
781 {
782 TCGLabel *l1;
783 int cond;
784 TCGv reg;
785
786 l1 = gen_new_label();
787 cond = (insn >> 8) & 0xf;
788 reg = DREG(insn, 0);
789 tcg_gen_andi_i32(reg, reg, 0xffffff00);
790 /* This is safe because we modify the reg directly, with no other values
791 live. */
792 gen_jmpcc(s, cond ^ 1, l1);
793 tcg_gen_ori_i32(reg, reg, 0xff);
794 gen_set_label(l1);
795 }
796
797 /* Force a TB lookup after an instruction that changes the CPU state. */
798 static void gen_lookup_tb(DisasContext *s)
799 {
800 gen_flush_cc_op(s);
801 tcg_gen_movi_i32(QREG_PC, s->pc);
802 s->is_jmp = DISAS_UPDATE;
803 }
804
805 /* Generate a jump to an immediate address. */
806 static void gen_jmp_im(DisasContext *s, uint32_t dest)
807 {
808 gen_flush_cc_op(s);
809 tcg_gen_movi_i32(QREG_PC, dest);
810 s->is_jmp = DISAS_JUMP;
811 }
812
813 /* Generate a jump to the address in qreg DEST. */
814 static void gen_jmp(DisasContext *s, TCGv dest)
815 {
816 gen_flush_cc_op(s);
817 tcg_gen_mov_i32(QREG_PC, dest);
818 s->is_jmp = DISAS_JUMP;
819 }
820
821 static void gen_exception(DisasContext *s, uint32_t where, int nr)
822 {
823 gen_flush_cc_op(s);
824 gen_jmp_im(s, where);
825 gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
826 }
827
828 static inline void gen_addr_fault(DisasContext *s)
829 {
830 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
831 }
832
833 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
834 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
835 op_sign ? EA_LOADS : EA_LOADU); \
836 if (IS_NULL_QREG(result)) { \
837 gen_addr_fault(s); \
838 return; \
839 } \
840 } while (0)
841
842 #define DEST_EA(env, insn, opsize, val, addrp) do { \
843 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
844 if (IS_NULL_QREG(ea_result)) { \
845 gen_addr_fault(s); \
846 return; \
847 } \
848 } while (0)
849
850 /* Generate a jump to an immediate address. */
851 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
852 {
853 TranslationBlock *tb;
854
855 tb = s->tb;
856 if (unlikely(s->singlestep_enabled)) {
857 gen_exception(s, dest, EXCP_DEBUG);
858 } else if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
859 (s->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
860 tcg_gen_goto_tb(n);
861 tcg_gen_movi_i32(QREG_PC, dest);
862 tcg_gen_exit_tb((uintptr_t)tb + n);
863 } else {
864 gen_jmp_im(s, dest);
865 tcg_gen_exit_tb(0);
866 }
867 s->is_jmp = DISAS_TB_JUMP;
868 }
869
870 DISAS_INSN(undef_mac)
871 {
872 gen_exception(s, s->pc - 2, EXCP_LINEA);
873 }
874
875 DISAS_INSN(undef_fpu)
876 {
877 gen_exception(s, s->pc - 2, EXCP_LINEF);
878 }
879
880 DISAS_INSN(undef)
881 {
882 M68kCPU *cpu = m68k_env_get_cpu(env);
883
884 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
885 cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
886 }
887
888 DISAS_INSN(mulw)
889 {
890 TCGv reg;
891 TCGv tmp;
892 TCGv src;
893 int sign;
894
895 sign = (insn & 0x100) != 0;
896 reg = DREG(insn, 9);
897 tmp = tcg_temp_new();
898 if (sign)
899 tcg_gen_ext16s_i32(tmp, reg);
900 else
901 tcg_gen_ext16u_i32(tmp, reg);
902 SRC_EA(env, src, OS_WORD, sign, NULL);
903 tcg_gen_mul_i32(tmp, tmp, src);
904 tcg_gen_mov_i32(reg, tmp);
905 /* Unlike m68k, coldfire always clears the overflow bit. */
906 gen_logic_cc(s, tmp);
907 }
908
909 DISAS_INSN(divw)
910 {
911 TCGv reg;
912 TCGv tmp;
913 TCGv src;
914 int sign;
915
916 sign = (insn & 0x100) != 0;
917 reg = DREG(insn, 9);
918 if (sign) {
919 tcg_gen_ext16s_i32(QREG_DIV1, reg);
920 } else {
921 tcg_gen_ext16u_i32(QREG_DIV1, reg);
922 }
923 SRC_EA(env, src, OS_WORD, sign, NULL);
924 tcg_gen_mov_i32(QREG_DIV2, src);
925 if (sign) {
926 gen_helper_divs(cpu_env, tcg_const_i32(1));
927 } else {
928 gen_helper_divu(cpu_env, tcg_const_i32(1));
929 }
930
931 tmp = tcg_temp_new();
932 src = tcg_temp_new();
933 tcg_gen_ext16u_i32(tmp, QREG_DIV1);
934 tcg_gen_shli_i32(src, QREG_DIV2, 16);
935 tcg_gen_or_i32(reg, tmp, src);
936 s->cc_op = CC_OP_FLAGS;
937 }
938
939 DISAS_INSN(divl)
940 {
941 TCGv num;
942 TCGv den;
943 TCGv reg;
944 uint16_t ext;
945
946 ext = cpu_lduw_code(env, s->pc);
947 s->pc += 2;
948 if (ext & 0x87f8) {
949 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
950 return;
951 }
952 num = DREG(ext, 12);
953 reg = DREG(ext, 0);
954 tcg_gen_mov_i32(QREG_DIV1, num);
955 SRC_EA(env, den, OS_LONG, 0, NULL);
956 tcg_gen_mov_i32(QREG_DIV2, den);
957 if (ext & 0x0800) {
958 gen_helper_divs(cpu_env, tcg_const_i32(0));
959 } else {
960 gen_helper_divu(cpu_env, tcg_const_i32(0));
961 }
962 if ((ext & 7) == ((ext >> 12) & 7)) {
963 /* div */
964 tcg_gen_mov_i32 (reg, QREG_DIV1);
965 } else {
966 /* rem */
967 tcg_gen_mov_i32 (reg, QREG_DIV2);
968 }
969 s->cc_op = CC_OP_FLAGS;
970 }
971
972 DISAS_INSN(addsub)
973 {
974 TCGv reg;
975 TCGv dest;
976 TCGv src;
977 TCGv tmp;
978 TCGv addr;
979 int add;
980
981 add = (insn & 0x4000) != 0;
982 reg = DREG(insn, 9);
983 dest = tcg_temp_new();
984 if (insn & 0x100) {
985 SRC_EA(env, tmp, OS_LONG, 0, &addr);
986 src = reg;
987 } else {
988 tmp = reg;
989 SRC_EA(env, src, OS_LONG, 0, NULL);
990 }
991 if (add) {
992 tcg_gen_add_i32(dest, tmp, src);
993 gen_helper_xflag_lt(QREG_CC_X, dest, src);
994 s->cc_op = CC_OP_ADD;
995 } else {
996 gen_helper_xflag_lt(QREG_CC_X, tmp, src);
997 tcg_gen_sub_i32(dest, tmp, src);
998 s->cc_op = CC_OP_SUB;
999 }
1000 gen_update_cc_add(dest, src);
1001 if (insn & 0x100) {
1002 DEST_EA(env, insn, OS_LONG, dest, &addr);
1003 } else {
1004 tcg_gen_mov_i32(reg, dest);
1005 }
1006 }
1007
1008
1009 /* Reverse the order of the bits in REG. */
1010 DISAS_INSN(bitrev)
1011 {
1012 TCGv reg;
1013 reg = DREG(insn, 0);
1014 gen_helper_bitrev(reg, reg);
1015 }
1016
1017 DISAS_INSN(bitop_reg)
1018 {
1019 int opsize;
1020 int op;
1021 TCGv src1;
1022 TCGv src2;
1023 TCGv tmp;
1024 TCGv addr;
1025 TCGv dest;
1026
1027 if ((insn & 0x38) != 0)
1028 opsize = OS_BYTE;
1029 else
1030 opsize = OS_LONG;
1031 op = (insn >> 6) & 3;
1032 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1033 src2 = DREG(insn, 9);
1034 dest = tcg_temp_new();
1035
1036 gen_flush_flags(s);
1037 tmp = tcg_temp_new();
1038 if (opsize == OS_BYTE)
1039 tcg_gen_andi_i32(tmp, src2, 7);
1040 else
1041 tcg_gen_andi_i32(tmp, src2, 31);
1042 src2 = tmp;
1043 tmp = tcg_temp_new();
1044 tcg_gen_shr_i32(tmp, src1, src2);
1045 tcg_gen_andi_i32(tmp, tmp, 1);
1046 tcg_gen_shli_i32(tmp, tmp, 2);
1047 /* Clear CCF_Z if bit set. */
1048 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1049 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1050
1051 tcg_gen_shl_i32(tmp, tcg_const_i32(1), src2);
1052 switch (op) {
1053 case 1: /* bchg */
1054 tcg_gen_xor_i32(dest, src1, tmp);
1055 break;
1056 case 2: /* bclr */
1057 tcg_gen_not_i32(tmp, tmp);
1058 tcg_gen_and_i32(dest, src1, tmp);
1059 break;
1060 case 3: /* bset */
1061 tcg_gen_or_i32(dest, src1, tmp);
1062 break;
1063 default: /* btst */
1064 break;
1065 }
1066 if (op)
1067 DEST_EA(env, insn, opsize, dest, &addr);
1068 }
1069
1070 DISAS_INSN(sats)
1071 {
1072 TCGv reg;
1073 reg = DREG(insn, 0);
1074 gen_flush_flags(s);
1075 gen_helper_sats(reg, reg, QREG_CC_DEST);
1076 gen_logic_cc(s, reg);
1077 }
1078
1079 static void gen_push(DisasContext *s, TCGv val)
1080 {
1081 TCGv tmp;
1082
1083 tmp = tcg_temp_new();
1084 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1085 gen_store(s, OS_LONG, tmp, val);
1086 tcg_gen_mov_i32(QREG_SP, tmp);
1087 }
1088
1089 DISAS_INSN(movem)
1090 {
1091 TCGv addr;
1092 int i;
1093 uint16_t mask;
1094 TCGv reg;
1095 TCGv tmp;
1096 int is_load;
1097
1098 mask = cpu_lduw_code(env, s->pc);
1099 s->pc += 2;
1100 tmp = gen_lea(env, s, insn, OS_LONG);
1101 if (IS_NULL_QREG(tmp)) {
1102 gen_addr_fault(s);
1103 return;
1104 }
1105 addr = tcg_temp_new();
1106 tcg_gen_mov_i32(addr, tmp);
1107 is_load = ((insn & 0x0400) != 0);
1108 for (i = 0; i < 16; i++, mask >>= 1) {
1109 if (mask & 1) {
1110 if (i < 8)
1111 reg = DREG(i, 0);
1112 else
1113 reg = AREG(i, 0);
1114 if (is_load) {
1115 tmp = gen_load(s, OS_LONG, addr, 0);
1116 tcg_gen_mov_i32(reg, tmp);
1117 } else {
1118 gen_store(s, OS_LONG, addr, reg);
1119 }
1120 if (mask != 1)
1121 tcg_gen_addi_i32(addr, addr, 4);
1122 }
1123 }
1124 }
1125
1126 DISAS_INSN(bitop_im)
1127 {
1128 int opsize;
1129 int op;
1130 TCGv src1;
1131 uint32_t mask;
1132 int bitnum;
1133 TCGv tmp;
1134 TCGv addr;
1135
1136 if ((insn & 0x38) != 0)
1137 opsize = OS_BYTE;
1138 else
1139 opsize = OS_LONG;
1140 op = (insn >> 6) & 3;
1141
1142 bitnum = cpu_lduw_code(env, s->pc);
1143 s->pc += 2;
1144 if (bitnum & 0xff00) {
1145 disas_undef(env, s, insn);
1146 return;
1147 }
1148
1149 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1150
1151 gen_flush_flags(s);
1152 if (opsize == OS_BYTE)
1153 bitnum &= 7;
1154 else
1155 bitnum &= 31;
1156 mask = 1 << bitnum;
1157
1158 tmp = tcg_temp_new();
1159 assert (CCF_Z == (1 << 2));
1160 if (bitnum > 2)
1161 tcg_gen_shri_i32(tmp, src1, bitnum - 2);
1162 else if (bitnum < 2)
1163 tcg_gen_shli_i32(tmp, src1, 2 - bitnum);
1164 else
1165 tcg_gen_mov_i32(tmp, src1);
1166 tcg_gen_andi_i32(tmp, tmp, CCF_Z);
1167 /* Clear CCF_Z if bit set. */
1168 tcg_gen_ori_i32(QREG_CC_DEST, QREG_CC_DEST, CCF_Z);
1169 tcg_gen_xor_i32(QREG_CC_DEST, QREG_CC_DEST, tmp);
1170 if (op) {
1171 switch (op) {
1172 case 1: /* bchg */
1173 tcg_gen_xori_i32(tmp, src1, mask);
1174 break;
1175 case 2: /* bclr */
1176 tcg_gen_andi_i32(tmp, src1, ~mask);
1177 break;
1178 case 3: /* bset */
1179 tcg_gen_ori_i32(tmp, src1, mask);
1180 break;
1181 default: /* btst */
1182 break;
1183 }
1184 DEST_EA(env, insn, opsize, tmp, &addr);
1185 }
1186 }
1187
1188 DISAS_INSN(arith_im)
1189 {
1190 int op;
1191 uint32_t im;
1192 TCGv src1;
1193 TCGv dest;
1194 TCGv addr;
1195
1196 op = (insn >> 9) & 7;
1197 SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
1198 im = read_im32(env, s);
1199 dest = tcg_temp_new();
1200 switch (op) {
1201 case 0: /* ori */
1202 tcg_gen_ori_i32(dest, src1, im);
1203 gen_logic_cc(s, dest);
1204 break;
1205 case 1: /* andi */
1206 tcg_gen_andi_i32(dest, src1, im);
1207 gen_logic_cc(s, dest);
1208 break;
1209 case 2: /* subi */
1210 tcg_gen_mov_i32(dest, src1);
1211 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1212 tcg_gen_subi_i32(dest, dest, im);
1213 gen_update_cc_add(dest, tcg_const_i32(im));
1214 s->cc_op = CC_OP_SUB;
1215 break;
1216 case 3: /* addi */
1217 tcg_gen_mov_i32(dest, src1);
1218 tcg_gen_addi_i32(dest, dest, im);
1219 gen_update_cc_add(dest, tcg_const_i32(im));
1220 gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
1221 s->cc_op = CC_OP_ADD;
1222 break;
1223 case 5: /* eori */
1224 tcg_gen_xori_i32(dest, src1, im);
1225 gen_logic_cc(s, dest);
1226 break;
1227 case 6: /* cmpi */
1228 tcg_gen_mov_i32(dest, src1);
1229 tcg_gen_subi_i32(dest, dest, im);
1230 gen_update_cc_add(dest, tcg_const_i32(im));
1231 s->cc_op = CC_OP_SUB;
1232 break;
1233 default:
1234 abort();
1235 }
1236 if (op != 6) {
1237 DEST_EA(env, insn, OS_LONG, dest, &addr);
1238 }
1239 }
1240
1241 DISAS_INSN(byterev)
1242 {
1243 TCGv reg;
1244
1245 reg = DREG(insn, 0);
1246 tcg_gen_bswap32_i32(reg, reg);
1247 }
1248
1249 DISAS_INSN(move)
1250 {
1251 TCGv src;
1252 TCGv dest;
1253 int op;
1254 int opsize;
1255
1256 switch (insn >> 12) {
1257 case 1: /* move.b */
1258 opsize = OS_BYTE;
1259 break;
1260 case 2: /* move.l */
1261 opsize = OS_LONG;
1262 break;
1263 case 3: /* move.w */
1264 opsize = OS_WORD;
1265 break;
1266 default:
1267 abort();
1268 }
1269 SRC_EA(env, src, opsize, 1, NULL);
1270 op = (insn >> 6) & 7;
1271 if (op == 1) {
1272 /* movea */
1273 /* The value will already have been sign extended. */
1274 dest = AREG(insn, 9);
1275 tcg_gen_mov_i32(dest, src);
1276 } else {
1277 /* normal move */
1278 uint16_t dest_ea;
1279 dest_ea = ((insn >> 9) & 7) | (op << 3);
1280 DEST_EA(env, dest_ea, opsize, src, NULL);
1281 /* This will be correct because loads sign extend. */
1282 gen_logic_cc(s, src);
1283 }
1284 }
1285
1286 DISAS_INSN(negx)
1287 {
1288 TCGv reg;
1289
1290 gen_flush_flags(s);
1291 reg = DREG(insn, 0);
1292 gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg);
1293 }
1294
1295 DISAS_INSN(lea)
1296 {
1297 TCGv reg;
1298 TCGv tmp;
1299
1300 reg = AREG(insn, 9);
1301 tmp = gen_lea(env, s, insn, OS_LONG);
1302 if (IS_NULL_QREG(tmp)) {
1303 gen_addr_fault(s);
1304 return;
1305 }
1306 tcg_gen_mov_i32(reg, tmp);
1307 }
1308
1309 DISAS_INSN(clr)
1310 {
1311 int opsize;
1312
1313 switch ((insn >> 6) & 3) {
1314 case 0: /* clr.b */
1315 opsize = OS_BYTE;
1316 break;
1317 case 1: /* clr.w */
1318 opsize = OS_WORD;
1319 break;
1320 case 2: /* clr.l */
1321 opsize = OS_LONG;
1322 break;
1323 default:
1324 abort();
1325 }
1326 DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
1327 gen_logic_cc(s, tcg_const_i32(0));
1328 }
1329
1330 static TCGv gen_get_ccr(DisasContext *s)
1331 {
1332 TCGv dest;
1333
1334 gen_flush_flags(s);
1335 dest = tcg_temp_new();
1336 tcg_gen_shli_i32(dest, QREG_CC_X, 4);
1337 tcg_gen_or_i32(dest, dest, QREG_CC_DEST);
1338 return dest;
1339 }
1340
1341 DISAS_INSN(move_from_ccr)
1342 {
1343 TCGv reg;
1344 TCGv ccr;
1345
1346 ccr = gen_get_ccr(s);
1347 reg = DREG(insn, 0);
1348 gen_partset_reg(OS_WORD, reg, ccr);
1349 }
1350
1351 DISAS_INSN(neg)
1352 {
1353 TCGv reg;
1354 TCGv src1;
1355
1356 reg = DREG(insn, 0);
1357 src1 = tcg_temp_new();
1358 tcg_gen_mov_i32(src1, reg);
1359 tcg_gen_neg_i32(reg, src1);
1360 s->cc_op = CC_OP_SUB;
1361 gen_update_cc_add(reg, src1);
1362 gen_helper_xflag_lt(QREG_CC_X, tcg_const_i32(0), src1);
1363 s->cc_op = CC_OP_SUB;
1364 }
1365
1366 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
1367 {
1368 tcg_gen_movi_i32(QREG_CC_DEST, val & 0xf);
1369 tcg_gen_movi_i32(QREG_CC_X, (val & 0x10) >> 4);
1370 if (!ccr_only) {
1371 gen_helper_set_sr(cpu_env, tcg_const_i32(val & 0xff00));
1372 }
1373 }
1374
1375 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
1376 int ccr_only)
1377 {
1378 TCGv tmp;
1379 TCGv reg;
1380
1381 s->cc_op = CC_OP_FLAGS;
1382 if ((insn & 0x38) == 0)
1383 {
1384 tmp = tcg_temp_new();
1385 reg = DREG(insn, 0);
1386 tcg_gen_andi_i32(QREG_CC_DEST, reg, 0xf);
1387 tcg_gen_shri_i32(tmp, reg, 4);
1388 tcg_gen_andi_i32(QREG_CC_X, tmp, 1);
1389 if (!ccr_only) {
1390 gen_helper_set_sr(cpu_env, reg);
1391 }
1392 }
1393 else if ((insn & 0x3f) == 0x3c)
1394 {
1395 uint16_t val;
1396 val = cpu_lduw_code(env, s->pc);
1397 s->pc += 2;
1398 gen_set_sr_im(s, val, ccr_only);
1399 }
1400 else
1401 disas_undef(env, s, insn);
1402 }
1403
1404 DISAS_INSN(move_to_ccr)
1405 {
1406 gen_set_sr(env, s, insn, 1);
1407 }
1408
1409 DISAS_INSN(not)
1410 {
1411 TCGv reg;
1412
1413 reg = DREG(insn, 0);
1414 tcg_gen_not_i32(reg, reg);
1415 gen_logic_cc(s, reg);
1416 }
1417
1418 DISAS_INSN(swap)
1419 {
1420 TCGv src1;
1421 TCGv src2;
1422 TCGv reg;
1423
1424 src1 = tcg_temp_new();
1425 src2 = tcg_temp_new();
1426 reg = DREG(insn, 0);
1427 tcg_gen_shli_i32(src1, reg, 16);
1428 tcg_gen_shri_i32(src2, reg, 16);
1429 tcg_gen_or_i32(reg, src1, src2);
1430 gen_logic_cc(s, reg);
1431 }
1432
1433 DISAS_INSN(pea)
1434 {
1435 TCGv tmp;
1436
1437 tmp = gen_lea(env, s, insn, OS_LONG);
1438 if (IS_NULL_QREG(tmp)) {
1439 gen_addr_fault(s);
1440 return;
1441 }
1442 gen_push(s, tmp);
1443 }
1444
1445 DISAS_INSN(ext)
1446 {
1447 int op;
1448 TCGv reg;
1449 TCGv tmp;
1450
1451 reg = DREG(insn, 0);
1452 op = (insn >> 6) & 7;
1453 tmp = tcg_temp_new();
1454 if (op == 3)
1455 tcg_gen_ext16s_i32(tmp, reg);
1456 else
1457 tcg_gen_ext8s_i32(tmp, reg);
1458 if (op == 2)
1459 gen_partset_reg(OS_WORD, reg, tmp);
1460 else
1461 tcg_gen_mov_i32(reg, tmp);
1462 gen_logic_cc(s, tmp);
1463 }
1464
1465 DISAS_INSN(tst)
1466 {
1467 int opsize;
1468 TCGv tmp;
1469
1470 switch ((insn >> 6) & 3) {
1471 case 0: /* tst.b */
1472 opsize = OS_BYTE;
1473 break;
1474 case 1: /* tst.w */
1475 opsize = OS_WORD;
1476 break;
1477 case 2: /* tst.l */
1478 opsize = OS_LONG;
1479 break;
1480 default:
1481 abort();
1482 }
1483 SRC_EA(env, tmp, opsize, 1, NULL);
1484 gen_logic_cc(s, tmp);
1485 }
1486
1487 DISAS_INSN(pulse)
1488 {
1489 /* Implemented as a NOP. */
1490 }
1491
1492 DISAS_INSN(illegal)
1493 {
1494 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
1495 }
1496
1497 /* ??? This should be atomic. */
1498 DISAS_INSN(tas)
1499 {
1500 TCGv dest;
1501 TCGv src1;
1502 TCGv addr;
1503
1504 dest = tcg_temp_new();
1505 SRC_EA(env, src1, OS_BYTE, 1, &addr);
1506 gen_logic_cc(s, src1);
1507 tcg_gen_ori_i32(dest, src1, 0x80);
1508 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1509 }
1510
1511 DISAS_INSN(mull)
1512 {
1513 uint16_t ext;
1514 TCGv reg;
1515 TCGv src1;
1516 TCGv dest;
1517
1518 /* The upper 32 bits of the product are discarded, so
1519 muls.l and mulu.l are functionally equivalent. */
1520 ext = cpu_lduw_code(env, s->pc);
1521 s->pc += 2;
1522 if (ext & 0x87ff) {
1523 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1524 return;
1525 }
1526 reg = DREG(ext, 12);
1527 SRC_EA(env, src1, OS_LONG, 0, NULL);
1528 dest = tcg_temp_new();
1529 tcg_gen_mul_i32(dest, src1, reg);
1530 tcg_gen_mov_i32(reg, dest);
1531 /* Unlike m68k, coldfire always clears the overflow bit. */
1532 gen_logic_cc(s, dest);
1533 }
1534
1535 DISAS_INSN(link)
1536 {
1537 int16_t offset;
1538 TCGv reg;
1539 TCGv tmp;
1540
1541 offset = cpu_ldsw_code(env, s->pc);
1542 s->pc += 2;
1543 reg = AREG(insn, 0);
1544 tmp = tcg_temp_new();
1545 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1546 gen_store(s, OS_LONG, tmp, reg);
1547 if ((insn & 7) != 7)
1548 tcg_gen_mov_i32(reg, tmp);
1549 tcg_gen_addi_i32(QREG_SP, tmp, offset);
1550 }
1551
1552 DISAS_INSN(unlk)
1553 {
1554 TCGv src;
1555 TCGv reg;
1556 TCGv tmp;
1557
1558 src = tcg_temp_new();
1559 reg = AREG(insn, 0);
1560 tcg_gen_mov_i32(src, reg);
1561 tmp = gen_load(s, OS_LONG, src, 0);
1562 tcg_gen_mov_i32(reg, tmp);
1563 tcg_gen_addi_i32(QREG_SP, src, 4);
1564 }
1565
1566 DISAS_INSN(nop)
1567 {
1568 }
1569
1570 DISAS_INSN(rts)
1571 {
1572 TCGv tmp;
1573
1574 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
1575 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
1576 gen_jmp(s, tmp);
1577 }
1578
1579 DISAS_INSN(jump)
1580 {
1581 TCGv tmp;
1582
1583 /* Load the target address first to ensure correct exception
1584 behavior. */
1585 tmp = gen_lea(env, s, insn, OS_LONG);
1586 if (IS_NULL_QREG(tmp)) {
1587 gen_addr_fault(s);
1588 return;
1589 }
1590 if ((insn & 0x40) == 0) {
1591 /* jsr */
1592 gen_push(s, tcg_const_i32(s->pc));
1593 }
1594 gen_jmp(s, tmp);
1595 }
1596
1597 DISAS_INSN(addsubq)
1598 {
1599 TCGv src1;
1600 TCGv src2;
1601 TCGv dest;
1602 int val;
1603 TCGv addr;
1604
1605 SRC_EA(env, src1, OS_LONG, 0, &addr);
1606 val = (insn >> 9) & 7;
1607 if (val == 0)
1608 val = 8;
1609 dest = tcg_temp_new();
1610 tcg_gen_mov_i32(dest, src1);
1611 if ((insn & 0x38) == 0x08) {
1612 /* Don't update condition codes if the destination is an
1613 address register. */
1614 if (insn & 0x0100) {
1615 tcg_gen_subi_i32(dest, dest, val);
1616 } else {
1617 tcg_gen_addi_i32(dest, dest, val);
1618 }
1619 } else {
1620 src2 = tcg_const_i32(val);
1621 if (insn & 0x0100) {
1622 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1623 tcg_gen_subi_i32(dest, dest, val);
1624 s->cc_op = CC_OP_SUB;
1625 } else {
1626 tcg_gen_addi_i32(dest, dest, val);
1627 gen_helper_xflag_lt(QREG_CC_X, dest, src2);
1628 s->cc_op = CC_OP_ADD;
1629 }
1630 gen_update_cc_add(dest, src2);
1631 }
1632 DEST_EA(env, insn, OS_LONG, dest, &addr);
1633 }
1634
1635 DISAS_INSN(tpf)
1636 {
1637 switch (insn & 7) {
1638 case 2: /* One extension word. */
1639 s->pc += 2;
1640 break;
1641 case 3: /* Two extension words. */
1642 s->pc += 4;
1643 break;
1644 case 4: /* No extension words. */
1645 break;
1646 default:
1647 disas_undef(env, s, insn);
1648 }
1649 }
1650
1651 DISAS_INSN(branch)
1652 {
1653 int32_t offset;
1654 uint32_t base;
1655 int op;
1656 TCGLabel *l1;
1657
1658 base = s->pc;
1659 op = (insn >> 8) & 0xf;
1660 offset = (int8_t)insn;
1661 if (offset == 0) {
1662 offset = cpu_ldsw_code(env, s->pc);
1663 s->pc += 2;
1664 } else if (offset == -1) {
1665 offset = read_im32(env, s);
1666 }
1667 if (op == 1) {
1668 /* bsr */
1669 gen_push(s, tcg_const_i32(s->pc));
1670 }
1671 gen_flush_cc_op(s);
1672 if (op > 1) {
1673 /* Bcc */
1674 l1 = gen_new_label();
1675 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
1676 gen_jmp_tb(s, 1, base + offset);
1677 gen_set_label(l1);
1678 gen_jmp_tb(s, 0, s->pc);
1679 } else {
1680 /* Unconditional branch. */
1681 gen_jmp_tb(s, 0, base + offset);
1682 }
1683 }
1684
1685 DISAS_INSN(moveq)
1686 {
1687 uint32_t val;
1688
1689 val = (int8_t)insn;
1690 tcg_gen_movi_i32(DREG(insn, 9), val);
1691 gen_logic_cc(s, tcg_const_i32(val));
1692 }
1693
1694 DISAS_INSN(mvzs)
1695 {
1696 int opsize;
1697 TCGv src;
1698 TCGv reg;
1699
1700 if (insn & 0x40)
1701 opsize = OS_WORD;
1702 else
1703 opsize = OS_BYTE;
1704 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
1705 reg = DREG(insn, 9);
1706 tcg_gen_mov_i32(reg, src);
1707 gen_logic_cc(s, src);
1708 }
1709
1710 DISAS_INSN(or)
1711 {
1712 TCGv reg;
1713 TCGv dest;
1714 TCGv src;
1715 TCGv addr;
1716
1717 reg = DREG(insn, 9);
1718 dest = tcg_temp_new();
1719 if (insn & 0x100) {
1720 SRC_EA(env, src, OS_LONG, 0, &addr);
1721 tcg_gen_or_i32(dest, src, reg);
1722 DEST_EA(env, insn, OS_LONG, dest, &addr);
1723 } else {
1724 SRC_EA(env, src, OS_LONG, 0, NULL);
1725 tcg_gen_or_i32(dest, src, reg);
1726 tcg_gen_mov_i32(reg, dest);
1727 }
1728 gen_logic_cc(s, dest);
1729 }
1730
1731 DISAS_INSN(suba)
1732 {
1733 TCGv src;
1734 TCGv reg;
1735
1736 SRC_EA(env, src, OS_LONG, 0, NULL);
1737 reg = AREG(insn, 9);
1738 tcg_gen_sub_i32(reg, reg, src);
1739 }
1740
1741 DISAS_INSN(subx)
1742 {
1743 TCGv reg;
1744 TCGv src;
1745
1746 gen_flush_flags(s);
1747 reg = DREG(insn, 9);
1748 src = DREG(insn, 0);
1749 gen_helper_subx_cc(reg, cpu_env, reg, src);
1750 }
1751
1752 DISAS_INSN(mov3q)
1753 {
1754 TCGv src;
1755 int val;
1756
1757 val = (insn >> 9) & 7;
1758 if (val == 0)
1759 val = -1;
1760 src = tcg_const_i32(val);
1761 gen_logic_cc(s, src);
1762 DEST_EA(env, insn, OS_LONG, src, NULL);
1763 }
1764
1765 DISAS_INSN(cmp)
1766 {
1767 int op;
1768 TCGv src;
1769 TCGv reg;
1770 TCGv dest;
1771 int opsize;
1772
1773 op = (insn >> 6) & 3;
1774 switch (op) {
1775 case 0: /* cmp.b */
1776 opsize = OS_BYTE;
1777 s->cc_op = CC_OP_CMPB;
1778 break;
1779 case 1: /* cmp.w */
1780 opsize = OS_WORD;
1781 s->cc_op = CC_OP_CMPW;
1782 break;
1783 case 2: /* cmp.l */
1784 opsize = OS_LONG;
1785 s->cc_op = CC_OP_SUB;
1786 break;
1787 default:
1788 abort();
1789 }
1790 SRC_EA(env, src, opsize, 1, NULL);
1791 reg = DREG(insn, 9);
1792 dest = tcg_temp_new();
1793 tcg_gen_sub_i32(dest, reg, src);
1794 gen_update_cc_add(dest, src);
1795 }
1796
1797 DISAS_INSN(cmpa)
1798 {
1799 int opsize;
1800 TCGv src;
1801 TCGv reg;
1802 TCGv dest;
1803
1804 if (insn & 0x100) {
1805 opsize = OS_LONG;
1806 } else {
1807 opsize = OS_WORD;
1808 }
1809 SRC_EA(env, src, opsize, 1, NULL);
1810 reg = AREG(insn, 9);
1811 dest = tcg_temp_new();
1812 tcg_gen_sub_i32(dest, reg, src);
1813 gen_update_cc_add(dest, src);
1814 s->cc_op = CC_OP_SUB;
1815 }
1816
1817 DISAS_INSN(eor)
1818 {
1819 TCGv src;
1820 TCGv reg;
1821 TCGv dest;
1822 TCGv addr;
1823
1824 SRC_EA(env, src, OS_LONG, 0, &addr);
1825 reg = DREG(insn, 9);
1826 dest = tcg_temp_new();
1827 tcg_gen_xor_i32(dest, src, reg);
1828 gen_logic_cc(s, dest);
1829 DEST_EA(env, insn, OS_LONG, dest, &addr);
1830 }
1831
1832 DISAS_INSN(and)
1833 {
1834 TCGv src;
1835 TCGv reg;
1836 TCGv dest;
1837 TCGv addr;
1838
1839 reg = DREG(insn, 9);
1840 dest = tcg_temp_new();
1841 if (insn & 0x100) {
1842 SRC_EA(env, src, OS_LONG, 0, &addr);
1843 tcg_gen_and_i32(dest, src, reg);
1844 DEST_EA(env, insn, OS_LONG, dest, &addr);
1845 } else {
1846 SRC_EA(env, src, OS_LONG, 0, NULL);
1847 tcg_gen_and_i32(dest, src, reg);
1848 tcg_gen_mov_i32(reg, dest);
1849 }
1850 gen_logic_cc(s, dest);
1851 }
1852
1853 DISAS_INSN(adda)
1854 {
1855 TCGv src;
1856 TCGv reg;
1857
1858 SRC_EA(env, src, OS_LONG, 0, NULL);
1859 reg = AREG(insn, 9);
1860 tcg_gen_add_i32(reg, reg, src);
1861 }
1862
1863 DISAS_INSN(addx)
1864 {
1865 TCGv reg;
1866 TCGv src;
1867
1868 gen_flush_flags(s);
1869 reg = DREG(insn, 9);
1870 src = DREG(insn, 0);
1871 gen_helper_addx_cc(reg, cpu_env, reg, src);
1872 s->cc_op = CC_OP_FLAGS;
1873 }
1874
1875 /* TODO: This could be implemented without helper functions. */
1876 DISAS_INSN(shift_im)
1877 {
1878 TCGv reg;
1879 int tmp;
1880 TCGv shift;
1881
1882 reg = DREG(insn, 0);
1883 tmp = (insn >> 9) & 7;
1884 if (tmp == 0)
1885 tmp = 8;
1886 shift = tcg_const_i32(tmp);
1887 /* No need to flush flags becuse we know we will set C flag. */
1888 if (insn & 0x100) {
1889 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1890 } else {
1891 if (insn & 8) {
1892 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1893 } else {
1894 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1895 }
1896 }
1897 s->cc_op = CC_OP_SHIFT;
1898 }
1899
1900 DISAS_INSN(shift_reg)
1901 {
1902 TCGv reg;
1903 TCGv shift;
1904
1905 reg = DREG(insn, 0);
1906 shift = DREG(insn, 9);
1907 /* Shift by zero leaves C flag unmodified. */
1908 gen_flush_flags(s);
1909 if (insn & 0x100) {
1910 gen_helper_shl_cc(reg, cpu_env, reg, shift);
1911 } else {
1912 if (insn & 8) {
1913 gen_helper_shr_cc(reg, cpu_env, reg, shift);
1914 } else {
1915 gen_helper_sar_cc(reg, cpu_env, reg, shift);
1916 }
1917 }
1918 s->cc_op = CC_OP_SHIFT;
1919 }
1920
1921 DISAS_INSN(ff1)
1922 {
1923 TCGv reg;
1924 reg = DREG(insn, 0);
1925 gen_logic_cc(s, reg);
1926 gen_helper_ff1(reg, reg);
1927 }
1928
1929 static TCGv gen_get_sr(DisasContext *s)
1930 {
1931 TCGv ccr;
1932 TCGv sr;
1933
1934 ccr = gen_get_ccr(s);
1935 sr = tcg_temp_new();
1936 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
1937 tcg_gen_or_i32(sr, sr, ccr);
1938 return sr;
1939 }
1940
1941 DISAS_INSN(strldsr)
1942 {
1943 uint16_t ext;
1944 uint32_t addr;
1945
1946 addr = s->pc - 2;
1947 ext = cpu_lduw_code(env, s->pc);
1948 s->pc += 2;
1949 if (ext != 0x46FC) {
1950 gen_exception(s, addr, EXCP_UNSUPPORTED);
1951 return;
1952 }
1953 ext = cpu_lduw_code(env, s->pc);
1954 s->pc += 2;
1955 if (IS_USER(s) || (ext & SR_S) == 0) {
1956 gen_exception(s, addr, EXCP_PRIVILEGE);
1957 return;
1958 }
1959 gen_push(s, gen_get_sr(s));
1960 gen_set_sr_im(s, ext, 0);
1961 }
1962
1963 DISAS_INSN(move_from_sr)
1964 {
1965 TCGv reg;
1966 TCGv sr;
1967
1968 if (IS_USER(s)) {
1969 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1970 return;
1971 }
1972 sr = gen_get_sr(s);
1973 reg = DREG(insn, 0);
1974 gen_partset_reg(OS_WORD, reg, sr);
1975 }
1976
1977 DISAS_INSN(move_to_sr)
1978 {
1979 if (IS_USER(s)) {
1980 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1981 return;
1982 }
1983 gen_set_sr(env, s, insn, 0);
1984 gen_lookup_tb(s);
1985 }
1986
1987 DISAS_INSN(move_from_usp)
1988 {
1989 if (IS_USER(s)) {
1990 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
1991 return;
1992 }
1993 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
1994 offsetof(CPUM68KState, sp[M68K_USP]));
1995 }
1996
1997 DISAS_INSN(move_to_usp)
1998 {
1999 if (IS_USER(s)) {
2000 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2001 return;
2002 }
2003 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
2004 offsetof(CPUM68KState, sp[M68K_USP]));
2005 }
2006
2007 DISAS_INSN(halt)
2008 {
2009 gen_exception(s, s->pc, EXCP_HALT_INSN);
2010 }
2011
2012 DISAS_INSN(stop)
2013 {
2014 uint16_t ext;
2015
2016 if (IS_USER(s)) {
2017 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2018 return;
2019 }
2020
2021 ext = cpu_lduw_code(env, s->pc);
2022 s->pc += 2;
2023
2024 gen_set_sr_im(s, ext, 0);
2025 tcg_gen_movi_i32(cpu_halted, 1);
2026 gen_exception(s, s->pc, EXCP_HLT);
2027 }
2028
2029 DISAS_INSN(rte)
2030 {
2031 if (IS_USER(s)) {
2032 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2033 return;
2034 }
2035 gen_exception(s, s->pc - 2, EXCP_RTE);
2036 }
2037
2038 DISAS_INSN(movec)
2039 {
2040 uint16_t ext;
2041 TCGv reg;
2042
2043 if (IS_USER(s)) {
2044 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2045 return;
2046 }
2047
2048 ext = cpu_lduw_code(env, s->pc);
2049 s->pc += 2;
2050
2051 if (ext & 0x8000) {
2052 reg = AREG(ext, 12);
2053 } else {
2054 reg = DREG(ext, 12);
2055 }
2056 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
2057 gen_lookup_tb(s);
2058 }
2059
2060 DISAS_INSN(intouch)
2061 {
2062 if (IS_USER(s)) {
2063 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2064 return;
2065 }
2066 /* ICache fetch. Implement as no-op. */
2067 }
2068
2069 DISAS_INSN(cpushl)
2070 {
2071 if (IS_USER(s)) {
2072 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2073 return;
2074 }
2075 /* Cache push/invalidate. Implement as no-op. */
2076 }
2077
2078 DISAS_INSN(wddata)
2079 {
2080 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2081 }
2082
2083 DISAS_INSN(wdebug)
2084 {
2085 M68kCPU *cpu = m68k_env_get_cpu(env);
2086
2087 if (IS_USER(s)) {
2088 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2089 return;
2090 }
2091 /* TODO: Implement wdebug. */
2092 cpu_abort(CPU(cpu), "WDEBUG not implemented");
2093 }
2094
2095 DISAS_INSN(trap)
2096 {
2097 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
2098 }
2099
2100 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2101 immediately before the next FP instruction is executed. */
2102 DISAS_INSN(fpu)
2103 {
2104 uint16_t ext;
2105 int32_t offset;
2106 int opmode;
2107 TCGv_i64 src;
2108 TCGv_i64 dest;
2109 TCGv_i64 res;
2110 TCGv tmp32;
2111 int round;
2112 int set_dest;
2113 int opsize;
2114
2115 ext = cpu_lduw_code(env, s->pc);
2116 s->pc += 2;
2117 opmode = ext & 0x7f;
2118 switch ((ext >> 13) & 7) {
2119 case 0: case 2:
2120 break;
2121 case 1:
2122 goto undef;
2123 case 3: /* fmove out */
2124 src = FREG(ext, 7);
2125 tmp32 = tcg_temp_new_i32();
2126 /* fmove */
2127 /* ??? TODO: Proper behavior on overflow. */
2128 switch ((ext >> 10) & 7) {
2129 case 0:
2130 opsize = OS_LONG;
2131 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2132 break;
2133 case 1:
2134 opsize = OS_SINGLE;
2135 gen_helper_f64_to_f32(tmp32, cpu_env, src);
2136 break;
2137 case 4:
2138 opsize = OS_WORD;
2139 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2140 break;
2141 case 5: /* OS_DOUBLE */
2142 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2143 switch ((insn >> 3) & 7) {
2144 case 2:
2145 case 3:
2146 break;
2147 case 4:
2148 tcg_gen_addi_i32(tmp32, tmp32, -8);
2149 break;
2150 case 5:
2151 offset = cpu_ldsw_code(env, s->pc);
2152 s->pc += 2;
2153 tcg_gen_addi_i32(tmp32, tmp32, offset);
2154 break;
2155 default:
2156 goto undef;
2157 }
2158 gen_store64(s, tmp32, src);
2159 switch ((insn >> 3) & 7) {
2160 case 3:
2161 tcg_gen_addi_i32(tmp32, tmp32, 8);
2162 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2163 break;
2164 case 4:
2165 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2166 break;
2167 }
2168 tcg_temp_free_i32(tmp32);
2169 return;
2170 case 6:
2171 opsize = OS_BYTE;
2172 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2173 break;
2174 default:
2175 goto undef;
2176 }
2177 DEST_EA(env, insn, opsize, tmp32, NULL);
2178 tcg_temp_free_i32(tmp32);
2179 return;
2180 case 4: /* fmove to control register. */
2181 switch ((ext >> 10) & 7) {
2182 case 4: /* FPCR */
2183 /* Not implemented. Ignore writes. */
2184 break;
2185 case 1: /* FPIAR */
2186 case 2: /* FPSR */
2187 default:
2188 cpu_abort(NULL, "Unimplemented: fmove to control %d",
2189 (ext >> 10) & 7);
2190 }
2191 break;
2192 case 5: /* fmove from control register. */
2193 switch ((ext >> 10) & 7) {
2194 case 4: /* FPCR */
2195 /* Not implemented. Always return zero. */
2196 tmp32 = tcg_const_i32(0);
2197 break;
2198 case 1: /* FPIAR */
2199 case 2: /* FPSR */
2200 default:
2201 cpu_abort(NULL, "Unimplemented: fmove from control %d",
2202 (ext >> 10) & 7);
2203 goto undef;
2204 }
2205 DEST_EA(env, insn, OS_LONG, tmp32, NULL);
2206 break;
2207 case 6: /* fmovem */
2208 case 7:
2209 {
2210 TCGv addr;
2211 uint16_t mask;
2212 int i;
2213 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
2214 goto undef;
2215 tmp32 = gen_lea(env, s, insn, OS_LONG);
2216 if (IS_NULL_QREG(tmp32)) {
2217 gen_addr_fault(s);
2218 return;
2219 }
2220 addr = tcg_temp_new_i32();
2221 tcg_gen_mov_i32(addr, tmp32);
2222 mask = 0x80;
2223 for (i = 0; i < 8; i++) {
2224 if (ext & mask) {
2225 dest = FREG(i, 0);
2226 if (ext & (1 << 13)) {
2227 /* store */
2228 tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
2229 } else {
2230 /* load */
2231 tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
2232 }
2233 if (ext & (mask - 1))
2234 tcg_gen_addi_i32(addr, addr, 8);
2235 }
2236 mask >>= 1;
2237 }
2238 tcg_temp_free_i32(addr);
2239 }
2240 return;
2241 }
2242 if (ext & (1 << 14)) {
2243 /* Source effective address. */
2244 switch ((ext >> 10) & 7) {
2245 case 0: opsize = OS_LONG; break;
2246 case 1: opsize = OS_SINGLE; break;
2247 case 4: opsize = OS_WORD; break;
2248 case 5: opsize = OS_DOUBLE; break;
2249 case 6: opsize = OS_BYTE; break;
2250 default:
2251 goto undef;
2252 }
2253 if (opsize == OS_DOUBLE) {
2254 tmp32 = tcg_temp_new_i32();
2255 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2256 switch ((insn >> 3) & 7) {
2257 case 2:
2258 case 3:
2259 break;
2260 case 4:
2261 tcg_gen_addi_i32(tmp32, tmp32, -8);
2262 break;
2263 case 5:
2264 offset = cpu_ldsw_code(env, s->pc);
2265 s->pc += 2;
2266 tcg_gen_addi_i32(tmp32, tmp32, offset);
2267 break;
2268 case 7:
2269 offset = cpu_ldsw_code(env, s->pc);
2270 offset += s->pc - 2;
2271 s->pc += 2;
2272 tcg_gen_addi_i32(tmp32, tmp32, offset);
2273 break;
2274 default:
2275 goto undef;
2276 }
2277 src = gen_load64(s, tmp32);
2278 switch ((insn >> 3) & 7) {
2279 case 3:
2280 tcg_gen_addi_i32(tmp32, tmp32, 8);
2281 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2282 break;
2283 case 4:
2284 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2285 break;
2286 }
2287 tcg_temp_free_i32(tmp32);
2288 } else {
2289 SRC_EA(env, tmp32, opsize, 1, NULL);
2290 src = tcg_temp_new_i64();
2291 switch (opsize) {
2292 case OS_LONG:
2293 case OS_WORD:
2294 case OS_BYTE:
2295 gen_helper_i32_to_f64(src, cpu_env, tmp32);
2296 break;
2297 case OS_SINGLE:
2298 gen_helper_f32_to_f64(src, cpu_env, tmp32);
2299 break;
2300 }
2301 }
2302 } else {
2303 /* Source register. */
2304 src = FREG(ext, 10);
2305 }
2306 dest = FREG(ext, 7);
2307 res = tcg_temp_new_i64();
2308 if (opmode != 0x3a)
2309 tcg_gen_mov_f64(res, dest);
2310 round = 1;
2311 set_dest = 1;
2312 switch (opmode) {
2313 case 0: case 0x40: case 0x44: /* fmove */
2314 tcg_gen_mov_f64(res, src);
2315 break;
2316 case 1: /* fint */
2317 gen_helper_iround_f64(res, cpu_env, src);
2318 round = 0;
2319 break;
2320 case 3: /* fintrz */
2321 gen_helper_itrunc_f64(res, cpu_env, src);
2322 round = 0;
2323 break;
2324 case 4: case 0x41: case 0x45: /* fsqrt */
2325 gen_helper_sqrt_f64(res, cpu_env, src);
2326 break;
2327 case 0x18: case 0x58: case 0x5c: /* fabs */
2328 gen_helper_abs_f64(res, src);
2329 break;
2330 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2331 gen_helper_chs_f64(res, src);
2332 break;
2333 case 0x20: case 0x60: case 0x64: /* fdiv */
2334 gen_helper_div_f64(res, cpu_env, res, src);
2335 break;
2336 case 0x22: case 0x62: case 0x66: /* fadd */
2337 gen_helper_add_f64(res, cpu_env, res, src);
2338 break;
2339 case 0x23: case 0x63: case 0x67: /* fmul */
2340 gen_helper_mul_f64(res, cpu_env, res, src);
2341 break;
2342 case 0x28: case 0x68: case 0x6c: /* fsub */
2343 gen_helper_sub_f64(res, cpu_env, res, src);
2344 break;
2345 case 0x38: /* fcmp */
2346 gen_helper_sub_cmp_f64(res, cpu_env, res, src);
2347 set_dest = 0;
2348 round = 0;
2349 break;
2350 case 0x3a: /* ftst */
2351 tcg_gen_mov_f64(res, src);
2352 set_dest = 0;
2353 round = 0;
2354 break;
2355 default:
2356 goto undef;
2357 }
2358 if (ext & (1 << 14)) {
2359 tcg_temp_free_i64(src);
2360 }
2361 if (round) {
2362 if (opmode & 0x40) {
2363 if ((opmode & 0x4) != 0)
2364 round = 0;
2365 } else if ((s->fpcr & M68K_FPCR_PREC) == 0) {
2366 round = 0;
2367 }
2368 }
2369 if (round) {
2370 TCGv tmp = tcg_temp_new_i32();
2371 gen_helper_f64_to_f32(tmp, cpu_env, res);
2372 gen_helper_f32_to_f64(res, cpu_env, tmp);
2373 tcg_temp_free_i32(tmp);
2374 }
2375 tcg_gen_mov_f64(QREG_FP_RESULT, res);
2376 if (set_dest) {
2377 tcg_gen_mov_f64(dest, res);
2378 }
2379 tcg_temp_free_i64(res);
2380 return;
2381 undef:
2382 /* FIXME: Is this right for offset addressing modes? */
2383 s->pc -= 2;
2384 disas_undef_fpu(env, s, insn);
2385 }
2386
2387 DISAS_INSN(fbcc)
2388 {
2389 uint32_t offset;
2390 uint32_t addr;
2391 TCGv flag;
2392 TCGLabel *l1;
2393
2394 addr = s->pc;
2395 offset = cpu_ldsw_code(env, s->pc);
2396 s->pc += 2;
2397 if (insn & (1 << 6)) {
2398 offset = (offset << 16) | cpu_lduw_code(env, s->pc);
2399 s->pc += 2;
2400 }
2401
2402 l1 = gen_new_label();
2403 /* TODO: Raise BSUN exception. */
2404 flag = tcg_temp_new();
2405 gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
2406 /* Jump to l1 if condition is true. */
2407 switch (insn & 0xf) {
2408 case 0: /* f */
2409 break;
2410 case 1: /* eq (=0) */
2411 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2412 break;
2413 case 2: /* ogt (=1) */
2414 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
2415 break;
2416 case 3: /* oge (=0 or =1) */
2417 tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
2418 break;
2419 case 4: /* olt (=-1) */
2420 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
2421 break;
2422 case 5: /* ole (=-1 or =0) */
2423 tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
2424 break;
2425 case 6: /* ogl (=-1 or =1) */
2426 tcg_gen_andi_i32(flag, flag, 1);
2427 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2428 break;
2429 case 7: /* or (=2) */
2430 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
2431 break;
2432 case 8: /* un (<2) */
2433 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
2434 break;
2435 case 9: /* ueq (=0 or =2) */
2436 tcg_gen_andi_i32(flag, flag, 1);
2437 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2438 break;
2439 case 10: /* ugt (>0) */
2440 tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
2441 break;
2442 case 11: /* uge (>=0) */
2443 tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
2444 break;
2445 case 12: /* ult (=-1 or =2) */
2446 tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
2447 break;
2448 case 13: /* ule (!=1) */
2449 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
2450 break;
2451 case 14: /* ne (!=0) */
2452 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2453 break;
2454 case 15: /* t */
2455 tcg_gen_br(l1);
2456 break;
2457 }
2458 gen_jmp_tb(s, 0, s->pc);
2459 gen_set_label(l1);
2460 gen_jmp_tb(s, 1, addr + offset);
2461 }
2462
2463 DISAS_INSN(frestore)
2464 {
2465 M68kCPU *cpu = m68k_env_get_cpu(env);
2466
2467 /* TODO: Implement frestore. */
2468 cpu_abort(CPU(cpu), "FRESTORE not implemented");
2469 }
2470
2471 DISAS_INSN(fsave)
2472 {
2473 M68kCPU *cpu = m68k_env_get_cpu(env);
2474
2475 /* TODO: Implement fsave. */
2476 cpu_abort(CPU(cpu), "FSAVE not implemented");
2477 }
2478
2479 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
2480 {
2481 TCGv tmp = tcg_temp_new();
2482 if (s->env->macsr & MACSR_FI) {
2483 if (upper)
2484 tcg_gen_andi_i32(tmp, val, 0xffff0000);
2485 else
2486 tcg_gen_shli_i32(tmp, val, 16);
2487 } else if (s->env->macsr & MACSR_SU) {
2488 if (upper)
2489 tcg_gen_sari_i32(tmp, val, 16);
2490 else
2491 tcg_gen_ext16s_i32(tmp, val);
2492 } else {
2493 if (upper)
2494 tcg_gen_shri_i32(tmp, val, 16);
2495 else
2496 tcg_gen_ext16u_i32(tmp, val);
2497 }
2498 return tmp;
2499 }
2500
2501 static void gen_mac_clear_flags(void)
2502 {
2503 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
2504 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
2505 }
2506
2507 DISAS_INSN(mac)
2508 {
2509 TCGv rx;
2510 TCGv ry;
2511 uint16_t ext;
2512 int acc;
2513 TCGv tmp;
2514 TCGv addr;
2515 TCGv loadval;
2516 int dual;
2517 TCGv saved_flags;
2518
2519 if (!s->done_mac) {
2520 s->mactmp = tcg_temp_new_i64();
2521 s->done_mac = 1;
2522 }
2523
2524 ext = cpu_lduw_code(env, s->pc);
2525 s->pc += 2;
2526
2527 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
2528 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
2529 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
2530 disas_undef(env, s, insn);
2531 return;
2532 }
2533 if (insn & 0x30) {
2534 /* MAC with load. */
2535 tmp = gen_lea(env, s, insn, OS_LONG);
2536 addr = tcg_temp_new();
2537 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
2538 /* Load the value now to ensure correct exception behavior.
2539 Perform writeback after reading the MAC inputs. */
2540 loadval = gen_load(s, OS_LONG, addr, 0);
2541
2542 acc ^= 1;
2543 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
2544 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
2545 } else {
2546 loadval = addr = NULL_QREG;
2547 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2548 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2549 }
2550
2551 gen_mac_clear_flags();
2552 #if 0
2553 l1 = -1;
2554 /* Disabled because conditional branches clobber temporary vars. */
2555 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
2556 /* Skip the multiply if we know we will ignore it. */
2557 l1 = gen_new_label();
2558 tmp = tcg_temp_new();
2559 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
2560 gen_op_jmp_nz32(tmp, l1);
2561 }
2562 #endif
2563
2564 if ((ext & 0x0800) == 0) {
2565 /* Word. */
2566 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
2567 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
2568 }
2569 if (s->env->macsr & MACSR_FI) {
2570 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
2571 } else {
2572 if (s->env->macsr & MACSR_SU)
2573 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
2574 else
2575 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
2576 switch ((ext >> 9) & 3) {
2577 case 1:
2578 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
2579 break;
2580 case 3:
2581 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
2582 break;
2583 }
2584 }
2585
2586 if (dual) {
2587 /* Save the overflow flag from the multiply. */
2588 saved_flags = tcg_temp_new();
2589 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
2590 } else {
2591 saved_flags = NULL_QREG;
2592 }
2593
2594 #if 0
2595 /* Disabled because conditional branches clobber temporary vars. */
2596 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
2597 /* Skip the accumulate if the value is already saturated. */
2598 l1 = gen_new_label();
2599 tmp = tcg_temp_new();
2600 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2601 gen_op_jmp_nz32(tmp, l1);
2602 }
2603 #endif
2604
2605 if (insn & 0x100)
2606 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2607 else
2608 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2609
2610 if (s->env->macsr & MACSR_FI)
2611 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2612 else if (s->env->macsr & MACSR_SU)
2613 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2614 else
2615 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2616
2617 #if 0
2618 /* Disabled because conditional branches clobber temporary vars. */
2619 if (l1 != -1)
2620 gen_set_label(l1);
2621 #endif
2622
2623 if (dual) {
2624 /* Dual accumulate variant. */
2625 acc = (ext >> 2) & 3;
2626 /* Restore the overflow flag from the multiplier. */
2627 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
2628 #if 0
2629 /* Disabled because conditional branches clobber temporary vars. */
2630 if ((s->env->macsr & MACSR_OMC) != 0) {
2631 /* Skip the accumulate if the value is already saturated. */
2632 l1 = gen_new_label();
2633 tmp = tcg_temp_new();
2634 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2635 gen_op_jmp_nz32(tmp, l1);
2636 }
2637 #endif
2638 if (ext & 2)
2639 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2640 else
2641 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2642 if (s->env->macsr & MACSR_FI)
2643 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2644 else if (s->env->macsr & MACSR_SU)
2645 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2646 else
2647 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2648 #if 0
2649 /* Disabled because conditional branches clobber temporary vars. */
2650 if (l1 != -1)
2651 gen_set_label(l1);
2652 #endif
2653 }
2654 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
2655
2656 if (insn & 0x30) {
2657 TCGv rw;
2658 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2659 tcg_gen_mov_i32(rw, loadval);
2660 /* FIXME: Should address writeback happen with the masked or
2661 unmasked value? */
2662 switch ((insn >> 3) & 7) {
2663 case 3: /* Post-increment. */
2664 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
2665 break;
2666 case 4: /* Pre-decrement. */
2667 tcg_gen_mov_i32(AREG(insn, 0), addr);
2668 }
2669 }
2670 }
2671
2672 DISAS_INSN(from_mac)
2673 {
2674 TCGv rx;
2675 TCGv_i64 acc;
2676 int accnum;
2677
2678 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2679 accnum = (insn >> 9) & 3;
2680 acc = MACREG(accnum);
2681 if (s->env->macsr & MACSR_FI) {
2682 gen_helper_get_macf(rx, cpu_env, acc);
2683 } else if ((s->env->macsr & MACSR_OMC) == 0) {
2684 tcg_gen_extrl_i64_i32(rx, acc);
2685 } else if (s->env->macsr & MACSR_SU) {
2686 gen_helper_get_macs(rx, acc);
2687 } else {
2688 gen_helper_get_macu(rx, acc);
2689 }
2690 if (insn & 0x40) {
2691 tcg_gen_movi_i64(acc, 0);
2692 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2693 }
2694 }
2695
2696 DISAS_INSN(move_mac)
2697 {
2698 /* FIXME: This can be done without a helper. */
2699 int src;
2700 TCGv dest;
2701 src = insn & 3;
2702 dest = tcg_const_i32((insn >> 9) & 3);
2703 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
2704 gen_mac_clear_flags();
2705 gen_helper_mac_set_flags(cpu_env, dest);
2706 }
2707
2708 DISAS_INSN(from_macsr)
2709 {
2710 TCGv reg;
2711
2712 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2713 tcg_gen_mov_i32(reg, QREG_MACSR);
2714 }
2715
2716 DISAS_INSN(from_mask)
2717 {
2718 TCGv reg;
2719 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2720 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
2721 }
2722
2723 DISAS_INSN(from_mext)
2724 {
2725 TCGv reg;
2726 TCGv acc;
2727 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2728 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2729 if (s->env->macsr & MACSR_FI)
2730 gen_helper_get_mac_extf(reg, cpu_env, acc);
2731 else
2732 gen_helper_get_mac_exti(reg, cpu_env, acc);
2733 }
2734
2735 DISAS_INSN(macsr_to_ccr)
2736 {
2737 tcg_gen_movi_i32(QREG_CC_X, 0);
2738 tcg_gen_andi_i32(QREG_CC_DEST, QREG_MACSR, 0xf);
2739 s->cc_op = CC_OP_FLAGS;
2740 }
2741
2742 DISAS_INSN(to_mac)
2743 {
2744 TCGv_i64 acc;
2745 TCGv val;
2746 int accnum;
2747 accnum = (insn >> 9) & 3;
2748 acc = MACREG(accnum);
2749 SRC_EA(env, val, OS_LONG, 0, NULL);
2750 if (s->env->macsr & MACSR_FI) {
2751 tcg_gen_ext_i32_i64(acc, val);
2752 tcg_gen_shli_i64(acc, acc, 8);
2753 } else if (s->env->macsr & MACSR_SU) {
2754 tcg_gen_ext_i32_i64(acc, val);
2755 } else {
2756 tcg_gen_extu_i32_i64(acc, val);
2757 }
2758 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2759 gen_mac_clear_flags();
2760 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
2761 }
2762
2763 DISAS_INSN(to_macsr)
2764 {
2765 TCGv val;
2766 SRC_EA(env, val, OS_LONG, 0, NULL);
2767 gen_helper_set_macsr(cpu_env, val);
2768 gen_lookup_tb(s);
2769 }
2770
2771 DISAS_INSN(to_mask)
2772 {
2773 TCGv val;
2774 SRC_EA(env, val, OS_LONG, 0, NULL);
2775 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
2776 }
2777
2778 DISAS_INSN(to_mext)
2779 {
2780 TCGv val;
2781 TCGv acc;
2782 SRC_EA(env, val, OS_LONG, 0, NULL);
2783 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2784 if (s->env->macsr & MACSR_FI)
2785 gen_helper_set_mac_extf(cpu_env, val, acc);
2786 else if (s->env->macsr & MACSR_SU)
2787 gen_helper_set_mac_exts(cpu_env, val, acc);
2788 else
2789 gen_helper_set_mac_extu(cpu_env, val, acc);
2790 }
2791
2792 static disas_proc opcode_table[65536];
2793
2794 static void
2795 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
2796 {
2797 int i;
2798 int from;
2799 int to;
2800
2801 /* Sanity check. All set bits must be included in the mask. */
2802 if (opcode & ~mask) {
2803 fprintf(stderr,
2804 "qemu internal error: bogus opcode definition %04x/%04x\n",
2805 opcode, mask);
2806 abort();
2807 }
2808 /* This could probably be cleverer. For now just optimize the case where
2809 the top bits are known. */
2810 /* Find the first zero bit in the mask. */
2811 i = 0x8000;
2812 while ((i & mask) != 0)
2813 i >>= 1;
2814 /* Iterate over all combinations of this and lower bits. */
2815 if (i == 0)
2816 i = 1;
2817 else
2818 i <<= 1;
2819 from = opcode & ~(i - 1);
2820 to = from + i;
2821 for (i = from; i < to; i++) {
2822 if ((i & mask) == opcode)
2823 opcode_table[i] = proc;
2824 }
2825 }
2826
2827 /* Register m68k opcode handlers. Order is important.
2828 Later insn override earlier ones. */
2829 void register_m68k_insns (CPUM68KState *env)
2830 {
2831 #define INSN(name, opcode, mask, feature) do { \
2832 if (m68k_feature(env, M68K_FEATURE_##feature)) \
2833 register_opcode(disas_##name, 0x##opcode, 0x##mask); \
2834 } while(0)
2835 INSN(undef, 0000, 0000, CF_ISA_A);
2836 INSN(arith_im, 0080, fff8, CF_ISA_A);
2837 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
2838 INSN(bitop_reg, 0100, f1c0, CF_ISA_A);
2839 INSN(bitop_reg, 0140, f1c0, CF_ISA_A);
2840 INSN(bitop_reg, 0180, f1c0, CF_ISA_A);
2841 INSN(bitop_reg, 01c0, f1c0, CF_ISA_A);
2842 INSN(arith_im, 0280, fff8, CF_ISA_A);
2843 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
2844 INSN(arith_im, 0480, fff8, CF_ISA_A);
2845 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
2846 INSN(arith_im, 0680, fff8, CF_ISA_A);
2847 INSN(bitop_im, 0800, ffc0, CF_ISA_A);
2848 INSN(bitop_im, 0840, ffc0, CF_ISA_A);
2849 INSN(bitop_im, 0880, ffc0, CF_ISA_A);
2850 INSN(bitop_im, 08c0, ffc0, CF_ISA_A);
2851 INSN(arith_im, 0a80, fff8, CF_ISA_A);
2852 INSN(arith_im, 0c00, ff38, CF_ISA_A);
2853 INSN(move, 1000, f000, CF_ISA_A);
2854 INSN(move, 2000, f000, CF_ISA_A);
2855 INSN(move, 3000, f000, CF_ISA_A);
2856 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
2857 INSN(negx, 4080, fff8, CF_ISA_A);
2858 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
2859 INSN(lea, 41c0, f1c0, CF_ISA_A);
2860 INSN(clr, 4200, ff00, CF_ISA_A);
2861 INSN(undef, 42c0, ffc0, CF_ISA_A);
2862 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
2863 INSN(neg, 4480, fff8, CF_ISA_A);
2864 INSN(move_to_ccr, 44c0, ffc0, CF_ISA_A);
2865 INSN(not, 4680, fff8, CF_ISA_A);
2866 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
2867 INSN(pea, 4840, ffc0, CF_ISA_A);
2868 INSN(swap, 4840, fff8, CF_ISA_A);
2869 INSN(movem, 48c0, fbc0, CF_ISA_A);
2870 INSN(ext, 4880, fff8, CF_ISA_A);
2871 INSN(ext, 48c0, fff8, CF_ISA_A);
2872 INSN(ext, 49c0, fff8, CF_ISA_A);
2873 INSN(tst, 4a00, ff00, CF_ISA_A);
2874 INSN(tas, 4ac0, ffc0, CF_ISA_B);
2875 INSN(halt, 4ac8, ffff, CF_ISA_A);
2876 INSN(pulse, 4acc, ffff, CF_ISA_A);
2877 INSN(illegal, 4afc, ffff, CF_ISA_A);
2878 INSN(mull, 4c00, ffc0, CF_ISA_A);
2879 INSN(divl, 4c40, ffc0, CF_ISA_A);
2880 INSN(sats, 4c80, fff8, CF_ISA_B);
2881 INSN(trap, 4e40, fff0, CF_ISA_A);
2882 INSN(link, 4e50, fff8, CF_ISA_A);
2883 INSN(unlk, 4e58, fff8, CF_ISA_A);
2884 INSN(move_to_usp, 4e60, fff8, USP);
2885 INSN(move_from_usp, 4e68, fff8, USP);
2886 INSN(nop, 4e71, ffff, CF_ISA_A);
2887 INSN(stop, 4e72, ffff, CF_ISA_A);
2888 INSN(rte, 4e73, ffff, CF_ISA_A);
2889 INSN(rts, 4e75, ffff, CF_ISA_A);
2890 INSN(movec, 4e7b, ffff, CF_ISA_A);
2891 INSN(jump, 4e80, ffc0, CF_ISA_A);
2892 INSN(jump, 4ec0, ffc0, CF_ISA_A);
2893 INSN(addsubq, 5180, f1c0, CF_ISA_A);
2894 INSN(scc, 50c0, f0f8, CF_ISA_A);
2895 INSN(addsubq, 5080, f1c0, CF_ISA_A);
2896 INSN(tpf, 51f8, fff8, CF_ISA_A);
2897
2898 /* Branch instructions. */
2899 INSN(branch, 6000, f000, CF_ISA_A);
2900 /* Disable long branch instructions, then add back the ones we want. */
2901 INSN(undef, 60ff, f0ff, CF_ISA_A); /* All long branches. */
2902 INSN(branch, 60ff, f0ff, CF_ISA_B);
2903 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
2904 INSN(branch, 60ff, ffff, BRAL);
2905
2906 INSN(moveq, 7000, f100, CF_ISA_A);
2907 INSN(mvzs, 7100, f100, CF_ISA_B);
2908 INSN(or, 8000, f000, CF_ISA_A);
2909 INSN(divw, 80c0, f0c0, CF_ISA_A);
2910 INSN(addsub, 9000, f000, CF_ISA_A);
2911 INSN(subx, 9180, f1f8, CF_ISA_A);
2912 INSN(suba, 91c0, f1c0, CF_ISA_A);
2913
2914 INSN(undef_mac, a000, f000, CF_ISA_A);
2915 INSN(mac, a000, f100, CF_EMAC);
2916 INSN(from_mac, a180, f9b0, CF_EMAC);
2917 INSN(move_mac, a110, f9fc, CF_EMAC);
2918 INSN(from_macsr,a980, f9f0, CF_EMAC);
2919 INSN(from_mask, ad80, fff0, CF_EMAC);
2920 INSN(from_mext, ab80, fbf0, CF_EMAC);
2921 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
2922 INSN(to_mac, a100, f9c0, CF_EMAC);
2923 INSN(to_macsr, a900, ffc0, CF_EMAC);
2924 INSN(to_mext, ab00, fbc0, CF_EMAC);
2925 INSN(to_mask, ad00, ffc0, CF_EMAC);
2926
2927 INSN(mov3q, a140, f1c0, CF_ISA_B);
2928 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
2929 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
2930 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
2931 INSN(cmp, b080, f1c0, CF_ISA_A);
2932 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
2933 INSN(eor, b180, f1c0, CF_ISA_A);
2934 INSN(and, c000, f000, CF_ISA_A);
2935 INSN(mulw, c0c0, f0c0, CF_ISA_A);
2936 INSN(addsub, d000, f000, CF_ISA_A);
2937 INSN(addx, d180, f1f8, CF_ISA_A);
2938 INSN(adda, d1c0, f1c0, CF_ISA_A);
2939 INSN(shift_im, e080, f0f0, CF_ISA_A);
2940 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
2941 INSN(undef_fpu, f000, f000, CF_ISA_A);
2942 INSN(fpu, f200, ffc0, CF_FPU);
2943 INSN(fbcc, f280, ffc0, CF_FPU);
2944 INSN(frestore, f340, ffc0, CF_FPU);
2945 INSN(fsave, f340, ffc0, CF_FPU);
2946 INSN(intouch, f340, ffc0, CF_ISA_A);
2947 INSN(cpushl, f428, ff38, CF_ISA_A);
2948 INSN(wddata, fb00, ff00, CF_ISA_A);
2949 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
2950 #undef INSN
2951 }
2952
2953 /* ??? Some of this implementation is not exception safe. We should always
2954 write back the result to memory before setting the condition codes. */
2955 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
2956 {
2957 uint16_t insn;
2958
2959 insn = cpu_lduw_code(env, s->pc);
2960 s->pc += 2;
2961
2962 opcode_table[insn](env, s, insn);
2963 }
2964
2965 /* generate intermediate code for basic block 'tb'. */
2966 void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
2967 {
2968 M68kCPU *cpu = m68k_env_get_cpu(env);
2969 CPUState *cs = CPU(cpu);
2970 DisasContext dc1, *dc = &dc1;
2971 target_ulong pc_start;
2972 int pc_offset;
2973 int num_insns;
2974 int max_insns;
2975
2976 /* generate intermediate code */
2977 pc_start = tb->pc;
2978
2979 dc->tb = tb;
2980
2981 dc->env = env;
2982 dc->is_jmp = DISAS_NEXT;
2983 dc->pc = pc_start;
2984 dc->cc_op = CC_OP_DYNAMIC;
2985 dc->singlestep_enabled = cs->singlestep_enabled;
2986 dc->fpcr = env->fpcr;
2987 dc->user = (env->sr & SR_S) == 0;
2988 dc->done_mac = 0;
2989 num_insns = 0;
2990 max_insns = tb->cflags & CF_COUNT_MASK;
2991 if (max_insns == 0) {
2992 max_insns = CF_COUNT_MASK;
2993 }
2994 if (max_insns > TCG_MAX_INSNS) {
2995 max_insns = TCG_MAX_INSNS;
2996 }
2997
2998 gen_tb_start(tb);
2999 do {
3000 pc_offset = dc->pc - pc_start;
3001 gen_throws_exception = NULL;
3002 tcg_gen_insn_start(dc->pc);
3003 num_insns++;
3004
3005 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3006 gen_exception(dc, dc->pc, EXCP_DEBUG);
3007 dc->is_jmp = DISAS_JUMP;
3008 /* The address covered by the breakpoint must be included in
3009 [tb->pc, tb->pc + tb->size) in order to for it to be
3010 properly cleared -- thus we increment the PC here so that
3011 the logic setting tb->size below does the right thing. */
3012 dc->pc += 2;
3013 break;
3014 }
3015
3016 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
3017 gen_io_start();
3018 }
3019
3020 dc->insn_pc = dc->pc;
3021 disas_m68k_insn(env, dc);
3022 } while (!dc->is_jmp && !tcg_op_buf_full() &&
3023 !cs->singlestep_enabled &&
3024 !singlestep &&
3025 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
3026 num_insns < max_insns);
3027
3028 if (tb->cflags & CF_LAST_IO)
3029 gen_io_end();
3030 if (unlikely(cs->singlestep_enabled)) {
3031 /* Make sure the pc is updated, and raise a debug exception. */
3032 if (!dc->is_jmp) {
3033 gen_flush_cc_op(dc);
3034 tcg_gen_movi_i32(QREG_PC, dc->pc);
3035 }
3036 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
3037 } else {
3038 switch(dc->is_jmp) {
3039 case DISAS_NEXT:
3040 gen_flush_cc_op(dc);
3041 gen_jmp_tb(dc, 0, dc->pc);
3042 break;
3043 default:
3044 case DISAS_JUMP:
3045 case DISAS_UPDATE:
3046 gen_flush_cc_op(dc);
3047 /* indicate that the hash table must be used to find the next TB */
3048 tcg_gen_exit_tb(0);
3049 break;
3050 case DISAS_TB_JUMP:
3051 /* nothing more to generate */
3052 break;
3053 }
3054 }
3055 gen_tb_end(tb, num_insns);
3056
3057 #ifdef DEBUG_DISAS
3058 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3059 qemu_log("----------------\n");
3060 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3061 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
3062 qemu_log("\n");
3063 }
3064 #endif
3065 tb->size = dc->pc - pc_start;
3066 tb->icount = num_insns;
3067 }
3068
3069 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3070 int flags)
3071 {
3072 M68kCPU *cpu = M68K_CPU(cs);
3073 CPUM68KState *env = &cpu->env;
3074 int i;
3075 uint16_t sr;
3076 CPU_DoubleU u;
3077 for (i = 0; i < 8; i++)
3078 {
3079 u.d = env->fregs[i];
3080 cpu_fprintf (f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3081 i, env->dregs[i], i, env->aregs[i],
3082 i, u.l.upper, u.l.lower, *(double *)&u.d);
3083 }
3084 cpu_fprintf (f, "PC = %08x ", env->pc);
3085 sr = env->sr;
3086 cpu_fprintf (f, "SR = %04x %c%c%c%c%c ", sr, (sr & 0x10) ? 'X' : '-',
3087 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
3088 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
3089 cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
3090 }
3091
3092 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
3093 target_ulong *data)
3094 {
3095 env->pc = data[0];
3096 }
QEmu