target-openrisc/mmu.c

   1 /*
   2  * OpenRISC MMU.
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Zhizhou Zhang <etouzh@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #include "exec/gdbstub.h"
  24 #include "qemu/host-utils.h"
  25 #ifndef CONFIG_USER_ONLY
  26 #include "hw/loader.h"
  27 #endif
  28
  29 #ifndef CONFIG_USER_ONLY
  30 int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
  31                                 hwaddr *physical,
  32                                 int *prot, target_ulong address, int rw)
  33 {
  34     *physical = address;
  35     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
  36     return TLBRET_MATCH;
  37 }
  38
  39 int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
  40                                hwaddr *physical,
  41                                int *prot, target_ulong address, int rw)
  42 {
  43     int vpn = address >> TARGET_PAGE_BITS;
  44     int idx = vpn & ITLB_MASK;
  45     int right = 0;
  46
  47     if ((cpu->env.tlb->itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
  48         return TLBRET_NOMATCH;
  49     }
  50     if (!(cpu->env.tlb->itlb[0][idx].mr & 1)) {
  51         return TLBRET_INVALID;
  52     }
  53
  54     if (cpu->env.sr & SR_SM) { /* supervisor mode */
  55         if (cpu->env.tlb->itlb[0][idx].tr & SXE) {
  56             right |= PAGE_EXEC;
  57         }
  58     } else {
  59         if (cpu->env.tlb->itlb[0][idx].tr & UXE) {
  60             right |= PAGE_EXEC;
  61         }
  62     }
  63
  64     if ((rw & 2) && ((right & PAGE_EXEC) == 0)) {
  65         return TLBRET_BADADDR;
  66     }
  67
  68     *physical = (cpu->env.tlb->itlb[0][idx].tr & TARGET_PAGE_MASK) |
  69                 (address & (TARGET_PAGE_SIZE-1));
  70     *prot = right;
  71     return TLBRET_MATCH;
  72 }
  73
  74 int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
  75                                hwaddr *physical,
  76                                int *prot, target_ulong address, int rw)
  77 {
  78     int vpn = address >> TARGET_PAGE_BITS;
  79     int idx = vpn & DTLB_MASK;
  80     int right = 0;
  81
  82     if ((cpu->env.tlb->dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
  83         return TLBRET_NOMATCH;
  84     }
  85     if (!(cpu->env.tlb->dtlb[0][idx].mr & 1)) {
  86         return TLBRET_INVALID;
  87     }
  88
  89     if (cpu->env.sr & SR_SM) { /* supervisor mode */
  90         if (cpu->env.tlb->dtlb[0][idx].tr & SRE) {
  91             right |= PAGE_READ;
  92         }
  93         if (cpu->env.tlb->dtlb[0][idx].tr & SWE) {
  94             right |= PAGE_WRITE;
  95         }
  96     } else {
  97         if (cpu->env.tlb->dtlb[0][idx].tr & URE) {
  98             right |= PAGE_READ;
  99         }
 100         if (cpu->env.tlb->dtlb[0][idx].tr & UWE) {
 101             right |= PAGE_WRITE;
 102         }
 103     }
 104
 105     if (!(rw & 1) && ((right & PAGE_READ) == 0)) {
 106         return TLBRET_BADADDR;
 107     }
 108     if ((rw & 1) && ((right & PAGE_WRITE) == 0)) {
 109         return TLBRET_BADADDR;
 110     }
 111
 112     *physical = (cpu->env.tlb->dtlb[0][idx].tr & TARGET_PAGE_MASK) |
 113                 (address & (TARGET_PAGE_SIZE-1));
 114     *prot = right;
 115     return TLBRET_MATCH;
 116 }
 117
 118 static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
 119                                       hwaddr *physical,
 120                                       int *prot, target_ulong address,
 121                                       int rw)
 122 {
 123     int ret = TLBRET_MATCH;
 124
 125     if (rw == 2) {    /* ITLB */
 126        *physical = 0;
 127         ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical,
 128                                                           prot, address, rw);
 129     } else {          /* DTLB */
 130         ret = cpu->env.tlb->cpu_openrisc_map_address_data(cpu, physical,
 131                                                           prot, address, rw);
 132     }
 133
 134     return ret;
 135 }
 136 #endif
 137
 138 static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
 139                                              target_ulong address,
 140                                              int rw, int tlb_error)
 141 {
 142     int exception = 0;
 143
 144     switch (tlb_error) {
 145     default:
 146         if (rw == 2) {
 147             exception = EXCP_IPF;
 148         } else {
 149             exception = EXCP_DPF;
 150         }
 151         break;
 152 #ifndef CONFIG_USER_ONLY
 153     case TLBRET_BADADDR:
 154         if (rw == 2) {
 155             exception = EXCP_IPF;
 156         } else {
 157             exception = EXCP_DPF;
 158         }
 159         break;
 160     case TLBRET_INVALID:
 161     case TLBRET_NOMATCH:
 162         /* No TLB match for a mapped address */
 163         if (rw == 2) {
 164             exception = EXCP_ITLBMISS;
 165         } else {
 166             exception = EXCP_DTLBMISS;
 167         }
 168         break;
 169 #endif
 170     }
 171
 172     cpu->env.exception_index = exception;
 173     cpu->env.eear = address;
 174 }
 175
 176 #ifndef CONFIG_USER_ONLY
 177 int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
 178                                   target_ulong address, int rw, int mmu_idx)
 179 {
 180     int ret = 0;
 181     hwaddr physical = 0;
 182     int prot = 0;
 183     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
 184
 185     ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot,
 186                                      address, rw);
 187
 188     if (ret == TLBRET_MATCH) {
 189         tlb_set_page(env, address & TARGET_PAGE_MASK,
 190                      physical & TARGET_PAGE_MASK, prot,
 191                      mmu_idx, TARGET_PAGE_SIZE);
 192         ret = 0;
 193     } else if (ret < 0) {
 194         cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
 195         ret = 1;
 196     }
 197
 198     return ret;
 199 }
 200 #else
 201 int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
 202                                   target_ulong address, int rw, int mmu_idx)
 203 {
 204     int ret = 0;
 205     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
 206
 207     cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
 208     ret = 1;
 209
 210     return ret;
 211 }
 212 #endif
 213
 214 #ifndef CONFIG_USER_ONLY
 215 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 216 {
 217     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
 218     hwaddr phys_addr;
 219     int prot;
 220
 221     if (cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0)) {
 222         return -1;
 223     }
 224
 225     return phys_addr;
 226 }
 227
 228 void cpu_openrisc_mmu_init(OpenRISCCPU *cpu)
 229 {
 230     cpu->env.tlb = g_malloc0(sizeof(CPUOpenRISCTLBContext));
 231
 232     cpu->env.tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
 233     cpu->env.tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
 234 }
 235 #endif