hw/pcie.c

   1 /*
   2  * pcie.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "sysemu.h"
  22 #include "range.h"
  23 #include "pci_bridge.h"
  24 #include "pcie.h"
  25 #include "msix.h"
  26 #include "msi.h"
  27 #include "pci_internals.h"
  28 #include "pcie_regs.h"
  29 #include "range.h"
  30
  31 //#define DEBUG_PCIE
  32 #ifdef DEBUG_PCIE
  33 # define PCIE_DPRINTF(fmt, ...)                                         \
  34     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  35 #else
  36 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
  37 #endif
  38 #define PCIE_DEV_PRINTF(dev, fmt, ...)                                  \
  39     PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  40
  41
  42 /***************************************************************************
  43  * pci express capability helper functions
  44  */
  45 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
  46 {
  47     int pos;
  48     uint8_t *exp_cap;
  49
  50     assert(pci_is_express(dev));
  51
  52     pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
  53                                  PCI_EXP_VER2_SIZEOF);
  54     if (pos < 0) {
  55         return pos;
  56     }
  57     dev->exp.exp_cap = pos;
  58     exp_cap = dev->config + pos;
  59
  60     /* capability register
  61        interrupt message number defaults to 0 */
  62     pci_set_word(exp_cap + PCI_EXP_FLAGS,
  63                  ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
  64                  PCI_EXP_FLAGS_VER2);
  65
  66     /* device capability register
  67      * table 7-12:
  68      * roll based error reporting bit must be set by all
  69      * Functions conforming to the ECN, PCI Express Base
  70      * Specification, Revision 1.1., or subsequent PCI Express Base
  71      * Specification revisions.
  72      */
  73     pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
  74
  75     pci_set_long(exp_cap + PCI_EXP_LNKCAP,
  76                  (port << PCI_EXP_LNKCAP_PN_SHIFT) |
  77                  PCI_EXP_LNKCAP_ASPMS_0S |
  78                  PCI_EXP_LNK_MLW_1 |
  79                  PCI_EXP_LNK_LS_25);
  80
  81     pci_set_word(exp_cap + PCI_EXP_LNKSTA,
  82                  PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
  83
  84     pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
  85                  PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
  86
  87     pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB);
  88     return pos;
  89 }
  90
  91 void pcie_cap_exit(PCIDevice *dev)
  92 {
  93     pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
  94 }
  95
  96 uint8_t pcie_cap_get_type(const PCIDevice *dev)
  97 {
  98     uint32_t pos = dev->exp.exp_cap;
  99     assert(pos > 0);
 100     return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
 101             PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
 102 }
 103
 104 /* MSI/MSI-X */
 105 /* pci express interrupt message number */
 106 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
 107 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
 108 {
 109     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 110     assert(vector < 32);
 111     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
 112     pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
 113                                vector << PCI_EXP_FLAGS_IRQ_SHIFT);
 114 }
 115
 116 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
 117 {
 118     return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
 119             PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
 120 }
 121
 122 void pcie_cap_deverr_init(PCIDevice *dev)
 123 {
 124     uint32_t pos = dev->exp.exp_cap;
 125     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
 126                                PCI_EXP_DEVCAP_RBER);
 127     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
 128                                PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 129                                PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 130     pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
 131                                PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
 132                                PCI_EXP_DEVSTA_URD | PCI_EXP_DEVSTA_URD);
 133 }
 134
 135 void pcie_cap_deverr_reset(PCIDevice *dev)
 136 {
 137     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 138     pci_long_test_and_clear_mask(devctl,
 139                                  PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 140                                  PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 141 }
 142
 143 /*
 144  * A PCI Express Hot-Plug Event has occured, so update slot status register
 145  * and notify OS of the event if necessary.
 146  *
 147  * 6.7.3 PCI Express Hot-Plug Events
 148  * 6.7.3.4 Software Notification of Hot-Plug Events
 149  */
 150 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
 151 {
 152     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 153     uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
 154     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 155
 156     PCIE_DEV_PRINTF(dev,
 157                     "sltctl: 0x%02"PRIx16" sltsta: 0x%02"PRIx16" event: %x\n",
 158                     sltctl, sltsta, event);
 159
 160     if (pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, event)) {
 161         return;
 162     }
 163     sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 164     PCIE_DEV_PRINTF(dev, "sltsta -> %02"PRIx16"\n", sltsta);
 165
 166     if ((sltctl & PCI_EXP_SLTCTL_HPIE) &&
 167         (sltctl & event & PCI_EXP_HP_EV_SUPPORTED)) {
 168         if (pci_msi_enabled(dev)) {
 169             pci_msi_notify(dev, pcie_cap_flags_get_vector(dev));
 170         } else {
 171             qemu_set_irq(dev->irq[dev->exp.hpev_intx], 1);
 172         }
 173     }
 174 }
 175
 176 static int pcie_cap_slot_hotplug(DeviceState *qdev,
 177                                  PCIDevice *pci_dev, int state)
 178 {
 179     PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
 180     uint8_t *exp_cap = d->config + d->exp.exp_cap;
 181     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 182
 183     if (!pci_dev->qdev.hotplugged) {
 184         assert(state); /* this case only happens at machine creation. */
 185         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 186                                    PCI_EXP_SLTSTA_PDS);
 187         return 0;
 188     }
 189
 190     PCIE_DEV_PRINTF(pci_dev, "hotplug state: %d\n", state);
 191     if (sltsta & PCI_EXP_SLTSTA_EIS) {
 192         /* the slot is electromechanically locked.
 193          * This error is propagated up to qdev and then to HMP/QMP.
 194          */
 195         return -EBUSY;
 196     }
 197
 198     /* TODO: multifunction hot-plug.
 199      * Right now, only a device of function = 0 is allowed to be
 200      * hot plugged/unplugged.
 201      */
 202     assert(PCI_FUNC(pci_dev->devfn) == 0);
 203
 204     if (state) {
 205         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 206                                    PCI_EXP_SLTSTA_PDS);
 207         pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 208     } else {
 209         qdev_free(&pci_dev->qdev);
 210         pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 211                                      PCI_EXP_SLTSTA_PDS);
 212         pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 213     }
 214     return 0;
 215 }
 216
 217 /* pci express slot for pci express root/downstream port
 218    PCI express capability slot registers */
 219 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
 220 {
 221     uint32_t pos = dev->exp.exp_cap;
 222
 223     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
 224                                PCI_EXP_FLAGS_SLOT);
 225
 226     pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
 227                                  ~PCI_EXP_SLTCAP_PSN);
 228     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
 229                                (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
 230                                PCI_EXP_SLTCAP_EIP |
 231                                PCI_EXP_SLTCAP_HPS |
 232                                PCI_EXP_SLTCAP_HPC |
 233                                PCI_EXP_SLTCAP_PIP |
 234                                PCI_EXP_SLTCAP_AIP |
 235                                PCI_EXP_SLTCAP_ABP);
 236
 237     pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
 238                                  PCI_EXP_SLTCTL_PIC |
 239                                  PCI_EXP_SLTCTL_AIC);
 240     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
 241                                PCI_EXP_SLTCTL_PIC_OFF |
 242                                PCI_EXP_SLTCTL_AIC_OFF);
 243     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 244                                PCI_EXP_SLTCTL_PIC |
 245                                PCI_EXP_SLTCTL_AIC |
 246                                PCI_EXP_SLTCTL_HPIE |
 247                                PCI_EXP_SLTCTL_CCIE |
 248                                PCI_EXP_SLTCTL_PDCE |
 249                                PCI_EXP_SLTCTL_ABPE);
 250     /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
 251      * make the bit writable here in order to detect 1b is written.
 252      * pcie_cap_slot_write_config() test-and-clear the bit, so
 253      * this bit always returns 0 to the guest.
 254      */
 255     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 256                                PCI_EXP_SLTCTL_EIC);
 257
 258     pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
 259                                PCI_EXP_HP_EV_SUPPORTED);
 260
 261     pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev)),
 262                     pcie_cap_slot_hotplug, &dev->qdev);
 263 }
 264
 265 void pcie_cap_slot_reset(PCIDevice *dev)
 266 {
 267     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 268
 269     PCIE_DEV_PRINTF(dev, "reset\n");
 270
 271     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 272                                  PCI_EXP_SLTCTL_EIC |
 273                                  PCI_EXP_SLTCTL_PIC |
 274                                  PCI_EXP_SLTCTL_AIC |
 275                                  PCI_EXP_SLTCTL_HPIE |
 276                                  PCI_EXP_SLTCTL_CCIE |
 277                                  PCI_EXP_SLTCTL_PDCE |
 278                                  PCI_EXP_SLTCTL_ABPE);
 279     pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
 280                                PCI_EXP_SLTCTL_PIC_OFF |
 281                                PCI_EXP_SLTCTL_AIC_OFF);
 282
 283     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 284                                  PCI_EXP_SLTSTA_EIS |/* on reset,
 285                                                         the lock is released */
 286                                  PCI_EXP_SLTSTA_CC |
 287                                  PCI_EXP_SLTSTA_PDC |
 288                                  PCI_EXP_SLTSTA_ABP);
 289 }
 290
 291 void pcie_cap_slot_write_config(PCIDevice *dev,
 292                                 uint32_t addr, uint32_t val, int len,
 293                                 uint16_t sltctl_prev)
 294 {
 295     uint32_t pos = dev->exp.exp_cap;
 296     uint8_t *exp_cap = dev->config + pos;
 297     uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
 298     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 299
 300     if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
 301         return;
 302     }
 303
 304     PCIE_DEV_PRINTF(dev,
 305                     "addr: 0x%"PRIx32" val: 0x%"PRIx32" len: %d\n"
 306                     "\tsltctl_prev: 0x%02"PRIx16" sltctl: 0x%02"PRIx16
 307                     " sltsta: 0x%02"PRIx16"\n",
 308                     addr, val, len, sltctl_prev, sltctl, sltsta);
 309
 310     /* SLTCTL */
 311     PCIE_DEV_PRINTF(dev, "sltctl: 0x%02"PRIx16" -> 0x%02"PRIx16"\n",
 312                     sltctl_prev, sltctl);
 313
 314     if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 315                                      PCI_EXP_SLTCTL_EIC)) {
 316         sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
 317         pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
 318         PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
 319                         "sltsta -> 0x%02"PRIx16"\n",
 320                         sltsta);
 321     }
 322
 323     /*
 324      * The events control bits might be enabled or disabled,
 325      * Check if the software notificastion condition is satisfied
 326      * or disatisfied.
 327      *
 328      * 6.7.3.4 Software Notification of Hot-plug events
 329      */
 330     if (pci_msi_enabled(dev)) {
 331         bool msi_trigger =
 332             (sltctl & PCI_EXP_SLTCTL_HPIE) &&
 333             ((sltctl_prev ^ sltctl) & sltctl & /* stlctl: 0 -> 1 */
 334              sltsta & PCI_EXP_HP_EV_SUPPORTED);
 335         if (msi_trigger) {
 336             pci_msi_notify(dev, pcie_cap_flags_get_vector(dev));
 337         }
 338     } else {
 339         int int_level =
 340             (sltctl & PCI_EXP_SLTCTL_HPIE) &&
 341             (sltctl & sltsta & PCI_EXP_HP_EV_SUPPORTED);
 342         qemu_set_irq(dev->irq[dev->exp.hpev_intx], int_level);
 343     }
 344
 345     if (!((sltctl_prev ^ sltctl) & PCI_EXP_SLTCTL_SUPPORTED)) {
 346         PCIE_DEV_PRINTF(dev,
 347                         "sprious command completion slctl "
 348                         "0x%"PRIx16" -> 0x%"PRIx16"\n",
 349                         sltctl_prev, sltctl);
 350     }
 351
 352     /*
 353      * 6.7.3.2 Command Completed Events
 354      *
 355      * Software issues a command to a hot-plug capable Downstream Port by
 356      * issuing a write transaction that targets any portion of the Port’s Slot
 357      * Control register. A single write to the Slot Control register is
 358      * considered to be a single command, even if the write affects more than
 359      * one field in the Slot Control register. In response to this transaction,
 360      * the Port must carry out the requested actions and then set the
 361      * associated status field for the command completed event. */
 362
 363     /* Real hardware might take a while to complete requested command because
 364      * physical movement would be involved like locking the electromechanical
 365      * lock.  However in our case, command is completed instantaneously above,
 366      * so send a command completion event right now.
 367      */
 368     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
 369 }
 370
 371 void pcie_cap_slot_push_attention_button(PCIDevice *dev)
 372 {
 373     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
 374 }
 375
 376 /* root control/capabilities/status. PME isn't emulated for now */
 377 void pcie_cap_root_init(PCIDevice *dev)
 378 {
 379     pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
 380                  PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
 381                  PCI_EXP_RTCTL_SEFEE);
 382 }
 383
 384 void pcie_cap_root_reset(PCIDevice *dev)
 385 {
 386     pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
 387 }
 388
 389 /*
 390  * TODO: implement FLR:
 391  * Right now sets the bit which indicates FLR is supported.
 392  */
 393 /* function level reset(FLR) */
 394 void pcie_cap_flr_init(PCIDevice *dev)
 395 {
 396     pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
 397                                PCI_EXP_DEVCAP_FLR);
 398
 399     /* Although reading BCR_FLR returns always 0,
 400      * the bit is made writable here in order to detect the 1b is written
 401      * pcie_cap_flr_write_config() test-and-clear the bit, so
 402      * this bit always returns 0 to the guest.
 403      */
 404     pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
 405                                PCI_EXP_DEVCTL_BCR_FLR);
 406 }
 407
 408 void pcie_cap_flr_write_config(PCIDevice *dev,
 409                                uint32_t addr, uint32_t val, int len)
 410 {
 411     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 412     if (pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR)) {
 413         /* TODO: implement FLR */
 414     }
 415 }
 416
 417 /* Alternative Routing-ID Interpretation (ARI) */
 418 /* ari forwarding support for down stream port */
 419 void pcie_cap_ari_init(PCIDevice *dev)
 420 {
 421     uint32_t pos = dev->exp.exp_cap;
 422     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
 423                                PCI_EXP_DEVCAP2_ARI);
 424     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
 425                                PCI_EXP_DEVCTL2_ARI);
 426 }
 427
 428 void pcie_cap_ari_reset(PCIDevice *dev)
 429 {
 430     uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
 431     pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
 432 }
 433
 434 bool pcie_cap_is_ari_enabled(const PCIDevice *dev)
 435 {
 436     if (!pci_is_express(dev)) {
 437         return false;
 438     }
 439     if (!dev->exp.exp_cap) {
 440         return false;
 441     }
 442
 443     return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
 444         PCI_EXP_DEVCTL2_ARI;
 445 }
 446
 447 /**************************************************************************
 448  * pci express extended capability allocation functions
 449  * uint16_t ext_cap_id (16 bit)
 450  * uint8_t cap_ver (4 bit)
 451  * uint16_t cap_offset (12 bit)
 452  * uint16_t ext_cap_size
 453  */
 454
 455 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id,
 456                                           uint16_t *prev_p)
 457 {
 458     uint16_t prev = 0;
 459     uint16_t next;
 460     uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
 461
 462     if (!header) {
 463         /* no extended capability */
 464         next = 0;
 465         goto out;
 466     }
 467     for (next = PCI_CONFIG_SPACE_SIZE; next;
 468          prev = next, next = PCI_EXT_CAP_NEXT(header)) {
 469
 470         assert(next >= PCI_CONFIG_SPACE_SIZE);
 471         assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
 472
 473         header = pci_get_long(dev->config + next);
 474         if (PCI_EXT_CAP_ID(header) == cap_id) {
 475             break;
 476         }
 477     }
 478
 479 out:
 480     if (prev_p) {
 481         *prev_p = prev;
 482     }
 483     return next;
 484 }
 485
 486 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
 487 {
 488     return pcie_find_capability_list(dev, cap_id, NULL);
 489 }
 490
 491 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
 492 {
 493     uint16_t header = pci_get_long(dev->config + pos);
 494     assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
 495     header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
 496         ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
 497     pci_set_long(dev->config + pos, header);
 498 }
 499
 500 /*
 501  * caller must supply valid (offset, size) * such that the range shouldn't
 502  * overlap with other capability or other registers.
 503  * This function doesn't check it.
 504  */
 505 void pcie_add_capability(PCIDevice *dev,
 506                          uint16_t cap_id, uint8_t cap_ver,
 507                          uint16_t offset, uint16_t size)
 508 {
 509     uint32_t header;
 510     uint16_t next;
 511
 512     assert(offset >= PCI_CONFIG_SPACE_SIZE);
 513     assert(offset < offset + size);
 514     assert(offset + size < PCIE_CONFIG_SPACE_SIZE);
 515     assert(size >= 8);
 516     assert(pci_is_express(dev));
 517
 518     if (offset == PCI_CONFIG_SPACE_SIZE) {
 519         header = pci_get_long(dev->config + offset);
 520         next = PCI_EXT_CAP_NEXT(header);
 521     } else {
 522         uint16_t prev;
 523
 524         /* 0 is reserved cap id. use internally to find the last capability
 525            in the linked list */
 526         next = pcie_find_capability_list(dev, 0, &prev);
 527
 528         assert(prev >= PCI_CONFIG_SPACE_SIZE);
 529         assert(next == 0);
 530         pcie_ext_cap_set_next(dev, prev, offset);
 531     }
 532     pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next));
 533
 534     /* Make capability read-only by default */
 535     memset(dev->wmask + offset, 0, size);
 536     memset(dev->w1cmask + offset, 0, size);
 537     /* Check capability by default */
 538     memset(dev->cmask + offset, 0xFF, size);
 539 }
 540
 541 /**************************************************************************
 542  * pci express extended capability helper functions
 543  */
 544
 545 /* ARI */
 546 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
 547 {
 548     pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
 549                         offset, PCI_ARI_SIZEOF);
 550     pci_set_long(dev->config + offset + PCI_ARI_CAP, PCI_ARI_CAP_NFN(nextfn));
 551 }