tcg-sparc: Define TCG_TARGET_INSN_UNIT_SIZE
[qemu.git] / target-arm / kvm64.c
blobe115879d9abbeb18e4fc593febc66b02b6129586
1 /*
2 * ARM implementation of KVM hooks, 64 bit specific code
4 * Copyright Mian-M. Hamayun 2013, Virtual Open Systems
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
9 */
11 #include <stdio.h>
12 #include <sys/types.h>
13 #include <sys/ioctl.h>
14 #include <sys/mman.h>
16 #include <linux/kvm.h>
18 #include "qemu-common.h"
19 #include "qemu/timer.h"
20 #include "sysemu/sysemu.h"
21 #include "sysemu/kvm.h"
22 #include "kvm_arm.h"
23 #include "cpu.h"
24 #include "hw/arm/arm.h"
26 static inline void set_feature(uint64_t *features, int feature)
28 *features |= 1ULL << feature;
31 bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
33 /* Identify the feature bits corresponding to the host CPU, and
34 * fill out the ARMHostCPUClass fields accordingly. To do this
35 * we have to create a scratch VM, create a single CPU inside it,
36 * and then query that CPU for the relevant ID registers.
37 * For AArch64 we currently don't care about ID registers at
38 * all; we just want to know the CPU type.
40 int fdarray[3];
41 uint64_t features = 0;
42 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
43 * we know these will only support creating one kind of guest CPU,
44 * which is its preferred CPU type. Fortunately these old kernels
45 * support only a very limited number of CPUs.
47 static const uint32_t cpus_to_try[] = {
48 KVM_ARM_TARGET_AEM_V8,
49 KVM_ARM_TARGET_FOUNDATION_V8,
50 KVM_ARM_TARGET_CORTEX_A57,
51 QEMU_KVM_ARM_TARGET_NONE
53 struct kvm_vcpu_init init;
55 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
56 return false;
59 ahcc->target = init.target;
60 ahcc->dtb_compatible = "arm,arm-v8";
62 kvm_arm_destroy_scratch_host_vcpu(fdarray);
64 /* We can assume any KVM supporting CPU is at least a v8
65 * with VFPv4+Neon; this in turn implies most of the other
66 * feature bits.
68 set_feature(&features, ARM_FEATURE_V8);
69 set_feature(&features, ARM_FEATURE_VFP4);
70 set_feature(&features, ARM_FEATURE_NEON);
71 set_feature(&features, ARM_FEATURE_AARCH64);
73 ahcc->features = features;
75 return true;
78 int kvm_arch_init_vcpu(CPUState *cs)
80 ARMCPU *cpu = ARM_CPU(cs);
81 struct kvm_vcpu_init init;
82 int ret;
84 if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
85 !arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
86 fprintf(stderr, "KVM is not supported for this guest CPU type\n");
87 return -EINVAL;
90 init.target = cpu->kvm_target;
91 memset(init.features, 0, sizeof(init.features));
92 if (cpu->start_powered_off) {
93 init.features[0] = 1 << KVM_ARM_VCPU_POWER_OFF;
95 ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init);
97 /* TODO : support for save/restore/reset of system regs via tuple list */
99 return ret;
102 #define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
103 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
105 int kvm_arch_put_registers(CPUState *cs, int level)
107 struct kvm_one_reg reg;
108 uint64_t val;
109 int i;
110 int ret;
112 ARMCPU *cpu = ARM_CPU(cs);
113 CPUARMState *env = &cpu->env;
115 for (i = 0; i < 31; i++) {
116 reg.id = AARCH64_CORE_REG(regs.regs[i]);
117 reg.addr = (uintptr_t) &env->xregs[i];
118 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
119 if (ret) {
120 return ret;
124 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
125 * QEMU side we keep the current SP in xregs[31] as well.
127 if (env->pstate & PSTATE_SP) {
128 env->sp_el[1] = env->xregs[31];
129 } else {
130 env->sp_el[0] = env->xregs[31];
133 reg.id = AARCH64_CORE_REG(regs.sp);
134 reg.addr = (uintptr_t) &env->sp_el[0];
135 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
136 if (ret) {
137 return ret;
140 reg.id = AARCH64_CORE_REG(sp_el1);
141 reg.addr = (uintptr_t) &env->sp_el[1];
142 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
143 if (ret) {
144 return ret;
147 /* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
148 val = pstate_read(env);
149 reg.id = AARCH64_CORE_REG(regs.pstate);
150 reg.addr = (uintptr_t) &val;
151 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
152 if (ret) {
153 return ret;
156 reg.id = AARCH64_CORE_REG(regs.pc);
157 reg.addr = (uintptr_t) &env->pc;
158 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
159 if (ret) {
160 return ret;
163 reg.id = AARCH64_CORE_REG(elr_el1);
164 reg.addr = (uintptr_t) &env->elr_el1;
165 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
166 if (ret) {
167 return ret;
170 for (i = 0; i < KVM_NR_SPSR; i++) {
171 reg.id = AARCH64_CORE_REG(spsr[i]);
172 reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
173 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
174 if (ret) {
175 return ret;
179 /* TODO:
180 * FP state
181 * system registers
183 return ret;
186 int kvm_arch_get_registers(CPUState *cs)
188 struct kvm_one_reg reg;
189 uint64_t val;
190 int i;
191 int ret;
193 ARMCPU *cpu = ARM_CPU(cs);
194 CPUARMState *env = &cpu->env;
196 for (i = 0; i < 31; i++) {
197 reg.id = AARCH64_CORE_REG(regs.regs[i]);
198 reg.addr = (uintptr_t) &env->xregs[i];
199 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
200 if (ret) {
201 return ret;
205 reg.id = AARCH64_CORE_REG(regs.sp);
206 reg.addr = (uintptr_t) &env->sp_el[0];
207 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
208 if (ret) {
209 return ret;
212 reg.id = AARCH64_CORE_REG(sp_el1);
213 reg.addr = (uintptr_t) &env->sp_el[1];
214 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
215 if (ret) {
216 return ret;
219 reg.id = AARCH64_CORE_REG(regs.pstate);
220 reg.addr = (uintptr_t) &val;
221 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
222 if (ret) {
223 return ret;
225 pstate_write(env, val);
227 /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
228 * QEMU side we keep the current SP in xregs[31] as well.
230 if (env->pstate & PSTATE_SP) {
231 env->xregs[31] = env->sp_el[1];
232 } else {
233 env->xregs[31] = env->sp_el[0];
236 reg.id = AARCH64_CORE_REG(regs.pc);
237 reg.addr = (uintptr_t) &env->pc;
238 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
239 if (ret) {
240 return ret;
243 reg.id = AARCH64_CORE_REG(elr_el1);
244 reg.addr = (uintptr_t) &env->elr_el1;
245 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
246 if (ret) {
247 return ret;
250 for (i = 0; i < KVM_NR_SPSR; i++) {
251 reg.id = AARCH64_CORE_REG(spsr[i]);
252 reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
253 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
254 if (ret) {
255 return ret;
259 /* TODO: other registers */
260 return ret;
263 void kvm_arch_reset_vcpu(CPUState *cs)