2 * Marvell MV88W8618 / Freecom MusicPal emulation.
4 * Copyright (c) 2008 Jan Kiszka
6 * This code is licensed under the GNU GPL v2.
8 * Contributions after 2012-01-13 are licensed under the terms of the
9 * GNU GPL, version 2 or (at your option) any later version.
12 #include "hw/sysbus.h"
13 #include "hw/arm/arm.h"
14 #include "hw/devices.h"
16 #include "sysemu/sysemu.h"
17 #include "hw/boards.h"
18 #include "hw/char/serial.h"
19 #include "qemu/timer.h"
20 #include "hw/ptimer.h"
21 #include "block/block.h"
22 #include "hw/block/flash.h"
23 #include "ui/console.h"
24 #include "hw/i2c/i2c.h"
25 #include "sysemu/blockdev.h"
26 #include "exec/address-spaces.h"
27 #include "ui/pixel_ops.h"
29 #define MP_MISC_BASE 0x80002000
30 #define MP_MISC_SIZE 0x00001000
32 #define MP_ETH_BASE 0x80008000
33 #define MP_ETH_SIZE 0x00001000
35 #define MP_WLAN_BASE 0x8000C000
36 #define MP_WLAN_SIZE 0x00000800
38 #define MP_UART1_BASE 0x8000C840
39 #define MP_UART2_BASE 0x8000C940
41 #define MP_GPIO_BASE 0x8000D000
42 #define MP_GPIO_SIZE 0x00001000
44 #define MP_FLASHCFG_BASE 0x90006000
45 #define MP_FLASHCFG_SIZE 0x00001000
47 #define MP_AUDIO_BASE 0x90007000
49 #define MP_PIC_BASE 0x90008000
50 #define MP_PIC_SIZE 0x00001000
52 #define MP_PIT_BASE 0x90009000
53 #define MP_PIT_SIZE 0x00001000
55 #define MP_LCD_BASE 0x9000c000
56 #define MP_LCD_SIZE 0x00001000
58 #define MP_SRAM_BASE 0xC0000000
59 #define MP_SRAM_SIZE 0x00020000
61 #define MP_RAM_DEFAULT_SIZE 32*1024*1024
62 #define MP_FLASH_SIZE_MAX 32*1024*1024
64 #define MP_TIMER1_IRQ 4
65 #define MP_TIMER2_IRQ 5
66 #define MP_TIMER3_IRQ 6
67 #define MP_TIMER4_IRQ 7
70 #define MP_UART1_IRQ 11
71 #define MP_UART2_IRQ 11
72 #define MP_GPIO_IRQ 12
74 #define MP_AUDIO_IRQ 30
76 /* Wolfson 8750 I2C address */
77 #define MP_WM_ADDR 0x1A
79 /* Ethernet register offsets */
80 #define MP_ETH_SMIR 0x010
81 #define MP_ETH_PCXR 0x408
82 #define MP_ETH_SDCMR 0x448
83 #define MP_ETH_ICR 0x450
84 #define MP_ETH_IMR 0x458
85 #define MP_ETH_FRDP0 0x480
86 #define MP_ETH_FRDP1 0x484
87 #define MP_ETH_FRDP2 0x488
88 #define MP_ETH_FRDP3 0x48C
89 #define MP_ETH_CRDP0 0x4A0
90 #define MP_ETH_CRDP1 0x4A4
91 #define MP_ETH_CRDP2 0x4A8
92 #define MP_ETH_CRDP3 0x4AC
93 #define MP_ETH_CTDP0 0x4E0
94 #define MP_ETH_CTDP1 0x4E4
97 #define MP_ETH_SMIR_DATA 0x0000FFFF
98 #define MP_ETH_SMIR_ADDR 0x03FF0000
99 #define MP_ETH_SMIR_OPCODE (1 << 26) /* Read value */
100 #define MP_ETH_SMIR_RDVALID (1 << 27)
103 #define MP_ETH_PHY1_BMSR 0x00210000
104 #define MP_ETH_PHY1_PHYSID1 0x00410000
105 #define MP_ETH_PHY1_PHYSID2 0x00610000
107 #define MP_PHY_BMSR_LINK 0x0004
108 #define MP_PHY_BMSR_AUTONEG 0x0008
110 #define MP_PHY_88E3015 0x01410E20
112 /* TX descriptor status */
113 #define MP_ETH_TX_OWN (1U << 31)
115 /* RX descriptor status */
116 #define MP_ETH_RX_OWN (1U << 31)
118 /* Interrupt cause/mask bits */
119 #define MP_ETH_IRQ_RX_BIT 0
120 #define MP_ETH_IRQ_RX (1 << MP_ETH_IRQ_RX_BIT)
121 #define MP_ETH_IRQ_TXHI_BIT 2
122 #define MP_ETH_IRQ_TXLO_BIT 3
124 /* Port config bits */
125 #define MP_ETH_PCXR_2BSM_BIT 28 /* 2-byte incoming suffix */
127 /* SDMA command bits */
128 #define MP_ETH_CMD_TXHI (1 << 23)
129 #define MP_ETH_CMD_TXLO (1 << 22)
131 typedef struct mv88w8618_tx_desc
{
139 typedef struct mv88w8618_rx_desc
{
142 uint16_t buffer_size
;
147 #define TYPE_MV88W8618_ETH "mv88w8618_eth"
148 #define MV88W8618_ETH(obj) \
149 OBJECT_CHECK(mv88w8618_eth_state, (obj), TYPE_MV88W8618_ETH)
151 typedef struct mv88w8618_eth_state
{
153 SysBusDevice parent_obj
;
162 uint32_t vlan_header
;
163 uint32_t tx_queue
[2];
164 uint32_t rx_queue
[4];
165 uint32_t frx_queue
[4];
169 } mv88w8618_eth_state
;
171 static void eth_rx_desc_put(uint32_t addr
, mv88w8618_rx_desc
*desc
)
173 cpu_to_le32s(&desc
->cmdstat
);
174 cpu_to_le16s(&desc
->bytes
);
175 cpu_to_le16s(&desc
->buffer_size
);
176 cpu_to_le32s(&desc
->buffer
);
177 cpu_to_le32s(&desc
->next
);
178 cpu_physical_memory_write(addr
, desc
, sizeof(*desc
));
181 static void eth_rx_desc_get(uint32_t addr
, mv88w8618_rx_desc
*desc
)
183 cpu_physical_memory_read(addr
, desc
, sizeof(*desc
));
184 le32_to_cpus(&desc
->cmdstat
);
185 le16_to_cpus(&desc
->bytes
);
186 le16_to_cpus(&desc
->buffer_size
);
187 le32_to_cpus(&desc
->buffer
);
188 le32_to_cpus(&desc
->next
);
191 static int eth_can_receive(NetClientState
*nc
)
196 static ssize_t
eth_receive(NetClientState
*nc
, const uint8_t *buf
, size_t size
)
198 mv88w8618_eth_state
*s
= qemu_get_nic_opaque(nc
);
200 mv88w8618_rx_desc desc
;
203 for (i
= 0; i
< 4; i
++) {
204 desc_addr
= s
->cur_rx
[i
];
209 eth_rx_desc_get(desc_addr
, &desc
);
210 if ((desc
.cmdstat
& MP_ETH_RX_OWN
) && desc
.buffer_size
>= size
) {
211 cpu_physical_memory_write(desc
.buffer
+ s
->vlan_header
,
213 desc
.bytes
= size
+ s
->vlan_header
;
214 desc
.cmdstat
&= ~MP_ETH_RX_OWN
;
215 s
->cur_rx
[i
] = desc
.next
;
217 s
->icr
|= MP_ETH_IRQ_RX
;
218 if (s
->icr
& s
->imr
) {
219 qemu_irq_raise(s
->irq
);
221 eth_rx_desc_put(desc_addr
, &desc
);
224 desc_addr
= desc
.next
;
225 } while (desc_addr
!= s
->rx_queue
[i
]);
230 static void eth_tx_desc_put(uint32_t addr
, mv88w8618_tx_desc
*desc
)
232 cpu_to_le32s(&desc
->cmdstat
);
233 cpu_to_le16s(&desc
->res
);
234 cpu_to_le16s(&desc
->bytes
);
235 cpu_to_le32s(&desc
->buffer
);
236 cpu_to_le32s(&desc
->next
);
237 cpu_physical_memory_write(addr
, desc
, sizeof(*desc
));
240 static void eth_tx_desc_get(uint32_t addr
, mv88w8618_tx_desc
*desc
)
242 cpu_physical_memory_read(addr
, desc
, sizeof(*desc
));
243 le32_to_cpus(&desc
->cmdstat
);
244 le16_to_cpus(&desc
->res
);
245 le16_to_cpus(&desc
->bytes
);
246 le32_to_cpus(&desc
->buffer
);
247 le32_to_cpus(&desc
->next
);
250 static void eth_send(mv88w8618_eth_state
*s
, int queue_index
)
252 uint32_t desc_addr
= s
->tx_queue
[queue_index
];
253 mv88w8618_tx_desc desc
;
259 eth_tx_desc_get(desc_addr
, &desc
);
260 next_desc
= desc
.next
;
261 if (desc
.cmdstat
& MP_ETH_TX_OWN
) {
264 cpu_physical_memory_read(desc
.buffer
, buf
, len
);
265 qemu_send_packet(qemu_get_queue(s
->nic
), buf
, len
);
267 desc
.cmdstat
&= ~MP_ETH_TX_OWN
;
268 s
->icr
|= 1 << (MP_ETH_IRQ_TXLO_BIT
- queue_index
);
269 eth_tx_desc_put(desc_addr
, &desc
);
271 desc_addr
= next_desc
;
272 } while (desc_addr
!= s
->tx_queue
[queue_index
]);
275 static uint64_t mv88w8618_eth_read(void *opaque
, hwaddr offset
,
278 mv88w8618_eth_state
*s
= opaque
;
282 if (s
->smir
& MP_ETH_SMIR_OPCODE
) {
283 switch (s
->smir
& MP_ETH_SMIR_ADDR
) {
284 case MP_ETH_PHY1_BMSR
:
285 return MP_PHY_BMSR_LINK
| MP_PHY_BMSR_AUTONEG
|
287 case MP_ETH_PHY1_PHYSID1
:
288 return (MP_PHY_88E3015
>> 16) | MP_ETH_SMIR_RDVALID
;
289 case MP_ETH_PHY1_PHYSID2
:
290 return (MP_PHY_88E3015
& 0xFFFF) | MP_ETH_SMIR_RDVALID
;
292 return MP_ETH_SMIR_RDVALID
;
303 case MP_ETH_FRDP0
... MP_ETH_FRDP3
:
304 return s
->frx_queue
[(offset
- MP_ETH_FRDP0
)/4];
306 case MP_ETH_CRDP0
... MP_ETH_CRDP3
:
307 return s
->rx_queue
[(offset
- MP_ETH_CRDP0
)/4];
309 case MP_ETH_CTDP0
... MP_ETH_CTDP1
:
310 return s
->tx_queue
[(offset
- MP_ETH_CTDP0
)/4];
317 static void mv88w8618_eth_write(void *opaque
, hwaddr offset
,
318 uint64_t value
, unsigned size
)
320 mv88w8618_eth_state
*s
= opaque
;
328 s
->vlan_header
= ((value
>> MP_ETH_PCXR_2BSM_BIT
) & 1) * 2;
332 if (value
& MP_ETH_CMD_TXHI
) {
335 if (value
& MP_ETH_CMD_TXLO
) {
338 if (value
& (MP_ETH_CMD_TXHI
| MP_ETH_CMD_TXLO
) && s
->icr
& s
->imr
) {
339 qemu_irq_raise(s
->irq
);
349 if (s
->icr
& s
->imr
) {
350 qemu_irq_raise(s
->irq
);
354 case MP_ETH_FRDP0
... MP_ETH_FRDP3
:
355 s
->frx_queue
[(offset
- MP_ETH_FRDP0
)/4] = value
;
358 case MP_ETH_CRDP0
... MP_ETH_CRDP3
:
359 s
->rx_queue
[(offset
- MP_ETH_CRDP0
)/4] =
360 s
->cur_rx
[(offset
- MP_ETH_CRDP0
)/4] = value
;
363 case MP_ETH_CTDP0
... MP_ETH_CTDP1
:
364 s
->tx_queue
[(offset
- MP_ETH_CTDP0
)/4] = value
;
369 static const MemoryRegionOps mv88w8618_eth_ops
= {
370 .read
= mv88w8618_eth_read
,
371 .write
= mv88w8618_eth_write
,
372 .endianness
= DEVICE_NATIVE_ENDIAN
,
375 static void eth_cleanup(NetClientState
*nc
)
377 mv88w8618_eth_state
*s
= qemu_get_nic_opaque(nc
);
382 static NetClientInfo net_mv88w8618_info
= {
383 .type
= NET_CLIENT_OPTIONS_KIND_NIC
,
384 .size
= sizeof(NICState
),
385 .can_receive
= eth_can_receive
,
386 .receive
= eth_receive
,
387 .cleanup
= eth_cleanup
,
390 static int mv88w8618_eth_init(SysBusDevice
*sbd
)
392 DeviceState
*dev
= DEVICE(sbd
);
393 mv88w8618_eth_state
*s
= MV88W8618_ETH(dev
);
395 sysbus_init_irq(sbd
, &s
->irq
);
396 s
->nic
= qemu_new_nic(&net_mv88w8618_info
, &s
->conf
,
397 object_get_typename(OBJECT(dev
)), dev
->id
, s
);
398 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_eth_ops
, s
,
399 "mv88w8618-eth", MP_ETH_SIZE
);
400 sysbus_init_mmio(sbd
, &s
->iomem
);
404 static const VMStateDescription mv88w8618_eth_vmsd
= {
405 .name
= "mv88w8618_eth",
407 .minimum_version_id
= 1,
408 .fields
= (VMStateField
[]) {
409 VMSTATE_UINT32(smir
, mv88w8618_eth_state
),
410 VMSTATE_UINT32(icr
, mv88w8618_eth_state
),
411 VMSTATE_UINT32(imr
, mv88w8618_eth_state
),
412 VMSTATE_UINT32(vlan_header
, mv88w8618_eth_state
),
413 VMSTATE_UINT32_ARRAY(tx_queue
, mv88w8618_eth_state
, 2),
414 VMSTATE_UINT32_ARRAY(rx_queue
, mv88w8618_eth_state
, 4),
415 VMSTATE_UINT32_ARRAY(frx_queue
, mv88w8618_eth_state
, 4),
416 VMSTATE_UINT32_ARRAY(cur_rx
, mv88w8618_eth_state
, 4),
417 VMSTATE_END_OF_LIST()
421 static Property mv88w8618_eth_properties
[] = {
422 DEFINE_NIC_PROPERTIES(mv88w8618_eth_state
, conf
),
423 DEFINE_PROP_END_OF_LIST(),
426 static void mv88w8618_eth_class_init(ObjectClass
*klass
, void *data
)
428 DeviceClass
*dc
= DEVICE_CLASS(klass
);
429 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
431 k
->init
= mv88w8618_eth_init
;
432 dc
->vmsd
= &mv88w8618_eth_vmsd
;
433 dc
->props
= mv88w8618_eth_properties
;
436 static const TypeInfo mv88w8618_eth_info
= {
437 .name
= TYPE_MV88W8618_ETH
,
438 .parent
= TYPE_SYS_BUS_DEVICE
,
439 .instance_size
= sizeof(mv88w8618_eth_state
),
440 .class_init
= mv88w8618_eth_class_init
,
443 /* LCD register offsets */
444 #define MP_LCD_IRQCTRL 0x180
445 #define MP_LCD_IRQSTAT 0x184
446 #define MP_LCD_SPICTRL 0x1ac
447 #define MP_LCD_INST 0x1bc
448 #define MP_LCD_DATA 0x1c0
451 #define MP_LCD_SPI_DATA 0x00100011
452 #define MP_LCD_SPI_CMD 0x00104011
453 #define MP_LCD_SPI_INVALID 0x00000000
456 #define MP_LCD_INST_SETPAGE0 0xB0
458 #define MP_LCD_INST_SETPAGE7 0xB7
460 #define MP_LCD_TEXTCOLOR 0xe0e0ff /* RRGGBB */
462 #define TYPE_MUSICPAL_LCD "musicpal_lcd"
463 #define MUSICPAL_LCD(obj) \
464 OBJECT_CHECK(musicpal_lcd_state, (obj), TYPE_MUSICPAL_LCD)
466 typedef struct musicpal_lcd_state
{
468 SysBusDevice parent_obj
;
478 uint8_t video_ram
[128*64/8];
479 } musicpal_lcd_state
;
481 static uint8_t scale_lcd_color(musicpal_lcd_state
*s
, uint8_t col
)
483 switch (s
->brightness
) {
489 return (col
* s
->brightness
) / 7;
493 #define SET_LCD_PIXEL(depth, type) \
494 static inline void glue(set_lcd_pixel, depth) \
495 (musicpal_lcd_state *s, int x, int y, type col) \
498 DisplaySurface *surface = qemu_console_surface(s->con); \
499 type *pixel = &((type *) surface_data(surface))[(y * 128 * 3 + x) * 3]; \
501 for (dy = 0; dy < 3; dy++, pixel += 127 * 3) \
502 for (dx = 0; dx < 3; dx++, pixel++) \
505 SET_LCD_PIXEL(8, uint8_t)
506 SET_LCD_PIXEL(16, uint16_t)
507 SET_LCD_PIXEL(32, uint32_t)
509 static void lcd_refresh(void *opaque
)
511 musicpal_lcd_state
*s
= opaque
;
512 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
515 switch (surface_bits_per_pixel(surface
)) {
518 #define LCD_REFRESH(depth, func) \
520 col = func(scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 16) & 0xff), \
521 scale_lcd_color(s, (MP_LCD_TEXTCOLOR >> 8) & 0xff), \
522 scale_lcd_color(s, MP_LCD_TEXTCOLOR & 0xff)); \
523 for (x = 0; x < 128; x++) { \
524 for (y = 0; y < 64; y++) { \
525 if (s->video_ram[x + (y/8)*128] & (1 << (y % 8))) { \
526 glue(set_lcd_pixel, depth)(s, x, y, col); \
528 glue(set_lcd_pixel, depth)(s, x, y, 0); \
533 LCD_REFRESH(8, rgb_to_pixel8
)
534 LCD_REFRESH(16, rgb_to_pixel16
)
535 LCD_REFRESH(32, (is_surface_bgr(surface
) ?
536 rgb_to_pixel32bgr
: rgb_to_pixel32
))
538 hw_error("unsupported colour depth %i\n",
539 surface_bits_per_pixel(surface
));
542 dpy_gfx_update(s
->con
, 0, 0, 128*3, 64*3);
545 static void lcd_invalidate(void *opaque
)
549 static void musicpal_lcd_gpio_brightness_in(void *opaque
, int irq
, int level
)
551 musicpal_lcd_state
*s
= opaque
;
552 s
->brightness
&= ~(1 << irq
);
553 s
->brightness
|= level
<< irq
;
556 static uint64_t musicpal_lcd_read(void *opaque
, hwaddr offset
,
559 musicpal_lcd_state
*s
= opaque
;
570 static void musicpal_lcd_write(void *opaque
, hwaddr offset
,
571 uint64_t value
, unsigned size
)
573 musicpal_lcd_state
*s
= opaque
;
581 if (value
== MP_LCD_SPI_DATA
|| value
== MP_LCD_SPI_CMD
) {
584 s
->mode
= MP_LCD_SPI_INVALID
;
589 if (value
>= MP_LCD_INST_SETPAGE0
&& value
<= MP_LCD_INST_SETPAGE7
) {
590 s
->page
= value
- MP_LCD_INST_SETPAGE0
;
596 if (s
->mode
== MP_LCD_SPI_CMD
) {
597 if (value
>= MP_LCD_INST_SETPAGE0
&&
598 value
<= MP_LCD_INST_SETPAGE7
) {
599 s
->page
= value
- MP_LCD_INST_SETPAGE0
;
602 } else if (s
->mode
== MP_LCD_SPI_DATA
) {
603 s
->video_ram
[s
->page
*128 + s
->page_off
] = value
;
604 s
->page_off
= (s
->page_off
+ 1) & 127;
610 static const MemoryRegionOps musicpal_lcd_ops
= {
611 .read
= musicpal_lcd_read
,
612 .write
= musicpal_lcd_write
,
613 .endianness
= DEVICE_NATIVE_ENDIAN
,
616 static const GraphicHwOps musicpal_gfx_ops
= {
617 .invalidate
= lcd_invalidate
,
618 .gfx_update
= lcd_refresh
,
621 static int musicpal_lcd_init(SysBusDevice
*sbd
)
623 DeviceState
*dev
= DEVICE(sbd
);
624 musicpal_lcd_state
*s
= MUSICPAL_LCD(dev
);
628 memory_region_init_io(&s
->iomem
, OBJECT(s
), &musicpal_lcd_ops
, s
,
629 "musicpal-lcd", MP_LCD_SIZE
);
630 sysbus_init_mmio(sbd
, &s
->iomem
);
632 s
->con
= graphic_console_init(dev
, 0, &musicpal_gfx_ops
, s
);
633 qemu_console_resize(s
->con
, 128*3, 64*3);
635 qdev_init_gpio_in(dev
, musicpal_lcd_gpio_brightness_in
, 3);
640 static const VMStateDescription musicpal_lcd_vmsd
= {
641 .name
= "musicpal_lcd",
643 .minimum_version_id
= 1,
644 .fields
= (VMStateField
[]) {
645 VMSTATE_UINT32(brightness
, musicpal_lcd_state
),
646 VMSTATE_UINT32(mode
, musicpal_lcd_state
),
647 VMSTATE_UINT32(irqctrl
, musicpal_lcd_state
),
648 VMSTATE_UINT32(page
, musicpal_lcd_state
),
649 VMSTATE_UINT32(page_off
, musicpal_lcd_state
),
650 VMSTATE_BUFFER(video_ram
, musicpal_lcd_state
),
651 VMSTATE_END_OF_LIST()
655 static void musicpal_lcd_class_init(ObjectClass
*klass
, void *data
)
657 DeviceClass
*dc
= DEVICE_CLASS(klass
);
658 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
660 k
->init
= musicpal_lcd_init
;
661 dc
->vmsd
= &musicpal_lcd_vmsd
;
664 static const TypeInfo musicpal_lcd_info
= {
665 .name
= TYPE_MUSICPAL_LCD
,
666 .parent
= TYPE_SYS_BUS_DEVICE
,
667 .instance_size
= sizeof(musicpal_lcd_state
),
668 .class_init
= musicpal_lcd_class_init
,
671 /* PIC register offsets */
672 #define MP_PIC_STATUS 0x00
673 #define MP_PIC_ENABLE_SET 0x08
674 #define MP_PIC_ENABLE_CLR 0x0C
676 #define TYPE_MV88W8618_PIC "mv88w8618_pic"
677 #define MV88W8618_PIC(obj) \
678 OBJECT_CHECK(mv88w8618_pic_state, (obj), TYPE_MV88W8618_PIC)
680 typedef struct mv88w8618_pic_state
{
682 SysBusDevice parent_obj
;
689 } mv88w8618_pic_state
;
691 static void mv88w8618_pic_update(mv88w8618_pic_state
*s
)
693 qemu_set_irq(s
->parent_irq
, (s
->level
& s
->enabled
));
696 static void mv88w8618_pic_set_irq(void *opaque
, int irq
, int level
)
698 mv88w8618_pic_state
*s
= opaque
;
701 s
->level
|= 1 << irq
;
703 s
->level
&= ~(1 << irq
);
705 mv88w8618_pic_update(s
);
708 static uint64_t mv88w8618_pic_read(void *opaque
, hwaddr offset
,
711 mv88w8618_pic_state
*s
= opaque
;
715 return s
->level
& s
->enabled
;
722 static void mv88w8618_pic_write(void *opaque
, hwaddr offset
,
723 uint64_t value
, unsigned size
)
725 mv88w8618_pic_state
*s
= opaque
;
728 case MP_PIC_ENABLE_SET
:
732 case MP_PIC_ENABLE_CLR
:
733 s
->enabled
&= ~value
;
737 mv88w8618_pic_update(s
);
740 static void mv88w8618_pic_reset(DeviceState
*d
)
742 mv88w8618_pic_state
*s
= MV88W8618_PIC(d
);
748 static const MemoryRegionOps mv88w8618_pic_ops
= {
749 .read
= mv88w8618_pic_read
,
750 .write
= mv88w8618_pic_write
,
751 .endianness
= DEVICE_NATIVE_ENDIAN
,
754 static int mv88w8618_pic_init(SysBusDevice
*dev
)
756 mv88w8618_pic_state
*s
= MV88W8618_PIC(dev
);
758 qdev_init_gpio_in(DEVICE(dev
), mv88w8618_pic_set_irq
, 32);
759 sysbus_init_irq(dev
, &s
->parent_irq
);
760 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_pic_ops
, s
,
761 "musicpal-pic", MP_PIC_SIZE
);
762 sysbus_init_mmio(dev
, &s
->iomem
);
766 static const VMStateDescription mv88w8618_pic_vmsd
= {
767 .name
= "mv88w8618_pic",
769 .minimum_version_id
= 1,
770 .fields
= (VMStateField
[]) {
771 VMSTATE_UINT32(level
, mv88w8618_pic_state
),
772 VMSTATE_UINT32(enabled
, mv88w8618_pic_state
),
773 VMSTATE_END_OF_LIST()
777 static void mv88w8618_pic_class_init(ObjectClass
*klass
, void *data
)
779 DeviceClass
*dc
= DEVICE_CLASS(klass
);
780 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
782 k
->init
= mv88w8618_pic_init
;
783 dc
->reset
= mv88w8618_pic_reset
;
784 dc
->vmsd
= &mv88w8618_pic_vmsd
;
787 static const TypeInfo mv88w8618_pic_info
= {
788 .name
= TYPE_MV88W8618_PIC
,
789 .parent
= TYPE_SYS_BUS_DEVICE
,
790 .instance_size
= sizeof(mv88w8618_pic_state
),
791 .class_init
= mv88w8618_pic_class_init
,
794 /* PIT register offsets */
795 #define MP_PIT_TIMER1_LENGTH 0x00
797 #define MP_PIT_TIMER4_LENGTH 0x0C
798 #define MP_PIT_CONTROL 0x10
799 #define MP_PIT_TIMER1_VALUE 0x14
801 #define MP_PIT_TIMER4_VALUE 0x20
802 #define MP_BOARD_RESET 0x34
804 /* Magic board reset value (probably some watchdog behind it) */
805 #define MP_BOARD_RESET_MAGIC 0x10000
807 typedef struct mv88w8618_timer_state
{
808 ptimer_state
*ptimer
;
812 } mv88w8618_timer_state
;
814 #define TYPE_MV88W8618_PIT "mv88w8618_pit"
815 #define MV88W8618_PIT(obj) \
816 OBJECT_CHECK(mv88w8618_pit_state, (obj), TYPE_MV88W8618_PIT)
818 typedef struct mv88w8618_pit_state
{
820 SysBusDevice parent_obj
;
824 mv88w8618_timer_state timer
[4];
825 } mv88w8618_pit_state
;
827 static void mv88w8618_timer_tick(void *opaque
)
829 mv88w8618_timer_state
*s
= opaque
;
831 qemu_irq_raise(s
->irq
);
834 static void mv88w8618_timer_init(SysBusDevice
*dev
, mv88w8618_timer_state
*s
,
839 sysbus_init_irq(dev
, &s
->irq
);
842 bh
= qemu_bh_new(mv88w8618_timer_tick
, s
);
843 s
->ptimer
= ptimer_init(bh
);
846 static uint64_t mv88w8618_pit_read(void *opaque
, hwaddr offset
,
849 mv88w8618_pit_state
*s
= opaque
;
850 mv88w8618_timer_state
*t
;
853 case MP_PIT_TIMER1_VALUE
... MP_PIT_TIMER4_VALUE
:
854 t
= &s
->timer
[(offset
-MP_PIT_TIMER1_VALUE
) >> 2];
855 return ptimer_get_count(t
->ptimer
);
862 static void mv88w8618_pit_write(void *opaque
, hwaddr offset
,
863 uint64_t value
, unsigned size
)
865 mv88w8618_pit_state
*s
= opaque
;
866 mv88w8618_timer_state
*t
;
870 case MP_PIT_TIMER1_LENGTH
... MP_PIT_TIMER4_LENGTH
:
871 t
= &s
->timer
[offset
>> 2];
874 ptimer_set_limit(t
->ptimer
, t
->limit
, 1);
876 ptimer_stop(t
->ptimer
);
881 for (i
= 0; i
< 4; i
++) {
883 if (value
& 0xf && t
->limit
> 0) {
884 ptimer_set_limit(t
->ptimer
, t
->limit
, 0);
885 ptimer_set_freq(t
->ptimer
, t
->freq
);
886 ptimer_run(t
->ptimer
, 0);
888 ptimer_stop(t
->ptimer
);
895 if (value
== MP_BOARD_RESET_MAGIC
) {
896 qemu_system_reset_request();
902 static void mv88w8618_pit_reset(DeviceState
*d
)
904 mv88w8618_pit_state
*s
= MV88W8618_PIT(d
);
907 for (i
= 0; i
< 4; i
++) {
908 ptimer_stop(s
->timer
[i
].ptimer
);
909 s
->timer
[i
].limit
= 0;
913 static const MemoryRegionOps mv88w8618_pit_ops
= {
914 .read
= mv88w8618_pit_read
,
915 .write
= mv88w8618_pit_write
,
916 .endianness
= DEVICE_NATIVE_ENDIAN
,
919 static int mv88w8618_pit_init(SysBusDevice
*dev
)
921 mv88w8618_pit_state
*s
= MV88W8618_PIT(dev
);
924 /* Letting them all run at 1 MHz is likely just a pragmatic
926 for (i
= 0; i
< 4; i
++) {
927 mv88w8618_timer_init(dev
, &s
->timer
[i
], 1000000);
930 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_pit_ops
, s
,
931 "musicpal-pit", MP_PIT_SIZE
);
932 sysbus_init_mmio(dev
, &s
->iomem
);
936 static const VMStateDescription mv88w8618_timer_vmsd
= {
939 .minimum_version_id
= 1,
940 .fields
= (VMStateField
[]) {
941 VMSTATE_PTIMER(ptimer
, mv88w8618_timer_state
),
942 VMSTATE_UINT32(limit
, mv88w8618_timer_state
),
943 VMSTATE_END_OF_LIST()
947 static const VMStateDescription mv88w8618_pit_vmsd
= {
948 .name
= "mv88w8618_pit",
950 .minimum_version_id
= 1,
951 .fields
= (VMStateField
[]) {
952 VMSTATE_STRUCT_ARRAY(timer
, mv88w8618_pit_state
, 4, 1,
953 mv88w8618_timer_vmsd
, mv88w8618_timer_state
),
954 VMSTATE_END_OF_LIST()
958 static void mv88w8618_pit_class_init(ObjectClass
*klass
, void *data
)
960 DeviceClass
*dc
= DEVICE_CLASS(klass
);
961 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
963 k
->init
= mv88w8618_pit_init
;
964 dc
->reset
= mv88w8618_pit_reset
;
965 dc
->vmsd
= &mv88w8618_pit_vmsd
;
968 static const TypeInfo mv88w8618_pit_info
= {
969 .name
= TYPE_MV88W8618_PIT
,
970 .parent
= TYPE_SYS_BUS_DEVICE
,
971 .instance_size
= sizeof(mv88w8618_pit_state
),
972 .class_init
= mv88w8618_pit_class_init
,
975 /* Flash config register offsets */
976 #define MP_FLASHCFG_CFGR0 0x04
978 #define TYPE_MV88W8618_FLASHCFG "mv88w8618_flashcfg"
979 #define MV88W8618_FLASHCFG(obj) \
980 OBJECT_CHECK(mv88w8618_flashcfg_state, (obj), TYPE_MV88W8618_FLASHCFG)
982 typedef struct mv88w8618_flashcfg_state
{
984 SysBusDevice parent_obj
;
989 } mv88w8618_flashcfg_state
;
991 static uint64_t mv88w8618_flashcfg_read(void *opaque
,
995 mv88w8618_flashcfg_state
*s
= opaque
;
998 case MP_FLASHCFG_CFGR0
:
1006 static void mv88w8618_flashcfg_write(void *opaque
, hwaddr offset
,
1007 uint64_t value
, unsigned size
)
1009 mv88w8618_flashcfg_state
*s
= opaque
;
1012 case MP_FLASHCFG_CFGR0
:
1018 static const MemoryRegionOps mv88w8618_flashcfg_ops
= {
1019 .read
= mv88w8618_flashcfg_read
,
1020 .write
= mv88w8618_flashcfg_write
,
1021 .endianness
= DEVICE_NATIVE_ENDIAN
,
1024 static int mv88w8618_flashcfg_init(SysBusDevice
*dev
)
1026 mv88w8618_flashcfg_state
*s
= MV88W8618_FLASHCFG(dev
);
1028 s
->cfgr0
= 0xfffe4285; /* Default as set by U-Boot for 8 MB flash */
1029 memory_region_init_io(&s
->iomem
, OBJECT(s
), &mv88w8618_flashcfg_ops
, s
,
1030 "musicpal-flashcfg", MP_FLASHCFG_SIZE
);
1031 sysbus_init_mmio(dev
, &s
->iomem
);
1035 static const VMStateDescription mv88w8618_flashcfg_vmsd
= {
1036 .name
= "mv88w8618_flashcfg",
1038 .minimum_version_id
= 1,
1039 .fields
= (VMStateField
[]) {
1040 VMSTATE_UINT32(cfgr0
, mv88w8618_flashcfg_state
),
1041 VMSTATE_END_OF_LIST()
1045 static void mv88w8618_flashcfg_class_init(ObjectClass
*klass
, void *data
)
1047 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1048 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1050 k
->init
= mv88w8618_flashcfg_init
;
1051 dc
->vmsd
= &mv88w8618_flashcfg_vmsd
;
1054 static const TypeInfo mv88w8618_flashcfg_info
= {
1055 .name
= TYPE_MV88W8618_FLASHCFG
,
1056 .parent
= TYPE_SYS_BUS_DEVICE
,
1057 .instance_size
= sizeof(mv88w8618_flashcfg_state
),
1058 .class_init
= mv88w8618_flashcfg_class_init
,
1061 /* Misc register offsets */
1062 #define MP_MISC_BOARD_REVISION 0x18
1064 #define MP_BOARD_REVISION 0x31
1067 SysBusDevice parent_obj
;
1069 } MusicPalMiscState
;
1071 #define TYPE_MUSICPAL_MISC "musicpal-misc"
1072 #define MUSICPAL_MISC(obj) \
1073 OBJECT_CHECK(MusicPalMiscState, (obj), TYPE_MUSICPAL_MISC)
1075 static uint64_t musicpal_misc_read(void *opaque
, hwaddr offset
,
1079 case MP_MISC_BOARD_REVISION
:
1080 return MP_BOARD_REVISION
;
1087 static void musicpal_misc_write(void *opaque
, hwaddr offset
,
1088 uint64_t value
, unsigned size
)
1092 static const MemoryRegionOps musicpal_misc_ops
= {
1093 .read
= musicpal_misc_read
,
1094 .write
= musicpal_misc_write
,
1095 .endianness
= DEVICE_NATIVE_ENDIAN
,
1098 static void musicpal_misc_init(Object
*obj
)
1100 SysBusDevice
*sd
= SYS_BUS_DEVICE(obj
);
1101 MusicPalMiscState
*s
= MUSICPAL_MISC(obj
);
1103 memory_region_init_io(&s
->iomem
, OBJECT(s
), &musicpal_misc_ops
, NULL
,
1104 "musicpal-misc", MP_MISC_SIZE
);
1105 sysbus_init_mmio(sd
, &s
->iomem
);
1108 static const TypeInfo musicpal_misc_info
= {
1109 .name
= TYPE_MUSICPAL_MISC
,
1110 .parent
= TYPE_SYS_BUS_DEVICE
,
1111 .instance_init
= musicpal_misc_init
,
1112 .instance_size
= sizeof(MusicPalMiscState
),
1115 /* WLAN register offsets */
1116 #define MP_WLAN_MAGIC1 0x11c
1117 #define MP_WLAN_MAGIC2 0x124
1119 static uint64_t mv88w8618_wlan_read(void *opaque
, hwaddr offset
,
1123 /* Workaround to allow loading the binary-only wlandrv.ko crap
1124 * from the original Freecom firmware. */
1125 case MP_WLAN_MAGIC1
:
1127 case MP_WLAN_MAGIC2
:
1135 static void mv88w8618_wlan_write(void *opaque
, hwaddr offset
,
1136 uint64_t value
, unsigned size
)
1140 static const MemoryRegionOps mv88w8618_wlan_ops
= {
1141 .read
= mv88w8618_wlan_read
,
1142 .write
=mv88w8618_wlan_write
,
1143 .endianness
= DEVICE_NATIVE_ENDIAN
,
1146 static int mv88w8618_wlan_init(SysBusDevice
*dev
)
1148 MemoryRegion
*iomem
= g_new(MemoryRegion
, 1);
1150 memory_region_init_io(iomem
, OBJECT(dev
), &mv88w8618_wlan_ops
, NULL
,
1151 "musicpal-wlan", MP_WLAN_SIZE
);
1152 sysbus_init_mmio(dev
, iomem
);
1156 /* GPIO register offsets */
1157 #define MP_GPIO_OE_LO 0x008
1158 #define MP_GPIO_OUT_LO 0x00c
1159 #define MP_GPIO_IN_LO 0x010
1160 #define MP_GPIO_IER_LO 0x014
1161 #define MP_GPIO_IMR_LO 0x018
1162 #define MP_GPIO_ISR_LO 0x020
1163 #define MP_GPIO_OE_HI 0x508
1164 #define MP_GPIO_OUT_HI 0x50c
1165 #define MP_GPIO_IN_HI 0x510
1166 #define MP_GPIO_IER_HI 0x514
1167 #define MP_GPIO_IMR_HI 0x518
1168 #define MP_GPIO_ISR_HI 0x520
1170 /* GPIO bits & masks */
1171 #define MP_GPIO_LCD_BRIGHTNESS 0x00070000
1172 #define MP_GPIO_I2C_DATA_BIT 29
1173 #define MP_GPIO_I2C_CLOCK_BIT 30
1175 /* LCD brightness bits in GPIO_OE_HI */
1176 #define MP_OE_LCD_BRIGHTNESS 0x0007
1178 #define TYPE_MUSICPAL_GPIO "musicpal_gpio"
1179 #define MUSICPAL_GPIO(obj) \
1180 OBJECT_CHECK(musicpal_gpio_state, (obj), TYPE_MUSICPAL_GPIO)
1182 typedef struct musicpal_gpio_state
{
1184 SysBusDevice parent_obj
;
1188 uint32_t lcd_brightness
;
1195 qemu_irq out
[5]; /* 3 brightness out + 2 lcd (data and clock ) */
1196 } musicpal_gpio_state
;
1198 static void musicpal_gpio_brightness_update(musicpal_gpio_state
*s
) {
1200 uint32_t brightness
;
1202 /* compute brightness ratio */
1203 switch (s
->lcd_brightness
) {
1237 /* set lcd brightness GPIOs */
1238 for (i
= 0; i
<= 2; i
++) {
1239 qemu_set_irq(s
->out
[i
], (brightness
>> i
) & 1);
1243 static void musicpal_gpio_pin_event(void *opaque
, int pin
, int level
)
1245 musicpal_gpio_state
*s
= opaque
;
1246 uint32_t mask
= 1 << pin
;
1247 uint32_t delta
= level
<< pin
;
1248 uint32_t old
= s
->in_state
& mask
;
1250 s
->in_state
&= ~mask
;
1251 s
->in_state
|= delta
;
1253 if ((old
^ delta
) &&
1254 ((level
&& (s
->imr
& mask
)) || (!level
&& (s
->ier
& mask
)))) {
1256 qemu_irq_raise(s
->irq
);
1260 static uint64_t musicpal_gpio_read(void *opaque
, hwaddr offset
,
1263 musicpal_gpio_state
*s
= opaque
;
1266 case MP_GPIO_OE_HI
: /* used for LCD brightness control */
1267 return s
->lcd_brightness
& MP_OE_LCD_BRIGHTNESS
;
1269 case MP_GPIO_OUT_LO
:
1270 return s
->out_state
& 0xFFFF;
1271 case MP_GPIO_OUT_HI
:
1272 return s
->out_state
>> 16;
1275 return s
->in_state
& 0xFFFF;
1277 return s
->in_state
>> 16;
1279 case MP_GPIO_IER_LO
:
1280 return s
->ier
& 0xFFFF;
1281 case MP_GPIO_IER_HI
:
1282 return s
->ier
>> 16;
1284 case MP_GPIO_IMR_LO
:
1285 return s
->imr
& 0xFFFF;
1286 case MP_GPIO_IMR_HI
:
1287 return s
->imr
>> 16;
1289 case MP_GPIO_ISR_LO
:
1290 return s
->isr
& 0xFFFF;
1291 case MP_GPIO_ISR_HI
:
1292 return s
->isr
>> 16;
1299 static void musicpal_gpio_write(void *opaque
, hwaddr offset
,
1300 uint64_t value
, unsigned size
)
1302 musicpal_gpio_state
*s
= opaque
;
1304 case MP_GPIO_OE_HI
: /* used for LCD brightness control */
1305 s
->lcd_brightness
= (s
->lcd_brightness
& MP_GPIO_LCD_BRIGHTNESS
) |
1306 (value
& MP_OE_LCD_BRIGHTNESS
);
1307 musicpal_gpio_brightness_update(s
);
1310 case MP_GPIO_OUT_LO
:
1311 s
->out_state
= (s
->out_state
& 0xFFFF0000) | (value
& 0xFFFF);
1313 case MP_GPIO_OUT_HI
:
1314 s
->out_state
= (s
->out_state
& 0xFFFF) | (value
<< 16);
1315 s
->lcd_brightness
= (s
->lcd_brightness
& 0xFFFF) |
1316 (s
->out_state
& MP_GPIO_LCD_BRIGHTNESS
);
1317 musicpal_gpio_brightness_update(s
);
1318 qemu_set_irq(s
->out
[3], (s
->out_state
>> MP_GPIO_I2C_DATA_BIT
) & 1);
1319 qemu_set_irq(s
->out
[4], (s
->out_state
>> MP_GPIO_I2C_CLOCK_BIT
) & 1);
1322 case MP_GPIO_IER_LO
:
1323 s
->ier
= (s
->ier
& 0xFFFF0000) | (value
& 0xFFFF);
1325 case MP_GPIO_IER_HI
:
1326 s
->ier
= (s
->ier
& 0xFFFF) | (value
<< 16);
1329 case MP_GPIO_IMR_LO
:
1330 s
->imr
= (s
->imr
& 0xFFFF0000) | (value
& 0xFFFF);
1332 case MP_GPIO_IMR_HI
:
1333 s
->imr
= (s
->imr
& 0xFFFF) | (value
<< 16);
1338 static const MemoryRegionOps musicpal_gpio_ops
= {
1339 .read
= musicpal_gpio_read
,
1340 .write
= musicpal_gpio_write
,
1341 .endianness
= DEVICE_NATIVE_ENDIAN
,
1344 static void musicpal_gpio_reset(DeviceState
*d
)
1346 musicpal_gpio_state
*s
= MUSICPAL_GPIO(d
);
1348 s
->lcd_brightness
= 0;
1350 s
->in_state
= 0xffffffff;
1356 static int musicpal_gpio_init(SysBusDevice
*sbd
)
1358 DeviceState
*dev
= DEVICE(sbd
);
1359 musicpal_gpio_state
*s
= MUSICPAL_GPIO(dev
);
1361 sysbus_init_irq(sbd
, &s
->irq
);
1363 memory_region_init_io(&s
->iomem
, OBJECT(s
), &musicpal_gpio_ops
, s
,
1364 "musicpal-gpio", MP_GPIO_SIZE
);
1365 sysbus_init_mmio(sbd
, &s
->iomem
);
1367 qdev_init_gpio_out(dev
, s
->out
, ARRAY_SIZE(s
->out
));
1369 qdev_init_gpio_in(dev
, musicpal_gpio_pin_event
, 32);
1374 static const VMStateDescription musicpal_gpio_vmsd
= {
1375 .name
= "musicpal_gpio",
1377 .minimum_version_id
= 1,
1378 .fields
= (VMStateField
[]) {
1379 VMSTATE_UINT32(lcd_brightness
, musicpal_gpio_state
),
1380 VMSTATE_UINT32(out_state
, musicpal_gpio_state
),
1381 VMSTATE_UINT32(in_state
, musicpal_gpio_state
),
1382 VMSTATE_UINT32(ier
, musicpal_gpio_state
),
1383 VMSTATE_UINT32(imr
, musicpal_gpio_state
),
1384 VMSTATE_UINT32(isr
, musicpal_gpio_state
),
1385 VMSTATE_END_OF_LIST()
1389 static void musicpal_gpio_class_init(ObjectClass
*klass
, void *data
)
1391 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1392 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1394 k
->init
= musicpal_gpio_init
;
1395 dc
->reset
= musicpal_gpio_reset
;
1396 dc
->vmsd
= &musicpal_gpio_vmsd
;
1399 static const TypeInfo musicpal_gpio_info
= {
1400 .name
= TYPE_MUSICPAL_GPIO
,
1401 .parent
= TYPE_SYS_BUS_DEVICE
,
1402 .instance_size
= sizeof(musicpal_gpio_state
),
1403 .class_init
= musicpal_gpio_class_init
,
1406 /* Keyboard codes & masks */
1407 #define KEY_RELEASED 0x80
1408 #define KEY_CODE 0x7f
1410 #define KEYCODE_TAB 0x0f
1411 #define KEYCODE_ENTER 0x1c
1412 #define KEYCODE_F 0x21
1413 #define KEYCODE_M 0x32
1415 #define KEYCODE_EXTENDED 0xe0
1416 #define KEYCODE_UP 0x48
1417 #define KEYCODE_DOWN 0x50
1418 #define KEYCODE_LEFT 0x4b
1419 #define KEYCODE_RIGHT 0x4d
1421 #define MP_KEY_WHEEL_VOL (1 << 0)
1422 #define MP_KEY_WHEEL_VOL_INV (1 << 1)
1423 #define MP_KEY_WHEEL_NAV (1 << 2)
1424 #define MP_KEY_WHEEL_NAV_INV (1 << 3)
1425 #define MP_KEY_BTN_FAVORITS (1 << 4)
1426 #define MP_KEY_BTN_MENU (1 << 5)
1427 #define MP_KEY_BTN_VOLUME (1 << 6)
1428 #define MP_KEY_BTN_NAVIGATION (1 << 7)
1430 #define TYPE_MUSICPAL_KEY "musicpal_key"
1431 #define MUSICPAL_KEY(obj) \
1432 OBJECT_CHECK(musicpal_key_state, (obj), TYPE_MUSICPAL_KEY)
1434 typedef struct musicpal_key_state
{
1436 SysBusDevice parent_obj
;
1440 uint32_t kbd_extended
;
1441 uint32_t pressed_keys
;
1443 } musicpal_key_state
;
1445 static void musicpal_key_event(void *opaque
, int keycode
)
1447 musicpal_key_state
*s
= opaque
;
1451 if (keycode
== KEYCODE_EXTENDED
) {
1452 s
->kbd_extended
= 1;
1456 if (s
->kbd_extended
) {
1457 switch (keycode
& KEY_CODE
) {
1459 event
= MP_KEY_WHEEL_NAV
| MP_KEY_WHEEL_NAV_INV
;
1463 event
= MP_KEY_WHEEL_NAV
;
1467 event
= MP_KEY_WHEEL_VOL
| MP_KEY_WHEEL_VOL_INV
;
1471 event
= MP_KEY_WHEEL_VOL
;
1475 switch (keycode
& KEY_CODE
) {
1477 event
= MP_KEY_BTN_FAVORITS
;
1481 event
= MP_KEY_BTN_VOLUME
;
1485 event
= MP_KEY_BTN_NAVIGATION
;
1489 event
= MP_KEY_BTN_MENU
;
1492 /* Do not repeat already pressed buttons */
1493 if (!(keycode
& KEY_RELEASED
) && (s
->pressed_keys
& event
)) {
1499 /* Raise GPIO pin first if repeating a key */
1500 if (!(keycode
& KEY_RELEASED
) && (s
->pressed_keys
& event
)) {
1501 for (i
= 0; i
<= 7; i
++) {
1502 if (event
& (1 << i
)) {
1503 qemu_set_irq(s
->out
[i
], 1);
1507 for (i
= 0; i
<= 7; i
++) {
1508 if (event
& (1 << i
)) {
1509 qemu_set_irq(s
->out
[i
], !!(keycode
& KEY_RELEASED
));
1512 if (keycode
& KEY_RELEASED
) {
1513 s
->pressed_keys
&= ~event
;
1515 s
->pressed_keys
|= event
;
1519 s
->kbd_extended
= 0;
1522 static int musicpal_key_init(SysBusDevice
*sbd
)
1524 DeviceState
*dev
= DEVICE(sbd
);
1525 musicpal_key_state
*s
= MUSICPAL_KEY(dev
);
1527 memory_region_init(&s
->iomem
, OBJECT(s
), "dummy", 0);
1528 sysbus_init_mmio(sbd
, &s
->iomem
);
1530 s
->kbd_extended
= 0;
1531 s
->pressed_keys
= 0;
1533 qdev_init_gpio_out(dev
, s
->out
, ARRAY_SIZE(s
->out
));
1535 qemu_add_kbd_event_handler(musicpal_key_event
, s
);
1540 static const VMStateDescription musicpal_key_vmsd
= {
1541 .name
= "musicpal_key",
1543 .minimum_version_id
= 1,
1544 .fields
= (VMStateField
[]) {
1545 VMSTATE_UINT32(kbd_extended
, musicpal_key_state
),
1546 VMSTATE_UINT32(pressed_keys
, musicpal_key_state
),
1547 VMSTATE_END_OF_LIST()
1551 static void musicpal_key_class_init(ObjectClass
*klass
, void *data
)
1553 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1554 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1556 k
->init
= musicpal_key_init
;
1557 dc
->vmsd
= &musicpal_key_vmsd
;
1560 static const TypeInfo musicpal_key_info
= {
1561 .name
= TYPE_MUSICPAL_KEY
,
1562 .parent
= TYPE_SYS_BUS_DEVICE
,
1563 .instance_size
= sizeof(musicpal_key_state
),
1564 .class_init
= musicpal_key_class_init
,
1567 static struct arm_boot_info musicpal_binfo
= {
1568 .loader_start
= 0x0,
1572 static void musicpal_init(MachineState
*machine
)
1574 const char *cpu_model
= machine
->cpu_model
;
1575 const char *kernel_filename
= machine
->kernel_filename
;
1576 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1577 const char *initrd_filename
= machine
->initrd_filename
;
1581 DeviceState
*i2c_dev
;
1582 DeviceState
*lcd_dev
;
1583 DeviceState
*key_dev
;
1584 DeviceState
*wm8750_dev
;
1588 unsigned long flash_size
;
1590 MemoryRegion
*address_space_mem
= get_system_memory();
1591 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
1592 MemoryRegion
*sram
= g_new(MemoryRegion
, 1);
1595 cpu_model
= "arm926";
1597 cpu
= cpu_arm_init(cpu_model
);
1599 fprintf(stderr
, "Unable to find CPU definition\n");
1603 /* For now we use a fixed - the original - RAM size */
1604 memory_region_init_ram(ram
, NULL
, "musicpal.ram", MP_RAM_DEFAULT_SIZE
,
1606 vmstate_register_ram_global(ram
);
1607 memory_region_add_subregion(address_space_mem
, 0, ram
);
1609 memory_region_init_ram(sram
, NULL
, "musicpal.sram", MP_SRAM_SIZE
,
1611 vmstate_register_ram_global(sram
);
1612 memory_region_add_subregion(address_space_mem
, MP_SRAM_BASE
, sram
);
1614 dev
= sysbus_create_simple(TYPE_MV88W8618_PIC
, MP_PIC_BASE
,
1615 qdev_get_gpio_in(DEVICE(cpu
), ARM_CPU_IRQ
));
1616 for (i
= 0; i
< 32; i
++) {
1617 pic
[i
] = qdev_get_gpio_in(dev
, i
);
1619 sysbus_create_varargs(TYPE_MV88W8618_PIT
, MP_PIT_BASE
, pic
[MP_TIMER1_IRQ
],
1620 pic
[MP_TIMER2_IRQ
], pic
[MP_TIMER3_IRQ
],
1621 pic
[MP_TIMER4_IRQ
], NULL
);
1623 if (serial_hds
[0]) {
1624 serial_mm_init(address_space_mem
, MP_UART1_BASE
, 2, pic
[MP_UART1_IRQ
],
1625 1825000, serial_hds
[0], DEVICE_NATIVE_ENDIAN
);
1627 if (serial_hds
[1]) {
1628 serial_mm_init(address_space_mem
, MP_UART2_BASE
, 2, pic
[MP_UART2_IRQ
],
1629 1825000, serial_hds
[1], DEVICE_NATIVE_ENDIAN
);
1632 /* Register flash */
1633 dinfo
= drive_get(IF_PFLASH
, 0, 0);
1635 flash_size
= bdrv_getlength(dinfo
->bdrv
);
1636 if (flash_size
!= 8*1024*1024 && flash_size
!= 16*1024*1024 &&
1637 flash_size
!= 32*1024*1024) {
1638 fprintf(stderr
, "Invalid flash image size\n");
1643 * The original U-Boot accesses the flash at 0xFE000000 instead of
1644 * 0xFF800000 (if there is 8 MB flash). So remap flash access if the
1645 * image is smaller than 32 MB.
1647 #ifdef TARGET_WORDS_BIGENDIAN
1648 pflash_cfi02_register(0x100000000ULL
-MP_FLASH_SIZE_MAX
, NULL
,
1649 "musicpal.flash", flash_size
,
1650 dinfo
->bdrv
, 0x10000,
1651 (flash_size
+ 0xffff) >> 16,
1652 MP_FLASH_SIZE_MAX
/ flash_size
,
1653 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1656 pflash_cfi02_register(0x100000000ULL
-MP_FLASH_SIZE_MAX
, NULL
,
1657 "musicpal.flash", flash_size
,
1658 dinfo
->bdrv
, 0x10000,
1659 (flash_size
+ 0xffff) >> 16,
1660 MP_FLASH_SIZE_MAX
/ flash_size
,
1661 2, 0x00BF, 0x236D, 0x0000, 0x0000,
1666 sysbus_create_simple(TYPE_MV88W8618_FLASHCFG
, MP_FLASHCFG_BASE
, NULL
);
1668 qemu_check_nic_model(&nd_table
[0], "mv88w8618");
1669 dev
= qdev_create(NULL
, TYPE_MV88W8618_ETH
);
1670 qdev_set_nic_properties(dev
, &nd_table
[0]);
1671 qdev_init_nofail(dev
);
1672 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, MP_ETH_BASE
);
1673 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, pic
[MP_ETH_IRQ
]);
1675 sysbus_create_simple("mv88w8618_wlan", MP_WLAN_BASE
, NULL
);
1677 sysbus_create_simple(TYPE_MUSICPAL_MISC
, MP_MISC_BASE
, NULL
);
1679 dev
= sysbus_create_simple(TYPE_MUSICPAL_GPIO
, MP_GPIO_BASE
,
1681 i2c_dev
= sysbus_create_simple("gpio_i2c", -1, NULL
);
1682 i2c
= (I2CBus
*)qdev_get_child_bus(i2c_dev
, "i2c");
1684 lcd_dev
= sysbus_create_simple(TYPE_MUSICPAL_LCD
, MP_LCD_BASE
, NULL
);
1685 key_dev
= sysbus_create_simple(TYPE_MUSICPAL_KEY
, -1, NULL
);
1688 qdev_connect_gpio_out(i2c_dev
, 0,
1689 qdev_get_gpio_in(dev
, MP_GPIO_I2C_DATA_BIT
));
1691 qdev_connect_gpio_out(dev
, 3, qdev_get_gpio_in(i2c_dev
, 0));
1693 qdev_connect_gpio_out(dev
, 4, qdev_get_gpio_in(i2c_dev
, 1));
1695 for (i
= 0; i
< 3; i
++) {
1696 qdev_connect_gpio_out(dev
, i
, qdev_get_gpio_in(lcd_dev
, i
));
1698 for (i
= 0; i
< 4; i
++) {
1699 qdev_connect_gpio_out(key_dev
, i
, qdev_get_gpio_in(dev
, i
+ 8));
1701 for (i
= 4; i
< 8; i
++) {
1702 qdev_connect_gpio_out(key_dev
, i
, qdev_get_gpio_in(dev
, i
+ 15));
1705 wm8750_dev
= i2c_create_slave(i2c
, "wm8750", MP_WM_ADDR
);
1706 dev
= qdev_create(NULL
, "mv88w8618_audio");
1707 s
= SYS_BUS_DEVICE(dev
);
1708 qdev_prop_set_ptr(dev
, "wm8750", wm8750_dev
);
1709 qdev_init_nofail(dev
);
1710 sysbus_mmio_map(s
, 0, MP_AUDIO_BASE
);
1711 sysbus_connect_irq(s
, 0, pic
[MP_AUDIO_IRQ
]);
1713 musicpal_binfo
.ram_size
= MP_RAM_DEFAULT_SIZE
;
1714 musicpal_binfo
.kernel_filename
= kernel_filename
;
1715 musicpal_binfo
.kernel_cmdline
= kernel_cmdline
;
1716 musicpal_binfo
.initrd_filename
= initrd_filename
;
1717 arm_load_kernel(cpu
, &musicpal_binfo
);
1720 static QEMUMachine musicpal_machine
= {
1722 .desc
= "Marvell 88w8618 / MusicPal (ARM926EJ-S)",
1723 .init
= musicpal_init
,
1726 static void musicpal_machine_init(void)
1728 qemu_register_machine(&musicpal_machine
);
1731 machine_init(musicpal_machine_init
);
1733 static void mv88w8618_wlan_class_init(ObjectClass
*klass
, void *data
)
1735 SysBusDeviceClass
*sdc
= SYS_BUS_DEVICE_CLASS(klass
);
1737 sdc
->init
= mv88w8618_wlan_init
;
1740 static const TypeInfo mv88w8618_wlan_info
= {
1741 .name
= "mv88w8618_wlan",
1742 .parent
= TYPE_SYS_BUS_DEVICE
,
1743 .instance_size
= sizeof(SysBusDevice
),
1744 .class_init
= mv88w8618_wlan_class_init
,
1747 static void musicpal_register_types(void)
1749 type_register_static(&mv88w8618_pic_info
);
1750 type_register_static(&mv88w8618_pit_info
);
1751 type_register_static(&mv88w8618_flashcfg_info
);
1752 type_register_static(&mv88w8618_eth_info
);
1753 type_register_static(&mv88w8618_wlan_info
);
1754 type_register_static(&musicpal_lcd_info
);
1755 type_register_static(&musicpal_gpio_info
);
1756 type_register_static(&musicpal_key_info
);
1757 type_register_static(&musicpal_misc_info
);
1760 type_init(musicpal_register_types
)