2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2019, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "sysemu/reset.h"
18 #include "monitor/monitor.h"
19 #include "hw/ppc/fdt.h"
20 #include "hw/ppc/pnv.h"
21 #include "hw/ppc/pnv_core.h"
22 #include "hw/ppc/pnv_xscom.h"
23 #include "hw/ppc/pnv_xive.h"
24 #include "hw/ppc/xive_regs.h"
25 #include "hw/qdev-properties.h"
26 #include "hw/ppc/ppc.h"
31 #include "pnv_xive_regs.h"
36 * Virtual structures table (VST)
38 #define SBE_PER_BYTE 4
40 typedef struct XiveVstInfo
{
46 static const XiveVstInfo vst_infos
[] = {
47 [VST_TSEL_IVT
] = { "EAT", sizeof(XiveEAS
), 16 },
48 [VST_TSEL_SBE
] = { "SBE", 1, 16 },
49 [VST_TSEL_EQDT
] = { "ENDT", sizeof(XiveEND
), 16 },
50 [VST_TSEL_VPDT
] = { "VPDT", sizeof(XiveNVT
), 32 },
53 * Interrupt fifo backing store table (not modeled) :
58 * 3 - Second escalate,
60 * 5 - IPI cascaded queue ?
62 [VST_TSEL_IRQ
] = { "IRQ", 1, 6 },
65 #define xive_error(xive, fmt, ...) \
66 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \
67 (xive)->chip->chip_id, ## __VA_ARGS__);
70 * QEMU version of the GETFIELD/SETFIELD macros
72 * TODO: It might be better to use the existing extract64() and
73 * deposit64() but this means that all the register definitions will
74 * change and become incompatible with the ones found in skiboot.
76 * Keep it as it is for now until we find a common ground.
78 static inline uint64_t GETFIELD(uint64_t mask
, uint64_t word
)
80 return (word
& mask
) >> ctz64(mask
);
83 static inline uint64_t SETFIELD(uint64_t mask
, uint64_t word
,
86 return (word
& ~mask
) | ((value
<< ctz64(mask
)) & mask
);
90 * When PC_TCTXT_CHIPID_OVERRIDE is configured, the PC_TCTXT_CHIPID
91 * field overrides the hardwired chip ID in the Powerbus operations
92 * and for CAM compares
94 static uint8_t pnv_xive_block_id(PnvXive
*xive
)
96 uint8_t blk
= xive
->chip
->chip_id
;
97 uint64_t cfg_val
= xive
->regs
[PC_TCTXT_CFG
>> 3];
99 if (cfg_val
& PC_TCTXT_CHIPID_OVERRIDE
) {
100 blk
= GETFIELD(PC_TCTXT_CHIPID
, cfg_val
);
107 * Remote access to controllers. HW uses MMIOs. For now, a simple scan
108 * of the chips is good enough.
110 * TODO: Block scope support
112 static PnvXive
*pnv_xive_get_remote(uint8_t blk
)
114 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
117 for (i
= 0; i
< pnv
->num_chips
; i
++) {
118 Pnv9Chip
*chip9
= PNV9_CHIP(pnv
->chips
[i
]);
119 PnvXive
*xive
= &chip9
->xive
;
121 if (pnv_xive_block_id(xive
) == blk
) {
129 * VST accessors for SBE, EAT, ENDT, NVT
131 * Indirect VST tables are arrays of VSDs pointing to a page (of same
132 * size). Each page is a direct VST table.
135 #define XIVE_VSD_SIZE 8
137 /* Indirect page size can be 4K, 64K, 2M, 16M. */
138 static uint64_t pnv_xive_vst_page_size_allowed(uint32_t page_shift
)
140 return page_shift
== 12 || page_shift
== 16 ||
141 page_shift
== 21 || page_shift
== 24;
144 static uint64_t pnv_xive_vst_addr_direct(PnvXive
*xive
, uint32_t type
,
145 uint64_t vsd
, uint32_t idx
)
147 const XiveVstInfo
*info
= &vst_infos
[type
];
148 uint64_t vst_addr
= vsd
& VSD_ADDRESS_MASK
;
149 uint64_t vst_tsize
= 1ull << (GETFIELD(VSD_TSIZE
, vsd
) + 12);
152 idx_max
= vst_tsize
/ info
->size
- 1;
155 xive_error(xive
, "VST: %s entry %x out of range [ 0 .. %x ] !?",
156 info
->name
, idx
, idx_max
);
161 return vst_addr
+ idx
* info
->size
;
164 static uint64_t pnv_xive_vst_addr_indirect(PnvXive
*xive
, uint32_t type
,
165 uint64_t vsd
, uint32_t idx
)
167 const XiveVstInfo
*info
= &vst_infos
[type
];
171 uint32_t vst_per_page
;
173 /* Get the page size of the indirect table. */
174 vsd_addr
= vsd
& VSD_ADDRESS_MASK
;
175 if (ldq_be_dma(&address_space_memory
, vsd_addr
, &vsd
,
176 MEMTXATTRS_UNSPECIFIED
)) {
177 xive_error(xive
, "VST: failed to access %s entry %x @0x%" PRIx64
,
178 info
->name
, idx
, vsd_addr
);
182 if (!(vsd
& VSD_ADDRESS_MASK
)) {
184 xive_error(xive
, "VST: invalid %s entry %x !?", info
->name
, idx
);
189 page_shift
= GETFIELD(VSD_TSIZE
, vsd
) + 12;
191 if (!pnv_xive_vst_page_size_allowed(page_shift
)) {
192 xive_error(xive
, "VST: invalid %s page shift %d", info
->name
,
197 vst_per_page
= (1ull << page_shift
) / info
->size
;
198 vsd_idx
= idx
/ vst_per_page
;
200 /* Load the VSD we are looking for, if not already done */
202 vsd_addr
= vsd_addr
+ vsd_idx
* XIVE_VSD_SIZE
;
203 if (ldq_be_dma(&address_space_memory
, vsd_addr
, &vsd
,
204 MEMTXATTRS_UNSPECIFIED
)) {
205 xive_error(xive
, "VST: failed to access %s entry %x @0x%"
206 PRIx64
, info
->name
, vsd_idx
, vsd_addr
);
210 if (!(vsd
& VSD_ADDRESS_MASK
)) {
212 xive_error(xive
, "VST: invalid %s entry %x !?", info
->name
, idx
);
218 * Check that the pages have a consistent size across the
221 if (page_shift
!= GETFIELD(VSD_TSIZE
, vsd
) + 12) {
222 xive_error(xive
, "VST: %s entry %x indirect page size differ !?",
228 return pnv_xive_vst_addr_direct(xive
, type
, vsd
, (idx
% vst_per_page
));
231 static uint64_t pnv_xive_vst_addr(PnvXive
*xive
, uint32_t type
, uint8_t blk
,
234 const XiveVstInfo
*info
= &vst_infos
[type
];
237 if (blk
>= info
->max_blocks
) {
238 xive_error(xive
, "VST: invalid block id %d for VST %s %d !?",
239 blk
, info
->name
, idx
);
243 vsd
= xive
->vsds
[type
][blk
];
245 /* Remote VST access */
246 if (GETFIELD(VSD_MODE
, vsd
) == VSD_MODE_FORWARD
) {
247 xive
= pnv_xive_get_remote(blk
);
249 return xive
? pnv_xive_vst_addr(xive
, type
, blk
, idx
) : 0;
252 if (VSD_INDIRECT
& vsd
) {
253 return pnv_xive_vst_addr_indirect(xive
, type
, vsd
, idx
);
256 return pnv_xive_vst_addr_direct(xive
, type
, vsd
, idx
);
259 static int pnv_xive_vst_read(PnvXive
*xive
, uint32_t type
, uint8_t blk
,
260 uint32_t idx
, void *data
)
262 const XiveVstInfo
*info
= &vst_infos
[type
];
263 uint64_t addr
= pnv_xive_vst_addr(xive
, type
, blk
, idx
);
269 cpu_physical_memory_read(addr
, data
, info
->size
);
273 #define XIVE_VST_WORD_ALL -1
275 static int pnv_xive_vst_write(PnvXive
*xive
, uint32_t type
, uint8_t blk
,
276 uint32_t idx
, void *data
, uint32_t word_number
)
278 const XiveVstInfo
*info
= &vst_infos
[type
];
279 uint64_t addr
= pnv_xive_vst_addr(xive
, type
, blk
, idx
);
285 if (word_number
== XIVE_VST_WORD_ALL
) {
286 cpu_physical_memory_write(addr
, data
, info
->size
);
288 cpu_physical_memory_write(addr
+ word_number
* 4,
289 data
+ word_number
* 4, 4);
294 static int pnv_xive_get_end(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
297 return pnv_xive_vst_read(PNV_XIVE(xrtr
), VST_TSEL_EQDT
, blk
, idx
, end
);
300 static int pnv_xive_write_end(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
301 XiveEND
*end
, uint8_t word_number
)
303 return pnv_xive_vst_write(PNV_XIVE(xrtr
), VST_TSEL_EQDT
, blk
, idx
, end
,
307 static int pnv_xive_end_update(PnvXive
*xive
)
309 uint8_t blk
= GETFIELD(VC_EQC_CWATCH_BLOCKID
,
310 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
311 uint32_t idx
= GETFIELD(VC_EQC_CWATCH_OFFSET
,
312 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
314 uint64_t eqc_watch
[4];
316 for (i
= 0; i
< ARRAY_SIZE(eqc_watch
); i
++) {
317 eqc_watch
[i
] = cpu_to_be64(xive
->regs
[(VC_EQC_CWATCH_DAT0
>> 3) + i
]);
320 return pnv_xive_vst_write(xive
, VST_TSEL_EQDT
, blk
, idx
, eqc_watch
,
324 static void pnv_xive_end_cache_load(PnvXive
*xive
)
326 uint8_t blk
= GETFIELD(VC_EQC_CWATCH_BLOCKID
,
327 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
328 uint32_t idx
= GETFIELD(VC_EQC_CWATCH_OFFSET
,
329 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
330 uint64_t eqc_watch
[4] = { 0 };
333 if (pnv_xive_vst_read(xive
, VST_TSEL_EQDT
, blk
, idx
, eqc_watch
)) {
334 xive_error(xive
, "VST: no END entry %x/%x !?", blk
, idx
);
337 for (i
= 0; i
< ARRAY_SIZE(eqc_watch
); i
++) {
338 xive
->regs
[(VC_EQC_CWATCH_DAT0
>> 3) + i
] = be64_to_cpu(eqc_watch
[i
]);
342 static int pnv_xive_get_nvt(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
345 return pnv_xive_vst_read(PNV_XIVE(xrtr
), VST_TSEL_VPDT
, blk
, idx
, nvt
);
348 static int pnv_xive_write_nvt(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
349 XiveNVT
*nvt
, uint8_t word_number
)
351 return pnv_xive_vst_write(PNV_XIVE(xrtr
), VST_TSEL_VPDT
, blk
, idx
, nvt
,
355 static int pnv_xive_nvt_update(PnvXive
*xive
)
357 uint8_t blk
= GETFIELD(PC_VPC_CWATCH_BLOCKID
,
358 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
359 uint32_t idx
= GETFIELD(PC_VPC_CWATCH_OFFSET
,
360 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
362 uint64_t vpc_watch
[8];
364 for (i
= 0; i
< ARRAY_SIZE(vpc_watch
); i
++) {
365 vpc_watch
[i
] = cpu_to_be64(xive
->regs
[(PC_VPC_CWATCH_DAT0
>> 3) + i
]);
368 return pnv_xive_vst_write(xive
, VST_TSEL_VPDT
, blk
, idx
, vpc_watch
,
372 static void pnv_xive_nvt_cache_load(PnvXive
*xive
)
374 uint8_t blk
= GETFIELD(PC_VPC_CWATCH_BLOCKID
,
375 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
376 uint32_t idx
= GETFIELD(PC_VPC_CWATCH_OFFSET
,
377 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
378 uint64_t vpc_watch
[8] = { 0 };
381 if (pnv_xive_vst_read(xive
, VST_TSEL_VPDT
, blk
, idx
, vpc_watch
)) {
382 xive_error(xive
, "VST: no NVT entry %x/%x !?", blk
, idx
);
385 for (i
= 0; i
< ARRAY_SIZE(vpc_watch
); i
++) {
386 xive
->regs
[(PC_VPC_CWATCH_DAT0
>> 3) + i
] = be64_to_cpu(vpc_watch
[i
]);
390 static int pnv_xive_get_eas(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
393 PnvXive
*xive
= PNV_XIVE(xrtr
);
396 * EAT lookups should be local to the IC
398 if (pnv_xive_block_id(xive
) != blk
) {
399 xive_error(xive
, "VST: EAS %x is remote !?", XIVE_EAS(blk
, idx
));
403 return pnv_xive_vst_read(xive
, VST_TSEL_IVT
, blk
, idx
, eas
);
406 static int pnv_xive_get_pq(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
409 PnvXive
*xive
= PNV_XIVE(xrtr
);
411 if (pnv_xive_block_id(xive
) != blk
) {
412 xive_error(xive
, "VST: EAS %x is remote !?", XIVE_EAS(blk
, idx
));
416 *pq
= xive_source_esb_get(&xive
->ipi_source
, idx
);
420 static int pnv_xive_set_pq(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
423 PnvXive
*xive
= PNV_XIVE(xrtr
);
425 if (pnv_xive_block_id(xive
) != blk
) {
426 xive_error(xive
, "VST: EAS %x is remote !?", XIVE_EAS(blk
, idx
));
430 *pq
= xive_source_esb_set(&xive
->ipi_source
, idx
, *pq
);
435 * One bit per thread id. The first register PC_THREAD_EN_REG0 covers
436 * the first cores 0-15 (normal) of the chip or 0-7 (fused). The
437 * second register covers cores 16-23 (normal) or 8-11 (fused).
439 static bool pnv_xive_is_cpu_enabled(PnvXive
*xive
, PowerPCCPU
*cpu
)
441 int pir
= ppc_cpu_pir(cpu
);
442 uint32_t fc
= PNV9_PIR2FUSEDCORE(pir
);
443 uint64_t reg
= fc
< 8 ? PC_THREAD_EN_REG0
: PC_THREAD_EN_REG1
;
444 uint32_t bit
= pir
& 0x3f;
446 return xive
->regs
[reg
>> 3] & PPC_BIT(bit
);
449 static int pnv_xive_match_nvt(XivePresenter
*xptr
, uint8_t format
,
450 uint8_t nvt_blk
, uint32_t nvt_idx
,
451 bool cam_ignore
, uint8_t priority
,
452 uint32_t logic_serv
, XiveTCTXMatch
*match
)
454 PnvXive
*xive
= PNV_XIVE(xptr
);
455 PnvChip
*chip
= xive
->chip
;
459 for (i
= 0; i
< chip
->nr_cores
; i
++) {
460 PnvCore
*pc
= chip
->cores
[i
];
461 CPUCore
*cc
= CPU_CORE(pc
);
463 for (j
= 0; j
< cc
->nr_threads
; j
++) {
464 PowerPCCPU
*cpu
= pc
->threads
[j
];
468 if (!pnv_xive_is_cpu_enabled(xive
, cpu
)) {
472 tctx
= XIVE_TCTX(pnv_cpu_state(cpu
)->intc
);
475 * Check the thread context CAM lines and record matches.
477 ring
= xive_presenter_tctx_match(xptr
, tctx
, format
, nvt_blk
,
478 nvt_idx
, cam_ignore
, logic_serv
);
480 * Save the context and follow on to catch duplicates, that we
485 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: already found a "
486 "thread context NVT %x/%x\n",
501 static uint8_t pnv_xive_get_block_id(XiveRouter
*xrtr
)
503 return pnv_xive_block_id(PNV_XIVE(xrtr
));
507 * The TIMA MMIO space is shared among the chips and to identify the
508 * chip from which the access is being done, we extract the chip id
511 static PnvXive
*pnv_xive_tm_get_xive(PowerPCCPU
*cpu
)
513 int pir
= ppc_cpu_pir(cpu
);
514 XivePresenter
*xptr
= XIVE_TCTX(pnv_cpu_state(cpu
)->intc
)->xptr
;
515 PnvXive
*xive
= PNV_XIVE(xptr
);
517 if (!pnv_xive_is_cpu_enabled(xive
, cpu
)) {
518 xive_error(xive
, "IC: CPU %x is not enabled", pir
);
524 * The internal sources (IPIs) of the interrupt controller have no
525 * knowledge of the XIVE chip on which they reside. Encode the block
526 * id in the source interrupt number before forwarding the source
527 * event notification to the Router. This is required on a multichip
530 static void pnv_xive_notify(XiveNotifier
*xn
, uint32_t srcno
, bool pq_checked
)
532 PnvXive
*xive
= PNV_XIVE(xn
);
533 uint8_t blk
= pnv_xive_block_id(xive
);
535 xive_router_notify(xn
, XIVE_EAS(blk
, srcno
), pq_checked
);
542 static uint64_t pnv_xive_vc_size(PnvXive
*xive
)
544 return (~xive
->regs
[CQ_VC_BARM
>> 3] + 1) & CQ_VC_BARM_MASK
;
547 static uint64_t pnv_xive_edt_shift(PnvXive
*xive
)
549 return ctz64(pnv_xive_vc_size(xive
) / XIVE_TABLE_EDT_MAX
);
552 static uint64_t pnv_xive_pc_size(PnvXive
*xive
)
554 return (~xive
->regs
[CQ_PC_BARM
>> 3] + 1) & CQ_PC_BARM_MASK
;
557 static uint32_t pnv_xive_nr_ipis(PnvXive
*xive
, uint8_t blk
)
559 uint64_t vsd
= xive
->vsds
[VST_TSEL_SBE
][blk
];
560 uint64_t vst_tsize
= 1ull << (GETFIELD(VSD_TSIZE
, vsd
) + 12);
562 return VSD_INDIRECT
& vsd
? 0 : vst_tsize
* SBE_PER_BYTE
;
566 * Compute the number of entries per indirect subpage.
568 static uint64_t pnv_xive_vst_per_subpage(PnvXive
*xive
, uint32_t type
)
570 uint8_t blk
= pnv_xive_block_id(xive
);
571 uint64_t vsd
= xive
->vsds
[type
][blk
];
572 const XiveVstInfo
*info
= &vst_infos
[type
];
576 /* For direct tables, fake a valid value */
577 if (!(VSD_INDIRECT
& vsd
)) {
581 /* Get the page size of the indirect table. */
582 vsd_addr
= vsd
& VSD_ADDRESS_MASK
;
583 if (ldq_be_dma(&address_space_memory
, vsd_addr
, &vsd
,
584 MEMTXATTRS_UNSPECIFIED
)) {
585 xive_error(xive
, "VST: failed to access %s entry @0x%" PRIx64
,
586 info
->name
, vsd_addr
);
590 if (!(vsd
& VSD_ADDRESS_MASK
)) {
592 xive_error(xive
, "VST: invalid %s entry %x !?", info
->name
, idx
);
597 page_shift
= GETFIELD(VSD_TSIZE
, vsd
) + 12;
599 if (!pnv_xive_vst_page_size_allowed(page_shift
)) {
600 xive_error(xive
, "VST: invalid %s page shift %d", info
->name
,
605 return (1ull << page_shift
) / info
->size
;
611 * The Virtualization Controller MMIO region containing the IPI ESB
612 * pages and END ESB pages is sub-divided into "sets" which map
613 * portions of the VC region to the different ESB pages. It is
614 * configured at runtime through the EDT "Domain Table" to let the
615 * firmware decide how to split the VC address space between IPI ESB
616 * pages and END ESB pages.
620 * Computes the overall size of the IPI or the END ESB pages
622 static uint64_t pnv_xive_edt_size(PnvXive
*xive
, uint64_t type
)
624 uint64_t edt_size
= 1ull << pnv_xive_edt_shift(xive
);
628 for (i
= 0; i
< XIVE_TABLE_EDT_MAX
; i
++) {
629 uint64_t edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[i
]);
631 if (edt_type
== type
) {
640 * Maps an offset of the VC region in the IPI or END region using the
641 * layout defined by the EDT "Domaine Table"
643 static uint64_t pnv_xive_edt_offset(PnvXive
*xive
, uint64_t vc_offset
,
647 uint64_t edt_size
= 1ull << pnv_xive_edt_shift(xive
);
648 uint64_t edt_offset
= vc_offset
;
650 for (i
= 0; i
< XIVE_TABLE_EDT_MAX
&& (i
* edt_size
) < vc_offset
; i
++) {
651 uint64_t edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[i
]);
653 if (edt_type
!= type
) {
654 edt_offset
-= edt_size
;
661 static void pnv_xive_edt_resize(PnvXive
*xive
)
663 uint64_t ipi_edt_size
= pnv_xive_edt_size(xive
, CQ_TDR_EDT_IPI
);
664 uint64_t end_edt_size
= pnv_xive_edt_size(xive
, CQ_TDR_EDT_EQ
);
666 memory_region_set_size(&xive
->ipi_edt_mmio
, ipi_edt_size
);
667 memory_region_add_subregion(&xive
->ipi_mmio
, 0, &xive
->ipi_edt_mmio
);
669 memory_region_set_size(&xive
->end_edt_mmio
, end_edt_size
);
670 memory_region_add_subregion(&xive
->end_mmio
, 0, &xive
->end_edt_mmio
);
674 * XIVE Table configuration. Only EDT is supported.
676 static int pnv_xive_table_set_data(PnvXive
*xive
, uint64_t val
)
678 uint64_t tsel
= xive
->regs
[CQ_TAR
>> 3] & CQ_TAR_TSEL
;
679 uint8_t tsel_index
= GETFIELD(CQ_TAR_TSEL_INDEX
, xive
->regs
[CQ_TAR
>> 3]);
680 uint64_t *xive_table
;
684 case CQ_TAR_TSEL_BLK
:
685 max_index
= ARRAY_SIZE(xive
->blk
);
686 xive_table
= xive
->blk
;
688 case CQ_TAR_TSEL_MIG
:
689 max_index
= ARRAY_SIZE(xive
->mig
);
690 xive_table
= xive
->mig
;
692 case CQ_TAR_TSEL_EDT
:
693 max_index
= ARRAY_SIZE(xive
->edt
);
694 xive_table
= xive
->edt
;
696 case CQ_TAR_TSEL_VDT
:
697 max_index
= ARRAY_SIZE(xive
->vdt
);
698 xive_table
= xive
->vdt
;
701 xive_error(xive
, "IC: invalid table %d", (int) tsel
);
705 if (tsel_index
>= max_index
) {
706 xive_error(xive
, "IC: invalid index %d", (int) tsel_index
);
710 xive_table
[tsel_index
] = val
;
712 if (xive
->regs
[CQ_TAR
>> 3] & CQ_TAR_TBL_AUTOINC
) {
713 xive
->regs
[CQ_TAR
>> 3] =
714 SETFIELD(CQ_TAR_TSEL_INDEX
, xive
->regs
[CQ_TAR
>> 3], ++tsel_index
);
718 * EDT configuration is complete. Resize the MMIO windows exposing
719 * the IPI and the END ESBs in the VC region.
721 if (tsel
== CQ_TAR_TSEL_EDT
&& tsel_index
== ARRAY_SIZE(xive
->edt
)) {
722 pnv_xive_edt_resize(xive
);
729 * Virtual Structure Tables (VST) configuration
731 static void pnv_xive_vst_set_exclusive(PnvXive
*xive
, uint8_t type
,
732 uint8_t blk
, uint64_t vsd
)
734 XiveENDSource
*end_xsrc
= &xive
->end_source
;
735 XiveSource
*xsrc
= &xive
->ipi_source
;
736 const XiveVstInfo
*info
= &vst_infos
[type
];
737 uint32_t page_shift
= GETFIELD(VSD_TSIZE
, vsd
) + 12;
738 uint64_t vst_tsize
= 1ull << page_shift
;
739 uint64_t vst_addr
= vsd
& VSD_ADDRESS_MASK
;
743 if (VSD_INDIRECT
& vsd
) {
744 if (!(xive
->regs
[VC_GLOBAL_CONFIG
>> 3] & VC_GCONF_INDIRECT
)) {
745 xive_error(xive
, "VST: %s indirect tables are not enabled",
750 if (!pnv_xive_vst_page_size_allowed(page_shift
)) {
751 xive_error(xive
, "VST: invalid %s page shift %d", info
->name
,
757 if (!QEMU_IS_ALIGNED(vst_addr
, 1ull << page_shift
)) {
758 xive_error(xive
, "VST: %s table address 0x%"PRIx64
" is not aligned with"
759 " page shift %d", info
->name
, vst_addr
, page_shift
);
763 /* Record the table configuration (in SRAM on HW) */
764 xive
->vsds
[type
][blk
] = vsd
;
766 /* Now tune the models with the configuration provided by the FW */
769 case VST_TSEL_IVT
: /* Nothing to be done */
774 * Backing store pages for the END.
776 * If the table is direct, we can compute the number of PQ
777 * entries provisioned by FW (such as skiboot) and resize the
778 * END ESB window accordingly.
780 if (!(VSD_INDIRECT
& vsd
)) {
781 memory_region_set_size(&end_xsrc
->esb_mmio
, (vst_tsize
/ info
->size
)
782 * (1ull << xsrc
->esb_shift
));
784 memory_region_add_subregion(&xive
->end_edt_mmio
, 0,
785 &end_xsrc
->esb_mmio
);
790 * Backing store pages for the source PQ bits. The model does
791 * not use these PQ bits backed in RAM because the XiveSource
794 * If the table is direct, we can compute the number of PQ
795 * entries provisioned by FW (such as skiboot) and resize the
796 * ESB window accordingly.
798 if (!(VSD_INDIRECT
& vsd
)) {
799 memory_region_set_size(&xsrc
->esb_mmio
, vst_tsize
* SBE_PER_BYTE
800 * (1ull << xsrc
->esb_shift
));
802 memory_region_add_subregion(&xive
->ipi_edt_mmio
, 0, &xsrc
->esb_mmio
);
805 case VST_TSEL_VPDT
: /* Not modeled */
806 case VST_TSEL_IRQ
: /* Not modeled */
808 * These tables contains the backing store pages for the
809 * interrupt fifos of the VC sub-engine in case of overflow.
814 g_assert_not_reached();
819 * Both PC and VC sub-engines are configured as each use the Virtual
820 * Structure Tables : SBE, EAS, END and NVT.
822 static void pnv_xive_vst_set_data(PnvXive
*xive
, uint64_t vsd
, bool pc_engine
)
824 uint8_t mode
= GETFIELD(VSD_MODE
, vsd
);
825 uint8_t type
= GETFIELD(VST_TABLE_SELECT
,
826 xive
->regs
[VC_VSD_TABLE_ADDR
>> 3]);
827 uint8_t blk
= GETFIELD(VST_TABLE_BLOCK
,
828 xive
->regs
[VC_VSD_TABLE_ADDR
>> 3]);
829 uint64_t vst_addr
= vsd
& VSD_ADDRESS_MASK
;
831 if (type
> VST_TSEL_IRQ
) {
832 xive_error(xive
, "VST: invalid table type %d", type
);
836 if (blk
>= vst_infos
[type
].max_blocks
) {
837 xive_error(xive
, "VST: invalid block id %d for"
838 " %s table", blk
, vst_infos
[type
].name
);
843 * Only take the VC sub-engine configuration into account because
844 * the XiveRouter model combines both VC and PC sub-engines
851 xive_error(xive
, "VST: invalid %s table address", vst_infos
[type
].name
);
856 case VSD_MODE_FORWARD
:
857 xive
->vsds
[type
][blk
] = vsd
;
860 case VSD_MODE_EXCLUSIVE
:
861 pnv_xive_vst_set_exclusive(xive
, type
, blk
, vsd
);
865 xive_error(xive
, "VST: unsupported table mode %d", mode
);
871 * Interrupt controller MMIO region. The layout is compatible between
874 * Page 0 sub-engine BARs
875 * 0x000 - 0x3FF IC registers
876 * 0x400 - 0x7FF PC registers
877 * 0x800 - 0xFFF VC registers
879 * Page 1 Notify page (writes only)
880 * 0x000 - 0x7FF HW interrupt triggers (PSI, PHB)
881 * 0x800 - 0xFFF forwards and syncs
883 * Page 2 LSI Trigger page (writes only) (not modeled)
884 * Page 3 LSI SB EOI page (reads only) (not modeled)
886 * Page 4-7 indirect TIMA
890 * IC - registers MMIO
892 static void pnv_xive_ic_reg_write(void *opaque
, hwaddr offset
,
893 uint64_t val
, unsigned size
)
895 PnvXive
*xive
= PNV_XIVE(opaque
);
896 MemoryRegion
*sysmem
= get_system_memory();
897 uint32_t reg
= offset
>> 3;
898 bool is_chip0
= xive
->chip
->chip_id
== 0;
903 * XIVE CQ (PowerBus bridge) settings
905 case CQ_MSGSND
: /* msgsnd for doorbells */
906 case CQ_FIRMASK_OR
: /* FIR error reporting */
909 if (val
& CQ_PBI_PC_64K
) {
912 if (val
& CQ_PBI_VC_64K
) {
916 case CQ_CFG_PB_GEN
: /* PowerBus General Configuration */
918 * TODO: CQ_INT_ADDR_OPT for 1-block-per-chip mode
923 * XIVE Virtualization Controller settings
925 case VC_GLOBAL_CONFIG
:
929 * XIVE Presenter Controller settings
931 case PC_GLOBAL_CONFIG
:
933 * PC_GCONF_CHIPID_OVR
934 * Overrides Int command Chip ID with the Chip ID field (DEBUG)
939 * TODO: block group support
945 * enable block tracking and exchange of block ownership
946 * information between Interrupt controllers
953 case VC_SBC_CONFIG
: /* Store EOI configuration */
955 * Configure store EOI if required by firwmare (skiboot has removed
956 * support recently though)
958 if (val
& (VC_SBC_CONF_CPLX_CIST
| VC_SBC_CONF_CIST_BOTH
)) {
959 xive
->ipi_source
.esb_flags
|= XIVE_SRC_STORE_EOI
;
963 case VC_EQC_CONFIG
: /* TODO: silent escalation */
964 case VC_AIB_TX_ORDER_TAG2
: /* relax ordering */
968 * XIVE BAR settings (XSCOM only)
971 /* bit4: resets all BAR registers */
974 case CQ_IC_BAR
: /* IC BAR. 8 pages */
975 xive
->ic_shift
= val
& CQ_IC_BAR_64K
? 16 : 12;
976 if (!(val
& CQ_IC_BAR_VALID
)) {
978 if (xive
->regs
[reg
] & CQ_IC_BAR_VALID
) {
979 memory_region_del_subregion(&xive
->ic_mmio
,
981 memory_region_del_subregion(&xive
->ic_mmio
,
982 &xive
->ic_notify_mmio
);
983 memory_region_del_subregion(&xive
->ic_mmio
,
985 memory_region_del_subregion(&xive
->ic_mmio
,
986 &xive
->tm_indirect_mmio
);
988 memory_region_del_subregion(sysmem
, &xive
->ic_mmio
);
991 xive
->ic_base
= val
& ~(CQ_IC_BAR_VALID
| CQ_IC_BAR_64K
);
992 if (!(xive
->regs
[reg
] & CQ_IC_BAR_VALID
)) {
993 memory_region_add_subregion(sysmem
, xive
->ic_base
,
996 memory_region_add_subregion(&xive
->ic_mmio
, 0,
998 memory_region_add_subregion(&xive
->ic_mmio
,
999 1ul << xive
->ic_shift
,
1000 &xive
->ic_notify_mmio
);
1001 memory_region_add_subregion(&xive
->ic_mmio
,
1002 2ul << xive
->ic_shift
,
1003 &xive
->ic_lsi_mmio
);
1004 memory_region_add_subregion(&xive
->ic_mmio
,
1005 4ull << xive
->ic_shift
,
1006 &xive
->tm_indirect_mmio
);
1011 case CQ_TM1_BAR
: /* TM BAR. 4 pages. Map only once */
1012 case CQ_TM2_BAR
: /* second TM BAR. for hotplug. Not modeled */
1013 xive
->tm_shift
= val
& CQ_TM_BAR_64K
? 16 : 12;
1014 if (!(val
& CQ_TM_BAR_VALID
)) {
1016 if (xive
->regs
[reg
] & CQ_TM_BAR_VALID
&& is_chip0
) {
1017 memory_region_del_subregion(sysmem
, &xive
->tm_mmio
);
1020 xive
->tm_base
= val
& ~(CQ_TM_BAR_VALID
| CQ_TM_BAR_64K
);
1021 if (!(xive
->regs
[reg
] & CQ_TM_BAR_VALID
) && is_chip0
) {
1022 memory_region_add_subregion(sysmem
, xive
->tm_base
,
1029 xive
->regs
[reg
] = val
;
1030 memory_region_set_size(&xive
->pc_mmio
, pnv_xive_pc_size(xive
));
1032 case CQ_PC_BAR
: /* From 32M to 512G */
1033 if (!(val
& CQ_PC_BAR_VALID
)) {
1035 if (xive
->regs
[reg
] & CQ_PC_BAR_VALID
) {
1036 memory_region_del_subregion(sysmem
, &xive
->pc_mmio
);
1039 xive
->pc_base
= val
& ~(CQ_PC_BAR_VALID
);
1040 if (!(xive
->regs
[reg
] & CQ_PC_BAR_VALID
)) {
1041 memory_region_add_subregion(sysmem
, xive
->pc_base
,
1048 xive
->regs
[reg
] = val
;
1049 memory_region_set_size(&xive
->vc_mmio
, pnv_xive_vc_size(xive
));
1051 case CQ_VC_BAR
: /* From 64M to 4TB */
1052 if (!(val
& CQ_VC_BAR_VALID
)) {
1054 if (xive
->regs
[reg
] & CQ_VC_BAR_VALID
) {
1055 memory_region_del_subregion(sysmem
, &xive
->vc_mmio
);
1058 xive
->vc_base
= val
& ~(CQ_VC_BAR_VALID
);
1059 if (!(xive
->regs
[reg
] & CQ_VC_BAR_VALID
)) {
1060 memory_region_add_subregion(sysmem
, xive
->vc_base
,
1067 * XIVE Table settings.
1069 case CQ_TAR
: /* Table Address */
1071 case CQ_TDR
: /* Table Data */
1072 pnv_xive_table_set_data(xive
, val
);
1076 * XIVE VC & PC Virtual Structure Table settings
1078 case VC_VSD_TABLE_ADDR
:
1079 case PC_VSD_TABLE_ADDR
: /* Virtual table selector */
1081 case VC_VSD_TABLE_DATA
: /* Virtual table setting */
1082 case PC_VSD_TABLE_DATA
:
1083 pnv_xive_vst_set_data(xive
, val
, offset
== PC_VSD_TABLE_DATA
);
1087 * Interrupt fifo overflow in memory backing store (Not modeled)
1089 case VC_IRQ_CONFIG_IPI
:
1090 case VC_IRQ_CONFIG_HW
:
1091 case VC_IRQ_CONFIG_CASCADE1
:
1092 case VC_IRQ_CONFIG_CASCADE2
:
1093 case VC_IRQ_CONFIG_REDIST
:
1094 case VC_IRQ_CONFIG_IPI_CASC
:
1098 * XIVE hardware thread enablement
1100 case PC_THREAD_EN_REG0
: /* Physical Thread Enable */
1101 case PC_THREAD_EN_REG1
: /* Physical Thread Enable (fused core) */
1104 case PC_THREAD_EN_REG0_SET
:
1105 xive
->regs
[PC_THREAD_EN_REG0
>> 3] |= val
;
1107 case PC_THREAD_EN_REG1_SET
:
1108 xive
->regs
[PC_THREAD_EN_REG1
>> 3] |= val
;
1110 case PC_THREAD_EN_REG0_CLR
:
1111 xive
->regs
[PC_THREAD_EN_REG0
>> 3] &= ~val
;
1113 case PC_THREAD_EN_REG1_CLR
:
1114 xive
->regs
[PC_THREAD_EN_REG1
>> 3] &= ~val
;
1118 * Indirect TIMA access set up. Defines the PIR of the HW thread
1121 case PC_TCTXT_INDIR0
... PC_TCTXT_INDIR3
:
1125 * XIVE PC & VC cache updates for EAS, NVT and END
1127 case VC_IVC_SCRUB_MASK
:
1128 case VC_IVC_SCRUB_TRIG
:
1131 case VC_EQC_CWATCH_SPEC
:
1132 val
&= ~VC_EQC_CWATCH_CONFLICT
; /* HW resets this bit */
1134 case VC_EQC_CWATCH_DAT1
... VC_EQC_CWATCH_DAT3
:
1136 case VC_EQC_CWATCH_DAT0
:
1137 /* writing to DATA0 triggers the cache write */
1138 xive
->regs
[reg
] = val
;
1139 pnv_xive_end_update(xive
);
1141 case VC_EQC_SCRUB_MASK
:
1142 case VC_EQC_SCRUB_TRIG
:
1144 * The scrubbing registers flush the cache in RAM and can also
1149 case PC_VPC_CWATCH_SPEC
:
1150 val
&= ~PC_VPC_CWATCH_CONFLICT
; /* HW resets this bit */
1152 case PC_VPC_CWATCH_DAT1
... PC_VPC_CWATCH_DAT7
:
1154 case PC_VPC_CWATCH_DAT0
:
1155 /* writing to DATA0 triggers the cache write */
1156 xive
->regs
[reg
] = val
;
1157 pnv_xive_nvt_update(xive
);
1159 case PC_VPC_SCRUB_MASK
:
1160 case PC_VPC_SCRUB_TRIG
:
1162 * The scrubbing registers flush the cache in RAM and can also
1169 * XIVE PC & VC cache invalidation
1173 case VC_AT_MACRO_KILL
:
1175 case PC_AT_KILL_MASK
:
1176 case VC_AT_MACRO_KILL_MASK
:
1180 xive_error(xive
, "IC: invalid write to reg=0x%"HWADDR_PRIx
, offset
);
1184 xive
->regs
[reg
] = val
;
1187 static uint64_t pnv_xive_ic_reg_read(void *opaque
, hwaddr offset
, unsigned size
)
1189 PnvXive
*xive
= PNV_XIVE(opaque
);
1191 uint32_t reg
= offset
>> 3;
1207 case PC_TCTXT_TRACK
:
1208 case PC_TCTXT_INDIR0
:
1209 case PC_TCTXT_INDIR1
:
1210 case PC_TCTXT_INDIR2
:
1211 case PC_TCTXT_INDIR3
:
1212 case PC_GLOBAL_CONFIG
:
1214 case PC_VPC_SCRUB_MASK
:
1216 case VC_GLOBAL_CONFIG
:
1217 case VC_AIB_TX_ORDER_TAG2
:
1219 case VC_IRQ_CONFIG_IPI
:
1220 case VC_IRQ_CONFIG_HW
:
1221 case VC_IRQ_CONFIG_CASCADE1
:
1222 case VC_IRQ_CONFIG_CASCADE2
:
1223 case VC_IRQ_CONFIG_REDIST
:
1224 case VC_IRQ_CONFIG_IPI_CASC
:
1226 case VC_EQC_SCRUB_MASK
:
1227 case VC_IVC_SCRUB_MASK
:
1229 case VC_AT_MACRO_KILL_MASK
:
1230 case VC_VSD_TABLE_ADDR
:
1231 case PC_VSD_TABLE_ADDR
:
1232 case VC_VSD_TABLE_DATA
:
1233 case PC_VSD_TABLE_DATA
:
1234 case PC_THREAD_EN_REG0
:
1235 case PC_THREAD_EN_REG1
:
1236 val
= xive
->regs
[reg
];
1240 * XIVE hardware thread enablement
1242 case PC_THREAD_EN_REG0_SET
:
1243 case PC_THREAD_EN_REG0_CLR
:
1244 val
= xive
->regs
[PC_THREAD_EN_REG0
>> 3];
1246 case PC_THREAD_EN_REG1_SET
:
1247 case PC_THREAD_EN_REG1_CLR
:
1248 val
= xive
->regs
[PC_THREAD_EN_REG1
>> 3];
1251 case CQ_MSGSND
: /* Identifies which cores have msgsnd enabled. */
1252 val
= 0xffffff0000000000;
1256 * XIVE PC & VC cache updates for EAS, NVT and END
1258 case VC_EQC_CWATCH_SPEC
:
1259 xive
->regs
[reg
] = ~(VC_EQC_CWATCH_FULL
| VC_EQC_CWATCH_CONFLICT
);
1260 val
= xive
->regs
[reg
];
1262 case VC_EQC_CWATCH_DAT0
:
1264 * Load DATA registers from cache with data requested by the
1267 pnv_xive_end_cache_load(xive
);
1268 val
= xive
->regs
[reg
];
1270 case VC_EQC_CWATCH_DAT1
... VC_EQC_CWATCH_DAT3
:
1271 val
= xive
->regs
[reg
];
1274 case PC_VPC_CWATCH_SPEC
:
1275 xive
->regs
[reg
] = ~(PC_VPC_CWATCH_FULL
| PC_VPC_CWATCH_CONFLICT
);
1276 val
= xive
->regs
[reg
];
1278 case PC_VPC_CWATCH_DAT0
:
1280 * Load DATA registers from cache with data requested by the
1283 pnv_xive_nvt_cache_load(xive
);
1284 val
= xive
->regs
[reg
];
1286 case PC_VPC_CWATCH_DAT1
... PC_VPC_CWATCH_DAT7
:
1287 val
= xive
->regs
[reg
];
1290 case PC_VPC_SCRUB_TRIG
:
1291 case VC_IVC_SCRUB_TRIG
:
1292 case VC_EQC_SCRUB_TRIG
:
1293 xive
->regs
[reg
] &= ~VC_SCRUB_VALID
;
1294 val
= xive
->regs
[reg
];
1298 * XIVE PC & VC cache invalidation
1301 xive
->regs
[reg
] &= ~PC_AT_KILL_VALID
;
1302 val
= xive
->regs
[reg
];
1304 case VC_AT_MACRO_KILL
:
1305 xive
->regs
[reg
] &= ~VC_KILL_VALID
;
1306 val
= xive
->regs
[reg
];
1310 * XIVE synchronisation
1313 val
= VC_EQC_SYNC_MASK
;
1317 xive_error(xive
, "IC: invalid read reg=0x%"HWADDR_PRIx
, offset
);
1323 static const MemoryRegionOps pnv_xive_ic_reg_ops
= {
1324 .read
= pnv_xive_ic_reg_read
,
1325 .write
= pnv_xive_ic_reg_write
,
1326 .endianness
= DEVICE_BIG_ENDIAN
,
1328 .min_access_size
= 8,
1329 .max_access_size
= 8,
1332 .min_access_size
= 8,
1333 .max_access_size
= 8,
1338 * IC - Notify MMIO port page (write only)
1340 #define PNV_XIVE_FORWARD_IPI 0x800 /* Forward IPI */
1341 #define PNV_XIVE_FORWARD_HW 0x880 /* Forward HW */
1342 #define PNV_XIVE_FORWARD_OS_ESC 0x900 /* Forward OS escalation */
1343 #define PNV_XIVE_FORWARD_HW_ESC 0x980 /* Forward Hyp escalation */
1344 #define PNV_XIVE_FORWARD_REDIS 0xa00 /* Forward Redistribution */
1345 #define PNV_XIVE_RESERVED5 0xa80 /* Cache line 5 PowerBUS operation */
1346 #define PNV_XIVE_RESERVED6 0xb00 /* Cache line 6 PowerBUS operation */
1347 #define PNV_XIVE_RESERVED7 0xb80 /* Cache line 7 PowerBUS operation */
1349 /* VC synchronisation */
1350 #define PNV_XIVE_SYNC_IPI 0xc00 /* Sync IPI */
1351 #define PNV_XIVE_SYNC_HW 0xc80 /* Sync HW */
1352 #define PNV_XIVE_SYNC_OS_ESC 0xd00 /* Sync OS escalation */
1353 #define PNV_XIVE_SYNC_HW_ESC 0xd80 /* Sync Hyp escalation */
1354 #define PNV_XIVE_SYNC_REDIS 0xe00 /* Sync Redistribution */
1356 /* PC synchronisation */
1357 #define PNV_XIVE_SYNC_PULL 0xe80 /* Sync pull context */
1358 #define PNV_XIVE_SYNC_PUSH 0xf00 /* Sync push context */
1359 #define PNV_XIVE_SYNC_VPC 0xf80 /* Sync remove VPC store */
1361 static void pnv_xive_ic_hw_trigger(PnvXive
*xive
, hwaddr addr
, uint64_t val
)
1366 trace_pnv_xive_ic_hw_trigger(addr
, val
);
1368 if (val
& XIVE_TRIGGER_END
) {
1369 xive_error(xive
, "IC: END trigger at @0x%"HWADDR_PRIx
" data 0x%"PRIx64
,
1375 * Forward the source event notification directly to the Router.
1376 * The source interrupt number should already be correctly encoded
1377 * with the chip block id by the sending device (PHB, PSI).
1379 blk
= XIVE_EAS_BLOCK(val
);
1380 idx
= XIVE_EAS_INDEX(val
);
1382 xive_router_notify(XIVE_NOTIFIER(xive
), XIVE_EAS(blk
, idx
),
1383 !!(val
& XIVE_TRIGGER_PQ
));
1386 static void pnv_xive_ic_notify_write(void *opaque
, hwaddr addr
, uint64_t val
,
1389 PnvXive
*xive
= PNV_XIVE(opaque
);
1391 /* VC: HW triggers */
1393 case 0x000 ... 0x7FF:
1394 pnv_xive_ic_hw_trigger(opaque
, addr
, val
);
1397 /* VC: Forwarded IRQs */
1398 case PNV_XIVE_FORWARD_IPI
:
1399 case PNV_XIVE_FORWARD_HW
:
1400 case PNV_XIVE_FORWARD_OS_ESC
:
1401 case PNV_XIVE_FORWARD_HW_ESC
:
1402 case PNV_XIVE_FORWARD_REDIS
:
1403 /* TODO: forwarded IRQs. Should be like HW triggers */
1404 xive_error(xive
, "IC: forwarded at @0x%"HWADDR_PRIx
" IRQ 0x%"PRIx64
,
1409 case PNV_XIVE_SYNC_IPI
:
1410 case PNV_XIVE_SYNC_HW
:
1411 case PNV_XIVE_SYNC_OS_ESC
:
1412 case PNV_XIVE_SYNC_HW_ESC
:
1413 case PNV_XIVE_SYNC_REDIS
:
1417 case PNV_XIVE_SYNC_PULL
:
1418 case PNV_XIVE_SYNC_PUSH
:
1419 case PNV_XIVE_SYNC_VPC
:
1423 xive_error(xive
, "IC: invalid notify write @%"HWADDR_PRIx
, addr
);
1427 static uint64_t pnv_xive_ic_notify_read(void *opaque
, hwaddr addr
,
1430 PnvXive
*xive
= PNV_XIVE(opaque
);
1432 /* loads are invalid */
1433 xive_error(xive
, "IC: invalid notify read @%"HWADDR_PRIx
, addr
);
1437 static const MemoryRegionOps pnv_xive_ic_notify_ops
= {
1438 .read
= pnv_xive_ic_notify_read
,
1439 .write
= pnv_xive_ic_notify_write
,
1440 .endianness
= DEVICE_BIG_ENDIAN
,
1442 .min_access_size
= 8,
1443 .max_access_size
= 8,
1446 .min_access_size
= 8,
1447 .max_access_size
= 8,
1452 * IC - LSI MMIO handlers (not modeled)
1455 static void pnv_xive_ic_lsi_write(void *opaque
, hwaddr addr
,
1456 uint64_t val
, unsigned size
)
1458 PnvXive
*xive
= PNV_XIVE(opaque
);
1460 xive_error(xive
, "IC: LSI invalid write @%"HWADDR_PRIx
, addr
);
1463 static uint64_t pnv_xive_ic_lsi_read(void *opaque
, hwaddr addr
, unsigned size
)
1465 PnvXive
*xive
= PNV_XIVE(opaque
);
1467 xive_error(xive
, "IC: LSI invalid read @%"HWADDR_PRIx
, addr
);
1471 static const MemoryRegionOps pnv_xive_ic_lsi_ops
= {
1472 .read
= pnv_xive_ic_lsi_read
,
1473 .write
= pnv_xive_ic_lsi_write
,
1474 .endianness
= DEVICE_BIG_ENDIAN
,
1476 .min_access_size
= 8,
1477 .max_access_size
= 8,
1480 .min_access_size
= 8,
1481 .max_access_size
= 8,
1486 * IC - Indirect TIMA MMIO handlers
1490 * When the TIMA is accessed from the indirect page, the thread id of
1491 * the target CPU is configured in the PC_TCTXT_INDIR0 register before
1492 * use. This is used for resets and for debug purpose also.
1494 static XiveTCTX
*pnv_xive_get_indirect_tctx(PnvXive
*xive
)
1496 PnvChip
*chip
= xive
->chip
;
1497 uint64_t tctxt_indir
= xive
->regs
[PC_TCTXT_INDIR0
>> 3];
1498 PowerPCCPU
*cpu
= NULL
;
1501 if (!(tctxt_indir
& PC_TCTXT_INDIR_VALID
)) {
1502 xive_error(xive
, "IC: no indirect TIMA access in progress");
1506 pir
= (chip
->chip_id
<< 8) | GETFIELD(PC_TCTXT_INDIR_THRDID
, tctxt_indir
);
1507 cpu
= pnv_chip_find_cpu(chip
, pir
);
1509 xive_error(xive
, "IC: invalid PIR %x for indirect access", pir
);
1513 /* Check that HW thread is XIVE enabled */
1514 if (!pnv_xive_is_cpu_enabled(xive
, cpu
)) {
1515 xive_error(xive
, "IC: CPU %x is not enabled", pir
);
1518 return XIVE_TCTX(pnv_cpu_state(cpu
)->intc
);
1521 static void xive_tm_indirect_write(void *opaque
, hwaddr offset
,
1522 uint64_t value
, unsigned size
)
1524 XiveTCTX
*tctx
= pnv_xive_get_indirect_tctx(PNV_XIVE(opaque
));
1526 xive_tctx_tm_write(XIVE_PRESENTER(opaque
), tctx
, offset
, value
, size
);
1529 static uint64_t xive_tm_indirect_read(void *opaque
, hwaddr offset
,
1532 XiveTCTX
*tctx
= pnv_xive_get_indirect_tctx(PNV_XIVE(opaque
));
1534 return xive_tctx_tm_read(XIVE_PRESENTER(opaque
), tctx
, offset
, size
);
1537 static const MemoryRegionOps xive_tm_indirect_ops
= {
1538 .read
= xive_tm_indirect_read
,
1539 .write
= xive_tm_indirect_write
,
1540 .endianness
= DEVICE_BIG_ENDIAN
,
1542 .min_access_size
= 1,
1543 .max_access_size
= 8,
1546 .min_access_size
= 1,
1547 .max_access_size
= 8,
1551 static void pnv_xive_tm_write(void *opaque
, hwaddr offset
,
1552 uint64_t value
, unsigned size
)
1554 PowerPCCPU
*cpu
= POWERPC_CPU(current_cpu
);
1555 PnvXive
*xive
= pnv_xive_tm_get_xive(cpu
);
1556 XiveTCTX
*tctx
= XIVE_TCTX(pnv_cpu_state(cpu
)->intc
);
1558 xive_tctx_tm_write(XIVE_PRESENTER(xive
), tctx
, offset
, value
, size
);
1561 static uint64_t pnv_xive_tm_read(void *opaque
, hwaddr offset
, unsigned size
)
1563 PowerPCCPU
*cpu
= POWERPC_CPU(current_cpu
);
1564 PnvXive
*xive
= pnv_xive_tm_get_xive(cpu
);
1565 XiveTCTX
*tctx
= XIVE_TCTX(pnv_cpu_state(cpu
)->intc
);
1567 return xive_tctx_tm_read(XIVE_PRESENTER(xive
), tctx
, offset
, size
);
1570 const MemoryRegionOps pnv_xive_tm_ops
= {
1571 .read
= pnv_xive_tm_read
,
1572 .write
= pnv_xive_tm_write
,
1573 .endianness
= DEVICE_BIG_ENDIAN
,
1575 .min_access_size
= 1,
1576 .max_access_size
= 8,
1579 .min_access_size
= 1,
1580 .max_access_size
= 8,
1585 * Interrupt controller XSCOM region.
1587 static uint64_t pnv_xive_xscom_read(void *opaque
, hwaddr addr
, unsigned size
)
1589 switch (addr
>> 3) {
1590 case X_VC_EQC_CONFIG
:
1591 /* FIXME (skiboot): This is the only XSCOM load. Bizarre. */
1592 return VC_EQC_SYNC_MASK
;
1594 return pnv_xive_ic_reg_read(opaque
, addr
, size
);
1598 static void pnv_xive_xscom_write(void *opaque
, hwaddr addr
,
1599 uint64_t val
, unsigned size
)
1601 pnv_xive_ic_reg_write(opaque
, addr
, val
, size
);
1604 static const MemoryRegionOps pnv_xive_xscom_ops
= {
1605 .read
= pnv_xive_xscom_read
,
1606 .write
= pnv_xive_xscom_write
,
1607 .endianness
= DEVICE_BIG_ENDIAN
,
1609 .min_access_size
= 8,
1610 .max_access_size
= 8,
1613 .min_access_size
= 8,
1614 .max_access_size
= 8,
1619 * Virtualization Controller MMIO region containing the IPI and END ESB pages
1621 static uint64_t pnv_xive_vc_read(void *opaque
, hwaddr offset
,
1624 PnvXive
*xive
= PNV_XIVE(opaque
);
1625 uint64_t edt_index
= offset
>> pnv_xive_edt_shift(xive
);
1626 uint64_t edt_type
= 0;
1627 uint64_t edt_offset
;
1629 AddressSpace
*edt_as
= NULL
;
1632 if (edt_index
< XIVE_TABLE_EDT_MAX
) {
1633 edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[edt_index
]);
1637 case CQ_TDR_EDT_IPI
:
1638 edt_as
= &xive
->ipi_as
;
1641 edt_as
= &xive
->end_as
;
1644 xive_error(xive
, "VC: invalid EDT type for read @%"HWADDR_PRIx
, offset
);
1648 /* Remap the offset for the targeted address space */
1649 edt_offset
= pnv_xive_edt_offset(xive
, offset
, edt_type
);
1651 ret
= address_space_ldq(edt_as
, edt_offset
, MEMTXATTRS_UNSPECIFIED
,
1654 if (result
!= MEMTX_OK
) {
1655 xive_error(xive
, "VC: %s read failed at @0x%"HWADDR_PRIx
" -> @0x%"
1656 HWADDR_PRIx
, edt_type
== CQ_TDR_EDT_IPI
? "IPI" : "END",
1657 offset
, edt_offset
);
1664 static void pnv_xive_vc_write(void *opaque
, hwaddr offset
,
1665 uint64_t val
, unsigned size
)
1667 PnvXive
*xive
= PNV_XIVE(opaque
);
1668 uint64_t edt_index
= offset
>> pnv_xive_edt_shift(xive
);
1669 uint64_t edt_type
= 0;
1670 uint64_t edt_offset
;
1672 AddressSpace
*edt_as
= NULL
;
1674 if (edt_index
< XIVE_TABLE_EDT_MAX
) {
1675 edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[edt_index
]);
1679 case CQ_TDR_EDT_IPI
:
1680 edt_as
= &xive
->ipi_as
;
1683 edt_as
= &xive
->end_as
;
1686 xive_error(xive
, "VC: invalid EDT type for write @%"HWADDR_PRIx
,
1691 /* Remap the offset for the targeted address space */
1692 edt_offset
= pnv_xive_edt_offset(xive
, offset
, edt_type
);
1694 address_space_stq(edt_as
, edt_offset
, val
, MEMTXATTRS_UNSPECIFIED
, &result
);
1695 if (result
!= MEMTX_OK
) {
1696 xive_error(xive
, "VC: write failed at @0x%"HWADDR_PRIx
, edt_offset
);
1700 static const MemoryRegionOps pnv_xive_vc_ops
= {
1701 .read
= pnv_xive_vc_read
,
1702 .write
= pnv_xive_vc_write
,
1703 .endianness
= DEVICE_BIG_ENDIAN
,
1705 .min_access_size
= 8,
1706 .max_access_size
= 8,
1709 .min_access_size
= 8,
1710 .max_access_size
= 8,
1715 * Presenter Controller MMIO region. The Virtualization Controller
1716 * updates the IPB in the NVT table when required. Not modeled.
1718 static uint64_t pnv_xive_pc_read(void *opaque
, hwaddr addr
,
1721 PnvXive
*xive
= PNV_XIVE(opaque
);
1723 xive_error(xive
, "PC: invalid read @%"HWADDR_PRIx
, addr
);
1727 static void pnv_xive_pc_write(void *opaque
, hwaddr addr
,
1728 uint64_t value
, unsigned size
)
1730 PnvXive
*xive
= PNV_XIVE(opaque
);
1732 xive_error(xive
, "PC: invalid write to VC @%"HWADDR_PRIx
, addr
);
1735 static const MemoryRegionOps pnv_xive_pc_ops
= {
1736 .read
= pnv_xive_pc_read
,
1737 .write
= pnv_xive_pc_write
,
1738 .endianness
= DEVICE_BIG_ENDIAN
,
1740 .min_access_size
= 8,
1741 .max_access_size
= 8,
1744 .min_access_size
= 8,
1745 .max_access_size
= 8,
1749 static void xive_nvt_pic_print_info(XiveNVT
*nvt
, uint32_t nvt_idx
,
1752 uint8_t eq_blk
= xive_get_field32(NVT_W1_EQ_BLOCK
, nvt
->w1
);
1753 uint32_t eq_idx
= xive_get_field32(NVT_W1_EQ_INDEX
, nvt
->w1
);
1755 if (!xive_nvt_is_valid(nvt
)) {
1759 monitor_printf(mon
, " %08x end:%02x/%04x IPB:%02x\n", nvt_idx
,
1761 xive_get_field32(NVT_W4_IPB
, nvt
->w4
));
1764 void pnv_xive_pic_print_info(PnvXive
*xive
, Monitor
*mon
)
1766 XiveRouter
*xrtr
= XIVE_ROUTER(xive
);
1767 uint8_t blk
= pnv_xive_block_id(xive
);
1768 uint8_t chip_id
= xive
->chip
->chip_id
;
1769 uint32_t srcno0
= XIVE_EAS(blk
, 0);
1770 uint32_t nr_ipis
= pnv_xive_nr_ipis(xive
, blk
);
1775 uint64_t xive_nvt_per_subpage
;
1777 monitor_printf(mon
, "XIVE[%x] #%d Source %08x .. %08x\n", chip_id
, blk
,
1778 srcno0
, srcno0
+ nr_ipis
- 1);
1779 xive_source_pic_print_info(&xive
->ipi_source
, srcno0
, mon
);
1781 monitor_printf(mon
, "XIVE[%x] #%d EAT %08x .. %08x\n", chip_id
, blk
,
1782 srcno0
, srcno0
+ nr_ipis
- 1);
1783 for (i
= 0; i
< nr_ipis
; i
++) {
1784 if (xive_router_get_eas(xrtr
, blk
, i
, &eas
)) {
1787 if (!xive_eas_is_masked(&eas
)) {
1788 xive_eas_pic_print_info(&eas
, i
, mon
);
1792 monitor_printf(mon
, "XIVE[%x] #%d ENDT\n", chip_id
, blk
);
1794 while (!xive_router_get_end(xrtr
, blk
, i
, &end
)) {
1795 xive_end_pic_print_info(&end
, i
++, mon
);
1798 monitor_printf(mon
, "XIVE[%x] #%d END Escalation EAT\n", chip_id
, blk
);
1800 while (!xive_router_get_end(xrtr
, blk
, i
, &end
)) {
1801 xive_end_eas_pic_print_info(&end
, i
++, mon
);
1804 monitor_printf(mon
, "XIVE[%x] #%d NVTT %08x .. %08x\n", chip_id
, blk
,
1805 0, XIVE_NVT_COUNT
- 1);
1806 xive_nvt_per_subpage
= pnv_xive_vst_per_subpage(xive
, VST_TSEL_VPDT
);
1807 for (i
= 0; i
< XIVE_NVT_COUNT
; i
+= xive_nvt_per_subpage
) {
1808 while (!xive_router_get_nvt(xrtr
, blk
, i
, &nvt
)) {
1809 xive_nvt_pic_print_info(&nvt
, i
++, mon
);
1814 static void pnv_xive_reset(void *dev
)
1816 PnvXive
*xive
= PNV_XIVE(dev
);
1817 XiveSource
*xsrc
= &xive
->ipi_source
;
1818 XiveENDSource
*end_xsrc
= &xive
->end_source
;
1820 /* Default page size (Should be changed at runtime to 64k) */
1821 xive
->ic_shift
= xive
->vc_shift
= xive
->pc_shift
= 12;
1823 /* Clear subregions */
1824 if (memory_region_is_mapped(&xsrc
->esb_mmio
)) {
1825 memory_region_del_subregion(&xive
->ipi_edt_mmio
, &xsrc
->esb_mmio
);
1828 if (memory_region_is_mapped(&xive
->ipi_edt_mmio
)) {
1829 memory_region_del_subregion(&xive
->ipi_mmio
, &xive
->ipi_edt_mmio
);
1832 if (memory_region_is_mapped(&end_xsrc
->esb_mmio
)) {
1833 memory_region_del_subregion(&xive
->end_edt_mmio
, &end_xsrc
->esb_mmio
);
1836 if (memory_region_is_mapped(&xive
->end_edt_mmio
)) {
1837 memory_region_del_subregion(&xive
->end_mmio
, &xive
->end_edt_mmio
);
1841 static void pnv_xive_init(Object
*obj
)
1843 PnvXive
*xive
= PNV_XIVE(obj
);
1845 object_initialize_child(obj
, "ipi_source", &xive
->ipi_source
,
1847 object_initialize_child(obj
, "end_source", &xive
->end_source
,
1848 TYPE_XIVE_END_SOURCE
);
1852 * Maximum number of IRQs and ENDs supported by HW
1854 #define PNV_XIVE_NR_IRQS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE))
1855 #define PNV_XIVE_NR_ENDS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE))
1857 static void pnv_xive_realize(DeviceState
*dev
, Error
**errp
)
1859 PnvXive
*xive
= PNV_XIVE(dev
);
1860 PnvXiveClass
*pxc
= PNV_XIVE_GET_CLASS(dev
);
1861 XiveSource
*xsrc
= &xive
->ipi_source
;
1862 XiveENDSource
*end_xsrc
= &xive
->end_source
;
1863 Error
*local_err
= NULL
;
1865 pxc
->parent_realize(dev
, &local_err
);
1867 error_propagate(errp
, local_err
);
1874 * The XiveSource and XiveENDSource objects are realized with the
1875 * maximum allowed HW configuration. The ESB MMIO regions will be
1876 * resized dynamically when the controller is configured by the FW
1877 * to limit accesses to resources not provisioned.
1879 object_property_set_int(OBJECT(xsrc
), "nr-irqs", PNV_XIVE_NR_IRQS
,
1881 object_property_set_link(OBJECT(xsrc
), "xive", OBJECT(xive
), &error_abort
);
1882 if (!qdev_realize(DEVICE(xsrc
), NULL
, errp
)) {
1886 object_property_set_int(OBJECT(end_xsrc
), "nr-ends", PNV_XIVE_NR_ENDS
,
1888 object_property_set_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
1890 if (!qdev_realize(DEVICE(end_xsrc
), NULL
, errp
)) {
1894 /* Default page size. Generally changed at runtime to 64k */
1895 xive
->ic_shift
= xive
->vc_shift
= xive
->pc_shift
= 12;
1897 /* XSCOM region, used for initial configuration of the BARs */
1898 memory_region_init_io(&xive
->xscom_regs
, OBJECT(dev
), &pnv_xive_xscom_ops
,
1899 xive
, "xscom-xive", PNV9_XSCOM_XIVE_SIZE
<< 3);
1901 /* Interrupt controller MMIO regions */
1902 memory_region_init(&xive
->ic_mmio
, OBJECT(dev
), "xive-ic",
1905 memory_region_init_io(&xive
->ic_reg_mmio
, OBJECT(dev
), &pnv_xive_ic_reg_ops
,
1906 xive
, "xive-ic-reg", 1 << xive
->ic_shift
);
1907 memory_region_init_io(&xive
->ic_notify_mmio
, OBJECT(dev
),
1908 &pnv_xive_ic_notify_ops
,
1909 xive
, "xive-ic-notify", 1 << xive
->ic_shift
);
1911 /* The Pervasive LSI trigger and EOI pages (not modeled) */
1912 memory_region_init_io(&xive
->ic_lsi_mmio
, OBJECT(dev
), &pnv_xive_ic_lsi_ops
,
1913 xive
, "xive-ic-lsi", 2 << xive
->ic_shift
);
1915 /* Thread Interrupt Management Area (Indirect) */
1916 memory_region_init_io(&xive
->tm_indirect_mmio
, OBJECT(dev
),
1917 &xive_tm_indirect_ops
,
1918 xive
, "xive-tima-indirect", PNV9_XIVE_TM_SIZE
);
1920 * Overall Virtualization Controller MMIO region containing the
1921 * IPI ESB pages and END ESB pages. The layout is defined by the
1922 * EDT "Domain table" and the accesses are dispatched using
1923 * address spaces for each.
1925 memory_region_init_io(&xive
->vc_mmio
, OBJECT(xive
), &pnv_xive_vc_ops
, xive
,
1926 "xive-vc", PNV9_XIVE_VC_SIZE
);
1928 memory_region_init(&xive
->ipi_mmio
, OBJECT(xive
), "xive-vc-ipi",
1930 address_space_init(&xive
->ipi_as
, &xive
->ipi_mmio
, "xive-vc-ipi");
1931 memory_region_init(&xive
->end_mmio
, OBJECT(xive
), "xive-vc-end",
1933 address_space_init(&xive
->end_as
, &xive
->end_mmio
, "xive-vc-end");
1936 * The MMIO windows exposing the IPI ESBs and the END ESBs in the
1937 * VC region. Their size is configured by the FW in the EDT table.
1939 memory_region_init(&xive
->ipi_edt_mmio
, OBJECT(xive
), "xive-vc-ipi-edt", 0);
1940 memory_region_init(&xive
->end_edt_mmio
, OBJECT(xive
), "xive-vc-end-edt", 0);
1942 /* Presenter Controller MMIO region (not modeled) */
1943 memory_region_init_io(&xive
->pc_mmio
, OBJECT(xive
), &pnv_xive_pc_ops
, xive
,
1944 "xive-pc", PNV9_XIVE_PC_SIZE
);
1946 /* Thread Interrupt Management Area (Direct) */
1947 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &pnv_xive_tm_ops
,
1948 xive
, "xive-tima", PNV9_XIVE_TM_SIZE
);
1950 qemu_register_reset(pnv_xive_reset
, dev
);
1953 static int pnv_xive_dt_xscom(PnvXScomInterface
*dev
, void *fdt
,
1956 const char compat
[] = "ibm,power9-xive-x";
1959 uint32_t lpc_pcba
= PNV9_XSCOM_XIVE_BASE
;
1961 cpu_to_be32(lpc_pcba
),
1962 cpu_to_be32(PNV9_XSCOM_XIVE_SIZE
)
1965 name
= g_strdup_printf("xive@%x", lpc_pcba
);
1966 offset
= fdt_add_subnode(fdt
, xscom_offset
, name
);
1970 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, sizeof(reg
))));
1971 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
,
1976 static Property pnv_xive_properties
[] = {
1977 DEFINE_PROP_UINT64("ic-bar", PnvXive
, ic_base
, 0),
1978 DEFINE_PROP_UINT64("vc-bar", PnvXive
, vc_base
, 0),
1979 DEFINE_PROP_UINT64("pc-bar", PnvXive
, pc_base
, 0),
1980 DEFINE_PROP_UINT64("tm-bar", PnvXive
, tm_base
, 0),
1981 /* The PnvChip id identifies the XIVE interrupt controller. */
1982 DEFINE_PROP_LINK("chip", PnvXive
, chip
, TYPE_PNV_CHIP
, PnvChip
*),
1983 DEFINE_PROP_END_OF_LIST(),
1986 static void pnv_xive_class_init(ObjectClass
*klass
, void *data
)
1988 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1989 PnvXScomInterfaceClass
*xdc
= PNV_XSCOM_INTERFACE_CLASS(klass
);
1990 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
1991 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
1992 XivePresenterClass
*xpc
= XIVE_PRESENTER_CLASS(klass
);
1993 PnvXiveClass
*pxc
= PNV_XIVE_CLASS(klass
);
1995 xdc
->dt_xscom
= pnv_xive_dt_xscom
;
1997 dc
->desc
= "PowerNV XIVE Interrupt Controller";
1998 device_class_set_parent_realize(dc
, pnv_xive_realize
, &pxc
->parent_realize
);
1999 dc
->realize
= pnv_xive_realize
;
2000 device_class_set_props(dc
, pnv_xive_properties
);
2002 xrc
->get_eas
= pnv_xive_get_eas
;
2003 xrc
->get_pq
= pnv_xive_get_pq
;
2004 xrc
->set_pq
= pnv_xive_set_pq
;
2005 xrc
->get_end
= pnv_xive_get_end
;
2006 xrc
->write_end
= pnv_xive_write_end
;
2007 xrc
->get_nvt
= pnv_xive_get_nvt
;
2008 xrc
->write_nvt
= pnv_xive_write_nvt
;
2009 xrc
->get_block_id
= pnv_xive_get_block_id
;
2011 xnc
->notify
= pnv_xive_notify
;
2012 xpc
->match_nvt
= pnv_xive_match_nvt
;
2015 static const TypeInfo pnv_xive_info
= {
2016 .name
= TYPE_PNV_XIVE
,
2017 .parent
= TYPE_XIVE_ROUTER
,
2018 .instance_init
= pnv_xive_init
,
2019 .instance_size
= sizeof(PnvXive
),
2020 .class_init
= pnv_xive_class_init
,
2021 .class_size
= sizeof(PnvXiveClass
),
2022 .interfaces
= (InterfaceInfo
[]) {
2023 { TYPE_PNV_XSCOM_INTERFACE
},
2028 static void pnv_xive_register_types(void)
2030 type_register_static(&pnv_xive_info
);
2033 type_init(pnv_xive_register_types
)