2 * ColdFire UART emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licensed under the GPL
8 #include "qemu/osdep.h"
10 #include "hw/m68k/mcf.h"
11 #include "sysemu/char.h"
12 #include "exec/address-spaces.h"
32 /* UART Status Register bits. */
33 #define MCF_UART_RxRDY 0x01
34 #define MCF_UART_FFULL 0x02
35 #define MCF_UART_TxRDY 0x04
36 #define MCF_UART_TxEMP 0x08
37 #define MCF_UART_OE 0x10
38 #define MCF_UART_PE 0x20
39 #define MCF_UART_FE 0x40
40 #define MCF_UART_RB 0x80
42 /* Interrupt flags. */
43 #define MCF_UART_TxINT 0x01
44 #define MCF_UART_RxINT 0x02
45 #define MCF_UART_DBINT 0x04
46 #define MCF_UART_COSINT 0x80
49 #define MCF_UART_BC0 0x01
50 #define MCF_UART_BC1 0x02
51 #define MCF_UART_PT 0x04
52 #define MCF_UART_PM0 0x08
53 #define MCF_UART_PM1 0x10
54 #define MCF_UART_ERR 0x20
55 #define MCF_UART_RxIRQ 0x40
56 #define MCF_UART_RxRTS 0x80
58 static void mcf_uart_update(mcf_uart_state
*s
)
60 s
->isr
&= ~(MCF_UART_TxINT
| MCF_UART_RxINT
);
61 if (s
->sr
& MCF_UART_TxRDY
)
62 s
->isr
|= MCF_UART_TxINT
;
63 if ((s
->sr
& ((s
->mr
[0] & MCF_UART_RxIRQ
)
64 ? MCF_UART_FFULL
: MCF_UART_RxRDY
)) != 0)
65 s
->isr
|= MCF_UART_RxINT
;
67 qemu_set_irq(s
->irq
, (s
->isr
& s
->imr
) != 0);
70 uint64_t mcf_uart_read(void *opaque
, hwaddr addr
,
73 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
74 switch (addr
& 0x3f) {
76 return s
->mr
[s
->current_mr
];
89 for (i
= 0; i
< s
->fifo_len
; i
++)
90 s
->fifo
[i
] = s
->fifo
[i
+ 1];
91 s
->sr
&= ~MCF_UART_FFULL
;
93 s
->sr
&= ~MCF_UART_RxRDY
;
95 qemu_chr_accept_input(s
->chr
);
99 /* TODO: Implement IPCR. */
112 /* Update TxRDY flag and set data if present and enabled. */
113 static void mcf_uart_do_tx(mcf_uart_state
*s
)
115 if (s
->tx_enabled
&& (s
->sr
& MCF_UART_TxEMP
) == 0) {
117 qemu_chr_fe_write(s
->chr
, (unsigned char *)&s
->tb
, 1);
118 s
->sr
|= MCF_UART_TxEMP
;
121 s
->sr
|= MCF_UART_TxRDY
;
123 s
->sr
&= ~MCF_UART_TxRDY
;
127 static void mcf_do_command(mcf_uart_state
*s
, uint8_t cmd
)
130 switch ((cmd
>> 4) & 7) {
133 case 1: /* Reset mode register pointer. */
136 case 2: /* Reset receiver. */
139 s
->sr
&= ~(MCF_UART_RxRDY
| MCF_UART_FFULL
);
141 case 3: /* Reset transmitter. */
143 s
->sr
|= MCF_UART_TxEMP
;
144 s
->sr
&= ~MCF_UART_TxRDY
;
146 case 4: /* Reset error status. */
148 case 5: /* Reset break-change interrupt. */
149 s
->isr
&= ~MCF_UART_DBINT
;
151 case 6: /* Start break. */
152 case 7: /* Stop break. */
156 /* Transmitter command. */
157 switch ((cmd
>> 2) & 3) {
160 case 1: /* Enable. */
164 case 2: /* Disable. */
168 case 3: /* Reserved. */
169 fprintf(stderr
, "mcf_uart: Bad TX command\n");
173 /* Receiver command. */
177 case 1: /* Enable. */
183 case 3: /* Reserved. */
184 fprintf(stderr
, "mcf_uart: Bad RX command\n");
189 void mcf_uart_write(void *opaque
, hwaddr addr
,
190 uint64_t val
, unsigned size
)
192 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
193 switch (addr
& 0x3f) {
195 s
->mr
[s
->current_mr
] = val
;
199 /* CSR is ignored. */
201 case 0x08: /* Command Register. */
202 mcf_do_command(s
, val
);
204 case 0x0c: /* Transmit Buffer. */
205 s
->sr
&= ~MCF_UART_TxEMP
;
210 /* ACR is ignored. */
221 static void mcf_uart_reset(mcf_uart_state
*s
)
226 s
->sr
= MCF_UART_TxEMP
;
233 static void mcf_uart_push_byte(mcf_uart_state
*s
, uint8_t data
)
235 /* Break events overwrite the last byte if the fifo is full. */
236 if (s
->fifo_len
== 4)
239 s
->fifo
[s
->fifo_len
] = data
;
241 s
->sr
|= MCF_UART_RxRDY
;
242 if (s
->fifo_len
== 4)
243 s
->sr
|= MCF_UART_FFULL
;
248 static void mcf_uart_event(void *opaque
, int event
)
250 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
253 case CHR_EVENT_BREAK
:
254 s
->isr
|= MCF_UART_DBINT
;
255 mcf_uart_push_byte(s
, 0);
262 static int mcf_uart_can_receive(void *opaque
)
264 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
266 return s
->rx_enabled
&& (s
->sr
& MCF_UART_FFULL
) == 0;
269 static void mcf_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
271 mcf_uart_state
*s
= (mcf_uart_state
*)opaque
;
273 mcf_uart_push_byte(s
, buf
[0]);
276 void *mcf_uart_init(qemu_irq irq
, CharDriverState
*chr
)
280 s
= g_malloc0(sizeof(mcf_uart_state
));
284 qemu_chr_fe_claim_no_fail(chr
);
285 qemu_chr_add_handlers(chr
, mcf_uart_can_receive
, mcf_uart_receive
,
292 static const MemoryRegionOps mcf_uart_ops
= {
293 .read
= mcf_uart_read
,
294 .write
= mcf_uart_write
,
295 .endianness
= DEVICE_NATIVE_ENDIAN
,
298 void mcf_uart_mm_init(MemoryRegion
*sysmem
,
301 CharDriverState
*chr
)
305 s
= mcf_uart_init(irq
, chr
);
306 memory_region_init_io(&s
->iomem
, NULL
, &mcf_uart_ops
, s
, "uart", 0x40);
307 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);