2 * Device model for Cadence UART
4 * Copyright (c) 2010 Xilinx Inc.
5 * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
6 * Copyright (c) 2012 PetaLogix Pty Ltd.
7 * Written by Haibing Ma
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "hw/sysbus.h"
21 #include "sysemu/char.h"
22 #include "qemu/timer.h"
24 #include "hw/char/cadence_uart.h"
26 #ifdef CADENCE_UART_ERR_DEBUG
27 #define DB_PRINT(...) do { \
28 fprintf(stderr, ": %s: ", __func__); \
29 fprintf(stderr, ## __VA_ARGS__); \
35 #define UART_SR_INTR_RTRIG 0x00000001
36 #define UART_SR_INTR_REMPTY 0x00000002
37 #define UART_SR_INTR_RFUL 0x00000004
38 #define UART_SR_INTR_TEMPTY 0x00000008
39 #define UART_SR_INTR_TFUL 0x00000010
40 /* somewhat awkwardly, TTRIG is misaligned between SR and ISR */
41 #define UART_SR_TTRIG 0x00002000
42 #define UART_INTR_TTRIG 0x00000400
43 /* bits fields in CSR that correlate to CISR. If any of these bits are set in
44 * SR, then the same bit in CISR is set high too */
45 #define UART_SR_TO_CISR_MASK 0x0000001F
47 #define UART_INTR_ROVR 0x00000020
48 #define UART_INTR_FRAME 0x00000040
49 #define UART_INTR_PARE 0x00000080
50 #define UART_INTR_TIMEOUT 0x00000100
51 #define UART_INTR_DMSI 0x00000200
52 #define UART_INTR_TOVR 0x00001000
54 #define UART_SR_RACTIVE 0x00000400
55 #define UART_SR_TACTIVE 0x00000800
56 #define UART_SR_FDELT 0x00001000
58 #define UART_CR_RXRST 0x00000001
59 #define UART_CR_TXRST 0x00000002
60 #define UART_CR_RX_EN 0x00000004
61 #define UART_CR_RX_DIS 0x00000008
62 #define UART_CR_TX_EN 0x00000010
63 #define UART_CR_TX_DIS 0x00000020
64 #define UART_CR_RST_TO 0x00000040
65 #define UART_CR_STARTBRK 0x00000080
66 #define UART_CR_STOPBRK 0x00000100
68 #define UART_MR_CLKS 0x00000001
69 #define UART_MR_CHRL 0x00000006
70 #define UART_MR_CHRL_SH 1
71 #define UART_MR_PAR 0x00000038
72 #define UART_MR_PAR_SH 3
73 #define UART_MR_NBSTOP 0x000000C0
74 #define UART_MR_NBSTOP_SH 6
75 #define UART_MR_CHMODE 0x00000300
76 #define UART_MR_CHMODE_SH 8
77 #define UART_MR_UCLKEN 0x00000400
78 #define UART_MR_IRMODE 0x00000800
80 #define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
81 #define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
82 #define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
83 #define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
84 #define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
85 #define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
86 #define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
87 #define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
88 #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
89 #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
91 #define UART_INPUT_CLK 50000000
95 #define R_IER (0x08/4)
96 #define R_IDR (0x0C/4)
97 #define R_IMR (0x10/4)
98 #define R_CISR (0x14/4)
99 #define R_BRGR (0x18/4)
100 #define R_RTOR (0x1C/4)
101 #define R_RTRIG (0x20/4)
102 #define R_MCR (0x24/4)
103 #define R_MSR (0x28/4)
104 #define R_SR (0x2C/4)
105 #define R_TX_RX (0x30/4)
106 #define R_BDIV (0x34/4)
107 #define R_FDEL (0x38/4)
108 #define R_PMIN (0x3C/4)
109 #define R_PWID (0x40/4)
110 #define R_TTRIG (0x44/4)
113 static void uart_update_status(CadenceUARTState
*s
)
117 s
->r
[R_SR
] |= s
->rx_count
== CADENCE_UART_RX_FIFO_SIZE
? UART_SR_INTR_RFUL
119 s
->r
[R_SR
] |= !s
->rx_count
? UART_SR_INTR_REMPTY
: 0;
120 s
->r
[R_SR
] |= s
->rx_count
>= s
->r
[R_RTRIG
] ? UART_SR_INTR_RTRIG
: 0;
122 s
->r
[R_SR
] |= s
->tx_count
== CADENCE_UART_TX_FIFO_SIZE
? UART_SR_INTR_TFUL
124 s
->r
[R_SR
] |= !s
->tx_count
? UART_SR_INTR_TEMPTY
: 0;
125 s
->r
[R_SR
] |= s
->tx_count
>= s
->r
[R_TTRIG
] ? UART_SR_TTRIG
: 0;
127 s
->r
[R_CISR
] |= s
->r
[R_SR
] & UART_SR_TO_CISR_MASK
;
128 s
->r
[R_CISR
] |= s
->r
[R_SR
] & UART_SR_TTRIG
? UART_INTR_TTRIG
: 0;
129 qemu_set_irq(s
->irq
, !!(s
->r
[R_IMR
] & s
->r
[R_CISR
]));
132 static void fifo_trigger_update(void *opaque
)
134 CadenceUARTState
*s
= opaque
;
136 s
->r
[R_CISR
] |= UART_INTR_TIMEOUT
;
138 uart_update_status(s
);
141 static void uart_rx_reset(CadenceUARTState
*s
)
146 qemu_chr_accept_input(s
->chr
);
150 static void uart_tx_reset(CadenceUARTState
*s
)
155 static void uart_send_breaks(CadenceUARTState
*s
)
157 int break_enabled
= 1;
160 qemu_chr_fe_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_BREAK
,
165 static void uart_parameters_setup(CadenceUARTState
*s
)
167 QEMUSerialSetParams ssp
;
168 unsigned int baud_rate
, packet_size
;
170 baud_rate
= (s
->r
[R_MR
] & UART_MR_CLKS
) ?
171 UART_INPUT_CLK
/ 8 : UART_INPUT_CLK
;
173 ssp
.speed
= baud_rate
/ (s
->r
[R_BRGR
] * (s
->r
[R_BDIV
] + 1));
176 switch (s
->r
[R_MR
] & UART_MR_PAR
) {
177 case UART_PARITY_EVEN
:
181 case UART_PARITY_ODD
:
190 switch (s
->r
[R_MR
] & UART_MR_CHRL
) {
191 case UART_DATA_BITS_6
:
194 case UART_DATA_BITS_7
:
202 switch (s
->r
[R_MR
] & UART_MR_NBSTOP
) {
203 case UART_STOP_BITS_1
:
211 packet_size
+= ssp
.data_bits
+ ssp
.stop_bits
;
212 s
->char_tx_time
= (NANOSECONDS_PER_SECOND
/ ssp
.speed
) * packet_size
;
214 qemu_chr_fe_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
218 static int uart_can_receive(void *opaque
)
220 CadenceUARTState
*s
= opaque
;
221 int ret
= MAX(CADENCE_UART_RX_FIFO_SIZE
, CADENCE_UART_TX_FIFO_SIZE
);
222 uint32_t ch_mode
= s
->r
[R_MR
] & UART_MR_CHMODE
;
224 if (ch_mode
== NORMAL_MODE
|| ch_mode
== ECHO_MODE
) {
225 ret
= MIN(ret
, CADENCE_UART_RX_FIFO_SIZE
- s
->rx_count
);
227 if (ch_mode
== REMOTE_LOOPBACK
|| ch_mode
== ECHO_MODE
) {
228 ret
= MIN(ret
, CADENCE_UART_TX_FIFO_SIZE
- s
->tx_count
);
233 static void uart_ctrl_update(CadenceUARTState
*s
)
235 if (s
->r
[R_CR
] & UART_CR_TXRST
) {
239 if (s
->r
[R_CR
] & UART_CR_RXRST
) {
243 s
->r
[R_CR
] &= ~(UART_CR_TXRST
| UART_CR_RXRST
);
245 if (s
->r
[R_CR
] & UART_CR_STARTBRK
&& !(s
->r
[R_CR
] & UART_CR_STOPBRK
)) {
250 static void uart_write_rx_fifo(void *opaque
, const uint8_t *buf
, int size
)
252 CadenceUARTState
*s
= opaque
;
253 uint64_t new_rx_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
256 if ((s
->r
[R_CR
] & UART_CR_RX_DIS
) || !(s
->r
[R_CR
] & UART_CR_RX_EN
)) {
260 if (s
->rx_count
== CADENCE_UART_RX_FIFO_SIZE
) {
261 s
->r
[R_CISR
] |= UART_INTR_ROVR
;
263 for (i
= 0; i
< size
; i
++) {
264 s
->rx_fifo
[s
->rx_wpos
] = buf
[i
];
265 s
->rx_wpos
= (s
->rx_wpos
+ 1) % CADENCE_UART_RX_FIFO_SIZE
;
268 timer_mod(s
->fifo_trigger_handle
, new_rx_time
+
269 (s
->char_tx_time
* 4));
271 uart_update_status(s
);
274 static gboolean
cadence_uart_xmit(GIOChannel
*chan
, GIOCondition cond
,
277 CadenceUARTState
*s
= opaque
;
280 /* instant drain the fifo when there's no back-end */
290 ret
= qemu_chr_fe_write(s
->chr
, s
->tx_fifo
, s
->tx_count
);
292 memmove(s
->tx_fifo
, s
->tx_fifo
+ ret
, s
->tx_count
);
295 int r
= qemu_chr_fe_add_watch(s
->chr
, G_IO_OUT
|G_IO_HUP
,
296 cadence_uart_xmit
, s
);
300 uart_update_status(s
);
304 static void uart_write_tx_fifo(CadenceUARTState
*s
, const uint8_t *buf
,
307 if ((s
->r
[R_CR
] & UART_CR_TX_DIS
) || !(s
->r
[R_CR
] & UART_CR_TX_EN
)) {
311 if (size
> CADENCE_UART_TX_FIFO_SIZE
- s
->tx_count
) {
312 size
= CADENCE_UART_TX_FIFO_SIZE
- s
->tx_count
;
314 * This can only be a guest error via a bad tx fifo register push,
315 * as can_receive() should stop remote loop and echo modes ever getting
318 qemu_log_mask(LOG_GUEST_ERROR
, "cadence_uart: TxFIFO overflow");
319 s
->r
[R_CISR
] |= UART_INTR_ROVR
;
322 memcpy(s
->tx_fifo
+ s
->tx_count
, buf
, size
);
325 cadence_uart_xmit(NULL
, G_IO_OUT
, s
);
328 static void uart_receive(void *opaque
, const uint8_t *buf
, int size
)
330 CadenceUARTState
*s
= opaque
;
331 uint32_t ch_mode
= s
->r
[R_MR
] & UART_MR_CHMODE
;
333 if (ch_mode
== NORMAL_MODE
|| ch_mode
== ECHO_MODE
) {
334 uart_write_rx_fifo(opaque
, buf
, size
);
336 if (ch_mode
== REMOTE_LOOPBACK
|| ch_mode
== ECHO_MODE
) {
337 uart_write_tx_fifo(s
, buf
, size
);
341 static void uart_event(void *opaque
, int event
)
343 CadenceUARTState
*s
= opaque
;
346 if (event
== CHR_EVENT_BREAK
) {
347 uart_write_rx_fifo(opaque
, &buf
, 1);
350 uart_update_status(s
);
353 static void uart_read_rx_fifo(CadenceUARTState
*s
, uint32_t *c
)
355 if ((s
->r
[R_CR
] & UART_CR_RX_DIS
) || !(s
->r
[R_CR
] & UART_CR_RX_EN
)) {
360 uint32_t rx_rpos
= (CADENCE_UART_RX_FIFO_SIZE
+ s
->rx_wpos
-
361 s
->rx_count
) % CADENCE_UART_RX_FIFO_SIZE
;
362 *c
= s
->rx_fifo
[rx_rpos
];
366 qemu_chr_accept_input(s
->chr
);
372 uart_update_status(s
);
375 static void uart_write(void *opaque
, hwaddr offset
,
376 uint64_t value
, unsigned size
)
378 CadenceUARTState
*s
= opaque
;
380 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset
, (unsigned)value
);
382 if (offset
>= CADENCE_UART_R_MAX
) {
386 case R_IER
: /* ier (wts imr) */
387 s
->r
[R_IMR
] |= value
;
389 case R_IDR
: /* idr (wtc imr) */
390 s
->r
[R_IMR
] &= ~value
;
392 case R_IMR
: /* imr (read only) */
394 case R_CISR
: /* cisr (wtc) */
395 s
->r
[R_CISR
] &= ~value
;
397 case R_TX_RX
: /* UARTDR */
398 switch (s
->r
[R_MR
] & UART_MR_CHMODE
) {
400 uart_write_tx_fifo(s
, (uint8_t *) &value
, 1);
403 uart_write_rx_fifo(opaque
, (uint8_t *) &value
, 1);
408 s
->r
[offset
] = value
;
416 uart_parameters_setup(s
);
419 uart_update_status(s
);
422 static uint64_t uart_read(void *opaque
, hwaddr offset
,
425 CadenceUARTState
*s
= opaque
;
429 if (offset
>= CADENCE_UART_R_MAX
) {
431 } else if (offset
== R_TX_RX
) {
432 uart_read_rx_fifo(s
, &c
);
437 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset
<< 2), (unsigned)c
);
441 static const MemoryRegionOps uart_ops
= {
444 .endianness
= DEVICE_NATIVE_ENDIAN
,
447 static void cadence_uart_reset(DeviceState
*dev
)
449 CadenceUARTState
*s
= CADENCE_UART(dev
);
451 s
->r
[R_CR
] = 0x00000128;
454 s
->r
[R_RTRIG
] = 0x00000020;
455 s
->r
[R_BRGR
] = 0x0000000F;
456 s
->r
[R_TTRIG
] = 0x00000020;
461 uart_update_status(s
);
464 static void cadence_uart_realize(DeviceState
*dev
, Error
**errp
)
466 CadenceUARTState
*s
= CADENCE_UART(dev
);
468 s
->fifo_trigger_handle
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
469 fifo_trigger_update
, s
);
472 qemu_chr_add_handlers(s
->chr
, uart_can_receive
, uart_receive
,
477 static void cadence_uart_init(Object
*obj
)
479 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
480 CadenceUARTState
*s
= CADENCE_UART(obj
);
482 memory_region_init_io(&s
->iomem
, obj
, &uart_ops
, s
, "uart", 0x1000);
483 sysbus_init_mmio(sbd
, &s
->iomem
);
484 sysbus_init_irq(sbd
, &s
->irq
);
486 s
->char_tx_time
= (NANOSECONDS_PER_SECOND
/ 9600) * 10;
489 static int cadence_uart_post_load(void *opaque
, int version_id
)
491 CadenceUARTState
*s
= opaque
;
493 uart_parameters_setup(s
);
494 uart_update_status(s
);
498 static const VMStateDescription vmstate_cadence_uart
= {
499 .name
= "cadence_uart",
501 .minimum_version_id
= 2,
502 .post_load
= cadence_uart_post_load
,
503 .fields
= (VMStateField
[]) {
504 VMSTATE_UINT32_ARRAY(r
, CadenceUARTState
, CADENCE_UART_R_MAX
),
505 VMSTATE_UINT8_ARRAY(rx_fifo
, CadenceUARTState
,
506 CADENCE_UART_RX_FIFO_SIZE
),
507 VMSTATE_UINT8_ARRAY(tx_fifo
, CadenceUARTState
,
508 CADENCE_UART_TX_FIFO_SIZE
),
509 VMSTATE_UINT32(rx_count
, CadenceUARTState
),
510 VMSTATE_UINT32(tx_count
, CadenceUARTState
),
511 VMSTATE_UINT32(rx_wpos
, CadenceUARTState
),
512 VMSTATE_TIMER_PTR(fifo_trigger_handle
, CadenceUARTState
),
513 VMSTATE_END_OF_LIST()
517 static Property cadence_uart_properties
[] = {
518 DEFINE_PROP_CHR("chardev", CadenceUARTState
, chr
),
519 DEFINE_PROP_END_OF_LIST(),
522 static void cadence_uart_class_init(ObjectClass
*klass
, void *data
)
524 DeviceClass
*dc
= DEVICE_CLASS(klass
);
526 dc
->realize
= cadence_uart_realize
;
527 dc
->vmsd
= &vmstate_cadence_uart
;
528 dc
->reset
= cadence_uart_reset
;
529 dc
->props
= cadence_uart_properties
;
532 static const TypeInfo cadence_uart_info
= {
533 .name
= TYPE_CADENCE_UART
,
534 .parent
= TYPE_SYS_BUS_DEVICE
,
535 .instance_size
= sizeof(CadenceUARTState
),
536 .instance_init
= cadence_uart_init
,
537 .class_init
= cadence_uart_class_init
,
540 static void cadence_uart_register_types(void)
542 type_register_static(&cadence_uart_info
);
545 type_init(cadence_uart_register_types
)