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virtio: combine the read of a descriptor
[qemu.git] / hw / ppc / ppc405_uc.c
blobec81f658c5c4bef1ccb9804c37df05c0ebb7df83
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "hw/ppc/ppc.h"
27 #include "hw/boards.h"
28 #include "ppc405.h"
29 #include "hw/char/serial.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "qemu/log.h"
33 #include "exec/address-spaces.h"
34
35 //#define DEBUG_OPBA
36 //#define DEBUG_SDRAM
37 //#define DEBUG_GPIO
38 //#define DEBUG_SERIAL
39 //#define DEBUG_OCM
40 //#define DEBUG_I2C
41 //#define DEBUG_GPT
42 //#define DEBUG_MAL
43 //#define DEBUG_CLOCKS
44 //#define DEBUG_CLOCKS_LL
45
46 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
47 uint32_t flags)
48 {
49 CPUState *cs = CPU(ppc_env_get_cpu(env));
50 ram_addr_t bdloc;
51 int i, n;
52
53 /* We put the bd structure at the top of memory */
54 if (bd->bi_memsize >= 0x01000000UL)
55 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
56 else
57 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
58 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
59 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
60 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
61 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
62 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
63 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
64 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
65 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
66 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
67 for (i = 0; i < 6; i++) {
68 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
69 }
70 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
71 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
72 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
73 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
74 for (i = 0; i < 4; i++) {
75 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
76 }
77 for (i = 0; i < 32; i++) {
78 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
79 }
80 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
81 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
82 for (i = 0; i < 6; i++) {
83 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
84 }
85 n = 0x6A;
86 if (flags & 0x00000001) {
87 for (i = 0; i < 6; i++)
88 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
89 }
90 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
91 n += 4;
92 for (i = 0; i < 2; i++) {
93 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
94 n += 4;
95 }
96
97 return bdloc;
98 }
99
100 /*****************************************************************************/
101 /* Shared peripherals */
102
103 /*****************************************************************************/
104 /* Peripheral local bus arbitrer */
105 enum {
106 PLB0_BESR = 0x084,
107 PLB0_BEAR = 0x086,
108 PLB0_ACR = 0x087,
109 };
110
111 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
112 struct ppc4xx_plb_t {
113 uint32_t acr;
114 uint32_t bear;
115 uint32_t besr;
116 };
117
118 static uint32_t dcr_read_plb (void *opaque, int dcrn)
119 {
120 ppc4xx_plb_t *plb;
121 uint32_t ret;
122
123 plb = opaque;
124 switch (dcrn) {
125 case PLB0_ACR:
126 ret = plb->acr;
127 break;
128 case PLB0_BEAR:
129 ret = plb->bear;
130 break;
131 case PLB0_BESR:
132 ret = plb->besr;
133 break;
134 default:
135 /* Avoid gcc warning */
136 ret = 0;
137 break;
138 }
139
140 return ret;
141 }
142
143 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
144 {
145 ppc4xx_plb_t *plb;
146
147 plb = opaque;
148 switch (dcrn) {
149 case PLB0_ACR:
150 /* We don't care about the actual parameters written as
151 * we don't manage any priorities on the bus
152 */
153 plb->acr = val & 0xF8000000;
154 break;
155 case PLB0_BEAR:
156 /* Read only */
157 break;
158 case PLB0_BESR:
159 /* Write-clear */
160 plb->besr &= ~val;
161 break;
162 }
163 }
164
165 static void ppc4xx_plb_reset (void *opaque)
166 {
167 ppc4xx_plb_t *plb;
168
169 plb = opaque;
170 plb->acr = 0x00000000;
171 plb->bear = 0x00000000;
172 plb->besr = 0x00000000;
173 }
174
175 static void ppc4xx_plb_init(CPUPPCState *env)
176 {
177 ppc4xx_plb_t *plb;
178
179 plb = g_malloc0(sizeof(ppc4xx_plb_t));
180 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
181 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
182 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
183 qemu_register_reset(ppc4xx_plb_reset, plb);
184 }
185
186 /*****************************************************************************/
187 /* PLB to OPB bridge */
188 enum {
189 POB0_BESR0 = 0x0A0,
190 POB0_BESR1 = 0x0A2,
191 POB0_BEAR = 0x0A4,
192 };
193
194 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
195 struct ppc4xx_pob_t {
196 uint32_t bear;
197 uint32_t besr0;
198 uint32_t besr1;
199 };
200
201 static uint32_t dcr_read_pob (void *opaque, int dcrn)
202 {
203 ppc4xx_pob_t *pob;
204 uint32_t ret;
205
206 pob = opaque;
207 switch (dcrn) {
208 case POB0_BEAR:
209 ret = pob->bear;
210 break;
211 case POB0_BESR0:
212 ret = pob->besr0;
213 break;
214 case POB0_BESR1:
215 ret = pob->besr1;
216 break;
217 default:
218 /* Avoid gcc warning */
219 ret = 0;
220 break;
221 }
222
223 return ret;
224 }
225
226 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
227 {
228 ppc4xx_pob_t *pob;
229
230 pob = opaque;
231 switch (dcrn) {
232 case POB0_BEAR:
233 /* Read only */
234 break;
235 case POB0_BESR0:
236 /* Write-clear */
237 pob->besr0 &= ~val;
238 break;
239 case POB0_BESR1:
240 /* Write-clear */
241 pob->besr1 &= ~val;
242 break;
243 }
244 }
245
246 static void ppc4xx_pob_reset (void *opaque)
247 {
248 ppc4xx_pob_t *pob;
249
250 pob = opaque;
251 /* No error */
252 pob->bear = 0x00000000;
253 pob->besr0 = 0x0000000;
254 pob->besr1 = 0x0000000;
255 }
256
257 static void ppc4xx_pob_init(CPUPPCState *env)
258 {
259 ppc4xx_pob_t *pob;
260
261 pob = g_malloc0(sizeof(ppc4xx_pob_t));
262 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
263 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
264 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
265 qemu_register_reset(ppc4xx_pob_reset, pob);
266 }
267
268 /*****************************************************************************/
269 /* OPB arbitrer */
270 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
271 struct ppc4xx_opba_t {
272 MemoryRegion io;
273 uint8_t cr;
274 uint8_t pr;
275 };
276
277 static uint32_t opba_readb (void *opaque, hwaddr addr)
278 {
279 ppc4xx_opba_t *opba;
280 uint32_t ret;
281
282 #ifdef DEBUG_OPBA
283 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
284 #endif
285 opba = opaque;
286 switch (addr) {
287 case 0x00:
288 ret = opba->cr;
289 break;
290 case 0x01:
291 ret = opba->pr;
292 break;
293 default:
294 ret = 0x00;
295 break;
296 }
297
298 return ret;
299 }
300
301 static void opba_writeb (void *opaque,
302 hwaddr addr, uint32_t value)
303 {
304 ppc4xx_opba_t *opba;
305
306 #ifdef DEBUG_OPBA
307 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
308 value);
309 #endif
310 opba = opaque;
311 switch (addr) {
312 case 0x00:
313 opba->cr = value & 0xF8;
314 break;
315 case 0x01:
316 opba->pr = value & 0xFF;
317 break;
318 default:
319 break;
320 }
321 }
322
323 static uint32_t opba_readw (void *opaque, hwaddr addr)
324 {
325 uint32_t ret;
326
327 #ifdef DEBUG_OPBA
328 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
329 #endif
330 ret = opba_readb(opaque, addr) << 8;
331 ret |= opba_readb(opaque, addr + 1);
332
333 return ret;
334 }
335
336 static void opba_writew (void *opaque,
337 hwaddr addr, uint32_t value)
338 {
339 #ifdef DEBUG_OPBA
340 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
341 value);
342 #endif
343 opba_writeb(opaque, addr, value >> 8);
344 opba_writeb(opaque, addr + 1, value);
345 }
346
347 static uint32_t opba_readl (void *opaque, hwaddr addr)
348 {
349 uint32_t ret;
350
351 #ifdef DEBUG_OPBA
352 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
353 #endif
354 ret = opba_readb(opaque, addr) << 24;
355 ret |= opba_readb(opaque, addr + 1) << 16;
356
357 return ret;
358 }
359
360 static void opba_writel (void *opaque,
361 hwaddr addr, uint32_t value)
362 {
363 #ifdef DEBUG_OPBA
364 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
365 value);
366 #endif
367 opba_writeb(opaque, addr, value >> 24);
368 opba_writeb(opaque, addr + 1, value >> 16);
369 }
370
371 static const MemoryRegionOps opba_ops = {
372 .old_mmio = {
373 .read = { opba_readb, opba_readw, opba_readl, },
374 .write = { opba_writeb, opba_writew, opba_writel, },
375 },
376 .endianness = DEVICE_NATIVE_ENDIAN,
377 };
378
379 static void ppc4xx_opba_reset (void *opaque)
380 {
381 ppc4xx_opba_t *opba;
382
383 opba = opaque;
384 opba->cr = 0x00; /* No dynamic priorities - park disabled */
385 opba->pr = 0x11;
386 }
387
388 static void ppc4xx_opba_init(hwaddr base)
389 {
390 ppc4xx_opba_t *opba;
391
392 opba = g_malloc0(sizeof(ppc4xx_opba_t));
393 #ifdef DEBUG_OPBA
394 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
395 #endif
396 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
397 memory_region_add_subregion(get_system_memory(), base, &opba->io);
398 qemu_register_reset(ppc4xx_opba_reset, opba);
399 }
400
401 /*****************************************************************************/
402 /* Code decompression controller */
403 /* XXX: TODO */
404
405 /*****************************************************************************/
406 /* Peripheral controller */
407 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
408 struct ppc4xx_ebc_t {
409 uint32_t addr;
410 uint32_t bcr[8];
411 uint32_t bap[8];
412 uint32_t bear;
413 uint32_t besr0;
414 uint32_t besr1;
415 uint32_t cfg;
416 };
417
418 enum {
419 EBC0_CFGADDR = 0x012,
420 EBC0_CFGDATA = 0x013,
421 };
422
423 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
424 {
425 ppc4xx_ebc_t *ebc;
426 uint32_t ret;
427
428 ebc = opaque;
429 switch (dcrn) {
430 case EBC0_CFGADDR:
431 ret = ebc->addr;
432 break;
433 case EBC0_CFGDATA:
434 switch (ebc->addr) {
435 case 0x00: /* B0CR */
436 ret = ebc->bcr[0];
437 break;
438 case 0x01: /* B1CR */
439 ret = ebc->bcr[1];
440 break;
441 case 0x02: /* B2CR */
442 ret = ebc->bcr[2];
443 break;
444 case 0x03: /* B3CR */
445 ret = ebc->bcr[3];
446 break;
447 case 0x04: /* B4CR */
448 ret = ebc->bcr[4];
449 break;
450 case 0x05: /* B5CR */
451 ret = ebc->bcr[5];
452 break;
453 case 0x06: /* B6CR */
454 ret = ebc->bcr[6];
455 break;
456 case 0x07: /* B7CR */
457 ret = ebc->bcr[7];
458 break;
459 case 0x10: /* B0AP */
460 ret = ebc->bap[0];
461 break;
462 case 0x11: /* B1AP */
463 ret = ebc->bap[1];
464 break;
465 case 0x12: /* B2AP */
466 ret = ebc->bap[2];
467 break;
468 case 0x13: /* B3AP */
469 ret = ebc->bap[3];
470 break;
471 case 0x14: /* B4AP */
472 ret = ebc->bap[4];
473 break;
474 case 0x15: /* B5AP */
475 ret = ebc->bap[5];
476 break;
477 case 0x16: /* B6AP */
478 ret = ebc->bap[6];
479 break;
480 case 0x17: /* B7AP */
481 ret = ebc->bap[7];
482 break;
483 case 0x20: /* BEAR */
484 ret = ebc->bear;
485 break;
486 case 0x21: /* BESR0 */
487 ret = ebc->besr0;
488 break;
489 case 0x22: /* BESR1 */
490 ret = ebc->besr1;
491 break;
492 case 0x23: /* CFG */
493 ret = ebc->cfg;
494 break;
495 default:
496 ret = 0x00000000;
497 break;
498 }
499 break;
500 default:
501 ret = 0x00000000;
502 break;
503 }
504
505 return ret;
506 }
507
508 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
509 {
510 ppc4xx_ebc_t *ebc;
511
512 ebc = opaque;
513 switch (dcrn) {
514 case EBC0_CFGADDR:
515 ebc->addr = val;
516 break;
517 case EBC0_CFGDATA:
518 switch (ebc->addr) {
519 case 0x00: /* B0CR */
520 break;
521 case 0x01: /* B1CR */
522 break;
523 case 0x02: /* B2CR */
524 break;
525 case 0x03: /* B3CR */
526 break;
527 case 0x04: /* B4CR */
528 break;
529 case 0x05: /* B5CR */
530 break;
531 case 0x06: /* B6CR */
532 break;
533 case 0x07: /* B7CR */
534 break;
535 case 0x10: /* B0AP */
536 break;
537 case 0x11: /* B1AP */
538 break;
539 case 0x12: /* B2AP */
540 break;
541 case 0x13: /* B3AP */
542 break;
543 case 0x14: /* B4AP */
544 break;
545 case 0x15: /* B5AP */
546 break;
547 case 0x16: /* B6AP */
548 break;
549 case 0x17: /* B7AP */
550 break;
551 case 0x20: /* BEAR */
552 break;
553 case 0x21: /* BESR0 */
554 break;
555 case 0x22: /* BESR1 */
556 break;
557 case 0x23: /* CFG */
558 break;
559 default:
560 break;
561 }
562 break;
563 default:
564 break;
565 }
566 }
567
568 static void ebc_reset (void *opaque)
569 {
570 ppc4xx_ebc_t *ebc;
571 int i;
572
573 ebc = opaque;
574 ebc->addr = 0x00000000;
575 ebc->bap[0] = 0x7F8FFE80;
576 ebc->bcr[0] = 0xFFE28000;
577 for (i = 0; i < 8; i++) {
578 ebc->bap[i] = 0x00000000;
579 ebc->bcr[i] = 0x00000000;
580 }
581 ebc->besr0 = 0x00000000;
582 ebc->besr1 = 0x00000000;
583 ebc->cfg = 0x80400000;
584 }
585
586 static void ppc405_ebc_init(CPUPPCState *env)
587 {
588 ppc4xx_ebc_t *ebc;
589
590 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
591 qemu_register_reset(&ebc_reset, ebc);
592 ppc_dcr_register(env, EBC0_CFGADDR,
593 ebc, &dcr_read_ebc, &dcr_write_ebc);
594 ppc_dcr_register(env, EBC0_CFGDATA,
595 ebc, &dcr_read_ebc, &dcr_write_ebc);
596 }
597
598 /*****************************************************************************/
599 /* DMA controller */
600 enum {
601 DMA0_CR0 = 0x100,
602 DMA0_CT0 = 0x101,
603 DMA0_DA0 = 0x102,
604 DMA0_SA0 = 0x103,
605 DMA0_SG0 = 0x104,
606 DMA0_CR1 = 0x108,
607 DMA0_CT1 = 0x109,
608 DMA0_DA1 = 0x10A,
609 DMA0_SA1 = 0x10B,
610 DMA0_SG1 = 0x10C,
611 DMA0_CR2 = 0x110,
612 DMA0_CT2 = 0x111,
613 DMA0_DA2 = 0x112,
614 DMA0_SA2 = 0x113,
615 DMA0_SG2 = 0x114,
616 DMA0_CR3 = 0x118,
617 DMA0_CT3 = 0x119,
618 DMA0_DA3 = 0x11A,
619 DMA0_SA3 = 0x11B,
620 DMA0_SG3 = 0x11C,
621 DMA0_SR = 0x120,
622 DMA0_SGC = 0x123,
623 DMA0_SLP = 0x125,
624 DMA0_POL = 0x126,
625 };
626
627 typedef struct ppc405_dma_t ppc405_dma_t;
628 struct ppc405_dma_t {
629 qemu_irq irqs[4];
630 uint32_t cr[4];
631 uint32_t ct[4];
632 uint32_t da[4];
633 uint32_t sa[4];
634 uint32_t sg[4];
635 uint32_t sr;
636 uint32_t sgc;
637 uint32_t slp;
638 uint32_t pol;
639 };
640
641 static uint32_t dcr_read_dma (void *opaque, int dcrn)
642 {
643 return 0;
644 }
645
646 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
647 {
648 }
649
650 static void ppc405_dma_reset (void *opaque)
651 {
652 ppc405_dma_t *dma;
653 int i;
654
655 dma = opaque;
656 for (i = 0; i < 4; i++) {
657 dma->cr[i] = 0x00000000;
658 dma->ct[i] = 0x00000000;
659 dma->da[i] = 0x00000000;
660 dma->sa[i] = 0x00000000;
661 dma->sg[i] = 0x00000000;
662 }
663 dma->sr = 0x00000000;
664 dma->sgc = 0x00000000;
665 dma->slp = 0x7C000000;
666 dma->pol = 0x00000000;
667 }
668
669 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
670 {
671 ppc405_dma_t *dma;
672
673 dma = g_malloc0(sizeof(ppc405_dma_t));
674 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
675 qemu_register_reset(&ppc405_dma_reset, dma);
676 ppc_dcr_register(env, DMA0_CR0,
677 dma, &dcr_read_dma, &dcr_write_dma);
678 ppc_dcr_register(env, DMA0_CT0,
679 dma, &dcr_read_dma, &dcr_write_dma);
680 ppc_dcr_register(env, DMA0_DA0,
681 dma, &dcr_read_dma, &dcr_write_dma);
682 ppc_dcr_register(env, DMA0_SA0,
683 dma, &dcr_read_dma, &dcr_write_dma);
684 ppc_dcr_register(env, DMA0_SG0,
685 dma, &dcr_read_dma, &dcr_write_dma);
686 ppc_dcr_register(env, DMA0_CR1,
687 dma, &dcr_read_dma, &dcr_write_dma);
688 ppc_dcr_register(env, DMA0_CT1,
689 dma, &dcr_read_dma, &dcr_write_dma);
690 ppc_dcr_register(env, DMA0_DA1,
691 dma, &dcr_read_dma, &dcr_write_dma);
692 ppc_dcr_register(env, DMA0_SA1,
693 dma, &dcr_read_dma, &dcr_write_dma);
694 ppc_dcr_register(env, DMA0_SG1,
695 dma, &dcr_read_dma, &dcr_write_dma);
696 ppc_dcr_register(env, DMA0_CR2,
697 dma, &dcr_read_dma, &dcr_write_dma);
698 ppc_dcr_register(env, DMA0_CT2,
699 dma, &dcr_read_dma, &dcr_write_dma);
700 ppc_dcr_register(env, DMA0_DA2,
701 dma, &dcr_read_dma, &dcr_write_dma);
702 ppc_dcr_register(env, DMA0_SA2,
703 dma, &dcr_read_dma, &dcr_write_dma);
704 ppc_dcr_register(env, DMA0_SG2,
705 dma, &dcr_read_dma, &dcr_write_dma);
706 ppc_dcr_register(env, DMA0_CR3,
707 dma, &dcr_read_dma, &dcr_write_dma);
708 ppc_dcr_register(env, DMA0_CT3,
709 dma, &dcr_read_dma, &dcr_write_dma);
710 ppc_dcr_register(env, DMA0_DA3,
711 dma, &dcr_read_dma, &dcr_write_dma);
712 ppc_dcr_register(env, DMA0_SA3,
713 dma, &dcr_read_dma, &dcr_write_dma);
714 ppc_dcr_register(env, DMA0_SG3,
715 dma, &dcr_read_dma, &dcr_write_dma);
716 ppc_dcr_register(env, DMA0_SR,
717 dma, &dcr_read_dma, &dcr_write_dma);
718 ppc_dcr_register(env, DMA0_SGC,
719 dma, &dcr_read_dma, &dcr_write_dma);
720 ppc_dcr_register(env, DMA0_SLP,
721 dma, &dcr_read_dma, &dcr_write_dma);
722 ppc_dcr_register(env, DMA0_POL,
723 dma, &dcr_read_dma, &dcr_write_dma);
724 }
725
726 /*****************************************************************************/
727 /* GPIO */
728 typedef struct ppc405_gpio_t ppc405_gpio_t;
729 struct ppc405_gpio_t {
730 MemoryRegion io;
731 uint32_t or;
732 uint32_t tcr;
733 uint32_t osrh;
734 uint32_t osrl;
735 uint32_t tsrh;
736 uint32_t tsrl;
737 uint32_t odr;
738 uint32_t ir;
739 uint32_t rr1;
740 uint32_t isr1h;
741 uint32_t isr1l;
742 };
743
744 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
745 {
746 #ifdef DEBUG_GPIO
747 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
748 #endif
749
750 return 0;
751 }
752
753 static void ppc405_gpio_writeb (void *opaque,
754 hwaddr addr, uint32_t value)
755 {
756 #ifdef DEBUG_GPIO
757 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
758 value);
759 #endif
760 }
761
762 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
763 {
764 #ifdef DEBUG_GPIO
765 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
766 #endif
767
768 return 0;
769 }
770
771 static void ppc405_gpio_writew (void *opaque,
772 hwaddr addr, uint32_t value)
773 {
774 #ifdef DEBUG_GPIO
775 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
776 value);
777 #endif
778 }
779
780 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
781 {
782 #ifdef DEBUG_GPIO
783 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
784 #endif
785
786 return 0;
787 }
788
789 static void ppc405_gpio_writel (void *opaque,
790 hwaddr addr, uint32_t value)
791 {
792 #ifdef DEBUG_GPIO
793 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
794 value);
795 #endif
796 }
797
798 static const MemoryRegionOps ppc405_gpio_ops = {
799 .old_mmio = {
800 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
801 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
802 },
803 .endianness = DEVICE_NATIVE_ENDIAN,
804 };
805
806 static void ppc405_gpio_reset (void *opaque)
807 {
808 }
809
810 static void ppc405_gpio_init(hwaddr base)
811 {
812 ppc405_gpio_t *gpio;
813
814 gpio = g_malloc0(sizeof(ppc405_gpio_t));
815 #ifdef DEBUG_GPIO
816 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
817 #endif
818 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
819 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
820 qemu_register_reset(&ppc405_gpio_reset, gpio);
821 }
822
823 /*****************************************************************************/
824 /* On Chip Memory */
825 enum {
826 OCM0_ISARC = 0x018,
827 OCM0_ISACNTL = 0x019,
828 OCM0_DSARC = 0x01A,
829 OCM0_DSACNTL = 0x01B,
830 };
831
832 typedef struct ppc405_ocm_t ppc405_ocm_t;
833 struct ppc405_ocm_t {
834 MemoryRegion ram;
835 MemoryRegion isarc_ram;
836 MemoryRegion dsarc_ram;
837 uint32_t isarc;
838 uint32_t isacntl;
839 uint32_t dsarc;
840 uint32_t dsacntl;
841 };
842
843 static void ocm_update_mappings (ppc405_ocm_t *ocm,
844 uint32_t isarc, uint32_t isacntl,
845 uint32_t dsarc, uint32_t dsacntl)
846 {
847 #ifdef DEBUG_OCM
848 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
849 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
850 " (%08" PRIx32 " %08" PRIx32 ")\n",
851 isarc, isacntl, dsarc, dsacntl,
852 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
853 #endif
854 if (ocm->isarc != isarc ||
855 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
856 if (ocm->isacntl & 0x80000000) {
857 /* Unmap previously assigned memory region */
858 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
859 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
860 }
861 if (isacntl & 0x80000000) {
862 /* Map new instruction memory region */
863 #ifdef DEBUG_OCM
864 printf("OCM map ISA %08" PRIx32 "\n", isarc);
865 #endif
866 memory_region_add_subregion(get_system_memory(), isarc,
867 &ocm->isarc_ram);
868 }
869 }
870 if (ocm->dsarc != dsarc ||
871 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
872 if (ocm->dsacntl & 0x80000000) {
873 /* Beware not to unmap the region we just mapped */
874 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
875 /* Unmap previously assigned memory region */
876 #ifdef DEBUG_OCM
877 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
878 #endif
879 memory_region_del_subregion(get_system_memory(),
880 &ocm->dsarc_ram);
881 }
882 }
883 if (dsacntl & 0x80000000) {
884 /* Beware not to remap the region we just mapped */
885 if (!(isacntl & 0x80000000) || dsarc != isarc) {
886 /* Map new data memory region */
887 #ifdef DEBUG_OCM
888 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
889 #endif
890 memory_region_add_subregion(get_system_memory(), dsarc,
891 &ocm->dsarc_ram);
892 }
893 }
894 }
895 }
896
897 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
898 {
899 ppc405_ocm_t *ocm;
900 uint32_t ret;
901
902 ocm = opaque;
903 switch (dcrn) {
904 case OCM0_ISARC:
905 ret = ocm->isarc;
906 break;
907 case OCM0_ISACNTL:
908 ret = ocm->isacntl;
909 break;
910 case OCM0_DSARC:
911 ret = ocm->dsarc;
912 break;
913 case OCM0_DSACNTL:
914 ret = ocm->dsacntl;
915 break;
916 default:
917 ret = 0;
918 break;
919 }
920
921 return ret;
922 }
923
924 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
925 {
926 ppc405_ocm_t *ocm;
927 uint32_t isarc, dsarc, isacntl, dsacntl;
928
929 ocm = opaque;
930 isarc = ocm->isarc;
931 dsarc = ocm->dsarc;
932 isacntl = ocm->isacntl;
933 dsacntl = ocm->dsacntl;
934 switch (dcrn) {
935 case OCM0_ISARC:
936 isarc = val & 0xFC000000;
937 break;
938 case OCM0_ISACNTL:
939 isacntl = val & 0xC0000000;
940 break;
941 case OCM0_DSARC:
942 isarc = val & 0xFC000000;
943 break;
944 case OCM0_DSACNTL:
945 isacntl = val & 0xC0000000;
946 break;
947 }
948 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
949 ocm->isarc = isarc;
950 ocm->dsarc = dsarc;
951 ocm->isacntl = isacntl;
952 ocm->dsacntl = dsacntl;
953 }
954
955 static void ocm_reset (void *opaque)
956 {
957 ppc405_ocm_t *ocm;
958 uint32_t isarc, dsarc, isacntl, dsacntl;
959
960 ocm = opaque;
961 isarc = 0x00000000;
962 isacntl = 0x00000000;
963 dsarc = 0x00000000;
964 dsacntl = 0x00000000;
965 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
966 ocm->isarc = isarc;
967 ocm->dsarc = dsarc;
968 ocm->isacntl = isacntl;
969 ocm->dsacntl = dsacntl;
970 }
971
972 static void ppc405_ocm_init(CPUPPCState *env)
973 {
974 ppc405_ocm_t *ocm;
975
976 ocm = g_malloc0(sizeof(ppc405_ocm_t));
977 /* XXX: Size is 4096 or 0x04000000 */
978 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096,
979 &error_fatal);
980 vmstate_register_ram_global(&ocm->isarc_ram);
981 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram,
982 0, 4096);
983 qemu_register_reset(&ocm_reset, ocm);
984 ppc_dcr_register(env, OCM0_ISARC,
985 ocm, &dcr_read_ocm, &dcr_write_ocm);
986 ppc_dcr_register(env, OCM0_ISACNTL,
987 ocm, &dcr_read_ocm, &dcr_write_ocm);
988 ppc_dcr_register(env, OCM0_DSARC,
989 ocm, &dcr_read_ocm, &dcr_write_ocm);
990 ppc_dcr_register(env, OCM0_DSACNTL,
991 ocm, &dcr_read_ocm, &dcr_write_ocm);
992 }
993
994 /*****************************************************************************/
995 /* I2C controller */
996 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
997 struct ppc4xx_i2c_t {
998 qemu_irq irq;
999 MemoryRegion iomem;
1000 uint8_t mdata;
1001 uint8_t lmadr;
1002 uint8_t hmadr;
1003 uint8_t cntl;
1004 uint8_t mdcntl;
1005 uint8_t sts;
1006 uint8_t extsts;
1007 uint8_t sdata;
1008 uint8_t lsadr;
1009 uint8_t hsadr;
1010 uint8_t clkdiv;
1011 uint8_t intrmsk;
1012 uint8_t xfrcnt;
1013 uint8_t xtcntlss;
1014 uint8_t directcntl;
1015 };
1016
1017 static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
1018 {
1019 ppc4xx_i2c_t *i2c;
1020 uint32_t ret;
1021
1022 #ifdef DEBUG_I2C
1023 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1024 #endif
1025 i2c = opaque;
1026 switch (addr) {
1027 case 0x00:
1028 // i2c_readbyte(&i2c->mdata);
1029 ret = i2c->mdata;
1030 break;
1031 case 0x02:
1032 ret = i2c->sdata;
1033 break;
1034 case 0x04:
1035 ret = i2c->lmadr;
1036 break;
1037 case 0x05:
1038 ret = i2c->hmadr;
1039 break;
1040 case 0x06:
1041 ret = i2c->cntl;
1042 break;
1043 case 0x07:
1044 ret = i2c->mdcntl;
1045 break;
1046 case 0x08:
1047 ret = i2c->sts;
1048 break;
1049 case 0x09:
1050 ret = i2c->extsts;
1051 break;
1052 case 0x0A:
1053 ret = i2c->lsadr;
1054 break;
1055 case 0x0B:
1056 ret = i2c->hsadr;
1057 break;
1058 case 0x0C:
1059 ret = i2c->clkdiv;
1060 break;
1061 case 0x0D:
1062 ret = i2c->intrmsk;
1063 break;
1064 case 0x0E:
1065 ret = i2c->xfrcnt;
1066 break;
1067 case 0x0F:
1068 ret = i2c->xtcntlss;
1069 break;
1070 case 0x10:
1071 ret = i2c->directcntl;
1072 break;
1073 default:
1074 ret = 0x00;
1075 break;
1076 }
1077 #ifdef DEBUG_I2C
1078 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1079 #endif
1080
1081 return ret;
1082 }
1083
1084 static void ppc4xx_i2c_writeb (void *opaque,
1085 hwaddr addr, uint32_t value)
1086 {
1087 ppc4xx_i2c_t *i2c;
1088
1089 #ifdef DEBUG_I2C
1090 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1091 value);
1092 #endif
1093 i2c = opaque;
1094 switch (addr) {
1095 case 0x00:
1096 i2c->mdata = value;
1097 // i2c_sendbyte(&i2c->mdata);
1098 break;
1099 case 0x02:
1100 i2c->sdata = value;
1101 break;
1102 case 0x04:
1103 i2c->lmadr = value;
1104 break;
1105 case 0x05:
1106 i2c->hmadr = value;
1107 break;
1108 case 0x06:
1109 i2c->cntl = value;
1110 break;
1111 case 0x07:
1112 i2c->mdcntl = value & 0xDF;
1113 break;
1114 case 0x08:
1115 i2c->sts &= ~(value & 0x0A);
1116 break;
1117 case 0x09:
1118 i2c->extsts &= ~(value & 0x8F);
1119 break;
1120 case 0x0A:
1121 i2c->lsadr = value;
1122 break;
1123 case 0x0B:
1124 i2c->hsadr = value;
1125 break;
1126 case 0x0C:
1127 i2c->clkdiv = value;
1128 break;
1129 case 0x0D:
1130 i2c->intrmsk = value;
1131 break;
1132 case 0x0E:
1133 i2c->xfrcnt = value & 0x77;
1134 break;
1135 case 0x0F:
1136 i2c->xtcntlss = value;
1137 break;
1138 case 0x10:
1139 i2c->directcntl = value & 0x7;
1140 break;
1141 }
1142 }
1143
1144 static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
1145 {
1146 uint32_t ret;
1147
1148 #ifdef DEBUG_I2C
1149 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1150 #endif
1151 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1152 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1153
1154 return ret;
1155 }
1156
1157 static void ppc4xx_i2c_writew (void *opaque,
1158 hwaddr addr, uint32_t value)
1159 {
1160 #ifdef DEBUG_I2C
1161 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1162 value);
1163 #endif
1164 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1165 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1166 }
1167
1168 static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
1169 {
1170 uint32_t ret;
1171
1172 #ifdef DEBUG_I2C
1173 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1174 #endif
1175 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1176 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1177 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1178 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1179
1180 return ret;
1181 }
1182
1183 static void ppc4xx_i2c_writel (void *opaque,
1184 hwaddr addr, uint32_t value)
1185 {
1186 #ifdef DEBUG_I2C
1187 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1188 value);
1189 #endif
1190 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1191 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1192 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1193 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1194 }
1195
1196 static const MemoryRegionOps i2c_ops = {
1197 .old_mmio = {
1198 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
1199 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
1200 },
1201 .endianness = DEVICE_NATIVE_ENDIAN,
1202 };
1203
1204 static void ppc4xx_i2c_reset (void *opaque)
1205 {
1206 ppc4xx_i2c_t *i2c;
1207
1208 i2c = opaque;
1209 i2c->mdata = 0x00;
1210 i2c->sdata = 0x00;
1211 i2c->cntl = 0x00;
1212 i2c->mdcntl = 0x00;
1213 i2c->sts = 0x00;
1214 i2c->extsts = 0x00;
1215 i2c->clkdiv = 0x00;
1216 i2c->xfrcnt = 0x00;
1217 i2c->directcntl = 0x0F;
1218 }
1219
1220 static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
1221 {
1222 ppc4xx_i2c_t *i2c;
1223
1224 i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
1225 i2c->irq = irq;
1226 #ifdef DEBUG_I2C
1227 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1228 #endif
1229 memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011);
1230 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
1231 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1232 }
1233
1234 /*****************************************************************************/
1235 /* General purpose timers */
1236 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1237 struct ppc4xx_gpt_t {
1238 MemoryRegion iomem;
1239 int64_t tb_offset;
1240 uint32_t tb_freq;
1241 QEMUTimer *timer;
1242 qemu_irq irqs[5];
1243 uint32_t oe;
1244 uint32_t ol;
1245 uint32_t im;
1246 uint32_t is;
1247 uint32_t ie;
1248 uint32_t comp[5];
1249 uint32_t mask[5];
1250 };
1251
1252 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
1253 {
1254 #ifdef DEBUG_GPT
1255 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1256 #endif
1257 /* XXX: generate a bus fault */
1258 return -1;
1259 }
1260
1261 static void ppc4xx_gpt_writeb (void *opaque,
1262 hwaddr addr, uint32_t value)
1263 {
1264 #ifdef DEBUG_I2C
1265 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1266 value);
1267 #endif
1268 /* XXX: generate a bus fault */
1269 }
1270
1271 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
1272 {
1273 #ifdef DEBUG_GPT
1274 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1275 #endif
1276 /* XXX: generate a bus fault */
1277 return -1;
1278 }
1279
1280 static void ppc4xx_gpt_writew (void *opaque,
1281 hwaddr addr, uint32_t value)
1282 {
1283 #ifdef DEBUG_I2C
1284 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1285 value);
1286 #endif
1287 /* XXX: generate a bus fault */
1288 }
1289
1290 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1291 {
1292 /* XXX: TODO */
1293 return 0;
1294 }
1295
1296 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1297 {
1298 /* XXX: TODO */
1299 }
1300
1301 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1302 {
1303 uint32_t mask;
1304 int i;
1305
1306 mask = 0x80000000;
1307 for (i = 0; i < 5; i++) {
1308 if (gpt->oe & mask) {
1309 /* Output is enabled */
1310 if (ppc4xx_gpt_compare(gpt, i)) {
1311 /* Comparison is OK */
1312 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1313 } else {
1314 /* Comparison is KO */
1315 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1316 }
1317 }
1318 mask = mask >> 1;
1319 }
1320 }
1321
1322 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1323 {
1324 uint32_t mask;
1325 int i;
1326
1327 mask = 0x00008000;
1328 for (i = 0; i < 5; i++) {
1329 if (gpt->is & gpt->im & mask)
1330 qemu_irq_raise(gpt->irqs[i]);
1331 else
1332 qemu_irq_lower(gpt->irqs[i]);
1333 mask = mask >> 1;
1334 }
1335 }
1336
1337 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1338 {
1339 /* XXX: TODO */
1340 }
1341
1342 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
1343 {
1344 ppc4xx_gpt_t *gpt;
1345 uint32_t ret;
1346 int idx;
1347
1348 #ifdef DEBUG_GPT
1349 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1350 #endif
1351 gpt = opaque;
1352 switch (addr) {
1353 case 0x00:
1354 /* Time base counter */
1355 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
1356 gpt->tb_freq, get_ticks_per_sec());
1357 break;
1358 case 0x10:
1359 /* Output enable */
1360 ret = gpt->oe;
1361 break;
1362 case 0x14:
1363 /* Output level */
1364 ret = gpt->ol;
1365 break;
1366 case 0x18:
1367 /* Interrupt mask */
1368 ret = gpt->im;
1369 break;
1370 case 0x1C:
1371 case 0x20:
1372 /* Interrupt status */
1373 ret = gpt->is;
1374 break;
1375 case 0x24:
1376 /* Interrupt enable */
1377 ret = gpt->ie;
1378 break;
1379 case 0x80 ... 0x90:
1380 /* Compare timer */
1381 idx = (addr - 0x80) >> 2;
1382 ret = gpt->comp[idx];
1383 break;
1384 case 0xC0 ... 0xD0:
1385 /* Compare mask */
1386 idx = (addr - 0xC0) >> 2;
1387 ret = gpt->mask[idx];
1388 break;
1389 default:
1390 ret = -1;
1391 break;
1392 }
1393
1394 return ret;
1395 }
1396
1397 static void ppc4xx_gpt_writel (void *opaque,
1398 hwaddr addr, uint32_t value)
1399 {
1400 ppc4xx_gpt_t *gpt;
1401 int idx;
1402
1403 #ifdef DEBUG_I2C
1404 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1405 value);
1406 #endif
1407 gpt = opaque;
1408 switch (addr) {
1409 case 0x00:
1410 /* Time base counter */
1411 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1412 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1413 ppc4xx_gpt_compute_timer(gpt);
1414 break;
1415 case 0x10:
1416 /* Output enable */
1417 gpt->oe = value & 0xF8000000;
1418 ppc4xx_gpt_set_outputs(gpt);
1419 break;
1420 case 0x14:
1421 /* Output level */
1422 gpt->ol = value & 0xF8000000;
1423 ppc4xx_gpt_set_outputs(gpt);
1424 break;
1425 case 0x18:
1426 /* Interrupt mask */
1427 gpt->im = value & 0x0000F800;
1428 break;
1429 case 0x1C:
1430 /* Interrupt status set */
1431 gpt->is |= value & 0x0000F800;
1432 ppc4xx_gpt_set_irqs(gpt);
1433 break;
1434 case 0x20:
1435 /* Interrupt status clear */
1436 gpt->is &= ~(value & 0x0000F800);
1437 ppc4xx_gpt_set_irqs(gpt);
1438 break;
1439 case 0x24:
1440 /* Interrupt enable */
1441 gpt->ie = value & 0x0000F800;
1442 ppc4xx_gpt_set_irqs(gpt);
1443 break;
1444 case 0x80 ... 0x90:
1445 /* Compare timer */
1446 idx = (addr - 0x80) >> 2;
1447 gpt->comp[idx] = value & 0xF8000000;
1448 ppc4xx_gpt_compute_timer(gpt);
1449 break;
1450 case 0xC0 ... 0xD0:
1451 /* Compare mask */
1452 idx = (addr - 0xC0) >> 2;
1453 gpt->mask[idx] = value & 0xF8000000;
1454 ppc4xx_gpt_compute_timer(gpt);
1455 break;
1456 }
1457 }
1458
1459 static const MemoryRegionOps gpt_ops = {
1460 .old_mmio = {
1461 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1462 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1463 },
1464 .endianness = DEVICE_NATIVE_ENDIAN,
1465 };
1466
1467 static void ppc4xx_gpt_cb (void *opaque)
1468 {
1469 ppc4xx_gpt_t *gpt;
1470
1471 gpt = opaque;
1472 ppc4xx_gpt_set_irqs(gpt);
1473 ppc4xx_gpt_set_outputs(gpt);
1474 ppc4xx_gpt_compute_timer(gpt);
1475 }
1476
1477 static void ppc4xx_gpt_reset (void *opaque)
1478 {
1479 ppc4xx_gpt_t *gpt;
1480 int i;
1481
1482 gpt = opaque;
1483 timer_del(gpt->timer);
1484 gpt->oe = 0x00000000;
1485 gpt->ol = 0x00000000;
1486 gpt->im = 0x00000000;
1487 gpt->is = 0x00000000;
1488 gpt->ie = 0x00000000;
1489 for (i = 0; i < 5; i++) {
1490 gpt->comp[i] = 0x00000000;
1491 gpt->mask[i] = 0x00000000;
1492 }
1493 }
1494
1495 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1496 {
1497 ppc4xx_gpt_t *gpt;
1498 int i;
1499
1500 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1501 for (i = 0; i < 5; i++) {
1502 gpt->irqs[i] = irqs[i];
1503 }
1504 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
1505 #ifdef DEBUG_GPT
1506 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1507 #endif
1508 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
1509 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1510 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1511 }
1512
1513 /*****************************************************************************/
1514 /* MAL */
1515 enum {
1516 MAL0_CFG = 0x180,
1517 MAL0_ESR = 0x181,
1518 MAL0_IER = 0x182,
1519 MAL0_TXCASR = 0x184,
1520 MAL0_TXCARR = 0x185,
1521 MAL0_TXEOBISR = 0x186,
1522 MAL0_TXDEIR = 0x187,
1523 MAL0_RXCASR = 0x190,
1524 MAL0_RXCARR = 0x191,
1525 MAL0_RXEOBISR = 0x192,
1526 MAL0_RXDEIR = 0x193,
1527 MAL0_TXCTP0R = 0x1A0,
1528 MAL0_TXCTP1R = 0x1A1,
1529 MAL0_TXCTP2R = 0x1A2,
1530 MAL0_TXCTP3R = 0x1A3,
1531 MAL0_RXCTP0R = 0x1C0,
1532 MAL0_RXCTP1R = 0x1C1,
1533 MAL0_RCBS0 = 0x1E0,
1534 MAL0_RCBS1 = 0x1E1,
1535 };
1536
1537 typedef struct ppc40x_mal_t ppc40x_mal_t;
1538 struct ppc40x_mal_t {
1539 qemu_irq irqs[4];
1540 uint32_t cfg;
1541 uint32_t esr;
1542 uint32_t ier;
1543 uint32_t txcasr;
1544 uint32_t txcarr;
1545 uint32_t txeobisr;
1546 uint32_t txdeir;
1547 uint32_t rxcasr;
1548 uint32_t rxcarr;
1549 uint32_t rxeobisr;
1550 uint32_t rxdeir;
1551 uint32_t txctpr[4];
1552 uint32_t rxctpr[2];
1553 uint32_t rcbs[2];
1554 };
1555
1556 static void ppc40x_mal_reset (void *opaque);
1557
1558 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1559 {
1560 ppc40x_mal_t *mal;
1561 uint32_t ret;
1562
1563 mal = opaque;
1564 switch (dcrn) {
1565 case MAL0_CFG:
1566 ret = mal->cfg;
1567 break;
1568 case MAL0_ESR:
1569 ret = mal->esr;
1570 break;
1571 case MAL0_IER:
1572 ret = mal->ier;
1573 break;
1574 case MAL0_TXCASR:
1575 ret = mal->txcasr;
1576 break;
1577 case MAL0_TXCARR:
1578 ret = mal->txcarr;
1579 break;
1580 case MAL0_TXEOBISR:
1581 ret = mal->txeobisr;
1582 break;
1583 case MAL0_TXDEIR:
1584 ret = mal->txdeir;
1585 break;
1586 case MAL0_RXCASR:
1587 ret = mal->rxcasr;
1588 break;
1589 case MAL0_RXCARR:
1590 ret = mal->rxcarr;
1591 break;
1592 case MAL0_RXEOBISR:
1593 ret = mal->rxeobisr;
1594 break;
1595 case MAL0_RXDEIR:
1596 ret = mal->rxdeir;
1597 break;
1598 case MAL0_TXCTP0R:
1599 ret = mal->txctpr[0];
1600 break;
1601 case MAL0_TXCTP1R:
1602 ret = mal->txctpr[1];
1603 break;
1604 case MAL0_TXCTP2R:
1605 ret = mal->txctpr[2];
1606 break;
1607 case MAL0_TXCTP3R:
1608 ret = mal->txctpr[3];
1609 break;
1610 case MAL0_RXCTP0R:
1611 ret = mal->rxctpr[0];
1612 break;
1613 case MAL0_RXCTP1R:
1614 ret = mal->rxctpr[1];
1615 break;
1616 case MAL0_RCBS0:
1617 ret = mal->rcbs[0];
1618 break;
1619 case MAL0_RCBS1:
1620 ret = mal->rcbs[1];
1621 break;
1622 default:
1623 ret = 0;
1624 break;
1625 }
1626
1627 return ret;
1628 }
1629
1630 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1631 {
1632 ppc40x_mal_t *mal;
1633 int idx;
1634
1635 mal = opaque;
1636 switch (dcrn) {
1637 case MAL0_CFG:
1638 if (val & 0x80000000)
1639 ppc40x_mal_reset(mal);
1640 mal->cfg = val & 0x00FFC087;
1641 break;
1642 case MAL0_ESR:
1643 /* Read/clear */
1644 mal->esr &= ~val;
1645 break;
1646 case MAL0_IER:
1647 mal->ier = val & 0x0000001F;
1648 break;
1649 case MAL0_TXCASR:
1650 mal->txcasr = val & 0xF0000000;
1651 break;
1652 case MAL0_TXCARR:
1653 mal->txcarr = val & 0xF0000000;
1654 break;
1655 case MAL0_TXEOBISR:
1656 /* Read/clear */
1657 mal->txeobisr &= ~val;
1658 break;
1659 case MAL0_TXDEIR:
1660 /* Read/clear */
1661 mal->txdeir &= ~val;
1662 break;
1663 case MAL0_RXCASR:
1664 mal->rxcasr = val & 0xC0000000;
1665 break;
1666 case MAL0_RXCARR:
1667 mal->rxcarr = val & 0xC0000000;
1668 break;
1669 case MAL0_RXEOBISR:
1670 /* Read/clear */
1671 mal->rxeobisr &= ~val;
1672 break;
1673 case MAL0_RXDEIR:
1674 /* Read/clear */
1675 mal->rxdeir &= ~val;
1676 break;
1677 case MAL0_TXCTP0R:
1678 idx = 0;
1679 goto update_tx_ptr;
1680 case MAL0_TXCTP1R:
1681 idx = 1;
1682 goto update_tx_ptr;
1683 case MAL0_TXCTP2R:
1684 idx = 2;
1685 goto update_tx_ptr;
1686 case MAL0_TXCTP3R:
1687 idx = 3;
1688 update_tx_ptr:
1689 mal->txctpr[idx] = val;
1690 break;
1691 case MAL0_RXCTP0R:
1692 idx = 0;
1693 goto update_rx_ptr;
1694 case MAL0_RXCTP1R:
1695 idx = 1;
1696 update_rx_ptr:
1697 mal->rxctpr[idx] = val;
1698 break;
1699 case MAL0_RCBS0:
1700 idx = 0;
1701 goto update_rx_size;
1702 case MAL0_RCBS1:
1703 idx = 1;
1704 update_rx_size:
1705 mal->rcbs[idx] = val & 0x000000FF;
1706 break;
1707 }
1708 }
1709
1710 static void ppc40x_mal_reset (void *opaque)
1711 {
1712 ppc40x_mal_t *mal;
1713
1714 mal = opaque;
1715 mal->cfg = 0x0007C000;
1716 mal->esr = 0x00000000;
1717 mal->ier = 0x00000000;
1718 mal->rxcasr = 0x00000000;
1719 mal->rxdeir = 0x00000000;
1720 mal->rxeobisr = 0x00000000;
1721 mal->txcasr = 0x00000000;
1722 mal->txdeir = 0x00000000;
1723 mal->txeobisr = 0x00000000;
1724 }
1725
1726 static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
1727 {
1728 ppc40x_mal_t *mal;
1729 int i;
1730
1731 mal = g_malloc0(sizeof(ppc40x_mal_t));
1732 for (i = 0; i < 4; i++)
1733 mal->irqs[i] = irqs[i];
1734 qemu_register_reset(&ppc40x_mal_reset, mal);
1735 ppc_dcr_register(env, MAL0_CFG,
1736 mal, &dcr_read_mal, &dcr_write_mal);
1737 ppc_dcr_register(env, MAL0_ESR,
1738 mal, &dcr_read_mal, &dcr_write_mal);
1739 ppc_dcr_register(env, MAL0_IER,
1740 mal, &dcr_read_mal, &dcr_write_mal);
1741 ppc_dcr_register(env, MAL0_TXCASR,
1742 mal, &dcr_read_mal, &dcr_write_mal);
1743 ppc_dcr_register(env, MAL0_TXCARR,
1744 mal, &dcr_read_mal, &dcr_write_mal);
1745 ppc_dcr_register(env, MAL0_TXEOBISR,
1746 mal, &dcr_read_mal, &dcr_write_mal);
1747 ppc_dcr_register(env, MAL0_TXDEIR,
1748 mal, &dcr_read_mal, &dcr_write_mal);
1749 ppc_dcr_register(env, MAL0_RXCASR,
1750 mal, &dcr_read_mal, &dcr_write_mal);
1751 ppc_dcr_register(env, MAL0_RXCARR,
1752 mal, &dcr_read_mal, &dcr_write_mal);
1753 ppc_dcr_register(env, MAL0_RXEOBISR,
1754 mal, &dcr_read_mal, &dcr_write_mal);
1755 ppc_dcr_register(env, MAL0_RXDEIR,
1756 mal, &dcr_read_mal, &dcr_write_mal);
1757 ppc_dcr_register(env, MAL0_TXCTP0R,
1758 mal, &dcr_read_mal, &dcr_write_mal);
1759 ppc_dcr_register(env, MAL0_TXCTP1R,
1760 mal, &dcr_read_mal, &dcr_write_mal);
1761 ppc_dcr_register(env, MAL0_TXCTP2R,
1762 mal, &dcr_read_mal, &dcr_write_mal);
1763 ppc_dcr_register(env, MAL0_TXCTP3R,
1764 mal, &dcr_read_mal, &dcr_write_mal);
1765 ppc_dcr_register(env, MAL0_RXCTP0R,
1766 mal, &dcr_read_mal, &dcr_write_mal);
1767 ppc_dcr_register(env, MAL0_RXCTP1R,
1768 mal, &dcr_read_mal, &dcr_write_mal);
1769 ppc_dcr_register(env, MAL0_RCBS0,
1770 mal, &dcr_read_mal, &dcr_write_mal);
1771 ppc_dcr_register(env, MAL0_RCBS1,
1772 mal, &dcr_read_mal, &dcr_write_mal);
1773 }
1774
1775 /*****************************************************************************/
1776 /* SPR */
1777 void ppc40x_core_reset(PowerPCCPU *cpu)
1778 {
1779 CPUPPCState *env = &cpu->env;
1780 target_ulong dbsr;
1781
1782 printf("Reset PowerPC core\n");
1783 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1784 dbsr = env->spr[SPR_40x_DBSR];
1785 dbsr &= ~0x00000300;
1786 dbsr |= 0x00000100;
1787 env->spr[SPR_40x_DBSR] = dbsr;
1788 }
1789
1790 void ppc40x_chip_reset(PowerPCCPU *cpu)
1791 {
1792 CPUPPCState *env = &cpu->env;
1793 target_ulong dbsr;
1794
1795 printf("Reset PowerPC chip\n");
1796 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1797 /* XXX: TODO reset all internal peripherals */
1798 dbsr = env->spr[SPR_40x_DBSR];
1799 dbsr &= ~0x00000300;
1800 dbsr |= 0x00000200;
1801 env->spr[SPR_40x_DBSR] = dbsr;
1802 }
1803
1804 void ppc40x_system_reset(PowerPCCPU *cpu)
1805 {
1806 printf("Reset PowerPC system\n");
1807 qemu_system_reset_request();
1808 }
1809
1810 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
1811 {
1812 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1813
1814 switch ((val >> 28) & 0x3) {
1815 case 0x0:
1816 /* No action */
1817 break;
1818 case 0x1:
1819 /* Core reset */
1820 ppc40x_core_reset(cpu);
1821 break;
1822 case 0x2:
1823 /* Chip reset */
1824 ppc40x_chip_reset(cpu);
1825 break;
1826 case 0x3:
1827 /* System reset */
1828 ppc40x_system_reset(cpu);
1829 break;
1830 }
1831 }
1832
1833 /*****************************************************************************/
1834 /* PowerPC 405CR */
1835 enum {
1836 PPC405CR_CPC0_PLLMR = 0x0B0,
1837 PPC405CR_CPC0_CR0 = 0x0B1,
1838 PPC405CR_CPC0_CR1 = 0x0B2,
1839 PPC405CR_CPC0_PSR = 0x0B4,
1840 PPC405CR_CPC0_JTAGID = 0x0B5,
1841 PPC405CR_CPC0_ER = 0x0B9,
1842 PPC405CR_CPC0_FR = 0x0BA,
1843 PPC405CR_CPC0_SR = 0x0BB,
1844 };
1845
1846 enum {
1847 PPC405CR_CPU_CLK = 0,
1848 PPC405CR_TMR_CLK = 1,
1849 PPC405CR_PLB_CLK = 2,
1850 PPC405CR_SDRAM_CLK = 3,
1851 PPC405CR_OPB_CLK = 4,
1852 PPC405CR_EXT_CLK = 5,
1853 PPC405CR_UART_CLK = 6,
1854 PPC405CR_CLK_NB = 7,
1855 };
1856
1857 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1858 struct ppc405cr_cpc_t {
1859 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1860 uint32_t sysclk;
1861 uint32_t psr;
1862 uint32_t cr0;
1863 uint32_t cr1;
1864 uint32_t jtagid;
1865 uint32_t pllmr;
1866 uint32_t er;
1867 uint32_t fr;
1868 };
1869
1870 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1871 {
1872 uint64_t VCO_out, PLL_out;
1873 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1874 int M, D0, D1, D2;
1875
1876 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1877 if (cpc->pllmr & 0x80000000) {
1878 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1879 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1880 M = D0 * D1 * D2;
1881 VCO_out = cpc->sysclk * M;
1882 if (VCO_out < 400000000 || VCO_out > 800000000) {
1883 /* PLL cannot lock */
1884 cpc->pllmr &= ~0x80000000;
1885 goto bypass_pll;
1886 }
1887 PLL_out = VCO_out / D2;
1888 } else {
1889 /* Bypass PLL */
1890 bypass_pll:
1891 M = D0;
1892 PLL_out = cpc->sysclk * M;
1893 }
1894 CPU_clk = PLL_out;
1895 if (cpc->cr1 & 0x00800000)
1896 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1897 else
1898 TMR_clk = CPU_clk;
1899 PLB_clk = CPU_clk / D0;
1900 SDRAM_clk = PLB_clk;
1901 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1902 OPB_clk = PLB_clk / D0;
1903 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1904 EXT_clk = PLB_clk / D0;
1905 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1906 UART_clk = CPU_clk / D0;
1907 /* Setup CPU clocks */
1908 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1909 /* Setup time-base clock */
1910 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1911 /* Setup PLB clock */
1912 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1913 /* Setup SDRAM clock */
1914 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1915 /* Setup OPB clock */
1916 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1917 /* Setup external clock */
1918 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1919 /* Setup UART clock */
1920 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1921 }
1922
1923 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1924 {
1925 ppc405cr_cpc_t *cpc;
1926 uint32_t ret;
1927
1928 cpc = opaque;
1929 switch (dcrn) {
1930 case PPC405CR_CPC0_PLLMR:
1931 ret = cpc->pllmr;
1932 break;
1933 case PPC405CR_CPC0_CR0:
1934 ret = cpc->cr0;
1935 break;
1936 case PPC405CR_CPC0_CR1:
1937 ret = cpc->cr1;
1938 break;
1939 case PPC405CR_CPC0_PSR:
1940 ret = cpc->psr;
1941 break;
1942 case PPC405CR_CPC0_JTAGID:
1943 ret = cpc->jtagid;
1944 break;
1945 case PPC405CR_CPC0_ER:
1946 ret = cpc->er;
1947 break;
1948 case PPC405CR_CPC0_FR:
1949 ret = cpc->fr;
1950 break;
1951 case PPC405CR_CPC0_SR:
1952 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1953 break;
1954 default:
1955 /* Avoid gcc warning */
1956 ret = 0;
1957 break;
1958 }
1959
1960 return ret;
1961 }
1962
1963 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1964 {
1965 ppc405cr_cpc_t *cpc;
1966
1967 cpc = opaque;
1968 switch (dcrn) {
1969 case PPC405CR_CPC0_PLLMR:
1970 cpc->pllmr = val & 0xFFF77C3F;
1971 break;
1972 case PPC405CR_CPC0_CR0:
1973 cpc->cr0 = val & 0x0FFFFFFE;
1974 break;
1975 case PPC405CR_CPC0_CR1:
1976 cpc->cr1 = val & 0x00800000;
1977 break;
1978 case PPC405CR_CPC0_PSR:
1979 /* Read-only */
1980 break;
1981 case PPC405CR_CPC0_JTAGID:
1982 /* Read-only */
1983 break;
1984 case PPC405CR_CPC0_ER:
1985 cpc->er = val & 0xBFFC0000;
1986 break;
1987 case PPC405CR_CPC0_FR:
1988 cpc->fr = val & 0xBFFC0000;
1989 break;
1990 case PPC405CR_CPC0_SR:
1991 /* Read-only */
1992 break;
1993 }
1994 }
1995
1996 static void ppc405cr_cpc_reset (void *opaque)
1997 {
1998 ppc405cr_cpc_t *cpc;
1999 int D;
2000
2001 cpc = opaque;
2002 /* Compute PLLMR value from PSR settings */
2003 cpc->pllmr = 0x80000000;
2004 /* PFWD */
2005 switch ((cpc->psr >> 30) & 3) {
2006 case 0:
2007 /* Bypass */
2008 cpc->pllmr &= ~0x80000000;
2009 break;
2010 case 1:
2011 /* Divide by 3 */
2012 cpc->pllmr |= 5 << 16;
2013 break;
2014 case 2:
2015 /* Divide by 4 */
2016 cpc->pllmr |= 4 << 16;
2017 break;
2018 case 3:
2019 /* Divide by 6 */
2020 cpc->pllmr |= 2 << 16;
2021 break;
2022 }
2023 /* PFBD */
2024 D = (cpc->psr >> 28) & 3;
2025 cpc->pllmr |= (D + 1) << 20;
2026 /* PT */
2027 D = (cpc->psr >> 25) & 7;
2028 switch (D) {
2029 case 0x2:
2030 cpc->pllmr |= 0x13;
2031 break;
2032 case 0x4:
2033 cpc->pllmr |= 0x15;
2034 break;
2035 case 0x5:
2036 cpc->pllmr |= 0x16;
2037 break;
2038 default:
2039 break;
2040 }
2041 /* PDC */
2042 D = (cpc->psr >> 23) & 3;
2043 cpc->pllmr |= D << 26;
2044 /* ODP */
2045 D = (cpc->psr >> 21) & 3;
2046 cpc->pllmr |= D << 10;
2047 /* EBPD */
2048 D = (cpc->psr >> 17) & 3;
2049 cpc->pllmr |= D << 24;
2050 cpc->cr0 = 0x0000003C;
2051 cpc->cr1 = 0x2B0D8800;
2052 cpc->er = 0x00000000;
2053 cpc->fr = 0x00000000;
2054 ppc405cr_clk_setup(cpc);
2055 }
2056
2057 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2058 {
2059 int D;
2060
2061 /* XXX: this should be read from IO pins */
2062 cpc->psr = 0x00000000; /* 8 bits ROM */
2063 /* PFWD */
2064 D = 0x2; /* Divide by 4 */
2065 cpc->psr |= D << 30;
2066 /* PFBD */
2067 D = 0x1; /* Divide by 2 */
2068 cpc->psr |= D << 28;
2069 /* PDC */
2070 D = 0x1; /* Divide by 2 */
2071 cpc->psr |= D << 23;
2072 /* PT */
2073 D = 0x5; /* M = 16 */
2074 cpc->psr |= D << 25;
2075 /* ODP */
2076 D = 0x1; /* Divide by 2 */
2077 cpc->psr |= D << 21;
2078 /* EBDP */
2079 D = 0x2; /* Divide by 4 */
2080 cpc->psr |= D << 17;
2081 }
2082
2083 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
2084 uint32_t sysclk)
2085 {
2086 ppc405cr_cpc_t *cpc;
2087
2088 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
2089 memcpy(cpc->clk_setup, clk_setup,
2090 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2091 cpc->sysclk = sysclk;
2092 cpc->jtagid = 0x42051049;
2093 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2094 &dcr_read_crcpc, &dcr_write_crcpc);
2095 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2096 &dcr_read_crcpc, &dcr_write_crcpc);
2097 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2098 &dcr_read_crcpc, &dcr_write_crcpc);
2099 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2100 &dcr_read_crcpc, &dcr_write_crcpc);
2101 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2102 &dcr_read_crcpc, &dcr_write_crcpc);
2103 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2104 &dcr_read_crcpc, &dcr_write_crcpc);
2105 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2106 &dcr_read_crcpc, &dcr_write_crcpc);
2107 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2108 &dcr_read_crcpc, &dcr_write_crcpc);
2109 ppc405cr_clk_init(cpc);
2110 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2111 }
2112
2113 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
2114 MemoryRegion ram_memories[4],
2115 hwaddr ram_bases[4],
2116 hwaddr ram_sizes[4],
2117 uint32_t sysclk, qemu_irq **picp,
2118 int do_init)
2119 {
2120 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2121 qemu_irq dma_irqs[4];
2122 PowerPCCPU *cpu;
2123 CPUPPCState *env;
2124 qemu_irq *pic, *irqs;
2125
2126 memset(clk_setup, 0, sizeof(clk_setup));
2127 cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2128 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2129 env = &cpu->env;
2130 /* Memory mapped devices registers */
2131 /* PLB arbitrer */
2132 ppc4xx_plb_init(env);
2133 /* PLB to OPB bridge */
2134 ppc4xx_pob_init(env);
2135 /* OBP arbitrer */
2136 ppc4xx_opba_init(0xef600600);
2137 /* Universal interrupt controller */
2138 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2139 irqs[PPCUIC_OUTPUT_INT] =
2140 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2141 irqs[PPCUIC_OUTPUT_CINT] =
2142 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2143 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2144 *picp = pic;
2145 /* SDRAM controller */
2146 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
2147 ram_bases, ram_sizes, do_init);
2148 /* External bus controller */
2149 ppc405_ebc_init(env);
2150 /* DMA controller */
2151 dma_irqs[0] = pic[26];
2152 dma_irqs[1] = pic[25];
2153 dma_irqs[2] = pic[24];
2154 dma_irqs[3] = pic[23];
2155 ppc405_dma_init(env, dma_irqs);
2156 /* Serial ports */
2157 if (serial_hds[0] != NULL) {
2158 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2159 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2160 DEVICE_BIG_ENDIAN);
2161 }
2162 if (serial_hds[1] != NULL) {
2163 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2164 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2165 DEVICE_BIG_ENDIAN);
2166 }
2167 /* IIC controller */
2168 ppc405_i2c_init(0xef600500, pic[2]);
2169 /* GPIO */
2170 ppc405_gpio_init(0xef600700);
2171 /* CPU control */
2172 ppc405cr_cpc_init(env, clk_setup, sysclk);
2173
2174 return env;
2175 }
2176
2177 /*****************************************************************************/
2178 /* PowerPC 405EP */
2179 /* CPU control */
2180 enum {
2181 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2182 PPC405EP_CPC0_BOOT = 0x0F1,
2183 PPC405EP_CPC0_EPCTL = 0x0F3,
2184 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2185 PPC405EP_CPC0_UCR = 0x0F5,
2186 PPC405EP_CPC0_SRR = 0x0F6,
2187 PPC405EP_CPC0_JTAGID = 0x0F7,
2188 PPC405EP_CPC0_PCI = 0x0F9,
2189 #if 0
2190 PPC405EP_CPC0_ER = xxx,
2191 PPC405EP_CPC0_FR = xxx,
2192 PPC405EP_CPC0_SR = xxx,
2193 #endif
2194 };
2195
2196 enum {
2197 PPC405EP_CPU_CLK = 0,
2198 PPC405EP_PLB_CLK = 1,
2199 PPC405EP_OPB_CLK = 2,
2200 PPC405EP_EBC_CLK = 3,
2201 PPC405EP_MAL_CLK = 4,
2202 PPC405EP_PCI_CLK = 5,
2203 PPC405EP_UART0_CLK = 6,
2204 PPC405EP_UART1_CLK = 7,
2205 PPC405EP_CLK_NB = 8,
2206 };
2207
2208 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2209 struct ppc405ep_cpc_t {
2210 uint32_t sysclk;
2211 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2212 uint32_t boot;
2213 uint32_t epctl;
2214 uint32_t pllmr[2];
2215 uint32_t ucr;
2216 uint32_t srr;
2217 uint32_t jtagid;
2218 uint32_t pci;
2219 /* Clock and power management */
2220 uint32_t er;
2221 uint32_t fr;
2222 uint32_t sr;
2223 };
2224
2225 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2226 {
2227 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2228 uint32_t UART0_clk, UART1_clk;
2229 uint64_t VCO_out, PLL_out;
2230 int M, D;
2231
2232 VCO_out = 0;
2233 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2234 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2235 #ifdef DEBUG_CLOCKS_LL
2236 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2237 #endif
2238 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2239 #ifdef DEBUG_CLOCKS_LL
2240 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2241 #endif
2242 VCO_out = cpc->sysclk * M * D;
2243 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2244 /* Error - unlock the PLL */
2245 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2246 #if 0
2247 cpc->pllmr[1] &= ~0x80000000;
2248 goto pll_bypass;
2249 #endif
2250 }
2251 PLL_out = VCO_out / D;
2252 /* Pretend the PLL is locked */
2253 cpc->boot |= 0x00000001;
2254 } else {
2255 #if 0
2256 pll_bypass:
2257 #endif
2258 PLL_out = cpc->sysclk;
2259 if (cpc->pllmr[1] & 0x40000000) {
2260 /* Pretend the PLL is not locked */
2261 cpc->boot &= ~0x00000001;
2262 }
2263 }
2264 /* Now, compute all other clocks */
2265 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2266 #ifdef DEBUG_CLOCKS_LL
2267 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2268 #endif
2269 CPU_clk = PLL_out / D;
2270 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2271 #ifdef DEBUG_CLOCKS_LL
2272 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2273 #endif
2274 PLB_clk = CPU_clk / D;
2275 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2276 #ifdef DEBUG_CLOCKS_LL
2277 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2278 #endif
2279 OPB_clk = PLB_clk / D;
2280 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2281 #ifdef DEBUG_CLOCKS_LL
2282 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2283 #endif
2284 EBC_clk = PLB_clk / D;
2285 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2286 #ifdef DEBUG_CLOCKS_LL
2287 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2288 #endif
2289 MAL_clk = PLB_clk / D;
2290 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2291 #ifdef DEBUG_CLOCKS_LL
2292 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2293 #endif
2294 PCI_clk = PLB_clk / D;
2295 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2296 #ifdef DEBUG_CLOCKS_LL
2297 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2298 #endif
2299 UART0_clk = PLL_out / D;
2300 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2301 #ifdef DEBUG_CLOCKS_LL
2302 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2303 #endif
2304 UART1_clk = PLL_out / D;
2305 #ifdef DEBUG_CLOCKS
2306 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2307 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2308 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2309 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2310 " UART1 %" PRIu32 "\n",
2311 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2312 UART0_clk, UART1_clk);
2313 #endif
2314 /* Setup CPU clocks */
2315 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2316 /* Setup PLB clock */
2317 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2318 /* Setup OPB clock */
2319 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2320 /* Setup external clock */
2321 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2322 /* Setup MAL clock */
2323 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2324 /* Setup PCI clock */
2325 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2326 /* Setup UART0 clock */
2327 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2328 /* Setup UART1 clock */
2329 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2330 }
2331
2332 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2333 {
2334 ppc405ep_cpc_t *cpc;
2335 uint32_t ret;
2336
2337 cpc = opaque;
2338 switch (dcrn) {
2339 case PPC405EP_CPC0_BOOT:
2340 ret = cpc->boot;
2341 break;
2342 case PPC405EP_CPC0_EPCTL:
2343 ret = cpc->epctl;
2344 break;
2345 case PPC405EP_CPC0_PLLMR0:
2346 ret = cpc->pllmr[0];
2347 break;
2348 case PPC405EP_CPC0_PLLMR1:
2349 ret = cpc->pllmr[1];
2350 break;
2351 case PPC405EP_CPC0_UCR:
2352 ret = cpc->ucr;
2353 break;
2354 case PPC405EP_CPC0_SRR:
2355 ret = cpc->srr;
2356 break;
2357 case PPC405EP_CPC0_JTAGID:
2358 ret = cpc->jtagid;
2359 break;
2360 case PPC405EP_CPC0_PCI:
2361 ret = cpc->pci;
2362 break;
2363 default:
2364 /* Avoid gcc warning */
2365 ret = 0;
2366 break;
2367 }
2368
2369 return ret;
2370 }
2371
2372 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2373 {
2374 ppc405ep_cpc_t *cpc;
2375
2376 cpc = opaque;
2377 switch (dcrn) {
2378 case PPC405EP_CPC0_BOOT:
2379 /* Read-only register */
2380 break;
2381 case PPC405EP_CPC0_EPCTL:
2382 /* Don't care for now */
2383 cpc->epctl = val & 0xC00000F3;
2384 break;
2385 case PPC405EP_CPC0_PLLMR0:
2386 cpc->pllmr[0] = val & 0x00633333;
2387 ppc405ep_compute_clocks(cpc);
2388 break;
2389 case PPC405EP_CPC0_PLLMR1:
2390 cpc->pllmr[1] = val & 0xC0F73FFF;
2391 ppc405ep_compute_clocks(cpc);
2392 break;
2393 case PPC405EP_CPC0_UCR:
2394 /* UART control - don't care for now */
2395 cpc->ucr = val & 0x003F7F7F;
2396 break;
2397 case PPC405EP_CPC0_SRR:
2398 cpc->srr = val;
2399 break;
2400 case PPC405EP_CPC0_JTAGID:
2401 /* Read-only */
2402 break;
2403 case PPC405EP_CPC0_PCI:
2404 cpc->pci = val;
2405 break;
2406 }
2407 }
2408
2409 static void ppc405ep_cpc_reset (void *opaque)
2410 {
2411 ppc405ep_cpc_t *cpc = opaque;
2412
2413 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2414 cpc->epctl = 0x00000000;
2415 cpc->pllmr[0] = 0x00011010;
2416 cpc->pllmr[1] = 0x40000000;
2417 cpc->ucr = 0x00000000;
2418 cpc->srr = 0x00040000;
2419 cpc->pci = 0x00000000;
2420 cpc->er = 0x00000000;
2421 cpc->fr = 0x00000000;
2422 cpc->sr = 0x00000000;
2423 ppc405ep_compute_clocks(cpc);
2424 }
2425
2426 /* XXX: sysclk should be between 25 and 100 MHz */
2427 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
2428 uint32_t sysclk)
2429 {
2430 ppc405ep_cpc_t *cpc;
2431
2432 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
2433 memcpy(cpc->clk_setup, clk_setup,
2434 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2435 cpc->jtagid = 0x20267049;
2436 cpc->sysclk = sysclk;
2437 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2438 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2439 &dcr_read_epcpc, &dcr_write_epcpc);
2440 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2441 &dcr_read_epcpc, &dcr_write_epcpc);
2442 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2443 &dcr_read_epcpc, &dcr_write_epcpc);
2444 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2445 &dcr_read_epcpc, &dcr_write_epcpc);
2446 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2447 &dcr_read_epcpc, &dcr_write_epcpc);
2448 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2449 &dcr_read_epcpc, &dcr_write_epcpc);
2450 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2451 &dcr_read_epcpc, &dcr_write_epcpc);
2452 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2453 &dcr_read_epcpc, &dcr_write_epcpc);
2454 #if 0
2455 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2456 &dcr_read_epcpc, &dcr_write_epcpc);
2457 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2458 &dcr_read_epcpc, &dcr_write_epcpc);
2459 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2460 &dcr_read_epcpc, &dcr_write_epcpc);
2461 #endif
2462 }
2463
2464 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
2465 MemoryRegion ram_memories[2],
2466 hwaddr ram_bases[2],
2467 hwaddr ram_sizes[2],
2468 uint32_t sysclk, qemu_irq **picp,
2469 int do_init)
2470 {
2471 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2472 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2473 PowerPCCPU *cpu;
2474 CPUPPCState *env;
2475 qemu_irq *pic, *irqs;
2476
2477 memset(clk_setup, 0, sizeof(clk_setup));
2478 /* init CPUs */
2479 cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2480 &tlb_clk_setup, sysclk);
2481 env = &cpu->env;
2482 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2483 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2484 /* Internal devices init */
2485 /* Memory mapped devices registers */
2486 /* PLB arbitrer */
2487 ppc4xx_plb_init(env);
2488 /* PLB to OPB bridge */
2489 ppc4xx_pob_init(env);
2490 /* OBP arbitrer */
2491 ppc4xx_opba_init(0xef600600);
2492 /* Initialize timers */
2493 ppc_booke_timers_init(cpu, sysclk, 0);
2494 /* Universal interrupt controller */
2495 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2496 irqs[PPCUIC_OUTPUT_INT] =
2497 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2498 irqs[PPCUIC_OUTPUT_CINT] =
2499 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2500 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2501 *picp = pic;
2502 /* SDRAM controller */
2503 /* XXX 405EP has no ECC interrupt */
2504 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2505 ram_bases, ram_sizes, do_init);
2506 /* External bus controller */
2507 ppc405_ebc_init(env);
2508 /* DMA controller */
2509 dma_irqs[0] = pic[5];
2510 dma_irqs[1] = pic[6];
2511 dma_irqs[2] = pic[7];
2512 dma_irqs[3] = pic[8];
2513 ppc405_dma_init(env, dma_irqs);
2514 /* IIC controller */
2515 ppc405_i2c_init(0xef600500, pic[2]);
2516 /* GPIO */
2517 ppc405_gpio_init(0xef600700);
2518 /* Serial ports */
2519 if (serial_hds[0] != NULL) {
2520 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2521 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2522 DEVICE_BIG_ENDIAN);
2523 }
2524 if (serial_hds[1] != NULL) {
2525 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2526 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2527 DEVICE_BIG_ENDIAN);
2528 }
2529 /* OCM */
2530 ppc405_ocm_init(env);
2531 /* GPT */
2532 gpt_irqs[0] = pic[19];
2533 gpt_irqs[1] = pic[20];
2534 gpt_irqs[2] = pic[21];
2535 gpt_irqs[3] = pic[22];
2536 gpt_irqs[4] = pic[23];
2537 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2538 /* PCI */
2539 /* Uses pic[3], pic[16], pic[18] */
2540 /* MAL */
2541 mal_irqs[0] = pic[11];
2542 mal_irqs[1] = pic[12];
2543 mal_irqs[2] = pic[13];
2544 mal_irqs[3] = pic[14];
2545 ppc405_mal_init(env, mal_irqs);
2546 /* Ethernet */
2547 /* Uses pic[9], pic[15], pic[17] */
2548 /* CPU control */
2549 ppc405ep_cpc_init(env, clk_setup, sysclk);
2550
2551 return env;
2552 }
QEmu