hw/arm/versatilepb.c

   1 /*
   2  * ARM Versatile Platform/Application Baseboard System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/sysbus.h"
  12 #include "hw/arm/arm.h"
  13 #include "hw/devices.h"
  14 #include "net/net.h"
  15 #include "sysemu/sysemu.h"
  16 #include "hw/pci/pci.h"
  17 #include "hw/i2c/i2c.h"
  18 #include "hw/boards.h"
  19 #include "sysemu/block-backend.h"
  20 #include "exec/address-spaces.h"
  21 #include "hw/block/flash.h"
  22 #include "qemu/error-report.h"
  23
  24 #define VERSATILE_FLASH_ADDR 0x34000000
  25 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024)
  26 #define VERSATILE_FLASH_SECT_SIZE (256 * 1024)
  27
  28 /* Primary interrupt controller.  */
  29
  30 #define TYPE_VERSATILE_PB_SIC "versatilepb_sic"
  31 #define VERSATILE_PB_SIC(obj) \
  32     OBJECT_CHECK(vpb_sic_state, (obj), TYPE_VERSATILE_PB_SIC)
  33
  34 typedef struct vpb_sic_state {
  35     SysBusDevice parent_obj;
  36
  37     MemoryRegion iomem;
  38     uint32_t level;
  39     uint32_t mask;
  40     uint32_t pic_enable;
  41     qemu_irq parent[32];
  42     int irq;
  43 } vpb_sic_state;
  44
  45 static const VMStateDescription vmstate_vpb_sic = {
  46     .name = "versatilepb_sic",
  47     .version_id = 1,
  48     .minimum_version_id = 1,
  49     .fields = (VMStateField[]) {
  50         VMSTATE_UINT32(level, vpb_sic_state),
  51         VMSTATE_UINT32(mask, vpb_sic_state),
  52         VMSTATE_UINT32(pic_enable, vpb_sic_state),
  53         VMSTATE_END_OF_LIST()
  54     }
  55 };
  56
  57 static void vpb_sic_update(vpb_sic_state *s)
  58 {
  59     uint32_t flags;
  60
  61     flags = s->level & s->mask;
  62     qemu_set_irq(s->parent[s->irq], flags != 0);
  63 }
  64
  65 static void vpb_sic_update_pic(vpb_sic_state *s)
  66 {
  67     int i;
  68     uint32_t mask;
  69
  70     for (i = 21; i <= 30; i++) {
  71         mask = 1u << i;
  72         if (!(s->pic_enable & mask))
  73             continue;
  74         qemu_set_irq(s->parent[i], (s->level & mask) != 0);
  75     }
  76 }
  77
  78 static void vpb_sic_set_irq(void *opaque, int irq, int level)
  79 {
  80     vpb_sic_state *s = (vpb_sic_state *)opaque;
  81     if (level)
  82         s->level |= 1u << irq;
  83     else
  84         s->level &= ~(1u << irq);
  85     if (s->pic_enable & (1u << irq))
  86         qemu_set_irq(s->parent[irq], level);
  87     vpb_sic_update(s);
  88 }
  89
  90 static uint64_t vpb_sic_read(void *opaque, hwaddr offset,
  91                              unsigned size)
  92 {
  93     vpb_sic_state *s = (vpb_sic_state *)opaque;
  94
  95     switch (offset >> 2) {
  96     case 0: /* STATUS */
  97         return s->level & s->mask;
  98     case 1: /* RAWSTAT */
  99         return s->level;
 100     case 2: /* ENABLE */
 101         return s->mask;
 102     case 4: /* SOFTINT */
 103         return s->level & 1;
 104     case 8: /* PICENABLE */
 105         return s->pic_enable;
 106     default:
 107         printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
 108         return 0;
 109     }
 110 }
 111
 112 static void vpb_sic_write(void *opaque, hwaddr offset,
 113                           uint64_t value, unsigned size)
 114 {
 115     vpb_sic_state *s = (vpb_sic_state *)opaque;
 116
 117     switch (offset >> 2) {
 118     case 2: /* ENSET */
 119         s->mask |= value;
 120         break;
 121     case 3: /* ENCLR */
 122         s->mask &= ~value;
 123         break;
 124     case 4: /* SOFTINTSET */
 125         if (value)
 126             s->mask |= 1;
 127         break;
 128     case 5: /* SOFTINTCLR */
 129         if (value)
 130             s->mask &= ~1u;
 131         break;
 132     case 8: /* PICENSET */
 133         s->pic_enable |= (value & 0x7fe00000);
 134         vpb_sic_update_pic(s);
 135         break;
 136     case 9: /* PICENCLR */
 137         s->pic_enable &= ~value;
 138         vpb_sic_update_pic(s);
 139         break;
 140     default:
 141         printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
 142         return;
 143     }
 144     vpb_sic_update(s);
 145 }
 146
 147 static const MemoryRegionOps vpb_sic_ops = {
 148     .read = vpb_sic_read,
 149     .write = vpb_sic_write,
 150     .endianness = DEVICE_NATIVE_ENDIAN,
 151 };
 152
 153 static int vpb_sic_init(SysBusDevice *sbd)
 154 {
 155     DeviceState *dev = DEVICE(sbd);
 156     vpb_sic_state *s = VERSATILE_PB_SIC(dev);
 157     int i;
 158
 159     qdev_init_gpio_in(dev, vpb_sic_set_irq, 32);
 160     for (i = 0; i < 32; i++) {
 161         sysbus_init_irq(sbd, &s->parent[i]);
 162     }
 163     s->irq = 31;
 164     memory_region_init_io(&s->iomem, OBJECT(s), &vpb_sic_ops, s,
 165                           "vpb-sic", 0x1000);
 166     sysbus_init_mmio(sbd, &s->iomem);
 167     return 0;
 168 }
 169
 170 /* Board init.  */
 171
 172 /* The AB and PB boards both use the same core, just with different
 173    peripherals and expansion busses.  For now we emulate a subset of the
 174    PB peripherals and just change the board ID.  */
 175
 176 static struct arm_boot_info versatile_binfo;
 177
 178 static void versatile_init(MachineState *machine, int board_id)
 179 {
 180     ObjectClass *cpu_oc;
 181     Object *cpuobj;
 182     ARMCPU *cpu;
 183     MemoryRegion *sysmem = get_system_memory();
 184     MemoryRegion *ram = g_new(MemoryRegion, 1);
 185     qemu_irq pic[32];
 186     qemu_irq sic[32];
 187     DeviceState *dev, *sysctl;
 188     SysBusDevice *busdev;
 189     DeviceState *pl041;
 190     PCIBus *pci_bus;
 191     NICInfo *nd;
 192     I2CBus *i2c;
 193     int n;
 194     int done_smc = 0;
 195     DriveInfo *dinfo;
 196
 197     if (!machine->cpu_model) {
 198         machine->cpu_model = "arm926";
 199     }
 200
 201     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, machine->cpu_model);
 202     if (!cpu_oc) {
 203         fprintf(stderr, "Unable to find CPU definition\n");
 204         exit(1);
 205     }
 206
 207     cpuobj = object_new(object_class_get_name(cpu_oc));
 208
 209     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
 210      * currently support EL3 so the CPU EL3 property is disabled before
 211      * realization.
 212      */
 213     if (object_property_find(cpuobj, "has_el3", NULL)) {
 214         object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
 215     }
 216
 217     object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 218
 219     cpu = ARM_CPU(cpuobj);
 220
 221     memory_region_allocate_system_memory(ram, NULL, "versatile.ram",
 222                                          machine->ram_size);
 223     /* ??? RAM should repeat to fill physical memory space.  */
 224     /* SDRAM at address zero.  */
 225     memory_region_add_subregion(sysmem, 0, ram);
 226
 227     sysctl = qdev_create(NULL, "realview_sysctl");
 228     qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
 229     qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
 230     qdev_init_nofail(sysctl);
 231     sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000);
 232
 233     dev = sysbus_create_varargs("pl190", 0x10140000,
 234                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
 235                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
 236                                 NULL);
 237     for (n = 0; n < 32; n++) {
 238         pic[n] = qdev_get_gpio_in(dev, n);
 239     }
 240     dev = sysbus_create_simple(TYPE_VERSATILE_PB_SIC, 0x10003000, NULL);
 241     for (n = 0; n < 32; n++) {
 242         sysbus_connect_irq(SYS_BUS_DEVICE(dev), n, pic[n]);
 243         sic[n] = qdev_get_gpio_in(dev, n);
 244     }
 245
 246     sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
 247     sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
 248
 249     dev = qdev_create(NULL, "versatile_pci");
 250     busdev = SYS_BUS_DEVICE(dev);
 251     qdev_init_nofail(dev);
 252     sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */
 253     sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */
 254     sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */
 255     sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */
 256     sysbus_mmio_map(busdev, 4, 0x44000000); /* PCI memory window 1 */
 257     sysbus_mmio_map(busdev, 5, 0x50000000); /* PCI memory window 2 */
 258     sysbus_mmio_map(busdev, 6, 0x60000000); /* PCI memory window 3 */
 259     sysbus_connect_irq(busdev, 0, sic[27]);
 260     sysbus_connect_irq(busdev, 1, sic[28]);
 261     sysbus_connect_irq(busdev, 2, sic[29]);
 262     sysbus_connect_irq(busdev, 3, sic[30]);
 263     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 264
 265     for(n = 0; n < nb_nics; n++) {
 266         nd = &nd_table[n];
 267
 268         if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
 269             smc91c111_init(nd, 0x10010000, sic[25]);
 270             done_smc = 1;
 271         } else {
 272             pci_nic_init_nofail(nd, pci_bus, "rtl8139", NULL);
 273         }
 274     }
 275     if (usb_enabled()) {
 276         pci_create_simple(pci_bus, -1, "pci-ohci");
 277     }
 278     n = drive_get_max_bus(IF_SCSI);
 279     while (n >= 0) {
 280         pci_create_simple(pci_bus, -1, "lsi53c895a");
 281         n--;
 282     }
 283
 284     sysbus_create_simple("pl011", 0x101f1000, pic[12]);
 285     sysbus_create_simple("pl011", 0x101f2000, pic[13]);
 286     sysbus_create_simple("pl011", 0x101f3000, pic[14]);
 287     sysbus_create_simple("pl011", 0x10009000, sic[6]);
 288
 289     sysbus_create_simple("pl080", 0x10130000, pic[17]);
 290     sysbus_create_simple("sp804", 0x101e2000, pic[4]);
 291     sysbus_create_simple("sp804", 0x101e3000, pic[5]);
 292
 293     sysbus_create_simple("pl061", 0x101e4000, pic[6]);
 294     sysbus_create_simple("pl061", 0x101e5000, pic[7]);
 295     sysbus_create_simple("pl061", 0x101e6000, pic[8]);
 296     sysbus_create_simple("pl061", 0x101e7000, pic[9]);
 297
 298     /* The versatile/PB actually has a modified Color LCD controller
 299        that includes hardware cursor support from the PL111.  */
 300     dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
 301     /* Wire up the mux control signals from the SYS_CLCD register */
 302     qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
 303
 304     sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
 305     sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
 306
 307     /* Add PL031 Real Time Clock. */
 308     sysbus_create_simple("pl031", 0x101e8000, pic[10]);
 309
 310     dev = sysbus_create_simple("versatile_i2c", 0x10002000, NULL);
 311     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
 312     i2c_create_slave(i2c, "ds1338", 0x68);
 313
 314     /* Add PL041 AACI Interface to the LM4549 codec */
 315     pl041 = qdev_create(NULL, "pl041");
 316     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 317     qdev_init_nofail(pl041);
 318     sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000);
 319     sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, sic[24]);
 320
 321     /* Memory map for Versatile/PB:  */
 322     /* 0x10000000 System registers.  */
 323     /* 0x10001000 PCI controller config registers.  */
 324     /* 0x10002000 Serial bus interface.  */
 325     /*  0x10003000 Secondary interrupt controller.  */
 326     /* 0x10004000 AACI (audio).  */
 327     /*  0x10005000 MMCI0.  */
 328     /*  0x10006000 KMI0 (keyboard).  */
 329     /*  0x10007000 KMI1 (mouse).  */
 330     /* 0x10008000 Character LCD Interface.  */
 331     /*  0x10009000 UART3.  */
 332     /* 0x1000a000 Smart card 1.  */
 333     /*  0x1000b000 MMCI1.  */
 334     /*  0x10010000 Ethernet.  */
 335     /* 0x10020000 USB.  */
 336     /* 0x10100000 SSMC.  */
 337     /* 0x10110000 MPMC.  */
 338     /*  0x10120000 CLCD Controller.  */
 339     /*  0x10130000 DMA Controller.  */
 340     /*  0x10140000 Vectored interrupt controller.  */
 341     /* 0x101d0000 AHB Monitor Interface.  */
 342     /* 0x101e0000 System Controller.  */
 343     /* 0x101e1000 Watchdog Interface.  */
 344     /* 0x101e2000 Timer 0/1.  */
 345     /* 0x101e3000 Timer 2/3.  */
 346     /* 0x101e4000 GPIO port 0.  */
 347     /* 0x101e5000 GPIO port 1.  */
 348     /* 0x101e6000 GPIO port 2.  */
 349     /* 0x101e7000 GPIO port 3.  */
 350     /* 0x101e8000 RTC.  */
 351     /* 0x101f0000 Smart card 0.  */
 352     /*  0x101f1000 UART0.  */
 353     /*  0x101f2000 UART1.  */
 354     /*  0x101f3000 UART2.  */
 355     /* 0x101f4000 SSPI.  */
 356     /* 0x34000000 NOR Flash */
 357
 358     dinfo = drive_get(IF_PFLASH, 0, 0);
 359     if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, NULL, "versatile.flash",
 360                           VERSATILE_FLASH_SIZE,
 361                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 362                           VERSATILE_FLASH_SECT_SIZE,
 363                           VERSATILE_FLASH_SIZE / VERSATILE_FLASH_SECT_SIZE,
 364                           4, 0x0089, 0x0018, 0x0000, 0x0, 0)) {
 365         fprintf(stderr, "qemu: Error registering flash memory.\n");
 366     }
 367
 368     versatile_binfo.ram_size = machine->ram_size;
 369     versatile_binfo.kernel_filename = machine->kernel_filename;
 370     versatile_binfo.kernel_cmdline = machine->kernel_cmdline;
 371     versatile_binfo.initrd_filename = machine->initrd_filename;
 372     versatile_binfo.board_id = board_id;
 373     arm_load_kernel(cpu, &versatile_binfo);
 374 }
 375
 376 static void vpb_init(MachineState *machine)
 377 {
 378     versatile_init(machine, 0x183);
 379 }
 380
 381 static void vab_init(MachineState *machine)
 382 {
 383     versatile_init(machine, 0x25e);
 384 }
 385
 386 static void versatilepb_class_init(ObjectClass *oc, void *data)
 387 {
 388     MachineClass *mc = MACHINE_CLASS(oc);
 389
 390     mc->desc = "ARM Versatile/PB (ARM926EJ-S)";
 391     mc->init = vpb_init;
 392     mc->block_default_type = IF_SCSI;
 393 }
 394
 395 static const TypeInfo versatilepb_type = {
 396     .name = MACHINE_TYPE_NAME("versatilepb"),
 397     .parent = TYPE_MACHINE,
 398     .class_init = versatilepb_class_init,
 399 };
 400
 401 static void versatileab_class_init(ObjectClass *oc, void *data)
 402 {
 403     MachineClass *mc = MACHINE_CLASS(oc);
 404
 405     mc->desc = "ARM Versatile/AB (ARM926EJ-S)";
 406     mc->init = vab_init;
 407     mc->block_default_type = IF_SCSI;
 408 }
 409
 410 static const TypeInfo versatileab_type = {
 411     .name = MACHINE_TYPE_NAME("versatileab"),
 412     .parent = TYPE_MACHINE,
 413     .class_init = versatileab_class_init,
 414 };
 415
 416 static void versatile_machine_init(void)
 417 {
 418     type_register_static(&versatilepb_type);
 419     type_register_static(&versatileab_type);
 420 }
 421
 422 machine_init(versatile_machine_init)
 423
 424 static void vpb_sic_class_init(ObjectClass *klass, void *data)
 425 {
 426     DeviceClass *dc = DEVICE_CLASS(klass);
 427     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 428
 429     k->init = vpb_sic_init;
 430     dc->vmsd = &vmstate_vpb_sic;
 431 }
 432
 433 static const TypeInfo vpb_sic_info = {
 434     .name          = TYPE_VERSATILE_PB_SIC,
 435     .parent        = TYPE_SYS_BUS_DEVICE,
 436     .instance_size = sizeof(vpb_sic_state),
 437     .class_init    = vpb_sic_class_init,
 438 };
 439
 440 static void versatilepb_register_types(void)
 441 {
 442     type_register_static(&vpb_sic_info);
 443 }
 444
 445 type_init(versatilepb_register_types)