hw/arm/integratorcp.c

   1 /*
   2  * ARM Integrator CP System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/sysbus.h"
  12 #include "hw/devices.h"
  13 #include "hw/boards.h"
  14 #include "hw/arm/arm.h"
  15 #include "hw/misc/arm_integrator_debug.h"
  16 #include "net/net.h"
  17 #include "exec/address-spaces.h"
  18 #include "sysemu/sysemu.h"
  19 #include "qemu/error-report.h"
  20
  21 #define TYPE_INTEGRATOR_CM "integrator_core"
  22 #define INTEGRATOR_CM(obj) \
  23     OBJECT_CHECK(IntegratorCMState, (obj), TYPE_INTEGRATOR_CM)
  24
  25 typedef struct IntegratorCMState {
  26     /*< private >*/
  27     SysBusDevice parent_obj;
  28     /*< public >*/
  29
  30     MemoryRegion iomem;
  31     uint32_t memsz;
  32     MemoryRegion flash;
  33     uint32_t cm_osc;
  34     uint32_t cm_ctrl;
  35     uint32_t cm_lock;
  36     uint32_t cm_auxosc;
  37     uint32_t cm_sdram;
  38     uint32_t cm_init;
  39     uint32_t cm_flags;
  40     uint32_t cm_nvflags;
  41     uint32_t cm_refcnt_offset;
  42     uint32_t int_level;
  43     uint32_t irq_enabled;
  44     uint32_t fiq_enabled;
  45 } IntegratorCMState;
  46
  47 static uint8_t integrator_spd[128] = {
  48    128, 8, 4, 11, 9, 1, 64, 0,  2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
  49    0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
  50 };
  51
  52 static uint64_t integratorcm_read(void *opaque, hwaddr offset,
  53                                   unsigned size)
  54 {
  55     IntegratorCMState *s = opaque;
  56     if (offset >= 0x100 && offset < 0x200) {
  57         /* CM_SPD */
  58         if (offset >= 0x180)
  59             return 0;
  60         return integrator_spd[offset >> 2];
  61     }
  62     switch (offset >> 2) {
  63     case 0: /* CM_ID */
  64         return 0x411a3001;
  65     case 1: /* CM_PROC */
  66         return 0;
  67     case 2: /* CM_OSC */
  68         return s->cm_osc;
  69     case 3: /* CM_CTRL */
  70         return s->cm_ctrl;
  71     case 4: /* CM_STAT */
  72         return 0x00100000;
  73     case 5: /* CM_LOCK */
  74         if (s->cm_lock == 0xa05f) {
  75             return 0x1a05f;
  76         } else {
  77             return s->cm_lock;
  78         }
  79     case 6: /* CM_LMBUSCNT */
  80         /* ??? High frequency timer.  */
  81         hw_error("integratorcm_read: CM_LMBUSCNT");
  82     case 7: /* CM_AUXOSC */
  83         return s->cm_auxosc;
  84     case 8: /* CM_SDRAM */
  85         return s->cm_sdram;
  86     case 9: /* CM_INIT */
  87         return s->cm_init;
  88     case 10: /* CM_REFCNT */
  89         /* This register, CM_REFCNT, provides a 32-bit count value.
  90          * The count increments at the fixed reference clock frequency of 24MHz
  91          * and can be used as a real-time counter.
  92          */
  93         return (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
  94                                   1000) - s->cm_refcnt_offset;
  95     case 12: /* CM_FLAGS */
  96         return s->cm_flags;
  97     case 14: /* CM_NVFLAGS */
  98         return s->cm_nvflags;
  99     case 16: /* CM_IRQ_STAT */
 100         return s->int_level & s->irq_enabled;
 101     case 17: /* CM_IRQ_RSTAT */
 102         return s->int_level;
 103     case 18: /* CM_IRQ_ENSET */
 104         return s->irq_enabled;
 105     case 20: /* CM_SOFT_INTSET */
 106         return s->int_level & 1;
 107     case 24: /* CM_FIQ_STAT */
 108         return s->int_level & s->fiq_enabled;
 109     case 25: /* CM_FIQ_RSTAT */
 110         return s->int_level;
 111     case 26: /* CM_FIQ_ENSET */
 112         return s->fiq_enabled;
 113     case 32: /* CM_VOLTAGE_CTL0 */
 114     case 33: /* CM_VOLTAGE_CTL1 */
 115     case 34: /* CM_VOLTAGE_CTL2 */
 116     case 35: /* CM_VOLTAGE_CTL3 */
 117         /* ??? Voltage control unimplemented.  */
 118         return 0;
 119     default:
 120         hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
 121                  (int)offset);
 122         return 0;
 123     }
 124 }
 125
 126 static void integratorcm_do_remap(IntegratorCMState *s)
 127 {
 128     /* Sync memory region state with CM_CTRL REMAP bit:
 129      * bit 0 => flash at address 0; bit 1 => RAM
 130      */
 131     memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
 132 }
 133
 134 static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)
 135 {
 136     if (value & 8) {
 137         qemu_system_reset_request();
 138     }
 139     if ((s->cm_ctrl ^ value) & 1) {
 140         /* (value & 1) != 0 means the green "MISC LED" is lit.
 141          * We don't have any nice place to display LEDs. printf is a bad
 142          * idea because Linux uses the LED as a heartbeat and the output
 143          * will swamp anything else on the terminal.
 144          */
 145     }
 146     /* Note that the RESET bit [3] always reads as zero */
 147     s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
 148     integratorcm_do_remap(s);
 149 }
 150
 151 static void integratorcm_update(IntegratorCMState *s)
 152 {
 153     /* ??? The CPU irq/fiq is raised when either the core module or base PIC
 154        are active.  */
 155     if (s->int_level & (s->irq_enabled | s->fiq_enabled))
 156         hw_error("Core module interrupt\n");
 157 }
 158
 159 static void integratorcm_write(void *opaque, hwaddr offset,
 160                                uint64_t value, unsigned size)
 161 {
 162     IntegratorCMState *s = opaque;
 163     switch (offset >> 2) {
 164     case 2: /* CM_OSC */
 165         if (s->cm_lock == 0xa05f)
 166             s->cm_osc = value;
 167         break;
 168     case 3: /* CM_CTRL */
 169         integratorcm_set_ctrl(s, value);
 170         break;
 171     case 5: /* CM_LOCK */
 172         s->cm_lock = value & 0xffff;
 173         break;
 174     case 7: /* CM_AUXOSC */
 175         if (s->cm_lock == 0xa05f)
 176             s->cm_auxosc = value;
 177         break;
 178     case 8: /* CM_SDRAM */
 179         s->cm_sdram = value;
 180         break;
 181     case 9: /* CM_INIT */
 182         /* ??? This can change the memory bus frequency.  */
 183         s->cm_init = value;
 184         break;
 185     case 12: /* CM_FLAGSS */
 186         s->cm_flags |= value;
 187         break;
 188     case 13: /* CM_FLAGSC */
 189         s->cm_flags &= ~value;
 190         break;
 191     case 14: /* CM_NVFLAGSS */
 192         s->cm_nvflags |= value;
 193         break;
 194     case 15: /* CM_NVFLAGSS */
 195         s->cm_nvflags &= ~value;
 196         break;
 197     case 18: /* CM_IRQ_ENSET */
 198         s->irq_enabled |= value;
 199         integratorcm_update(s);
 200         break;
 201     case 19: /* CM_IRQ_ENCLR */
 202         s->irq_enabled &= ~value;
 203         integratorcm_update(s);
 204         break;
 205     case 20: /* CM_SOFT_INTSET */
 206         s->int_level |= (value & 1);
 207         integratorcm_update(s);
 208         break;
 209     case 21: /* CM_SOFT_INTCLR */
 210         s->int_level &= ~(value & 1);
 211         integratorcm_update(s);
 212         break;
 213     case 26: /* CM_FIQ_ENSET */
 214         s->fiq_enabled |= value;
 215         integratorcm_update(s);
 216         break;
 217     case 27: /* CM_FIQ_ENCLR */
 218         s->fiq_enabled &= ~value;
 219         integratorcm_update(s);
 220         break;
 221     case 32: /* CM_VOLTAGE_CTL0 */
 222     case 33: /* CM_VOLTAGE_CTL1 */
 223     case 34: /* CM_VOLTAGE_CTL2 */
 224     case 35: /* CM_VOLTAGE_CTL3 */
 225         /* ??? Voltage control unimplemented.  */
 226         break;
 227     default:
 228         hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
 229                  (int)offset);
 230         break;
 231     }
 232 }
 233
 234 /* Integrator/CM control registers.  */
 235
 236 static const MemoryRegionOps integratorcm_ops = {
 237     .read = integratorcm_read,
 238     .write = integratorcm_write,
 239     .endianness = DEVICE_NATIVE_ENDIAN,
 240 };
 241
 242 static int integratorcm_init(SysBusDevice *dev)
 243 {
 244     IntegratorCMState *s = INTEGRATOR_CM(dev);
 245
 246     s->cm_osc = 0x01000048;
 247     /* ??? What should the high bits of this value be?  */
 248     s->cm_auxosc = 0x0007feff;
 249     s->cm_sdram = 0x00011122;
 250     if (s->memsz >= 256) {
 251         integrator_spd[31] = 64;
 252         s->cm_sdram |= 0x10;
 253     } else if (s->memsz >= 128) {
 254         integrator_spd[31] = 32;
 255         s->cm_sdram |= 0x0c;
 256     } else if (s->memsz >= 64) {
 257         integrator_spd[31] = 16;
 258         s->cm_sdram |= 0x08;
 259     } else if (s->memsz >= 32) {
 260         integrator_spd[31] = 4;
 261         s->cm_sdram |= 0x04;
 262     } else {
 263         integrator_spd[31] = 2;
 264     }
 265     memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
 266     s->cm_init = 0x00000112;
 267     s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24,
 268                                    1000);
 269     memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000,
 270                            &error_fatal);
 271     vmstate_register_ram_global(&s->flash);
 272
 273     memory_region_init_io(&s->iomem, OBJECT(s), &integratorcm_ops, s,
 274                           "integratorcm", 0x00800000);
 275     sysbus_init_mmio(dev, &s->iomem);
 276
 277     integratorcm_do_remap(s);
 278     /* ??? Save/restore.  */
 279     return 0;
 280 }
 281
 282 /* Integrator/CP hardware emulation.  */
 283 /* Primary interrupt controller.  */
 284
 285 #define TYPE_INTEGRATOR_PIC "integrator_pic"
 286 #define INTEGRATOR_PIC(obj) \
 287    OBJECT_CHECK(icp_pic_state, (obj), TYPE_INTEGRATOR_PIC)
 288
 289 typedef struct icp_pic_state {
 290     /*< private >*/
 291     SysBusDevice parent_obj;
 292     /*< public >*/
 293
 294     MemoryRegion iomem;
 295     uint32_t level;
 296     uint32_t irq_enabled;
 297     uint32_t fiq_enabled;
 298     qemu_irq parent_irq;
 299     qemu_irq parent_fiq;
 300 } icp_pic_state;
 301
 302 static void icp_pic_update(icp_pic_state *s)
 303 {
 304     uint32_t flags;
 305
 306     flags = (s->level & s->irq_enabled);
 307     qemu_set_irq(s->parent_irq, flags != 0);
 308     flags = (s->level & s->fiq_enabled);
 309     qemu_set_irq(s->parent_fiq, flags != 0);
 310 }
 311
 312 static void icp_pic_set_irq(void *opaque, int irq, int level)
 313 {
 314     icp_pic_state *s = (icp_pic_state *)opaque;
 315     if (level)
 316         s->level |= 1 << irq;
 317     else
 318         s->level &= ~(1 << irq);
 319     icp_pic_update(s);
 320 }
 321
 322 static uint64_t icp_pic_read(void *opaque, hwaddr offset,
 323                              unsigned size)
 324 {
 325     icp_pic_state *s = (icp_pic_state *)opaque;
 326
 327     switch (offset >> 2) {
 328     case 0: /* IRQ_STATUS */
 329         return s->level & s->irq_enabled;
 330     case 1: /* IRQ_RAWSTAT */
 331         return s->level;
 332     case 2: /* IRQ_ENABLESET */
 333         return s->irq_enabled;
 334     case 4: /* INT_SOFTSET */
 335         return s->level & 1;
 336     case 8: /* FRQ_STATUS */
 337         return s->level & s->fiq_enabled;
 338     case 9: /* FRQ_RAWSTAT */
 339         return s->level;
 340     case 10: /* FRQ_ENABLESET */
 341         return s->fiq_enabled;
 342     case 3: /* IRQ_ENABLECLR */
 343     case 5: /* INT_SOFTCLR */
 344     case 11: /* FRQ_ENABLECLR */
 345     default:
 346         printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
 347         return 0;
 348     }
 349 }
 350
 351 static void icp_pic_write(void *opaque, hwaddr offset,
 352                           uint64_t value, unsigned size)
 353 {
 354     icp_pic_state *s = (icp_pic_state *)opaque;
 355
 356     switch (offset >> 2) {
 357     case 2: /* IRQ_ENABLESET */
 358         s->irq_enabled |= value;
 359         break;
 360     case 3: /* IRQ_ENABLECLR */
 361         s->irq_enabled &= ~value;
 362         break;
 363     case 4: /* INT_SOFTSET */
 364         if (value & 1)
 365             icp_pic_set_irq(s, 0, 1);
 366         break;
 367     case 5: /* INT_SOFTCLR */
 368         if (value & 1)
 369             icp_pic_set_irq(s, 0, 0);
 370         break;
 371     case 10: /* FRQ_ENABLESET */
 372         s->fiq_enabled |= value;
 373         break;
 374     case 11: /* FRQ_ENABLECLR */
 375         s->fiq_enabled &= ~value;
 376         break;
 377     case 0: /* IRQ_STATUS */
 378     case 1: /* IRQ_RAWSTAT */
 379     case 8: /* FRQ_STATUS */
 380     case 9: /* FRQ_RAWSTAT */
 381     default:
 382         printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
 383         return;
 384     }
 385     icp_pic_update(s);
 386 }
 387
 388 static const MemoryRegionOps icp_pic_ops = {
 389     .read = icp_pic_read,
 390     .write = icp_pic_write,
 391     .endianness = DEVICE_NATIVE_ENDIAN,
 392 };
 393
 394 static int icp_pic_init(SysBusDevice *sbd)
 395 {
 396     DeviceState *dev = DEVICE(sbd);
 397     icp_pic_state *s = INTEGRATOR_PIC(dev);
 398
 399     qdev_init_gpio_in(dev, icp_pic_set_irq, 32);
 400     sysbus_init_irq(sbd, &s->parent_irq);
 401     sysbus_init_irq(sbd, &s->parent_fiq);
 402     memory_region_init_io(&s->iomem, OBJECT(s), &icp_pic_ops, s,
 403                           "icp-pic", 0x00800000);
 404     sysbus_init_mmio(sbd, &s->iomem);
 405     return 0;
 406 }
 407
 408 /* CP control registers.  */
 409
 410 #define TYPE_ICP_CONTROL_REGS "icp-ctrl-regs"
 411 #define ICP_CONTROL_REGS(obj) \
 412     OBJECT_CHECK(ICPCtrlRegsState, (obj), TYPE_ICP_CONTROL_REGS)
 413
 414 typedef struct ICPCtrlRegsState {
 415     /*< private >*/
 416     SysBusDevice parent_obj;
 417     /*< public >*/
 418
 419     MemoryRegion iomem;
 420
 421     qemu_irq mmc_irq;
 422     uint32_t intreg_state;
 423 } ICPCtrlRegsState;
 424
 425 #define ICP_GPIO_MMC_WPROT      "mmc-wprot"
 426 #define ICP_GPIO_MMC_CARDIN     "mmc-cardin"
 427
 428 #define ICP_INTREG_WPROT        (1 << 0)
 429 #define ICP_INTREG_CARDIN       (1 << 3)
 430
 431 static uint64_t icp_control_read(void *opaque, hwaddr offset,
 432                                  unsigned size)
 433 {
 434     ICPCtrlRegsState *s = opaque;
 435
 436     switch (offset >> 2) {
 437     case 0: /* CP_IDFIELD */
 438         return 0x41034003;
 439     case 1: /* CP_FLASHPROG */
 440         return 0;
 441     case 2: /* CP_INTREG */
 442         return s->intreg_state;
 443     case 3: /* CP_DECODE */
 444         return 0x11;
 445     default:
 446         hw_error("icp_control_read: Bad offset %x\n", (int)offset);
 447         return 0;
 448     }
 449 }
 450
 451 static void icp_control_write(void *opaque, hwaddr offset,
 452                           uint64_t value, unsigned size)
 453 {
 454     ICPCtrlRegsState *s = opaque;
 455
 456     switch (offset >> 2) {
 457     case 2: /* CP_INTREG */
 458         s->intreg_state &= ~(value & ICP_INTREG_CARDIN);
 459         qemu_set_irq(s->mmc_irq, !!(s->intreg_state & ICP_INTREG_CARDIN));
 460         break;
 461     case 1: /* CP_FLASHPROG */
 462     case 3: /* CP_DECODE */
 463         /* Nothing interesting implemented yet.  */
 464         break;
 465     default:
 466         hw_error("icp_control_write: Bad offset %x\n", (int)offset);
 467     }
 468 }
 469
 470 static const MemoryRegionOps icp_control_ops = {
 471     .read = icp_control_read,
 472     .write = icp_control_write,
 473     .endianness = DEVICE_NATIVE_ENDIAN,
 474 };
 475
 476 static void icp_control_mmc_wprot(void *opaque, int line, int level)
 477 {
 478     ICPCtrlRegsState *s = opaque;
 479
 480     s->intreg_state &= ~ICP_INTREG_WPROT;
 481     if (level) {
 482         s->intreg_state |= ICP_INTREG_WPROT;
 483     }
 484 }
 485
 486 static void icp_control_mmc_cardin(void *opaque, int line, int level)
 487 {
 488     ICPCtrlRegsState *s = opaque;
 489
 490     /* line is released by writing to CP_INTREG */
 491     if (level) {
 492         s->intreg_state |= ICP_INTREG_CARDIN;
 493         qemu_set_irq(s->mmc_irq, 1);
 494     }
 495 }
 496
 497 static void icp_control_init(Object *obj)
 498 {
 499     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 500     ICPCtrlRegsState *s = ICP_CONTROL_REGS(obj);
 501     DeviceState *dev = DEVICE(obj);
 502
 503     memory_region_init_io(&s->iomem, OBJECT(s), &icp_control_ops, s,
 504                           "icp_ctrl_regs", 0x00800000);
 505     sysbus_init_mmio(sbd, &s->iomem);
 506
 507     qdev_init_gpio_in_named(dev, icp_control_mmc_wprot, ICP_GPIO_MMC_WPROT, 1);
 508     qdev_init_gpio_in_named(dev, icp_control_mmc_cardin,
 509                             ICP_GPIO_MMC_CARDIN, 1);
 510     sysbus_init_irq(sbd, &s->mmc_irq);
 511 }
 512
 513
 514 /* Board init.  */
 515
 516 static struct arm_boot_info integrator_binfo = {
 517     .loader_start = 0x0,
 518     .board_id = 0x113,
 519 };
 520
 521 static void integratorcp_init(MachineState *machine)
 522 {
 523     ram_addr_t ram_size = machine->ram_size;
 524     const char *cpu_model = machine->cpu_model;
 525     const char *kernel_filename = machine->kernel_filename;
 526     const char *kernel_cmdline = machine->kernel_cmdline;
 527     const char *initrd_filename = machine->initrd_filename;
 528     ObjectClass *cpu_oc;
 529     Object *cpuobj;
 530     ARMCPU *cpu;
 531     MemoryRegion *address_space_mem = get_system_memory();
 532     MemoryRegion *ram = g_new(MemoryRegion, 1);
 533     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
 534     qemu_irq pic[32];
 535     DeviceState *dev, *sic, *icp;
 536     int i;
 537
 538     if (!cpu_model) {
 539         cpu_model = "arm926";
 540     }
 541
 542     cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
 543     if (!cpu_oc) {
 544         fprintf(stderr, "Unable to find CPU definition\n");
 545         exit(1);
 546     }
 547
 548     cpuobj = object_new(object_class_get_name(cpu_oc));
 549
 550     /* By default ARM1176 CPUs have EL3 enabled.  This board does not
 551      * currently support EL3 so the CPU EL3 property is disabled before
 552      * realization.
 553      */
 554     if (object_property_find(cpuobj, "has_el3", NULL)) {
 555         object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
 556     }
 557
 558     object_property_set_bool(cpuobj, true, "realized", &error_fatal);
 559
 560     cpu = ARM_CPU(cpuobj);
 561
 562     memory_region_allocate_system_memory(ram, NULL, "integrator.ram",
 563                                          ram_size);
 564     /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash.  */
 565     /* ??? RAM should repeat to fill physical memory space.  */
 566     /* SDRAM at address zero*/
 567     memory_region_add_subregion(address_space_mem, 0, ram);
 568     /* And again at address 0x80000000 */
 569     memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
 570     memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
 571
 572     dev = qdev_create(NULL, TYPE_INTEGRATOR_CM);
 573     qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
 574     qdev_init_nofail(dev);
 575     sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
 576
 577     dev = sysbus_create_varargs(TYPE_INTEGRATOR_PIC, 0x14000000,
 578                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
 579                                 qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
 580                                 NULL);
 581     for (i = 0; i < 32; i++) {
 582         pic[i] = qdev_get_gpio_in(dev, i);
 583     }
 584     sic = sysbus_create_simple(TYPE_INTEGRATOR_PIC, 0xca000000, pic[26]);
 585     sysbus_create_varargs("integrator_pit", 0x13000000,
 586                           pic[5], pic[6], pic[7], NULL);
 587     sysbus_create_simple("pl031", 0x15000000, pic[8]);
 588     sysbus_create_simple("pl011", 0x16000000, pic[1]);
 589     sysbus_create_simple("pl011", 0x17000000, pic[2]);
 590     icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000,
 591                                qdev_get_gpio_in(sic, 3));
 592     sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
 593     sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
 594     sysbus_create_simple(TYPE_INTEGRATOR_DEBUG, 0x1a000000, 0);
 595
 596     dev = sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
 597     qdev_connect_gpio_out(dev, 0,
 598                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));
 599     qdev_connect_gpio_out(dev, 1,
 600                           qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));
 601
 602     if (nd_table[0].used)
 603         smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
 604
 605     sysbus_create_simple("pl110", 0xc0000000, pic[22]);
 606
 607     integrator_binfo.ram_size = ram_size;
 608     integrator_binfo.kernel_filename = kernel_filename;
 609     integrator_binfo.kernel_cmdline = kernel_cmdline;
 610     integrator_binfo.initrd_filename = initrd_filename;
 611     arm_load_kernel(cpu, &integrator_binfo);
 612 }
 613
 614 static void integratorcp_machine_init(MachineClass *mc)
 615 {
 616     mc->desc = "ARM Integrator/CP (ARM926EJ-S)";
 617     mc->init = integratorcp_init;
 618 }
 619
 620 DEFINE_MACHINE("integratorcp", integratorcp_machine_init)
 621
 622 static Property core_properties[] = {
 623     DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
 624     DEFINE_PROP_END_OF_LIST(),
 625 };
 626
 627 static void core_class_init(ObjectClass *klass, void *data)
 628 {
 629     DeviceClass *dc = DEVICE_CLASS(klass);
 630     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 631
 632     k->init = integratorcm_init;
 633     dc->props = core_properties;
 634 }
 635
 636 static const TypeInfo core_info = {
 637     .name          = TYPE_INTEGRATOR_CM,
 638     .parent        = TYPE_SYS_BUS_DEVICE,
 639     .instance_size = sizeof(IntegratorCMState),
 640     .class_init    = core_class_init,
 641 };
 642
 643 static void icp_pic_class_init(ObjectClass *klass, void *data)
 644 {
 645     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 646
 647     sdc->init = icp_pic_init;
 648 }
 649
 650 static const TypeInfo icp_pic_info = {
 651     .name          = TYPE_INTEGRATOR_PIC,
 652     .parent        = TYPE_SYS_BUS_DEVICE,
 653     .instance_size = sizeof(icp_pic_state),
 654     .class_init    = icp_pic_class_init,
 655 };
 656
 657 static const TypeInfo icp_ctrl_regs_info = {
 658     .name          = TYPE_ICP_CONTROL_REGS,
 659     .parent        = TYPE_SYS_BUS_DEVICE,
 660     .instance_size = sizeof(ICPCtrlRegsState),
 661     .instance_init = icp_control_init,
 662 };
 663
 664 static void integratorcp_register_types(void)
 665 {
 666     type_register_static(&icp_pic_info);
 667     type_register_static(&core_info);
 668     type_register_static(&icp_ctrl_regs_info);
 669 }
 670
 671 type_init(integratorcp_register_types)