target-unicore32/helper.c

   1 /*
   2  * Copyright (C) 2010-2011 GUAN Xue-tao
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <stdio.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11
  12 #include "cpu.h"
  13 #include "exec-all.h"
  14 #include "gdbstub.h"
  15 #include "helper.h"
  16 #include "qemu-common.h"
  17 #include "host-utils.h"
  18
  19 static inline void set_feature(CPUState *env, int feature)
  20 {
  21     env->features |= feature;
  22 }
  23
  24 struct uc32_cpu_t {
  25     uint32_t id;
  26     const char *name;
  27 };
  28
  29 static const struct uc32_cpu_t uc32_cpu_names[] = {
  30     { UC32_CPUID_UCV2, "UniCore-II"},
  31     { UC32_CPUID_ANY, "any"},
  32     { 0, NULL}
  33 };
  34
  35 /* return 0 if not found */
  36 static uint32_t uc32_cpu_find_by_name(const char *name)
  37 {
  38     int i;
  39     uint32_t id;
  40
  41     id = 0;
  42     for (i = 0; uc32_cpu_names[i].name; i++) {
  43         if (strcmp(name, uc32_cpu_names[i].name) == 0) {
  44             id = uc32_cpu_names[i].id;
  45             break;
  46         }
  47     }
  48     return id;
  49 }
  50
  51 CPUState *uc32_cpu_init(const char *cpu_model)
  52 {
  53     CPUState *env;
  54     uint32_t id;
  55     static int inited = 1;
  56
  57     env = qemu_mallocz(sizeof(CPUState));
  58     cpu_exec_init(env);
  59
  60     id = uc32_cpu_find_by_name(cpu_model);
  61     switch (id) {
  62     case UC32_CPUID_UCV2:
  63         set_feature(env, UC32_HWCAP_CMOV);
  64         set_feature(env, UC32_HWCAP_UCF64);
  65         env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
  66         env->cp0.c0_cachetype = 0x1dd20d2;
  67         env->cp0.c1_sys = 0x00090078;
  68         break;
  69     case UC32_CPUID_ANY: /* For userspace emulation.  */
  70         set_feature(env, UC32_HWCAP_CMOV);
  71         set_feature(env, UC32_HWCAP_UCF64);
  72         break;
  73     default:
  74         cpu_abort(env, "Bad CPU ID: %x\n", id);
  75     }
  76
  77     env->cpu_model_str = cpu_model;
  78     env->cp0.c0_cpuid = id;
  79     env->uncached_asr = ASR_MODE_USER;
  80     env->regs[31] = 0;
  81
  82     if (inited) {
  83         inited = 0;
  84         uc32_translate_init();
  85     }
  86
  87     tlb_flush(env, 1);
  88     qemu_init_vcpu(env);
  89     return env;
  90 }
  91
  92 uint32_t HELPER(clo)(uint32_t x)
  93 {
  94     return clo32(x);
  95 }
  96
  97 uint32_t HELPER(clz)(uint32_t x)
  98 {
  99     return clz32(x);
 100 }
 101
 102 void do_interrupt(CPUState *env)
 103 {
 104     env->exception_index = -1;
 105 }
 106
 107 int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
 108                               int mmu_idx, int is_softmmu)
 109 {
 110     env->exception_index = UC32_EXCP_TRAP;
 111     env->cp0.c4_faultaddr = address;
 112     return 1;
 113 }
 114
 115 /* These should probably raise undefined insn exceptions.  */
 116 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
 117 {
 118     int op1 = (insn >> 8) & 0xf;
 119     cpu_abort(env, "cp%i insn %08x\n", op1, insn);
 120     return;
 121 }
 122
 123 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
 124 {
 125     int op1 = (insn >> 8) & 0xf;
 126     cpu_abort(env, "cp%i insn %08x\n", op1, insn);
 127     return 0;
 128 }
 129
 130 void HELPER(set_cp0)(CPUState *env, uint32_t insn, uint32_t val)
 131 {
 132     cpu_abort(env, "cp0 insn %08x\n", insn);
 133 }
 134
 135 uint32_t HELPER(get_cp0)(CPUState *env, uint32_t insn)
 136 {
 137     cpu_abort(env, "cp0 insn %08x\n", insn);
 138     return 0;
 139 }
 140
 141 void switch_mode(CPUState *env, int mode)
 142 {
 143     if (mode != ASR_MODE_USER) {
 144         cpu_abort(env, "Tried to switch out of user mode\n");
 145     }
 146 }
 147
 148 void HELPER(set_r29_banked)(CPUState *env, uint32_t mode, uint32_t val)
 149 {
 150     cpu_abort(env, "banked r29 write\n");
 151 }
 152
 153 uint32_t HELPER(get_r29_banked)(CPUState *env, uint32_t mode)
 154 {
 155     cpu_abort(env, "banked r29 read\n");
 156     return 0;
 157 }
 158
 159 /* UniCore-F64 support.  We follow the convention used for F64 instrunctions:
 160    Single precition routines have a "s" suffix, double precision a
 161    "d" suffix.  */
 162
 163 /* Convert host exception flags to f64 form.  */
 164 static inline int ucf64_exceptbits_from_host(int host_bits)
 165 {
 166     int target_bits = 0;
 167
 168     if (host_bits & float_flag_invalid) {
 169         target_bits |= UCF64_FPSCR_FLAG_INVALID;
 170     }
 171     if (host_bits & float_flag_divbyzero) {
 172         target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
 173     }
 174     if (host_bits & float_flag_overflow) {
 175         target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
 176     }
 177     if (host_bits & float_flag_underflow) {
 178         target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
 179     }
 180     if (host_bits & float_flag_inexact) {
 181         target_bits |= UCF64_FPSCR_FLAG_INEXACT;
 182     }
 183     return target_bits;
 184 }
 185
 186 uint32_t HELPER(ucf64_get_fpscr)(CPUState *env)
 187 {
 188     int i;
 189     uint32_t fpscr;
 190
 191     fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
 192     i = get_float_exception_flags(&env->ucf64.fp_status);
 193     fpscr |= ucf64_exceptbits_from_host(i);
 194     return fpscr;
 195 }
 196
 197 /* Convert ucf64 exception flags to target form.  */
 198 static inline int ucf64_exceptbits_to_host(int target_bits)
 199 {
 200     int host_bits = 0;
 201
 202     if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
 203         host_bits |= float_flag_invalid;
 204     }
 205     if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
 206         host_bits |= float_flag_divbyzero;
 207     }
 208     if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
 209         host_bits |= float_flag_overflow;
 210     }
 211     if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
 212         host_bits |= float_flag_underflow;
 213     }
 214     if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
 215         host_bits |= float_flag_inexact;
 216     }
 217     return host_bits;
 218 }
 219
 220 void HELPER(ucf64_set_fpscr)(CPUState *env, uint32_t val)
 221 {
 222     int i;
 223     uint32_t changed;
 224
 225     changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
 226     env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
 227
 228     changed ^= val;
 229     if (changed & (UCF64_FPSCR_RND_MASK)) {
 230         i = UCF64_FPSCR_RND(val);
 231         switch (i) {
 232         case 0:
 233             i = float_round_nearest_even;
 234             break;
 235         case 1:
 236             i = float_round_to_zero;
 237             break;
 238         case 2:
 239             i = float_round_up;
 240             break;
 241         case 3:
 242             i = float_round_down;
 243             break;
 244         default: /* 100 and 101 not implement */
 245             cpu_abort(env, "Unsupported UniCore-F64 round mode");
 246         }
 247         set_float_rounding_mode(i, &env->ucf64.fp_status);
 248     }
 249
 250     i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
 251     set_float_exception_flags(i, &env->ucf64.fp_status);
 252 }
 253
 254 float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUState *env)
 255 {
 256     return float32_add(a, b, &env->ucf64.fp_status);
 257 }
 258
 259 float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUState *env)
 260 {
 261     return float64_add(a, b, &env->ucf64.fp_status);
 262 }
 263
 264 float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUState *env)
 265 {
 266     return float32_sub(a, b, &env->ucf64.fp_status);
 267 }
 268
 269 float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUState *env)
 270 {
 271     return float64_sub(a, b, &env->ucf64.fp_status);
 272 }
 273
 274 float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUState *env)
 275 {
 276     return float32_mul(a, b, &env->ucf64.fp_status);
 277 }
 278
 279 float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUState *env)
 280 {
 281     return float64_mul(a, b, &env->ucf64.fp_status);
 282 }
 283
 284 float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUState *env)
 285 {
 286     return float32_div(a, b, &env->ucf64.fp_status);
 287 }
 288
 289 float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUState *env)
 290 {
 291     return float64_div(a, b, &env->ucf64.fp_status);
 292 }
 293
 294 float32 HELPER(ucf64_negs)(float32 a)
 295 {
 296     return float32_chs(a);
 297 }
 298
 299 float64 HELPER(ucf64_negd)(float64 a)
 300 {
 301     return float64_chs(a);
 302 }
 303
 304 float32 HELPER(ucf64_abss)(float32 a)
 305 {
 306     return float32_abs(a);
 307 }
 308
 309 float64 HELPER(ucf64_absd)(float64 a)
 310 {
 311     return float64_abs(a);
 312 }
 313
 314 /* XXX: check quiet/signaling case */
 315 void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c, CPUState *env)
 316 {
 317     int flag;
 318     flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
 319     env->CF = 0;
 320     switch (c & 0x7) {
 321     case 0: /* F */
 322         break;
 323     case 1: /* UN */
 324         if (flag == 2) {
 325             env->CF = 1;
 326         }
 327         break;
 328     case 2: /* EQ */
 329         if (flag == 0) {
 330             env->CF = 1;
 331         }
 332         break;
 333     case 3: /* UEQ */
 334         if ((flag == 0) || (flag == 2)) {
 335             env->CF = 1;
 336         }
 337         break;
 338     case 4: /* OLT */
 339         if (flag == -1) {
 340             env->CF = 1;
 341         }
 342         break;
 343     case 5: /* ULT */
 344         if ((flag == -1) || (flag == 2)) {
 345             env->CF = 1;
 346         }
 347         break;
 348     case 6: /* OLE */
 349         if ((flag == -1) || (flag == 0)) {
 350             env->CF = 1;
 351         }
 352         break;
 353     case 7: /* ULE */
 354         if (flag != 1) {
 355             env->CF = 1;
 356         }
 357         break;
 358     }
 359     env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
 360                     | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
 361 }
 362
 363 void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c, CPUState *env)
 364 {
 365     int flag;
 366     flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
 367     env->CF = 0;
 368     switch (c & 0x7) {
 369     case 0: /* F */
 370         break;
 371     case 1: /* UN */
 372         if (flag == 2) {
 373             env->CF = 1;
 374         }
 375         break;
 376     case 2: /* EQ */
 377         if (flag == 0) {
 378             env->CF = 1;
 379         }
 380         break;
 381     case 3: /* UEQ */
 382         if ((flag == 0) || (flag == 2)) {
 383             env->CF = 1;
 384         }
 385         break;
 386     case 4: /* OLT */
 387         if (flag == -1) {
 388             env->CF = 1;
 389         }
 390         break;
 391     case 5: /* ULT */
 392         if ((flag == -1) || (flag == 2)) {
 393             env->CF = 1;
 394         }
 395         break;
 396     case 6: /* OLE */
 397         if ((flag == -1) || (flag == 0)) {
 398             env->CF = 1;
 399         }
 400         break;
 401     case 7: /* ULE */
 402         if (flag != 1) {
 403             env->CF = 1;
 404         }
 405         break;
 406     }
 407     env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
 408                     | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
 409 }
 410
 411 /* Helper routines to perform bitwise copies between float and int.  */
 412 static inline float32 ucf64_itos(uint32_t i)
 413 {
 414     union {
 415         uint32_t i;
 416         float32 s;
 417     } v;
 418
 419     v.i = i;
 420     return v.s;
 421 }
 422
 423 static inline uint32_t ucf64_stoi(float32 s)
 424 {
 425     union {
 426         uint32_t i;
 427         float32 s;
 428     } v;
 429
 430     v.s = s;
 431     return v.i;
 432 }
 433
 434 static inline float64 ucf64_itod(uint64_t i)
 435 {
 436     union {
 437         uint64_t i;
 438         float64 d;
 439     } v;
 440
 441     v.i = i;
 442     return v.d;
 443 }
 444
 445 static inline uint64_t ucf64_dtoi(float64 d)
 446 {
 447     union {
 448         uint64_t i;
 449         float64 d;
 450     } v;
 451
 452     v.d = d;
 453     return v.i;
 454 }
 455
 456 /* Integer to float conversion.  */
 457 float32 HELPER(ucf64_si2sf)(float32 x, CPUState *env)
 458 {
 459     return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
 460 }
 461
 462 float64 HELPER(ucf64_si2df)(float32 x, CPUState *env)
 463 {
 464     return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
 465 }
 466
 467 /* Float to integer conversion.  */
 468 float32 HELPER(ucf64_sf2si)(float32 x, CPUState *env)
 469 {
 470     return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
 471 }
 472
 473 float32 HELPER(ucf64_df2si)(float64 x, CPUState *env)
 474 {
 475     return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
 476 }
 477
 478 /* floating point conversion */
 479 float64 HELPER(ucf64_sf2df)(float32 x, CPUState *env)
 480 {
 481     return float32_to_float64(x, &env->ucf64.fp_status);
 482 }
 483
 484 float32 HELPER(ucf64_df2sf)(float64 x, CPUState *env)
 485 {
 486     return float64_to_float32(x, &env->ucf64.fp_status);
 487 }