4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
37 #define ENABLE_ARCH_4T arm_feature(env, ARM_FEATURE_V4T)
38 #define ENABLE_ARCH_5 arm_feature(env, ARM_FEATURE_V5)
39 /* currently all emulated v5 cores are also v5TE, so don't bother */
40 #define ENABLE_ARCH_5TE arm_feature(env, ARM_FEATURE_V5)
41 #define ENABLE_ARCH_5J 0
42 #define ENABLE_ARCH_6 arm_feature(env, ARM_FEATURE_V6)
43 #define ENABLE_ARCH_6K arm_feature(env, ARM_FEATURE_V6K)
44 #define ENABLE_ARCH_6T2 arm_feature(env, ARM_FEATURE_THUMB2)
45 #define ENABLE_ARCH_7 arm_feature(env, ARM_FEATURE_V7)
47 #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0)
49 /* internal defines */
50 typedef struct DisasContext
{
53 /* Nonzero if this instruction has been conditionally skipped. */
55 /* The label that will be jumped to when the instruction is skipped. */
57 /* Thumb-2 condtional execution bits. */
60 struct TranslationBlock
*tb
;
61 int singlestep_enabled
;
63 #if !defined(CONFIG_USER_ONLY)
71 static uint32_t gen_opc_condexec_bits
[OPC_BUF_SIZE
];
73 #if defined(CONFIG_USER_ONLY)
76 #define IS_USER(s) (s->user)
79 /* These instructions trap after executing, so defer them until after the
80 conditional executions state has been updated. */
84 static TCGv_ptr cpu_env
;
85 /* We reuse the same 64-bit temporaries for efficiency. */
86 static TCGv_i64 cpu_V0
, cpu_V1
, cpu_M0
;
87 static TCGv_i32 cpu_R
[16];
88 static TCGv_i32 cpu_exclusive_addr
;
89 static TCGv_i32 cpu_exclusive_val
;
90 static TCGv_i32 cpu_exclusive_high
;
91 #ifdef CONFIG_USER_ONLY
92 static TCGv_i32 cpu_exclusive_test
;
93 static TCGv_i32 cpu_exclusive_info
;
96 /* FIXME: These should be removed. */
97 static TCGv cpu_F0s
, cpu_F1s
;
98 static TCGv_i64 cpu_F0d
, cpu_F1d
;
100 #include "gen-icount.h"
102 static const char *regnames
[] =
103 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" };
106 /* initialize TCG globals. */
107 void arm_translate_init(void)
111 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
113 for (i
= 0; i
< 16; i
++) {
114 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
115 offsetof(CPUState
, regs
[i
]),
118 cpu_exclusive_addr
= tcg_global_mem_new_i32(TCG_AREG0
,
119 offsetof(CPUState
, exclusive_addr
), "exclusive_addr");
120 cpu_exclusive_val
= tcg_global_mem_new_i32(TCG_AREG0
,
121 offsetof(CPUState
, exclusive_val
), "exclusive_val");
122 cpu_exclusive_high
= tcg_global_mem_new_i32(TCG_AREG0
,
123 offsetof(CPUState
, exclusive_high
), "exclusive_high");
124 #ifdef CONFIG_USER_ONLY
125 cpu_exclusive_test
= tcg_global_mem_new_i32(TCG_AREG0
,
126 offsetof(CPUState
, exclusive_test
), "exclusive_test");
127 cpu_exclusive_info
= tcg_global_mem_new_i32(TCG_AREG0
,
128 offsetof(CPUState
, exclusive_info
), "exclusive_info");
135 static inline TCGv
load_cpu_offset(int offset
)
137 TCGv tmp
= tcg_temp_new_i32();
138 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
142 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
144 static inline void store_cpu_offset(TCGv var
, int offset
)
146 tcg_gen_st_i32(var
, cpu_env
, offset
);
147 tcg_temp_free_i32(var
);
150 #define store_cpu_field(var, name) \
151 store_cpu_offset(var, offsetof(CPUState, name))
153 /* Set a variable to the value of a CPU register. */
154 static void load_reg_var(DisasContext
*s
, TCGv var
, int reg
)
158 /* normaly, since we updated PC, we need only to add one insn */
160 addr
= (long)s
->pc
+ 2;
162 addr
= (long)s
->pc
+ 4;
163 tcg_gen_movi_i32(var
, addr
);
165 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
169 /* Create a new temporary and set it to the value of a CPU register. */
170 static inline TCGv
load_reg(DisasContext
*s
, int reg
)
172 TCGv tmp
= tcg_temp_new_i32();
173 load_reg_var(s
, tmp
, reg
);
177 /* Set a CPU register. The source must be a temporary and will be
179 static void store_reg(DisasContext
*s
, int reg
, TCGv var
)
182 tcg_gen_andi_i32(var
, var
, ~1);
183 s
->is_jmp
= DISAS_JUMP
;
185 tcg_gen_mov_i32(cpu_R
[reg
], var
);
186 tcg_temp_free_i32(var
);
189 /* Value extensions. */
190 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
191 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
192 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
193 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
195 #define gen_sxtb16(var) gen_helper_sxtb16(var, var)
196 #define gen_uxtb16(var) gen_helper_uxtb16(var, var)
199 static inline void gen_set_cpsr(TCGv var
, uint32_t mask
)
201 TCGv tmp_mask
= tcg_const_i32(mask
);
202 gen_helper_cpsr_write(var
, tmp_mask
);
203 tcg_temp_free_i32(tmp_mask
);
205 /* Set NZCV flags from the high 4 bits of var. */
206 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
208 static void gen_exception(int excp
)
210 TCGv tmp
= tcg_temp_new_i32();
211 tcg_gen_movi_i32(tmp
, excp
);
212 gen_helper_exception(tmp
);
213 tcg_temp_free_i32(tmp
);
216 static void gen_smul_dual(TCGv a
, TCGv b
)
218 TCGv tmp1
= tcg_temp_new_i32();
219 TCGv tmp2
= tcg_temp_new_i32();
220 tcg_gen_ext16s_i32(tmp1
, a
);
221 tcg_gen_ext16s_i32(tmp2
, b
);
222 tcg_gen_mul_i32(tmp1
, tmp1
, tmp2
);
223 tcg_temp_free_i32(tmp2
);
224 tcg_gen_sari_i32(a
, a
, 16);
225 tcg_gen_sari_i32(b
, b
, 16);
226 tcg_gen_mul_i32(b
, b
, a
);
227 tcg_gen_mov_i32(a
, tmp1
);
228 tcg_temp_free_i32(tmp1
);
231 /* Byteswap each halfword. */
232 static void gen_rev16(TCGv var
)
234 TCGv tmp
= tcg_temp_new_i32();
235 tcg_gen_shri_i32(tmp
, var
, 8);
236 tcg_gen_andi_i32(tmp
, tmp
, 0x00ff00ff);
237 tcg_gen_shli_i32(var
, var
, 8);
238 tcg_gen_andi_i32(var
, var
, 0xff00ff00);
239 tcg_gen_or_i32(var
, var
, tmp
);
240 tcg_temp_free_i32(tmp
);
243 /* Byteswap low halfword and sign extend. */
244 static void gen_revsh(TCGv var
)
246 tcg_gen_ext16u_i32(var
, var
);
247 tcg_gen_bswap16_i32(var
, var
);
248 tcg_gen_ext16s_i32(var
, var
);
251 /* Unsigned bitfield extract. */
252 static void gen_ubfx(TCGv var
, int shift
, uint32_t mask
)
255 tcg_gen_shri_i32(var
, var
, shift
);
256 tcg_gen_andi_i32(var
, var
, mask
);
259 /* Signed bitfield extract. */
260 static void gen_sbfx(TCGv var
, int shift
, int width
)
265 tcg_gen_sari_i32(var
, var
, shift
);
266 if (shift
+ width
< 32) {
267 signbit
= 1u << (width
- 1);
268 tcg_gen_andi_i32(var
, var
, (1u << width
) - 1);
269 tcg_gen_xori_i32(var
, var
, signbit
);
270 tcg_gen_subi_i32(var
, var
, signbit
);
274 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
275 static void gen_bfi(TCGv dest
, TCGv base
, TCGv val
, int shift
, uint32_t mask
)
277 tcg_gen_andi_i32(val
, val
, mask
);
278 tcg_gen_shli_i32(val
, val
, shift
);
279 tcg_gen_andi_i32(base
, base
, ~(mask
<< shift
));
280 tcg_gen_or_i32(dest
, base
, val
);
283 /* Return (b << 32) + a. Mark inputs as dead */
284 static TCGv_i64
gen_addq_msw(TCGv_i64 a
, TCGv b
)
286 TCGv_i64 tmp64
= tcg_temp_new_i64();
288 tcg_gen_extu_i32_i64(tmp64
, b
);
289 tcg_temp_free_i32(b
);
290 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
291 tcg_gen_add_i64(a
, tmp64
, a
);
293 tcg_temp_free_i64(tmp64
);
297 /* Return (b << 32) - a. Mark inputs as dead. */
298 static TCGv_i64
gen_subq_msw(TCGv_i64 a
, TCGv b
)
300 TCGv_i64 tmp64
= tcg_temp_new_i64();
302 tcg_gen_extu_i32_i64(tmp64
, b
);
303 tcg_temp_free_i32(b
);
304 tcg_gen_shli_i64(tmp64
, tmp64
, 32);
305 tcg_gen_sub_i64(a
, tmp64
, a
);
307 tcg_temp_free_i64(tmp64
);
311 /* FIXME: Most targets have native widening multiplication.
312 It would be good to use that instead of a full wide multiply. */
313 /* 32x32->64 multiply. Marks inputs as dead. */
314 static TCGv_i64
gen_mulu_i64_i32(TCGv a
, TCGv b
)
316 TCGv_i64 tmp1
= tcg_temp_new_i64();
317 TCGv_i64 tmp2
= tcg_temp_new_i64();
319 tcg_gen_extu_i32_i64(tmp1
, a
);
320 tcg_temp_free_i32(a
);
321 tcg_gen_extu_i32_i64(tmp2
, b
);
322 tcg_temp_free_i32(b
);
323 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
324 tcg_temp_free_i64(tmp2
);
328 static TCGv_i64
gen_muls_i64_i32(TCGv a
, TCGv b
)
330 TCGv_i64 tmp1
= tcg_temp_new_i64();
331 TCGv_i64 tmp2
= tcg_temp_new_i64();
333 tcg_gen_ext_i32_i64(tmp1
, a
);
334 tcg_temp_free_i32(a
);
335 tcg_gen_ext_i32_i64(tmp2
, b
);
336 tcg_temp_free_i32(b
);
337 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
338 tcg_temp_free_i64(tmp2
);
342 /* Swap low and high halfwords. */
343 static void gen_swap_half(TCGv var
)
345 TCGv tmp
= tcg_temp_new_i32();
346 tcg_gen_shri_i32(tmp
, var
, 16);
347 tcg_gen_shli_i32(var
, var
, 16);
348 tcg_gen_or_i32(var
, var
, tmp
);
349 tcg_temp_free_i32(tmp
);
352 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
353 tmp = (t0 ^ t1) & 0x8000;
356 t0 = (t0 + t1) ^ tmp;
359 static void gen_add16(TCGv t0
, TCGv t1
)
361 TCGv tmp
= tcg_temp_new_i32();
362 tcg_gen_xor_i32(tmp
, t0
, t1
);
363 tcg_gen_andi_i32(tmp
, tmp
, 0x8000);
364 tcg_gen_andi_i32(t0
, t0
, ~0x8000);
365 tcg_gen_andi_i32(t1
, t1
, ~0x8000);
366 tcg_gen_add_i32(t0
, t0
, t1
);
367 tcg_gen_xor_i32(t0
, t0
, tmp
);
368 tcg_temp_free_i32(tmp
);
369 tcg_temp_free_i32(t1
);
372 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
374 /* Set CF to the top bit of var. */
375 static void gen_set_CF_bit31(TCGv var
)
377 TCGv tmp
= tcg_temp_new_i32();
378 tcg_gen_shri_i32(tmp
, var
, 31);
380 tcg_temp_free_i32(tmp
);
383 /* Set N and Z flags from var. */
384 static inline void gen_logic_CC(TCGv var
)
386 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, NF
));
387 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, ZF
));
391 static void gen_adc(TCGv t0
, TCGv t1
)
394 tcg_gen_add_i32(t0
, t0
, t1
);
395 tmp
= load_cpu_field(CF
);
396 tcg_gen_add_i32(t0
, t0
, tmp
);
397 tcg_temp_free_i32(tmp
);
400 /* dest = T0 + T1 + CF. */
401 static void gen_add_carry(TCGv dest
, TCGv t0
, TCGv t1
)
404 tcg_gen_add_i32(dest
, t0
, t1
);
405 tmp
= load_cpu_field(CF
);
406 tcg_gen_add_i32(dest
, dest
, tmp
);
407 tcg_temp_free_i32(tmp
);
410 /* dest = T0 - T1 + CF - 1. */
411 static void gen_sub_carry(TCGv dest
, TCGv t0
, TCGv t1
)
414 tcg_gen_sub_i32(dest
, t0
, t1
);
415 tmp
= load_cpu_field(CF
);
416 tcg_gen_add_i32(dest
, dest
, tmp
);
417 tcg_gen_subi_i32(dest
, dest
, 1);
418 tcg_temp_free_i32(tmp
);
421 /* FIXME: Implement this natively. */
422 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
424 static void shifter_out_im(TCGv var
, int shift
)
426 TCGv tmp
= tcg_temp_new_i32();
428 tcg_gen_andi_i32(tmp
, var
, 1);
430 tcg_gen_shri_i32(tmp
, var
, shift
);
432 tcg_gen_andi_i32(tmp
, tmp
, 1);
435 tcg_temp_free_i32(tmp
);
438 /* Shift by immediate. Includes special handling for shift == 0. */
439 static inline void gen_arm_shift_im(TCGv var
, int shiftop
, int shift
, int flags
)
445 shifter_out_im(var
, 32 - shift
);
446 tcg_gen_shli_i32(var
, var
, shift
);
452 tcg_gen_shri_i32(var
, var
, 31);
455 tcg_gen_movi_i32(var
, 0);
458 shifter_out_im(var
, shift
- 1);
459 tcg_gen_shri_i32(var
, var
, shift
);
466 shifter_out_im(var
, shift
- 1);
469 tcg_gen_sari_i32(var
, var
, shift
);
471 case 3: /* ROR/RRX */
474 shifter_out_im(var
, shift
- 1);
475 tcg_gen_rotri_i32(var
, var
, shift
); break;
477 TCGv tmp
= load_cpu_field(CF
);
479 shifter_out_im(var
, 0);
480 tcg_gen_shri_i32(var
, var
, 1);
481 tcg_gen_shli_i32(tmp
, tmp
, 31);
482 tcg_gen_or_i32(var
, var
, tmp
);
483 tcg_temp_free_i32(tmp
);
488 static inline void gen_arm_shift_reg(TCGv var
, int shiftop
,
489 TCGv shift
, int flags
)
493 case 0: gen_helper_shl_cc(var
, var
, shift
); break;
494 case 1: gen_helper_shr_cc(var
, var
, shift
); break;
495 case 2: gen_helper_sar_cc(var
, var
, shift
); break;
496 case 3: gen_helper_ror_cc(var
, var
, shift
); break;
500 case 0: gen_helper_shl(var
, var
, shift
); break;
501 case 1: gen_helper_shr(var
, var
, shift
); break;
502 case 2: gen_helper_sar(var
, var
, shift
); break;
503 case 3: tcg_gen_andi_i32(shift
, shift
, 0x1f);
504 tcg_gen_rotr_i32(var
, var
, shift
); break;
507 tcg_temp_free_i32(shift
);
510 #define PAS_OP(pfx) \
512 case 0: gen_pas_helper(glue(pfx,add16)); break; \
513 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
514 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
515 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
516 case 4: gen_pas_helper(glue(pfx,add8)); break; \
517 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
519 static void gen_arm_parallel_addsub(int op1
, int op2
, TCGv a
, TCGv b
)
524 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
526 tmp
= tcg_temp_new_ptr();
527 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
529 tcg_temp_free_ptr(tmp
);
532 tmp
= tcg_temp_new_ptr();
533 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
535 tcg_temp_free_ptr(tmp
);
537 #undef gen_pas_helper
538 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
551 #undef gen_pas_helper
556 /* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
557 #define PAS_OP(pfx) \
559 case 0: gen_pas_helper(glue(pfx,add8)); break; \
560 case 1: gen_pas_helper(glue(pfx,add16)); break; \
561 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
562 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
563 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
564 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
566 static void gen_thumb2_parallel_addsub(int op1
, int op2
, TCGv a
, TCGv b
)
571 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
573 tmp
= tcg_temp_new_ptr();
574 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
576 tcg_temp_free_ptr(tmp
);
579 tmp
= tcg_temp_new_ptr();
580 tcg_gen_addi_ptr(tmp
, cpu_env
, offsetof(CPUState
, GE
));
582 tcg_temp_free_ptr(tmp
);
584 #undef gen_pas_helper
585 #define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
598 #undef gen_pas_helper
603 static void gen_test_cc(int cc
, int label
)
611 tmp
= load_cpu_field(ZF
);
612 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
615 tmp
= load_cpu_field(ZF
);
616 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
619 tmp
= load_cpu_field(CF
);
620 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
623 tmp
= load_cpu_field(CF
);
624 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
627 tmp
= load_cpu_field(NF
);
628 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
631 tmp
= load_cpu_field(NF
);
632 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
635 tmp
= load_cpu_field(VF
);
636 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
639 tmp
= load_cpu_field(VF
);
640 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
642 case 8: /* hi: C && !Z */
643 inv
= gen_new_label();
644 tmp
= load_cpu_field(CF
);
645 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
646 tcg_temp_free_i32(tmp
);
647 tmp
= load_cpu_field(ZF
);
648 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
651 case 9: /* ls: !C || Z */
652 tmp
= load_cpu_field(CF
);
653 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
654 tcg_temp_free_i32(tmp
);
655 tmp
= load_cpu_field(ZF
);
656 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
658 case 10: /* ge: N == V -> N ^ V == 0 */
659 tmp
= load_cpu_field(VF
);
660 tmp2
= load_cpu_field(NF
);
661 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
662 tcg_temp_free_i32(tmp2
);
663 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
665 case 11: /* lt: N != V -> N ^ V != 0 */
666 tmp
= load_cpu_field(VF
);
667 tmp2
= load_cpu_field(NF
);
668 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
669 tcg_temp_free_i32(tmp2
);
670 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
672 case 12: /* gt: !Z && N == V */
673 inv
= gen_new_label();
674 tmp
= load_cpu_field(ZF
);
675 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
676 tcg_temp_free_i32(tmp
);
677 tmp
= load_cpu_field(VF
);
678 tmp2
= load_cpu_field(NF
);
679 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
680 tcg_temp_free_i32(tmp2
);
681 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
684 case 13: /* le: Z || N != V */
685 tmp
= load_cpu_field(ZF
);
686 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
687 tcg_temp_free_i32(tmp
);
688 tmp
= load_cpu_field(VF
);
689 tmp2
= load_cpu_field(NF
);
690 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
691 tcg_temp_free_i32(tmp2
);
692 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
695 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
698 tcg_temp_free_i32(tmp
);
701 static const uint8_t table_logic_cc
[16] = {
720 /* Set PC and Thumb state from an immediate address. */
721 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
725 s
->is_jmp
= DISAS_UPDATE
;
726 if (s
->thumb
!= (addr
& 1)) {
727 tmp
= tcg_temp_new_i32();
728 tcg_gen_movi_i32(tmp
, addr
& 1);
729 tcg_gen_st_i32(tmp
, cpu_env
, offsetof(CPUState
, thumb
));
730 tcg_temp_free_i32(tmp
);
732 tcg_gen_movi_i32(cpu_R
[15], addr
& ~1);
735 /* Set PC and Thumb state from var. var is marked as dead. */
736 static inline void gen_bx(DisasContext
*s
, TCGv var
)
738 s
->is_jmp
= DISAS_UPDATE
;
739 tcg_gen_andi_i32(cpu_R
[15], var
, ~1);
740 tcg_gen_andi_i32(var
, var
, 1);
741 store_cpu_field(var
, thumb
);
744 /* Variant of store_reg which uses branch&exchange logic when storing
745 to r15 in ARM architecture v7 and above. The source must be a temporary
746 and will be marked as dead. */
747 static inline void store_reg_bx(CPUState
*env
, DisasContext
*s
,
750 if (reg
== 15 && ENABLE_ARCH_7
) {
753 store_reg(s
, reg
, var
);
757 /* Variant of store_reg which uses branch&exchange logic when storing
758 * to r15 in ARM architecture v5T and above. This is used for storing
759 * the results of a LDR/LDM/POP into r15, and corresponds to the cases
760 * in the ARM ARM which use the LoadWritePC() pseudocode function. */
761 static inline void store_reg_from_load(CPUState
*env
, DisasContext
*s
,
764 if (reg
== 15 && ENABLE_ARCH_5
) {
767 store_reg(s
, reg
, var
);
771 static inline TCGv
gen_ld8s(TCGv addr
, int index
)
773 TCGv tmp
= tcg_temp_new_i32();
774 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
777 static inline TCGv
gen_ld8u(TCGv addr
, int index
)
779 TCGv tmp
= tcg_temp_new_i32();
780 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
783 static inline TCGv
gen_ld16s(TCGv addr
, int index
)
785 TCGv tmp
= tcg_temp_new_i32();
786 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
789 static inline TCGv
gen_ld16u(TCGv addr
, int index
)
791 TCGv tmp
= tcg_temp_new_i32();
792 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
795 static inline TCGv
gen_ld32(TCGv addr
, int index
)
797 TCGv tmp
= tcg_temp_new_i32();
798 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
801 static inline TCGv_i64
gen_ld64(TCGv addr
, int index
)
803 TCGv_i64 tmp
= tcg_temp_new_i64();
804 tcg_gen_qemu_ld64(tmp
, addr
, index
);
807 static inline void gen_st8(TCGv val
, TCGv addr
, int index
)
809 tcg_gen_qemu_st8(val
, addr
, index
);
810 tcg_temp_free_i32(val
);
812 static inline void gen_st16(TCGv val
, TCGv addr
, int index
)
814 tcg_gen_qemu_st16(val
, addr
, index
);
815 tcg_temp_free_i32(val
);
817 static inline void gen_st32(TCGv val
, TCGv addr
, int index
)
819 tcg_gen_qemu_st32(val
, addr
, index
);
820 tcg_temp_free_i32(val
);
822 static inline void gen_st64(TCGv_i64 val
, TCGv addr
, int index
)
824 tcg_gen_qemu_st64(val
, addr
, index
);
825 tcg_temp_free_i64(val
);
828 static inline void gen_set_pc_im(uint32_t val
)
830 tcg_gen_movi_i32(cpu_R
[15], val
);
833 /* Force a TB lookup after an instruction that changes the CPU state. */
834 static inline void gen_lookup_tb(DisasContext
*s
)
836 tcg_gen_movi_i32(cpu_R
[15], s
->pc
& ~1);
837 s
->is_jmp
= DISAS_UPDATE
;
840 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
843 int val
, rm
, shift
, shiftop
;
846 if (!(insn
& (1 << 25))) {
849 if (!(insn
& (1 << 23)))
852 tcg_gen_addi_i32(var
, var
, val
);
856 shift
= (insn
>> 7) & 0x1f;
857 shiftop
= (insn
>> 5) & 3;
858 offset
= load_reg(s
, rm
);
859 gen_arm_shift_im(offset
, shiftop
, shift
, 0);
860 if (!(insn
& (1 << 23)))
861 tcg_gen_sub_i32(var
, var
, offset
);
863 tcg_gen_add_i32(var
, var
, offset
);
864 tcg_temp_free_i32(offset
);
868 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
874 if (insn
& (1 << 22)) {
876 val
= (insn
& 0xf) | ((insn
>> 4) & 0xf0);
877 if (!(insn
& (1 << 23)))
881 tcg_gen_addi_i32(var
, var
, val
);
885 tcg_gen_addi_i32(var
, var
, extra
);
887 offset
= load_reg(s
, rm
);
888 if (!(insn
& (1 << 23)))
889 tcg_gen_sub_i32(var
, var
, offset
);
891 tcg_gen_add_i32(var
, var
, offset
);
892 tcg_temp_free_i32(offset
);
896 #define VFP_OP2(name) \
897 static inline void gen_vfp_##name(int dp) \
900 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, cpu_F1d, cpu_env); \
902 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, cpu_F1s, cpu_env); \
912 static inline void gen_vfp_abs(int dp
)
915 gen_helper_vfp_absd(cpu_F0d
, cpu_F0d
);
917 gen_helper_vfp_abss(cpu_F0s
, cpu_F0s
);
920 static inline void gen_vfp_neg(int dp
)
923 gen_helper_vfp_negd(cpu_F0d
, cpu_F0d
);
925 gen_helper_vfp_negs(cpu_F0s
, cpu_F0s
);
928 static inline void gen_vfp_sqrt(int dp
)
931 gen_helper_vfp_sqrtd(cpu_F0d
, cpu_F0d
, cpu_env
);
933 gen_helper_vfp_sqrts(cpu_F0s
, cpu_F0s
, cpu_env
);
936 static inline void gen_vfp_cmp(int dp
)
939 gen_helper_vfp_cmpd(cpu_F0d
, cpu_F1d
, cpu_env
);
941 gen_helper_vfp_cmps(cpu_F0s
, cpu_F1s
, cpu_env
);
944 static inline void gen_vfp_cmpe(int dp
)
947 gen_helper_vfp_cmped(cpu_F0d
, cpu_F1d
, cpu_env
);
949 gen_helper_vfp_cmpes(cpu_F0s
, cpu_F1s
, cpu_env
);
952 static inline void gen_vfp_F1_ld0(int dp
)
955 tcg_gen_movi_i64(cpu_F1d
, 0);
957 tcg_gen_movi_i32(cpu_F1s
, 0);
960 static inline void gen_vfp_uito(int dp
)
963 gen_helper_vfp_uitod(cpu_F0d
, cpu_F0s
, cpu_env
);
965 gen_helper_vfp_uitos(cpu_F0s
, cpu_F0s
, cpu_env
);
968 static inline void gen_vfp_sito(int dp
)
971 gen_helper_vfp_sitod(cpu_F0d
, cpu_F0s
, cpu_env
);
973 gen_helper_vfp_sitos(cpu_F0s
, cpu_F0s
, cpu_env
);
976 static inline void gen_vfp_toui(int dp
)
979 gen_helper_vfp_touid(cpu_F0s
, cpu_F0d
, cpu_env
);
981 gen_helper_vfp_touis(cpu_F0s
, cpu_F0s
, cpu_env
);
984 static inline void gen_vfp_touiz(int dp
)
987 gen_helper_vfp_touizd(cpu_F0s
, cpu_F0d
, cpu_env
);
989 gen_helper_vfp_touizs(cpu_F0s
, cpu_F0s
, cpu_env
);
992 static inline void gen_vfp_tosi(int dp
)
995 gen_helper_vfp_tosid(cpu_F0s
, cpu_F0d
, cpu_env
);
997 gen_helper_vfp_tosis(cpu_F0s
, cpu_F0s
, cpu_env
);
1000 static inline void gen_vfp_tosiz(int dp
)
1003 gen_helper_vfp_tosizd(cpu_F0s
, cpu_F0d
, cpu_env
);
1005 gen_helper_vfp_tosizs(cpu_F0s
, cpu_F0s
, cpu_env
);
1008 #define VFP_GEN_FIX(name) \
1009 static inline void gen_vfp_##name(int dp, int shift) \
1011 TCGv tmp_shift = tcg_const_i32(shift); \
1013 gen_helper_vfp_##name##d(cpu_F0d, cpu_F0d, tmp_shift, cpu_env);\
1015 gen_helper_vfp_##name##s(cpu_F0s, cpu_F0s, tmp_shift, cpu_env);\
1016 tcg_temp_free_i32(tmp_shift); \
1028 static inline void gen_vfp_ld(DisasContext
*s
, int dp
, TCGv addr
)
1031 tcg_gen_qemu_ld64(cpu_F0d
, addr
, IS_USER(s
));
1033 tcg_gen_qemu_ld32u(cpu_F0s
, addr
, IS_USER(s
));
1036 static inline void gen_vfp_st(DisasContext
*s
, int dp
, TCGv addr
)
1039 tcg_gen_qemu_st64(cpu_F0d
, addr
, IS_USER(s
));
1041 tcg_gen_qemu_st32(cpu_F0s
, addr
, IS_USER(s
));
1045 vfp_reg_offset (int dp
, int reg
)
1048 return offsetof(CPUARMState
, vfp
.regs
[reg
]);
1050 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1051 + offsetof(CPU_DoubleU
, l
.upper
);
1053 return offsetof(CPUARMState
, vfp
.regs
[reg
>> 1])
1054 + offsetof(CPU_DoubleU
, l
.lower
);
1058 /* Return the offset of a 32-bit piece of a NEON register.
1059 zero is the least significant end of the register. */
1061 neon_reg_offset (int reg
, int n
)
1065 return vfp_reg_offset(0, sreg
);
1068 static TCGv
neon_load_reg(int reg
, int pass
)
1070 TCGv tmp
= tcg_temp_new_i32();
1071 tcg_gen_ld_i32(tmp
, cpu_env
, neon_reg_offset(reg
, pass
));
1075 static void neon_store_reg(int reg
, int pass
, TCGv var
)
1077 tcg_gen_st_i32(var
, cpu_env
, neon_reg_offset(reg
, pass
));
1078 tcg_temp_free_i32(var
);
1081 static inline void neon_load_reg64(TCGv_i64 var
, int reg
)
1083 tcg_gen_ld_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1086 static inline void neon_store_reg64(TCGv_i64 var
, int reg
)
1088 tcg_gen_st_i64(var
, cpu_env
, vfp_reg_offset(1, reg
));
1091 #define tcg_gen_ld_f32 tcg_gen_ld_i32
1092 #define tcg_gen_ld_f64 tcg_gen_ld_i64
1093 #define tcg_gen_st_f32 tcg_gen_st_i32
1094 #define tcg_gen_st_f64 tcg_gen_st_i64
1096 static inline void gen_mov_F0_vreg(int dp
, int reg
)
1099 tcg_gen_ld_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1101 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1104 static inline void gen_mov_F1_vreg(int dp
, int reg
)
1107 tcg_gen_ld_f64(cpu_F1d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1109 tcg_gen_ld_f32(cpu_F1s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1112 static inline void gen_mov_vreg_F0(int dp
, int reg
)
1115 tcg_gen_st_f64(cpu_F0d
, cpu_env
, vfp_reg_offset(dp
, reg
));
1117 tcg_gen_st_f32(cpu_F0s
, cpu_env
, vfp_reg_offset(dp
, reg
));
1120 #define ARM_CP_RW_BIT (1 << 20)
1122 static inline void iwmmxt_load_reg(TCGv_i64 var
, int reg
)
1124 tcg_gen_ld_i64(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.regs
[reg
]));
1127 static inline void iwmmxt_store_reg(TCGv_i64 var
, int reg
)
1129 tcg_gen_st_i64(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.regs
[reg
]));
1132 static inline TCGv
iwmmxt_load_creg(int reg
)
1134 TCGv var
= tcg_temp_new_i32();
1135 tcg_gen_ld_i32(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.cregs
[reg
]));
1139 static inline void iwmmxt_store_creg(int reg
, TCGv var
)
1141 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUState
, iwmmxt
.cregs
[reg
]));
1142 tcg_temp_free_i32(var
);
1145 static inline void gen_op_iwmmxt_movq_wRn_M0(int rn
)
1147 iwmmxt_store_reg(cpu_M0
, rn
);
1150 static inline void gen_op_iwmmxt_movq_M0_wRn(int rn
)
1152 iwmmxt_load_reg(cpu_M0
, rn
);
1155 static inline void gen_op_iwmmxt_orq_M0_wRn(int rn
)
1157 iwmmxt_load_reg(cpu_V1
, rn
);
1158 tcg_gen_or_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1161 static inline void gen_op_iwmmxt_andq_M0_wRn(int rn
)
1163 iwmmxt_load_reg(cpu_V1
, rn
);
1164 tcg_gen_and_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1167 static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn
)
1169 iwmmxt_load_reg(cpu_V1
, rn
);
1170 tcg_gen_xor_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1173 #define IWMMXT_OP(name) \
1174 static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \
1176 iwmmxt_load_reg(cpu_V1, rn); \
1177 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \
1180 #define IWMMXT_OP_SIZE(name) \
1181 IWMMXT_OP(name##b) \
1182 IWMMXT_OP(name##w) \
1185 #define IWMMXT_OP_1(name) \
1186 static inline void gen_op_iwmmxt_##name##_M0(void) \
1188 gen_helper_iwmmxt_##name(cpu_M0, cpu_M0); \
1202 IWMMXT_OP_SIZE(unpackl
)
1203 IWMMXT_OP_SIZE(unpackh
)
1205 IWMMXT_OP_1(unpacklub
)
1206 IWMMXT_OP_1(unpackluw
)
1207 IWMMXT_OP_1(unpacklul
)
1208 IWMMXT_OP_1(unpackhub
)
1209 IWMMXT_OP_1(unpackhuw
)
1210 IWMMXT_OP_1(unpackhul
)
1211 IWMMXT_OP_1(unpacklsb
)
1212 IWMMXT_OP_1(unpacklsw
)
1213 IWMMXT_OP_1(unpacklsl
)
1214 IWMMXT_OP_1(unpackhsb
)
1215 IWMMXT_OP_1(unpackhsw
)
1216 IWMMXT_OP_1(unpackhsl
)
1218 IWMMXT_OP_SIZE(cmpeq
)
1219 IWMMXT_OP_SIZE(cmpgtu
)
1220 IWMMXT_OP_SIZE(cmpgts
)
1222 IWMMXT_OP_SIZE(mins
)
1223 IWMMXT_OP_SIZE(minu
)
1224 IWMMXT_OP_SIZE(maxs
)
1225 IWMMXT_OP_SIZE(maxu
)
1227 IWMMXT_OP_SIZE(subn
)
1228 IWMMXT_OP_SIZE(addn
)
1229 IWMMXT_OP_SIZE(subu
)
1230 IWMMXT_OP_SIZE(addu
)
1231 IWMMXT_OP_SIZE(subs
)
1232 IWMMXT_OP_SIZE(adds
)
1248 static void gen_op_iwmmxt_set_mup(void)
1251 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1252 tcg_gen_ori_i32(tmp
, tmp
, 2);
1253 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1256 static void gen_op_iwmmxt_set_cup(void)
1259 tmp
= load_cpu_field(iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1260 tcg_gen_ori_i32(tmp
, tmp
, 1);
1261 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCon
]);
1264 static void gen_op_iwmmxt_setpsr_nz(void)
1266 TCGv tmp
= tcg_temp_new_i32();
1267 gen_helper_iwmmxt_setpsr_nz(tmp
, cpu_M0
);
1268 store_cpu_field(tmp
, iwmmxt
.cregs
[ARM_IWMMXT_wCASF
]);
1271 static inline void gen_op_iwmmxt_addl_M0_wRn(int rn
)
1273 iwmmxt_load_reg(cpu_V1
, rn
);
1274 tcg_gen_ext32u_i64(cpu_V1
, cpu_V1
);
1275 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1278 static inline int gen_iwmmxt_address(DisasContext
*s
, uint32_t insn
, TCGv dest
)
1284 rd
= (insn
>> 16) & 0xf;
1285 tmp
= load_reg(s
, rd
);
1287 offset
= (insn
& 0xff) << ((insn
>> 7) & 2);
1288 if (insn
& (1 << 24)) {
1290 if (insn
& (1 << 23))
1291 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1293 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1294 tcg_gen_mov_i32(dest
, tmp
);
1295 if (insn
& (1 << 21))
1296 store_reg(s
, rd
, tmp
);
1298 tcg_temp_free_i32(tmp
);
1299 } else if (insn
& (1 << 21)) {
1301 tcg_gen_mov_i32(dest
, tmp
);
1302 if (insn
& (1 << 23))
1303 tcg_gen_addi_i32(tmp
, tmp
, offset
);
1305 tcg_gen_addi_i32(tmp
, tmp
, -offset
);
1306 store_reg(s
, rd
, tmp
);
1307 } else if (!(insn
& (1 << 23)))
1312 static inline int gen_iwmmxt_shift(uint32_t insn
, uint32_t mask
, TCGv dest
)
1314 int rd
= (insn
>> 0) & 0xf;
1317 if (insn
& (1 << 8)) {
1318 if (rd
< ARM_IWMMXT_wCGR0
|| rd
> ARM_IWMMXT_wCGR3
) {
1321 tmp
= iwmmxt_load_creg(rd
);
1324 tmp
= tcg_temp_new_i32();
1325 iwmmxt_load_reg(cpu_V0
, rd
);
1326 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
1328 tcg_gen_andi_i32(tmp
, tmp
, mask
);
1329 tcg_gen_mov_i32(dest
, tmp
);
1330 tcg_temp_free_i32(tmp
);
1334 /* Disassemble an iwMMXt instruction. Returns nonzero if an error occured
1335 (ie. an undefined instruction). */
1336 static int disas_iwmmxt_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
1339 int rdhi
, rdlo
, rd0
, rd1
, i
;
1341 TCGv tmp
, tmp2
, tmp3
;
1343 if ((insn
& 0x0e000e00) == 0x0c000000) {
1344 if ((insn
& 0x0fe00ff0) == 0x0c400000) {
1346 rdlo
= (insn
>> 12) & 0xf;
1347 rdhi
= (insn
>> 16) & 0xf;
1348 if (insn
& ARM_CP_RW_BIT
) { /* TMRRC */
1349 iwmmxt_load_reg(cpu_V0
, wrd
);
1350 tcg_gen_trunc_i64_i32(cpu_R
[rdlo
], cpu_V0
);
1351 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
1352 tcg_gen_trunc_i64_i32(cpu_R
[rdhi
], cpu_V0
);
1353 } else { /* TMCRR */
1354 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
1355 iwmmxt_store_reg(cpu_V0
, wrd
);
1356 gen_op_iwmmxt_set_mup();
1361 wrd
= (insn
>> 12) & 0xf;
1362 addr
= tcg_temp_new_i32();
1363 if (gen_iwmmxt_address(s
, insn
, addr
)) {
1364 tcg_temp_free_i32(addr
);
1367 if (insn
& ARM_CP_RW_BIT
) {
1368 if ((insn
>> 28) == 0xf) { /* WLDRW wCx */
1369 tmp
= tcg_temp_new_i32();
1370 tcg_gen_qemu_ld32u(tmp
, addr
, IS_USER(s
));
1371 iwmmxt_store_creg(wrd
, tmp
);
1374 if (insn
& (1 << 8)) {
1375 if (insn
& (1 << 22)) { /* WLDRD */
1376 tcg_gen_qemu_ld64(cpu_M0
, addr
, IS_USER(s
));
1378 } else { /* WLDRW wRd */
1379 tmp
= gen_ld32(addr
, IS_USER(s
));
1382 if (insn
& (1 << 22)) { /* WLDRH */
1383 tmp
= gen_ld16u(addr
, IS_USER(s
));
1384 } else { /* WLDRB */
1385 tmp
= gen_ld8u(addr
, IS_USER(s
));
1389 tcg_gen_extu_i32_i64(cpu_M0
, tmp
);
1390 tcg_temp_free_i32(tmp
);
1392 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1395 if ((insn
>> 28) == 0xf) { /* WSTRW wCx */
1396 tmp
= iwmmxt_load_creg(wrd
);
1397 gen_st32(tmp
, addr
, IS_USER(s
));
1399 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1400 tmp
= tcg_temp_new_i32();
1401 if (insn
& (1 << 8)) {
1402 if (insn
& (1 << 22)) { /* WSTRD */
1403 tcg_temp_free_i32(tmp
);
1404 tcg_gen_qemu_st64(cpu_M0
, addr
, IS_USER(s
));
1405 } else { /* WSTRW wRd */
1406 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1407 gen_st32(tmp
, addr
, IS_USER(s
));
1410 if (insn
& (1 << 22)) { /* WSTRH */
1411 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1412 gen_st16(tmp
, addr
, IS_USER(s
));
1413 } else { /* WSTRB */
1414 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1415 gen_st8(tmp
, addr
, IS_USER(s
));
1420 tcg_temp_free_i32(addr
);
1424 if ((insn
& 0x0f000000) != 0x0e000000)
1427 switch (((insn
>> 12) & 0xf00) | ((insn
>> 4) & 0xff)) {
1428 case 0x000: /* WOR */
1429 wrd
= (insn
>> 12) & 0xf;
1430 rd0
= (insn
>> 0) & 0xf;
1431 rd1
= (insn
>> 16) & 0xf;
1432 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1433 gen_op_iwmmxt_orq_M0_wRn(rd1
);
1434 gen_op_iwmmxt_setpsr_nz();
1435 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1436 gen_op_iwmmxt_set_mup();
1437 gen_op_iwmmxt_set_cup();
1439 case 0x011: /* TMCR */
1442 rd
= (insn
>> 12) & 0xf;
1443 wrd
= (insn
>> 16) & 0xf;
1445 case ARM_IWMMXT_wCID
:
1446 case ARM_IWMMXT_wCASF
:
1448 case ARM_IWMMXT_wCon
:
1449 gen_op_iwmmxt_set_cup();
1451 case ARM_IWMMXT_wCSSF
:
1452 tmp
= iwmmxt_load_creg(wrd
);
1453 tmp2
= load_reg(s
, rd
);
1454 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1455 tcg_temp_free_i32(tmp2
);
1456 iwmmxt_store_creg(wrd
, tmp
);
1458 case ARM_IWMMXT_wCGR0
:
1459 case ARM_IWMMXT_wCGR1
:
1460 case ARM_IWMMXT_wCGR2
:
1461 case ARM_IWMMXT_wCGR3
:
1462 gen_op_iwmmxt_set_cup();
1463 tmp
= load_reg(s
, rd
);
1464 iwmmxt_store_creg(wrd
, tmp
);
1470 case 0x100: /* WXOR */
1471 wrd
= (insn
>> 12) & 0xf;
1472 rd0
= (insn
>> 0) & 0xf;
1473 rd1
= (insn
>> 16) & 0xf;
1474 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1475 gen_op_iwmmxt_xorq_M0_wRn(rd1
);
1476 gen_op_iwmmxt_setpsr_nz();
1477 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1478 gen_op_iwmmxt_set_mup();
1479 gen_op_iwmmxt_set_cup();
1481 case 0x111: /* TMRC */
1484 rd
= (insn
>> 12) & 0xf;
1485 wrd
= (insn
>> 16) & 0xf;
1486 tmp
= iwmmxt_load_creg(wrd
);
1487 store_reg(s
, rd
, tmp
);
1489 case 0x300: /* WANDN */
1490 wrd
= (insn
>> 12) & 0xf;
1491 rd0
= (insn
>> 0) & 0xf;
1492 rd1
= (insn
>> 16) & 0xf;
1493 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1494 tcg_gen_neg_i64(cpu_M0
, cpu_M0
);
1495 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1496 gen_op_iwmmxt_setpsr_nz();
1497 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1498 gen_op_iwmmxt_set_mup();
1499 gen_op_iwmmxt_set_cup();
1501 case 0x200: /* WAND */
1502 wrd
= (insn
>> 12) & 0xf;
1503 rd0
= (insn
>> 0) & 0xf;
1504 rd1
= (insn
>> 16) & 0xf;
1505 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1506 gen_op_iwmmxt_andq_M0_wRn(rd1
);
1507 gen_op_iwmmxt_setpsr_nz();
1508 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1509 gen_op_iwmmxt_set_mup();
1510 gen_op_iwmmxt_set_cup();
1512 case 0x810: case 0xa10: /* WMADD */
1513 wrd
= (insn
>> 12) & 0xf;
1514 rd0
= (insn
>> 0) & 0xf;
1515 rd1
= (insn
>> 16) & 0xf;
1516 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1517 if (insn
& (1 << 21))
1518 gen_op_iwmmxt_maddsq_M0_wRn(rd1
);
1520 gen_op_iwmmxt_madduq_M0_wRn(rd1
);
1521 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1522 gen_op_iwmmxt_set_mup();
1524 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1525 wrd
= (insn
>> 12) & 0xf;
1526 rd0
= (insn
>> 16) & 0xf;
1527 rd1
= (insn
>> 0) & 0xf;
1528 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1529 switch ((insn
>> 22) & 3) {
1531 gen_op_iwmmxt_unpacklb_M0_wRn(rd1
);
1534 gen_op_iwmmxt_unpacklw_M0_wRn(rd1
);
1537 gen_op_iwmmxt_unpackll_M0_wRn(rd1
);
1542 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1543 gen_op_iwmmxt_set_mup();
1544 gen_op_iwmmxt_set_cup();
1546 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1547 wrd
= (insn
>> 12) & 0xf;
1548 rd0
= (insn
>> 16) & 0xf;
1549 rd1
= (insn
>> 0) & 0xf;
1550 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1551 switch ((insn
>> 22) & 3) {
1553 gen_op_iwmmxt_unpackhb_M0_wRn(rd1
);
1556 gen_op_iwmmxt_unpackhw_M0_wRn(rd1
);
1559 gen_op_iwmmxt_unpackhl_M0_wRn(rd1
);
1564 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1565 gen_op_iwmmxt_set_mup();
1566 gen_op_iwmmxt_set_cup();
1568 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1569 wrd
= (insn
>> 12) & 0xf;
1570 rd0
= (insn
>> 16) & 0xf;
1571 rd1
= (insn
>> 0) & 0xf;
1572 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1573 if (insn
& (1 << 22))
1574 gen_op_iwmmxt_sadw_M0_wRn(rd1
);
1576 gen_op_iwmmxt_sadb_M0_wRn(rd1
);
1577 if (!(insn
& (1 << 20)))
1578 gen_op_iwmmxt_addl_M0_wRn(wrd
);
1579 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1580 gen_op_iwmmxt_set_mup();
1582 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1583 wrd
= (insn
>> 12) & 0xf;
1584 rd0
= (insn
>> 16) & 0xf;
1585 rd1
= (insn
>> 0) & 0xf;
1586 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1587 if (insn
& (1 << 21)) {
1588 if (insn
& (1 << 20))
1589 gen_op_iwmmxt_mulshw_M0_wRn(rd1
);
1591 gen_op_iwmmxt_mulslw_M0_wRn(rd1
);
1593 if (insn
& (1 << 20))
1594 gen_op_iwmmxt_muluhw_M0_wRn(rd1
);
1596 gen_op_iwmmxt_mululw_M0_wRn(rd1
);
1598 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1599 gen_op_iwmmxt_set_mup();
1601 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1602 wrd
= (insn
>> 12) & 0xf;
1603 rd0
= (insn
>> 16) & 0xf;
1604 rd1
= (insn
>> 0) & 0xf;
1605 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1606 if (insn
& (1 << 21))
1607 gen_op_iwmmxt_macsw_M0_wRn(rd1
);
1609 gen_op_iwmmxt_macuw_M0_wRn(rd1
);
1610 if (!(insn
& (1 << 20))) {
1611 iwmmxt_load_reg(cpu_V1
, wrd
);
1612 tcg_gen_add_i64(cpu_M0
, cpu_M0
, cpu_V1
);
1614 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1615 gen_op_iwmmxt_set_mup();
1617 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1618 wrd
= (insn
>> 12) & 0xf;
1619 rd0
= (insn
>> 16) & 0xf;
1620 rd1
= (insn
>> 0) & 0xf;
1621 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1622 switch ((insn
>> 22) & 3) {
1624 gen_op_iwmmxt_cmpeqb_M0_wRn(rd1
);
1627 gen_op_iwmmxt_cmpeqw_M0_wRn(rd1
);
1630 gen_op_iwmmxt_cmpeql_M0_wRn(rd1
);
1635 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1636 gen_op_iwmmxt_set_mup();
1637 gen_op_iwmmxt_set_cup();
1639 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1640 wrd
= (insn
>> 12) & 0xf;
1641 rd0
= (insn
>> 16) & 0xf;
1642 rd1
= (insn
>> 0) & 0xf;
1643 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1644 if (insn
& (1 << 22)) {
1645 if (insn
& (1 << 20))
1646 gen_op_iwmmxt_avgw1_M0_wRn(rd1
);
1648 gen_op_iwmmxt_avgw0_M0_wRn(rd1
);
1650 if (insn
& (1 << 20))
1651 gen_op_iwmmxt_avgb1_M0_wRn(rd1
);
1653 gen_op_iwmmxt_avgb0_M0_wRn(rd1
);
1655 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1656 gen_op_iwmmxt_set_mup();
1657 gen_op_iwmmxt_set_cup();
1659 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1660 wrd
= (insn
>> 12) & 0xf;
1661 rd0
= (insn
>> 16) & 0xf;
1662 rd1
= (insn
>> 0) & 0xf;
1663 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1664 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCGR0
+ ((insn
>> 20) & 3));
1665 tcg_gen_andi_i32(tmp
, tmp
, 7);
1666 iwmmxt_load_reg(cpu_V1
, rd1
);
1667 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
1668 tcg_temp_free_i32(tmp
);
1669 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1670 gen_op_iwmmxt_set_mup();
1672 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1673 if (((insn
>> 6) & 3) == 3)
1675 rd
= (insn
>> 12) & 0xf;
1676 wrd
= (insn
>> 16) & 0xf;
1677 tmp
= load_reg(s
, rd
);
1678 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1679 switch ((insn
>> 6) & 3) {
1681 tmp2
= tcg_const_i32(0xff);
1682 tmp3
= tcg_const_i32((insn
& 7) << 3);
1685 tmp2
= tcg_const_i32(0xffff);
1686 tmp3
= tcg_const_i32((insn
& 3) << 4);
1689 tmp2
= tcg_const_i32(0xffffffff);
1690 tmp3
= tcg_const_i32((insn
& 1) << 5);
1696 gen_helper_iwmmxt_insr(cpu_M0
, cpu_M0
, tmp
, tmp2
, tmp3
);
1697 tcg_temp_free(tmp3
);
1698 tcg_temp_free(tmp2
);
1699 tcg_temp_free_i32(tmp
);
1700 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1701 gen_op_iwmmxt_set_mup();
1703 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1704 rd
= (insn
>> 12) & 0xf;
1705 wrd
= (insn
>> 16) & 0xf;
1706 if (rd
== 15 || ((insn
>> 22) & 3) == 3)
1708 gen_op_iwmmxt_movq_M0_wRn(wrd
);
1709 tmp
= tcg_temp_new_i32();
1710 switch ((insn
>> 22) & 3) {
1712 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 7) << 3);
1713 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1715 tcg_gen_ext8s_i32(tmp
, tmp
);
1717 tcg_gen_andi_i32(tmp
, tmp
, 0xff);
1721 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 3) << 4);
1722 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1724 tcg_gen_ext16s_i32(tmp
, tmp
);
1726 tcg_gen_andi_i32(tmp
, tmp
, 0xffff);
1730 tcg_gen_shri_i64(cpu_M0
, cpu_M0
, (insn
& 1) << 5);
1731 tcg_gen_trunc_i64_i32(tmp
, cpu_M0
);
1734 store_reg(s
, rd
, tmp
);
1736 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1737 if ((insn
& 0x000ff008) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1739 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1740 switch ((insn
>> 22) & 3) {
1742 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 7) << 2) + 0);
1745 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 3) << 3) + 4);
1748 tcg_gen_shri_i32(tmp
, tmp
, ((insn
& 1) << 4) + 12);
1751 tcg_gen_shli_i32(tmp
, tmp
, 28);
1753 tcg_temp_free_i32(tmp
);
1755 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1756 if (((insn
>> 6) & 3) == 3)
1758 rd
= (insn
>> 12) & 0xf;
1759 wrd
= (insn
>> 16) & 0xf;
1760 tmp
= load_reg(s
, rd
);
1761 switch ((insn
>> 6) & 3) {
1763 gen_helper_iwmmxt_bcstb(cpu_M0
, tmp
);
1766 gen_helper_iwmmxt_bcstw(cpu_M0
, tmp
);
1769 gen_helper_iwmmxt_bcstl(cpu_M0
, tmp
);
1772 tcg_temp_free_i32(tmp
);
1773 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1774 gen_op_iwmmxt_set_mup();
1776 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1777 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1779 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1780 tmp2
= tcg_temp_new_i32();
1781 tcg_gen_mov_i32(tmp2
, tmp
);
1782 switch ((insn
>> 22) & 3) {
1784 for (i
= 0; i
< 7; i
++) {
1785 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1786 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1790 for (i
= 0; i
< 3; i
++) {
1791 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1792 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1796 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
1797 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1801 tcg_temp_free_i32(tmp2
);
1802 tcg_temp_free_i32(tmp
);
1804 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1805 wrd
= (insn
>> 12) & 0xf;
1806 rd0
= (insn
>> 16) & 0xf;
1807 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1808 switch ((insn
>> 22) & 3) {
1810 gen_helper_iwmmxt_addcb(cpu_M0
, cpu_M0
);
1813 gen_helper_iwmmxt_addcw(cpu_M0
, cpu_M0
);
1816 gen_helper_iwmmxt_addcl(cpu_M0
, cpu_M0
);
1821 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1822 gen_op_iwmmxt_set_mup();
1824 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
1825 if ((insn
& 0x000ff00f) != 0x0003f000 || ((insn
>> 22) & 3) == 3)
1827 tmp
= iwmmxt_load_creg(ARM_IWMMXT_wCASF
);
1828 tmp2
= tcg_temp_new_i32();
1829 tcg_gen_mov_i32(tmp2
, tmp
);
1830 switch ((insn
>> 22) & 3) {
1832 for (i
= 0; i
< 7; i
++) {
1833 tcg_gen_shli_i32(tmp2
, tmp2
, 4);
1834 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1838 for (i
= 0; i
< 3; i
++) {
1839 tcg_gen_shli_i32(tmp2
, tmp2
, 8);
1840 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1844 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
1845 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1849 tcg_temp_free_i32(tmp2
);
1850 tcg_temp_free_i32(tmp
);
1852 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
1853 rd
= (insn
>> 12) & 0xf;
1854 rd0
= (insn
>> 16) & 0xf;
1855 if ((insn
& 0xf) != 0 || ((insn
>> 22) & 3) == 3)
1857 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1858 tmp
= tcg_temp_new_i32();
1859 switch ((insn
>> 22) & 3) {
1861 gen_helper_iwmmxt_msbb(tmp
, cpu_M0
);
1864 gen_helper_iwmmxt_msbw(tmp
, cpu_M0
);
1867 gen_helper_iwmmxt_msbl(tmp
, cpu_M0
);
1870 store_reg(s
, rd
, tmp
);
1872 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
1873 case 0x906: case 0xb06: case 0xd06: case 0xf06:
1874 wrd
= (insn
>> 12) & 0xf;
1875 rd0
= (insn
>> 16) & 0xf;
1876 rd1
= (insn
>> 0) & 0xf;
1877 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1878 switch ((insn
>> 22) & 3) {
1880 if (insn
& (1 << 21))
1881 gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1
);
1883 gen_op_iwmmxt_cmpgtub_M0_wRn(rd1
);
1886 if (insn
& (1 << 21))
1887 gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1
);
1889 gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1
);
1892 if (insn
& (1 << 21))
1893 gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1
);
1895 gen_op_iwmmxt_cmpgtul_M0_wRn(rd1
);
1900 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1901 gen_op_iwmmxt_set_mup();
1902 gen_op_iwmmxt_set_cup();
1904 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
1905 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
1906 wrd
= (insn
>> 12) & 0xf;
1907 rd0
= (insn
>> 16) & 0xf;
1908 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1909 switch ((insn
>> 22) & 3) {
1911 if (insn
& (1 << 21))
1912 gen_op_iwmmxt_unpacklsb_M0();
1914 gen_op_iwmmxt_unpacklub_M0();
1917 if (insn
& (1 << 21))
1918 gen_op_iwmmxt_unpacklsw_M0();
1920 gen_op_iwmmxt_unpackluw_M0();
1923 if (insn
& (1 << 21))
1924 gen_op_iwmmxt_unpacklsl_M0();
1926 gen_op_iwmmxt_unpacklul_M0();
1931 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1932 gen_op_iwmmxt_set_mup();
1933 gen_op_iwmmxt_set_cup();
1935 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
1936 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
1937 wrd
= (insn
>> 12) & 0xf;
1938 rd0
= (insn
>> 16) & 0xf;
1939 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1940 switch ((insn
>> 22) & 3) {
1942 if (insn
& (1 << 21))
1943 gen_op_iwmmxt_unpackhsb_M0();
1945 gen_op_iwmmxt_unpackhub_M0();
1948 if (insn
& (1 << 21))
1949 gen_op_iwmmxt_unpackhsw_M0();
1951 gen_op_iwmmxt_unpackhuw_M0();
1954 if (insn
& (1 << 21))
1955 gen_op_iwmmxt_unpackhsl_M0();
1957 gen_op_iwmmxt_unpackhul_M0();
1962 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1963 gen_op_iwmmxt_set_mup();
1964 gen_op_iwmmxt_set_cup();
1966 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
1967 case 0x214: case 0x614: case 0xa14: case 0xe14:
1968 if (((insn
>> 22) & 3) == 0)
1970 wrd
= (insn
>> 12) & 0xf;
1971 rd0
= (insn
>> 16) & 0xf;
1972 gen_op_iwmmxt_movq_M0_wRn(rd0
);
1973 tmp
= tcg_temp_new_i32();
1974 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
1975 tcg_temp_free_i32(tmp
);
1978 switch ((insn
>> 22) & 3) {
1980 gen_helper_iwmmxt_srlw(cpu_M0
, cpu_M0
, tmp
);
1983 gen_helper_iwmmxt_srll(cpu_M0
, cpu_M0
, tmp
);
1986 gen_helper_iwmmxt_srlq(cpu_M0
, cpu_M0
, tmp
);
1989 tcg_temp_free_i32(tmp
);
1990 gen_op_iwmmxt_movq_wRn_M0(wrd
);
1991 gen_op_iwmmxt_set_mup();
1992 gen_op_iwmmxt_set_cup();
1994 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
1995 case 0x014: case 0x414: case 0x814: case 0xc14:
1996 if (((insn
>> 22) & 3) == 0)
1998 wrd
= (insn
>> 12) & 0xf;
1999 rd0
= (insn
>> 16) & 0xf;
2000 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2001 tmp
= tcg_temp_new_i32();
2002 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2003 tcg_temp_free_i32(tmp
);
2006 switch ((insn
>> 22) & 3) {
2008 gen_helper_iwmmxt_sraw(cpu_M0
, cpu_M0
, tmp
);
2011 gen_helper_iwmmxt_sral(cpu_M0
, cpu_M0
, tmp
);
2014 gen_helper_iwmmxt_sraq(cpu_M0
, cpu_M0
, tmp
);
2017 tcg_temp_free_i32(tmp
);
2018 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2019 gen_op_iwmmxt_set_mup();
2020 gen_op_iwmmxt_set_cup();
2022 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2023 case 0x114: case 0x514: case 0x914: case 0xd14:
2024 if (((insn
>> 22) & 3) == 0)
2026 wrd
= (insn
>> 12) & 0xf;
2027 rd0
= (insn
>> 16) & 0xf;
2028 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2029 tmp
= tcg_temp_new_i32();
2030 if (gen_iwmmxt_shift(insn
, 0xff, tmp
)) {
2031 tcg_temp_free_i32(tmp
);
2034 switch ((insn
>> 22) & 3) {
2036 gen_helper_iwmmxt_sllw(cpu_M0
, cpu_M0
, tmp
);
2039 gen_helper_iwmmxt_slll(cpu_M0
, cpu_M0
, tmp
);
2042 gen_helper_iwmmxt_sllq(cpu_M0
, cpu_M0
, tmp
);
2045 tcg_temp_free_i32(tmp
);
2046 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2047 gen_op_iwmmxt_set_mup();
2048 gen_op_iwmmxt_set_cup();
2050 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2051 case 0x314: case 0x714: case 0xb14: case 0xf14:
2052 if (((insn
>> 22) & 3) == 0)
2054 wrd
= (insn
>> 12) & 0xf;
2055 rd0
= (insn
>> 16) & 0xf;
2056 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2057 tmp
= tcg_temp_new_i32();
2058 switch ((insn
>> 22) & 3) {
2060 if (gen_iwmmxt_shift(insn
, 0xf, tmp
)) {
2061 tcg_temp_free_i32(tmp
);
2064 gen_helper_iwmmxt_rorw(cpu_M0
, cpu_M0
, tmp
);
2067 if (gen_iwmmxt_shift(insn
, 0x1f, tmp
)) {
2068 tcg_temp_free_i32(tmp
);
2071 gen_helper_iwmmxt_rorl(cpu_M0
, cpu_M0
, tmp
);
2074 if (gen_iwmmxt_shift(insn
, 0x3f, tmp
)) {
2075 tcg_temp_free_i32(tmp
);
2078 gen_helper_iwmmxt_rorq(cpu_M0
, cpu_M0
, tmp
);
2081 tcg_temp_free_i32(tmp
);
2082 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2083 gen_op_iwmmxt_set_mup();
2084 gen_op_iwmmxt_set_cup();
2086 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2087 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2088 wrd
= (insn
>> 12) & 0xf;
2089 rd0
= (insn
>> 16) & 0xf;
2090 rd1
= (insn
>> 0) & 0xf;
2091 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2092 switch ((insn
>> 22) & 3) {
2094 if (insn
& (1 << 21))
2095 gen_op_iwmmxt_minsb_M0_wRn(rd1
);
2097 gen_op_iwmmxt_minub_M0_wRn(rd1
);
2100 if (insn
& (1 << 21))
2101 gen_op_iwmmxt_minsw_M0_wRn(rd1
);
2103 gen_op_iwmmxt_minuw_M0_wRn(rd1
);
2106 if (insn
& (1 << 21))
2107 gen_op_iwmmxt_minsl_M0_wRn(rd1
);
2109 gen_op_iwmmxt_minul_M0_wRn(rd1
);
2114 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2115 gen_op_iwmmxt_set_mup();
2117 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2118 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2119 wrd
= (insn
>> 12) & 0xf;
2120 rd0
= (insn
>> 16) & 0xf;
2121 rd1
= (insn
>> 0) & 0xf;
2122 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2123 switch ((insn
>> 22) & 3) {
2125 if (insn
& (1 << 21))
2126 gen_op_iwmmxt_maxsb_M0_wRn(rd1
);
2128 gen_op_iwmmxt_maxub_M0_wRn(rd1
);
2131 if (insn
& (1 << 21))
2132 gen_op_iwmmxt_maxsw_M0_wRn(rd1
);
2134 gen_op_iwmmxt_maxuw_M0_wRn(rd1
);
2137 if (insn
& (1 << 21))
2138 gen_op_iwmmxt_maxsl_M0_wRn(rd1
);
2140 gen_op_iwmmxt_maxul_M0_wRn(rd1
);
2145 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2146 gen_op_iwmmxt_set_mup();
2148 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2149 case 0x402: case 0x502: case 0x602: case 0x702:
2150 wrd
= (insn
>> 12) & 0xf;
2151 rd0
= (insn
>> 16) & 0xf;
2152 rd1
= (insn
>> 0) & 0xf;
2153 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2154 tmp
= tcg_const_i32((insn
>> 20) & 3);
2155 iwmmxt_load_reg(cpu_V1
, rd1
);
2156 gen_helper_iwmmxt_align(cpu_M0
, cpu_M0
, cpu_V1
, tmp
);
2158 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2159 gen_op_iwmmxt_set_mup();
2161 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2162 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2163 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2164 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2165 wrd
= (insn
>> 12) & 0xf;
2166 rd0
= (insn
>> 16) & 0xf;
2167 rd1
= (insn
>> 0) & 0xf;
2168 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2169 switch ((insn
>> 20) & 0xf) {
2171 gen_op_iwmmxt_subnb_M0_wRn(rd1
);
2174 gen_op_iwmmxt_subub_M0_wRn(rd1
);
2177 gen_op_iwmmxt_subsb_M0_wRn(rd1
);
2180 gen_op_iwmmxt_subnw_M0_wRn(rd1
);
2183 gen_op_iwmmxt_subuw_M0_wRn(rd1
);
2186 gen_op_iwmmxt_subsw_M0_wRn(rd1
);
2189 gen_op_iwmmxt_subnl_M0_wRn(rd1
);
2192 gen_op_iwmmxt_subul_M0_wRn(rd1
);
2195 gen_op_iwmmxt_subsl_M0_wRn(rd1
);
2200 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2201 gen_op_iwmmxt_set_mup();
2202 gen_op_iwmmxt_set_cup();
2204 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2205 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2206 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2207 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2208 wrd
= (insn
>> 12) & 0xf;
2209 rd0
= (insn
>> 16) & 0xf;
2210 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2211 tmp
= tcg_const_i32(((insn
>> 16) & 0xf0) | (insn
& 0x0f));
2212 gen_helper_iwmmxt_shufh(cpu_M0
, cpu_M0
, tmp
);
2214 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2215 gen_op_iwmmxt_set_mup();
2216 gen_op_iwmmxt_set_cup();
2218 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2219 case 0x418: case 0x518: case 0x618: case 0x718:
2220 case 0x818: case 0x918: case 0xa18: case 0xb18:
2221 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2222 wrd
= (insn
>> 12) & 0xf;
2223 rd0
= (insn
>> 16) & 0xf;
2224 rd1
= (insn
>> 0) & 0xf;
2225 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2226 switch ((insn
>> 20) & 0xf) {
2228 gen_op_iwmmxt_addnb_M0_wRn(rd1
);
2231 gen_op_iwmmxt_addub_M0_wRn(rd1
);
2234 gen_op_iwmmxt_addsb_M0_wRn(rd1
);
2237 gen_op_iwmmxt_addnw_M0_wRn(rd1
);
2240 gen_op_iwmmxt_adduw_M0_wRn(rd1
);
2243 gen_op_iwmmxt_addsw_M0_wRn(rd1
);
2246 gen_op_iwmmxt_addnl_M0_wRn(rd1
);
2249 gen_op_iwmmxt_addul_M0_wRn(rd1
);
2252 gen_op_iwmmxt_addsl_M0_wRn(rd1
);
2257 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2258 gen_op_iwmmxt_set_mup();
2259 gen_op_iwmmxt_set_cup();
2261 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2262 case 0x408: case 0x508: case 0x608: case 0x708:
2263 case 0x808: case 0x908: case 0xa08: case 0xb08:
2264 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2265 if (!(insn
& (1 << 20)) || ((insn
>> 22) & 3) == 0)
2267 wrd
= (insn
>> 12) & 0xf;
2268 rd0
= (insn
>> 16) & 0xf;
2269 rd1
= (insn
>> 0) & 0xf;
2270 gen_op_iwmmxt_movq_M0_wRn(rd0
);
2271 switch ((insn
>> 22) & 3) {
2273 if (insn
& (1 << 21))
2274 gen_op_iwmmxt_packsw_M0_wRn(rd1
);
2276 gen_op_iwmmxt_packuw_M0_wRn(rd1
);
2279 if (insn
& (1 << 21))
2280 gen_op_iwmmxt_packsl_M0_wRn(rd1
);
2282 gen_op_iwmmxt_packul_M0_wRn(rd1
);
2285 if (insn
& (1 << 21))
2286 gen_op_iwmmxt_packsq_M0_wRn(rd1
);
2288 gen_op_iwmmxt_packuq_M0_wRn(rd1
);
2291 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2292 gen_op_iwmmxt_set_mup();
2293 gen_op_iwmmxt_set_cup();
2295 case 0x201: case 0x203: case 0x205: case 0x207:
2296 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2297 case 0x211: case 0x213: case 0x215: case 0x217:
2298 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2299 wrd
= (insn
>> 5) & 0xf;
2300 rd0
= (insn
>> 12) & 0xf;
2301 rd1
= (insn
>> 0) & 0xf;
2302 if (rd0
== 0xf || rd1
== 0xf)
2304 gen_op_iwmmxt_movq_M0_wRn(wrd
);
2305 tmp
= load_reg(s
, rd0
);
2306 tmp2
= load_reg(s
, rd1
);
2307 switch ((insn
>> 16) & 0xf) {
2308 case 0x0: /* TMIA */
2309 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2311 case 0x8: /* TMIAPH */
2312 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2314 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2315 if (insn
& (1 << 16))
2316 tcg_gen_shri_i32(tmp
, tmp
, 16);
2317 if (insn
& (1 << 17))
2318 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2319 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2322 tcg_temp_free_i32(tmp2
);
2323 tcg_temp_free_i32(tmp
);
2326 tcg_temp_free_i32(tmp2
);
2327 tcg_temp_free_i32(tmp
);
2328 gen_op_iwmmxt_movq_wRn_M0(wrd
);
2329 gen_op_iwmmxt_set_mup();
2338 /* Disassemble an XScale DSP instruction. Returns nonzero if an error occured
2339 (ie. an undefined instruction). */
2340 static int disas_dsp_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2342 int acc
, rd0
, rd1
, rdhi
, rdlo
;
2345 if ((insn
& 0x0ff00f10) == 0x0e200010) {
2346 /* Multiply with Internal Accumulate Format */
2347 rd0
= (insn
>> 12) & 0xf;
2349 acc
= (insn
>> 5) & 7;
2354 tmp
= load_reg(s
, rd0
);
2355 tmp2
= load_reg(s
, rd1
);
2356 switch ((insn
>> 16) & 0xf) {
2358 gen_helper_iwmmxt_muladdsl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2360 case 0x8: /* MIAPH */
2361 gen_helper_iwmmxt_muladdsw(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2363 case 0xc: /* MIABB */
2364 case 0xd: /* MIABT */
2365 case 0xe: /* MIATB */
2366 case 0xf: /* MIATT */
2367 if (insn
& (1 << 16))
2368 tcg_gen_shri_i32(tmp
, tmp
, 16);
2369 if (insn
& (1 << 17))
2370 tcg_gen_shri_i32(tmp2
, tmp2
, 16);
2371 gen_helper_iwmmxt_muladdswl(cpu_M0
, cpu_M0
, tmp
, tmp2
);
2376 tcg_temp_free_i32(tmp2
);
2377 tcg_temp_free_i32(tmp
);
2379 gen_op_iwmmxt_movq_wRn_M0(acc
);
2383 if ((insn
& 0x0fe00ff8) == 0x0c400000) {
2384 /* Internal Accumulator Access Format */
2385 rdhi
= (insn
>> 16) & 0xf;
2386 rdlo
= (insn
>> 12) & 0xf;
2392 if (insn
& ARM_CP_RW_BIT
) { /* MRA */
2393 iwmmxt_load_reg(cpu_V0
, acc
);
2394 tcg_gen_trunc_i64_i32(cpu_R
[rdlo
], cpu_V0
);
2395 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
2396 tcg_gen_trunc_i64_i32(cpu_R
[rdhi
], cpu_V0
);
2397 tcg_gen_andi_i32(cpu_R
[rdhi
], cpu_R
[rdhi
], (1 << (40 - 32)) - 1);
2399 tcg_gen_concat_i32_i64(cpu_V0
, cpu_R
[rdlo
], cpu_R
[rdhi
]);
2400 iwmmxt_store_reg(cpu_V0
, acc
);
2408 /* Disassemble system coprocessor instruction. Return nonzero if
2409 instruction is not defined. */
2410 static int disas_cp_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2413 uint32_t rd
= (insn
>> 12) & 0xf;
2414 uint32_t cp
= (insn
>> 8) & 0xf;
2419 if (insn
& ARM_CP_RW_BIT
) {
2420 if (!env
->cp
[cp
].cp_read
)
2422 gen_set_pc_im(s
->pc
);
2423 tmp
= tcg_temp_new_i32();
2424 tmp2
= tcg_const_i32(insn
);
2425 gen_helper_get_cp(tmp
, cpu_env
, tmp2
);
2426 tcg_temp_free(tmp2
);
2427 store_reg(s
, rd
, tmp
);
2429 if (!env
->cp
[cp
].cp_write
)
2431 gen_set_pc_im(s
->pc
);
2432 tmp
= load_reg(s
, rd
);
2433 tmp2
= tcg_const_i32(insn
);
2434 gen_helper_set_cp(cpu_env
, tmp2
, tmp
);
2435 tcg_temp_free(tmp2
);
2436 tcg_temp_free_i32(tmp
);
2441 static int cp15_user_ok(uint32_t insn
)
2443 int cpn
= (insn
>> 16) & 0xf;
2444 int cpm
= insn
& 0xf;
2445 int op
= ((insn
>> 5) & 7) | ((insn
>> 18) & 0x38);
2447 if (cpn
== 13 && cpm
== 0) {
2449 if (op
== 2 || (op
== 3 && (insn
& ARM_CP_RW_BIT
)))
2453 /* ISB, DSB, DMB. */
2454 if ((cpm
== 5 && op
== 4)
2455 || (cpm
== 10 && (op
== 4 || op
== 5)))
2461 static int cp15_tls_load_store(CPUState
*env
, DisasContext
*s
, uint32_t insn
, uint32_t rd
)
2464 int cpn
= (insn
>> 16) & 0xf;
2465 int cpm
= insn
& 0xf;
2466 int op
= ((insn
>> 5) & 7) | ((insn
>> 18) & 0x38);
2468 if (!arm_feature(env
, ARM_FEATURE_V6K
))
2471 if (!(cpn
== 13 && cpm
== 0))
2474 if (insn
& ARM_CP_RW_BIT
) {
2477 tmp
= load_cpu_field(cp15
.c13_tls1
);
2480 tmp
= load_cpu_field(cp15
.c13_tls2
);
2483 tmp
= load_cpu_field(cp15
.c13_tls3
);
2488 store_reg(s
, rd
, tmp
);
2491 tmp
= load_reg(s
, rd
);
2494 store_cpu_field(tmp
, cp15
.c13_tls1
);
2497 store_cpu_field(tmp
, cp15
.c13_tls2
);
2500 store_cpu_field(tmp
, cp15
.c13_tls3
);
2503 tcg_temp_free_i32(tmp
);
2510 /* Disassemble system coprocessor (cp15) instruction. Return nonzero if
2511 instruction is not defined. */
2512 static int disas_cp15_insn(CPUState
*env
, DisasContext
*s
, uint32_t insn
)
2517 /* M profile cores use memory mapped registers instead of cp15. */
2518 if (arm_feature(env
, ARM_FEATURE_M
))
2521 if ((insn
& (1 << 25)) == 0) {
2522 if (insn
& (1 << 20)) {
2526 /* mcrr. Used for block cache operations, so implement as no-op. */
2529 if ((insn
& (1 << 4)) == 0) {
2533 if (IS_USER(s
) && !cp15_user_ok(insn
)) {
2537 /* Pre-v7 versions of the architecture implemented WFI via coprocessor
2538 * instructions rather than a separate instruction.
2540 if ((insn
& 0x0fff0fff) == 0x0e070f90) {
2541 /* 0,c7,c0,4: Standard v6 WFI (also used in some pre-v6 cores).
2542 * In v7, this must NOP.
2544 if (!arm_feature(env
, ARM_FEATURE_V7
)) {
2545 /* Wait for interrupt. */
2546 gen_set_pc_im(s
->pc
);
2547 s
->is_jmp
= DISAS_WFI
;
2552 if ((insn
& 0x0fff0fff) == 0x0e070f58) {
2553 /* 0,c7,c8,2: Not all pre-v6 cores implemented this WFI,
2554 * so this is slightly over-broad.
2556 if (!arm_feature(env
, ARM_FEATURE_V6
)) {
2557 /* Wait for interrupt. */
2558 gen_set_pc_im(s
->pc
);
2559 s
->is_jmp
= DISAS_WFI
;
2562 /* Otherwise fall through to handle via helper function.
2563 * In particular, on v7 and some v6 cores this is one of
2564 * the VA-PA registers.
2568 rd
= (insn
>> 12) & 0xf;
2570 if (cp15_tls_load_store(env
, s
, insn
, rd
))
2573 tmp2
= tcg_const_i32(insn
);
2574 if (insn
& ARM_CP_RW_BIT
) {
2575 tmp
= tcg_temp_new_i32();
2576 gen_helper_get_cp15(tmp
, cpu_env
, tmp2
);
2577 /* If the destination register is r15 then sets condition codes. */
2579 store_reg(s
, rd
, tmp
);
2581 tcg_temp_free_i32(tmp
);
2583 tmp
= load_reg(s
, rd
);
2584 gen_helper_set_cp15(cpu_env
, tmp2
, tmp
);
2585 tcg_temp_free_i32(tmp
);
2586 /* Normally we would always end the TB here, but Linux
2587 * arch/arm/mach-pxa/sleep.S expects two instructions following
2588 * an MMU enable to execute from cache. Imitate this behaviour. */
2589 if (!arm_feature(env
, ARM_FEATURE_XSCALE
) ||
2590 (insn
& 0x0fff0fff) != 0x0e010f10)
2593 tcg_temp_free_i32(tmp2
);
2597 #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
2598 #define VFP_SREG(insn, bigbit, smallbit) \
2599 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2600 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2601 if (arm_feature(env, ARM_FEATURE_VFP3)) { \
2602 reg = (((insn) >> (bigbit)) & 0x0f) \
2603 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2605 if (insn & (1 << (smallbit))) \
2607 reg = ((insn) >> (bigbit)) & 0x0f; \
2610 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2611 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2612 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2613 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2614 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2615 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2617 /* Move between integer and VFP cores. */
2618 static TCGv
gen_vfp_mrs(void)
2620 TCGv tmp
= tcg_temp_new_i32();
2621 tcg_gen_mov_i32(tmp
, cpu_F0s
);
2625 static void gen_vfp_msr(TCGv tmp
)
2627 tcg_gen_mov_i32(cpu_F0s
, tmp
);
2628 tcg_temp_free_i32(tmp
);
2631 static void gen_neon_dup_u8(TCGv var
, int shift
)
2633 TCGv tmp
= tcg_temp_new_i32();
2635 tcg_gen_shri_i32(var
, var
, shift
);
2636 tcg_gen_ext8u_i32(var
, var
);
2637 tcg_gen_shli_i32(tmp
, var
, 8);
2638 tcg_gen_or_i32(var
, var
, tmp
);
2639 tcg_gen_shli_i32(tmp
, var
, 16);
2640 tcg_gen_or_i32(var
, var
, tmp
);
2641 tcg_temp_free_i32(tmp
);
2644 static void gen_neon_dup_low16(TCGv var
)
2646 TCGv tmp
= tcg_temp_new_i32();
2647 tcg_gen_ext16u_i32(var
, var
);
2648 tcg_gen_shli_i32(tmp
, var
, 16);
2649 tcg_gen_or_i32(var
, var
, tmp
);
2650 tcg_temp_free_i32(tmp
);
2653 static void gen_neon_dup_high16(TCGv var
)
2655 TCGv tmp
= tcg_temp_new_i32();
2656 tcg_gen_andi_i32(var
, var
, 0xffff0000);
2657 tcg_gen_shri_i32(tmp
, var
, 16);
2658 tcg_gen_or_i32(var
, var
, tmp
);
2659 tcg_temp_free_i32(tmp
);
2662 static TCGv
gen_load_and_replicate(DisasContext
*s
, TCGv addr
, int size
)
2664 /* Load a single Neon element and replicate into a 32 bit TCG reg */
2668 tmp
= gen_ld8u(addr
, IS_USER(s
));
2669 gen_neon_dup_u8(tmp
, 0);
2672 tmp
= gen_ld16u(addr
, IS_USER(s
));
2673 gen_neon_dup_low16(tmp
);
2676 tmp
= gen_ld32(addr
, IS_USER(s
));
2678 default: /* Avoid compiler warnings. */
2684 /* Disassemble a VFP instruction. Returns nonzero if an error occured
2685 (ie. an undefined instruction). */
2686 static int disas_vfp_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
2688 uint32_t rd
, rn
, rm
, op
, i
, n
, offset
, delta_d
, delta_m
, bank_mask
;
2694 if (!arm_feature(env
, ARM_FEATURE_VFP
))
2697 if (!s
->vfp_enabled
) {
2698 /* VFP disabled. Only allow fmxr/fmrx to/from some control regs. */
2699 if ((insn
& 0x0fe00fff) != 0x0ee00a10)
2701 rn
= (insn
>> 16) & 0xf;
2702 if (rn
!= ARM_VFP_FPSID
&& rn
!= ARM_VFP_FPEXC
2703 && rn
!= ARM_VFP_MVFR1
&& rn
!= ARM_VFP_MVFR0
)
2706 dp
= ((insn
& 0xf00) == 0xb00);
2707 switch ((insn
>> 24) & 0xf) {
2709 if (insn
& (1 << 4)) {
2710 /* single register transfer */
2711 rd
= (insn
>> 12) & 0xf;
2716 VFP_DREG_N(rn
, insn
);
2719 if (insn
& 0x00c00060
2720 && !arm_feature(env
, ARM_FEATURE_NEON
))
2723 pass
= (insn
>> 21) & 1;
2724 if (insn
& (1 << 22)) {
2726 offset
= ((insn
>> 5) & 3) * 8;
2727 } else if (insn
& (1 << 5)) {
2729 offset
= (insn
& (1 << 6)) ? 16 : 0;
2734 if (insn
& ARM_CP_RW_BIT
) {
2736 tmp
= neon_load_reg(rn
, pass
);
2740 tcg_gen_shri_i32(tmp
, tmp
, offset
);
2741 if (insn
& (1 << 23))
2747 if (insn
& (1 << 23)) {
2749 tcg_gen_shri_i32(tmp
, tmp
, 16);
2755 tcg_gen_sari_i32(tmp
, tmp
, 16);
2764 store_reg(s
, rd
, tmp
);
2767 tmp
= load_reg(s
, rd
);
2768 if (insn
& (1 << 23)) {
2771 gen_neon_dup_u8(tmp
, 0);
2772 } else if (size
== 1) {
2773 gen_neon_dup_low16(tmp
);
2775 for (n
= 0; n
<= pass
* 2; n
++) {
2776 tmp2
= tcg_temp_new_i32();
2777 tcg_gen_mov_i32(tmp2
, tmp
);
2778 neon_store_reg(rn
, n
, tmp2
);
2780 neon_store_reg(rn
, n
, tmp
);
2785 tmp2
= neon_load_reg(rn
, pass
);
2786 gen_bfi(tmp
, tmp2
, tmp
, offset
, 0xff);
2787 tcg_temp_free_i32(tmp2
);
2790 tmp2
= neon_load_reg(rn
, pass
);
2791 gen_bfi(tmp
, tmp2
, tmp
, offset
, 0xffff);
2792 tcg_temp_free_i32(tmp2
);
2797 neon_store_reg(rn
, pass
, tmp
);
2801 if ((insn
& 0x6f) != 0x00)
2803 rn
= VFP_SREG_N(insn
);
2804 if (insn
& ARM_CP_RW_BIT
) {
2806 if (insn
& (1 << 21)) {
2807 /* system register */
2812 /* VFP2 allows access to FSID from userspace.
2813 VFP3 restricts all id registers to privileged
2816 && arm_feature(env
, ARM_FEATURE_VFP3
))
2818 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2823 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2825 case ARM_VFP_FPINST
:
2826 case ARM_VFP_FPINST2
:
2827 /* Not present in VFP3. */
2829 || arm_feature(env
, ARM_FEATURE_VFP3
))
2831 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2835 tmp
= load_cpu_field(vfp
.xregs
[ARM_VFP_FPSCR
]);
2836 tcg_gen_andi_i32(tmp
, tmp
, 0xf0000000);
2838 tmp
= tcg_temp_new_i32();
2839 gen_helper_vfp_get_fpscr(tmp
, cpu_env
);
2845 || !arm_feature(env
, ARM_FEATURE_VFP3
))
2847 tmp
= load_cpu_field(vfp
.xregs
[rn
]);
2853 gen_mov_F0_vreg(0, rn
);
2854 tmp
= gen_vfp_mrs();
2857 /* Set the 4 flag bits in the CPSR. */
2859 tcg_temp_free_i32(tmp
);
2861 store_reg(s
, rd
, tmp
);
2865 tmp
= load_reg(s
, rd
);
2866 if (insn
& (1 << 21)) {
2868 /* system register */
2873 /* Writes are ignored. */
2876 gen_helper_vfp_set_fpscr(cpu_env
, tmp
);
2877 tcg_temp_free_i32(tmp
);
2883 /* TODO: VFP subarchitecture support.
2884 * For now, keep the EN bit only */
2885 tcg_gen_andi_i32(tmp
, tmp
, 1 << 30);
2886 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
2889 case ARM_VFP_FPINST
:
2890 case ARM_VFP_FPINST2
:
2891 store_cpu_field(tmp
, vfp
.xregs
[rn
]);
2898 gen_mov_vreg_F0(0, rn
);
2903 /* data processing */
2904 /* The opcode is in bits 23, 21, 20 and 6. */
2905 op
= ((insn
>> 20) & 8) | ((insn
>> 19) & 6) | ((insn
>> 6) & 1);
2909 rn
= ((insn
>> 15) & 0x1e) | ((insn
>> 7) & 1);
2911 /* rn is register number */
2912 VFP_DREG_N(rn
, insn
);
2915 if (op
== 15 && (rn
== 15 || ((rn
& 0x1c) == 0x18))) {
2916 /* Integer or single precision destination. */
2917 rd
= VFP_SREG_D(insn
);
2919 VFP_DREG_D(rd
, insn
);
2922 (((rn
& 0x1c) == 0x10) || ((rn
& 0x14) == 0x14))) {
2923 /* VCVT from int is always from S reg regardless of dp bit.
2924 * VCVT with immediate frac_bits has same format as SREG_M
2926 rm
= VFP_SREG_M(insn
);
2928 VFP_DREG_M(rm
, insn
);
2931 rn
= VFP_SREG_N(insn
);
2932 if (op
== 15 && rn
== 15) {
2933 /* Double precision destination. */
2934 VFP_DREG_D(rd
, insn
);
2936 rd
= VFP_SREG_D(insn
);
2938 /* NB that we implicitly rely on the encoding for the frac_bits
2939 * in VCVT of fixed to float being the same as that of an SREG_M
2941 rm
= VFP_SREG_M(insn
);
2944 veclen
= s
->vec_len
;
2945 if (op
== 15 && rn
> 3)
2948 /* Shut up compiler warnings. */
2959 /* Figure out what type of vector operation this is. */
2960 if ((rd
& bank_mask
) == 0) {
2965 delta_d
= (s
->vec_stride
>> 1) + 1;
2967 delta_d
= s
->vec_stride
+ 1;
2969 if ((rm
& bank_mask
) == 0) {
2970 /* mixed scalar/vector */
2979 /* Load the initial operands. */
2984 /* Integer source */
2985 gen_mov_F0_vreg(0, rm
);
2990 gen_mov_F0_vreg(dp
, rd
);
2991 gen_mov_F1_vreg(dp
, rm
);
2995 /* Compare with zero */
2996 gen_mov_F0_vreg(dp
, rd
);
3007 /* Source and destination the same. */
3008 gen_mov_F0_vreg(dp
, rd
);
3011 /* One source operand. */
3012 gen_mov_F0_vreg(dp
, rm
);
3016 /* Two source operands. */
3017 gen_mov_F0_vreg(dp
, rn
);
3018 gen_mov_F1_vreg(dp
, rm
);
3022 /* Perform the calculation. */
3024 case 0: /* mac: fd + (fn * fm) */
3026 gen_mov_F1_vreg(dp
, rd
);
3029 case 1: /* nmac: fd - (fn * fm) */
3032 gen_mov_F1_vreg(dp
, rd
);
3035 case 2: /* msc: -fd + (fn * fm) */
3037 gen_mov_F1_vreg(dp
, rd
);
3040 case 3: /* nmsc: -fd - (fn * fm) */
3043 gen_mov_F1_vreg(dp
, rd
);
3046 case 4: /* mul: fn * fm */
3049 case 5: /* nmul: -(fn * fm) */
3053 case 6: /* add: fn + fm */
3056 case 7: /* sub: fn - fm */
3059 case 8: /* div: fn / fm */
3062 case 14: /* fconst */
3063 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3066 n
= (insn
<< 12) & 0x80000000;
3067 i
= ((insn
>> 12) & 0x70) | (insn
& 0xf);
3074 tcg_gen_movi_i64(cpu_F0d
, ((uint64_t)n
) << 32);
3081 tcg_gen_movi_i32(cpu_F0s
, n
);
3084 case 15: /* extension space */
3098 case 4: /* vcvtb.f32.f16 */
3099 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3101 tmp
= gen_vfp_mrs();
3102 tcg_gen_ext16u_i32(tmp
, tmp
);
3103 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
, cpu_env
);
3104 tcg_temp_free_i32(tmp
);
3106 case 5: /* vcvtt.f32.f16 */
3107 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3109 tmp
= gen_vfp_mrs();
3110 tcg_gen_shri_i32(tmp
, tmp
, 16);
3111 gen_helper_vfp_fcvt_f16_to_f32(cpu_F0s
, tmp
, cpu_env
);
3112 tcg_temp_free_i32(tmp
);
3114 case 6: /* vcvtb.f16.f32 */
3115 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3117 tmp
= tcg_temp_new_i32();
3118 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
3119 gen_mov_F0_vreg(0, rd
);
3120 tmp2
= gen_vfp_mrs();
3121 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
3122 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3123 tcg_temp_free_i32(tmp2
);
3126 case 7: /* vcvtt.f16.f32 */
3127 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
))
3129 tmp
= tcg_temp_new_i32();
3130 gen_helper_vfp_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
3131 tcg_gen_shli_i32(tmp
, tmp
, 16);
3132 gen_mov_F0_vreg(0, rd
);
3133 tmp2
= gen_vfp_mrs();
3134 tcg_gen_ext16u_i32(tmp2
, tmp2
);
3135 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3136 tcg_temp_free_i32(tmp2
);
3148 case 11: /* cmpez */
3152 case 15: /* single<->double conversion */
3154 gen_helper_vfp_fcvtsd(cpu_F0s
, cpu_F0d
, cpu_env
);
3156 gen_helper_vfp_fcvtds(cpu_F0d
, cpu_F0s
, cpu_env
);
3158 case 16: /* fuito */
3161 case 17: /* fsito */
3164 case 20: /* fshto */
3165 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3167 gen_vfp_shto(dp
, 16 - rm
);
3169 case 21: /* fslto */
3170 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3172 gen_vfp_slto(dp
, 32 - rm
);
3174 case 22: /* fuhto */
3175 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3177 gen_vfp_uhto(dp
, 16 - rm
);
3179 case 23: /* fulto */
3180 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3182 gen_vfp_ulto(dp
, 32 - rm
);
3184 case 24: /* ftoui */
3187 case 25: /* ftouiz */
3190 case 26: /* ftosi */
3193 case 27: /* ftosiz */
3196 case 28: /* ftosh */
3197 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3199 gen_vfp_tosh(dp
, 16 - rm
);
3201 case 29: /* ftosl */
3202 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3204 gen_vfp_tosl(dp
, 32 - rm
);
3206 case 30: /* ftouh */
3207 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3209 gen_vfp_touh(dp
, 16 - rm
);
3211 case 31: /* ftoul */
3212 if (!arm_feature(env
, ARM_FEATURE_VFP3
))
3214 gen_vfp_toul(dp
, 32 - rm
);
3216 default: /* undefined */
3217 printf ("rn:%d\n", rn
);
3221 default: /* undefined */
3222 printf ("op:%d\n", op
);
3226 /* Write back the result. */
3227 if (op
== 15 && (rn
>= 8 && rn
<= 11))
3228 ; /* Comparison, do nothing. */
3229 else if (op
== 15 && dp
&& ((rn
& 0x1c) == 0x18))
3230 /* VCVT double to int: always integer result. */
3231 gen_mov_vreg_F0(0, rd
);
3232 else if (op
== 15 && rn
== 15)
3234 gen_mov_vreg_F0(!dp
, rd
);
3236 gen_mov_vreg_F0(dp
, rd
);
3238 /* break out of the loop if we have finished */
3242 if (op
== 15 && delta_m
== 0) {
3243 /* single source one-many */
3245 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3247 gen_mov_vreg_F0(dp
, rd
);
3251 /* Setup the next operands. */
3253 rd
= ((rd
+ delta_d
) & (bank_mask
- 1))
3257 /* One source operand. */
3258 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3260 gen_mov_F0_vreg(dp
, rm
);
3262 /* Two source operands. */
3263 rn
= ((rn
+ delta_d
) & (bank_mask
- 1))
3265 gen_mov_F0_vreg(dp
, rn
);
3267 rm
= ((rm
+ delta_m
) & (bank_mask
- 1))
3269 gen_mov_F1_vreg(dp
, rm
);
3277 if ((insn
& 0x03e00000) == 0x00400000) {
3278 /* two-register transfer */
3279 rn
= (insn
>> 16) & 0xf;
3280 rd
= (insn
>> 12) & 0xf;
3282 VFP_DREG_M(rm
, insn
);
3284 rm
= VFP_SREG_M(insn
);
3287 if (insn
& ARM_CP_RW_BIT
) {
3290 gen_mov_F0_vreg(0, rm
* 2);
3291 tmp
= gen_vfp_mrs();
3292 store_reg(s
, rd
, tmp
);
3293 gen_mov_F0_vreg(0, rm
* 2 + 1);
3294 tmp
= gen_vfp_mrs();
3295 store_reg(s
, rn
, tmp
);
3297 gen_mov_F0_vreg(0, rm
);
3298 tmp
= gen_vfp_mrs();
3299 store_reg(s
, rd
, tmp
);
3300 gen_mov_F0_vreg(0, rm
+ 1);
3301 tmp
= gen_vfp_mrs();
3302 store_reg(s
, rn
, tmp
);
3307 tmp
= load_reg(s
, rd
);
3309 gen_mov_vreg_F0(0, rm
* 2);
3310 tmp
= load_reg(s
, rn
);
3312 gen_mov_vreg_F0(0, rm
* 2 + 1);
3314 tmp
= load_reg(s
, rd
);
3316 gen_mov_vreg_F0(0, rm
);
3317 tmp
= load_reg(s
, rn
);
3319 gen_mov_vreg_F0(0, rm
+ 1);
3324 rn
= (insn
>> 16) & 0xf;
3326 VFP_DREG_D(rd
, insn
);
3328 rd
= VFP_SREG_D(insn
);
3329 if (s
->thumb
&& rn
== 15) {
3330 addr
= tcg_temp_new_i32();
3331 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
3333 addr
= load_reg(s
, rn
);
3335 if ((insn
& 0x01200000) == 0x01000000) {
3336 /* Single load/store */
3337 offset
= (insn
& 0xff) << 2;
3338 if ((insn
& (1 << 23)) == 0)
3340 tcg_gen_addi_i32(addr
, addr
, offset
);
3341 if (insn
& (1 << 20)) {
3342 gen_vfp_ld(s
, dp
, addr
);
3343 gen_mov_vreg_F0(dp
, rd
);
3345 gen_mov_F0_vreg(dp
, rd
);
3346 gen_vfp_st(s
, dp
, addr
);
3348 tcg_temp_free_i32(addr
);
3350 /* load/store multiple */
3352 n
= (insn
>> 1) & 0x7f;
3356 if (insn
& (1 << 24)) /* pre-decrement */
3357 tcg_gen_addi_i32(addr
, addr
, -((insn
& 0xff) << 2));
3363 for (i
= 0; i
< n
; i
++) {
3364 if (insn
& ARM_CP_RW_BIT
) {
3366 gen_vfp_ld(s
, dp
, addr
);
3367 gen_mov_vreg_F0(dp
, rd
+ i
);
3370 gen_mov_F0_vreg(dp
, rd
+ i
);
3371 gen_vfp_st(s
, dp
, addr
);
3373 tcg_gen_addi_i32(addr
, addr
, offset
);
3375 if (insn
& (1 << 21)) {
3377 if (insn
& (1 << 24))
3378 offset
= -offset
* n
;
3379 else if (dp
&& (insn
& 1))
3385 tcg_gen_addi_i32(addr
, addr
, offset
);
3386 store_reg(s
, rn
, addr
);
3388 tcg_temp_free_i32(addr
);
3394 /* Should never happen. */
3400 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint32_t dest
)
3402 TranslationBlock
*tb
;
3405 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
3407 gen_set_pc_im(dest
);
3408 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
3410 gen_set_pc_im(dest
);
3415 static inline void gen_jmp (DisasContext
*s
, uint32_t dest
)
3417 if (unlikely(s
->singlestep_enabled
)) {
3418 /* An indirect jump so that we still trigger the debug exception. */
3423 gen_goto_tb(s
, 0, dest
);
3424 s
->is_jmp
= DISAS_TB_JUMP
;
3428 static inline void gen_mulxy(TCGv t0
, TCGv t1
, int x
, int y
)
3431 tcg_gen_sari_i32(t0
, t0
, 16);
3435 tcg_gen_sari_i32(t1
, t1
, 16);
3438 tcg_gen_mul_i32(t0
, t0
, t1
);
3441 /* Return the mask of PSR bits set by a MSR instruction. */
3442 static uint32_t msr_mask(CPUState
*env
, DisasContext
*s
, int flags
, int spsr
) {
3446 if (flags
& (1 << 0))
3448 if (flags
& (1 << 1))
3450 if (flags
& (1 << 2))
3452 if (flags
& (1 << 3))
3455 /* Mask out undefined bits. */
3456 mask
&= ~CPSR_RESERVED
;
3457 if (!arm_feature(env
, ARM_FEATURE_V4T
))
3459 if (!arm_feature(env
, ARM_FEATURE_V5
))
3460 mask
&= ~CPSR_Q
; /* V5TE in reality*/
3461 if (!arm_feature(env
, ARM_FEATURE_V6
))
3462 mask
&= ~(CPSR_E
| CPSR_GE
);
3463 if (!arm_feature(env
, ARM_FEATURE_THUMB2
))
3465 /* Mask out execution state bits. */
3468 /* Mask out privileged bits. */
3474 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
3475 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int spsr
, TCGv t0
)
3479 /* ??? This is also undefined in system mode. */
3483 tmp
= load_cpu_field(spsr
);
3484 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
3485 tcg_gen_andi_i32(t0
, t0
, mask
);
3486 tcg_gen_or_i32(tmp
, tmp
, t0
);
3487 store_cpu_field(tmp
, spsr
);
3489 gen_set_cpsr(t0
, mask
);
3491 tcg_temp_free_i32(t0
);
3496 /* Returns nonzero if access to the PSR is not permitted. */
3497 static int gen_set_psr_im(DisasContext
*s
, uint32_t mask
, int spsr
, uint32_t val
)
3500 tmp
= tcg_temp_new_i32();
3501 tcg_gen_movi_i32(tmp
, val
);
3502 return gen_set_psr(s
, mask
, spsr
, tmp
);
3505 /* Generate an old-style exception return. Marks pc as dead. */
3506 static void gen_exception_return(DisasContext
*s
, TCGv pc
)
3509 store_reg(s
, 15, pc
);
3510 tmp
= load_cpu_field(spsr
);
3511 gen_set_cpsr(tmp
, 0xffffffff);
3512 tcg_temp_free_i32(tmp
);
3513 s
->is_jmp
= DISAS_UPDATE
;
3516 /* Generate a v6 exception return. Marks both values as dead. */
3517 static void gen_rfe(DisasContext
*s
, TCGv pc
, TCGv cpsr
)
3519 gen_set_cpsr(cpsr
, 0xffffffff);
3520 tcg_temp_free_i32(cpsr
);
3521 store_reg(s
, 15, pc
);
3522 s
->is_jmp
= DISAS_UPDATE
;
3526 gen_set_condexec (DisasContext
*s
)
3528 if (s
->condexec_mask
) {
3529 uint32_t val
= (s
->condexec_cond
<< 4) | (s
->condexec_mask
>> 1);
3530 TCGv tmp
= tcg_temp_new_i32();
3531 tcg_gen_movi_i32(tmp
, val
);
3532 store_cpu_field(tmp
, condexec_bits
);
3536 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
)
3538 gen_set_condexec(s
);
3539 gen_set_pc_im(s
->pc
- offset
);
3540 gen_exception(excp
);
3541 s
->is_jmp
= DISAS_JUMP
;
3544 static void gen_nop_hint(DisasContext
*s
, int val
)
3548 gen_set_pc_im(s
->pc
);
3549 s
->is_jmp
= DISAS_WFI
;
3553 /* TODO: Implement SEV and WFE. May help SMP performance. */
3559 #define CPU_V001 cpu_V0, cpu_V0, cpu_V1
3561 static inline void gen_neon_add(int size
, TCGv t0
, TCGv t1
)
3564 case 0: gen_helper_neon_add_u8(t0
, t0
, t1
); break;
3565 case 1: gen_helper_neon_add_u16(t0
, t0
, t1
); break;
3566 case 2: tcg_gen_add_i32(t0
, t0
, t1
); break;
3571 static inline void gen_neon_rsb(int size
, TCGv t0
, TCGv t1
)
3574 case 0: gen_helper_neon_sub_u8(t0
, t1
, t0
); break;
3575 case 1: gen_helper_neon_sub_u16(t0
, t1
, t0
); break;
3576 case 2: tcg_gen_sub_i32(t0
, t1
, t0
); break;
3581 /* 32-bit pairwise ops end up the same as the elementwise versions. */
3582 #define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32
3583 #define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32
3584 #define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32
3585 #define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32
3587 #define GEN_NEON_INTEGER_OP_ENV(name) do { \
3588 switch ((size << 1) | u) { \
3590 gen_helper_neon_##name##_s8(tmp, cpu_env, tmp, tmp2); \
3593 gen_helper_neon_##name##_u8(tmp, cpu_env, tmp, tmp2); \
3596 gen_helper_neon_##name##_s16(tmp, cpu_env, tmp, tmp2); \
3599 gen_helper_neon_##name##_u16(tmp, cpu_env, tmp, tmp2); \
3602 gen_helper_neon_##name##_s32(tmp, cpu_env, tmp, tmp2); \
3605 gen_helper_neon_##name##_u32(tmp, cpu_env, tmp, tmp2); \
3607 default: return 1; \
3610 #define GEN_NEON_INTEGER_OP(name) do { \
3611 switch ((size << 1) | u) { \
3613 gen_helper_neon_##name##_s8(tmp, tmp, tmp2); \
3616 gen_helper_neon_##name##_u8(tmp, tmp, tmp2); \
3619 gen_helper_neon_##name##_s16(tmp, tmp, tmp2); \
3622 gen_helper_neon_##name##_u16(tmp, tmp, tmp2); \
3625 gen_helper_neon_##name##_s32(tmp, tmp, tmp2); \
3628 gen_helper_neon_##name##_u32(tmp, tmp, tmp2); \
3630 default: return 1; \
3633 static TCGv
neon_load_scratch(int scratch
)
3635 TCGv tmp
= tcg_temp_new_i32();
3636 tcg_gen_ld_i32(tmp
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3640 static void neon_store_scratch(int scratch
, TCGv var
)
3642 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUARMState
, vfp
.scratch
[scratch
]));
3643 tcg_temp_free_i32(var
);
3646 static inline TCGv
neon_get_scalar(int size
, int reg
)
3650 tmp
= neon_load_reg(reg
& 7, reg
>> 4);
3652 gen_neon_dup_high16(tmp
);
3654 gen_neon_dup_low16(tmp
);
3657 tmp
= neon_load_reg(reg
& 15, reg
>> 4);
3662 static int gen_neon_unzip(int rd
, int rm
, int size
, int q
)
3665 if (!q
&& size
== 2) {
3668 tmp
= tcg_const_i32(rd
);
3669 tmp2
= tcg_const_i32(rm
);
3673 gen_helper_neon_qunzip8(tmp
, tmp2
);
3676 gen_helper_neon_qunzip16(tmp
, tmp2
);
3679 gen_helper_neon_qunzip32(tmp
, tmp2
);
3687 gen_helper_neon_unzip8(tmp
, tmp2
);
3690 gen_helper_neon_unzip16(tmp
, tmp2
);
3696 tcg_temp_free_i32(tmp
);
3697 tcg_temp_free_i32(tmp2
);
3701 static int gen_neon_zip(int rd
, int rm
, int size
, int q
)
3704 if (!q
&& size
== 2) {
3707 tmp
= tcg_const_i32(rd
);
3708 tmp2
= tcg_const_i32(rm
);
3712 gen_helper_neon_qzip8(tmp
, tmp2
);
3715 gen_helper_neon_qzip16(tmp
, tmp2
);
3718 gen_helper_neon_qzip32(tmp
, tmp2
);
3726 gen_helper_neon_zip8(tmp
, tmp2
);
3729 gen_helper_neon_zip16(tmp
, tmp2
);
3735 tcg_temp_free_i32(tmp
);
3736 tcg_temp_free_i32(tmp2
);
3740 static void gen_neon_trn_u8(TCGv t0
, TCGv t1
)
3744 rd
= tcg_temp_new_i32();
3745 tmp
= tcg_temp_new_i32();
3747 tcg_gen_shli_i32(rd
, t0
, 8);
3748 tcg_gen_andi_i32(rd
, rd
, 0xff00ff00);
3749 tcg_gen_andi_i32(tmp
, t1
, 0x00ff00ff);
3750 tcg_gen_or_i32(rd
, rd
, tmp
);
3752 tcg_gen_shri_i32(t1
, t1
, 8);
3753 tcg_gen_andi_i32(t1
, t1
, 0x00ff00ff);
3754 tcg_gen_andi_i32(tmp
, t0
, 0xff00ff00);
3755 tcg_gen_or_i32(t1
, t1
, tmp
);
3756 tcg_gen_mov_i32(t0
, rd
);
3758 tcg_temp_free_i32(tmp
);
3759 tcg_temp_free_i32(rd
);
3762 static void gen_neon_trn_u16(TCGv t0
, TCGv t1
)
3766 rd
= tcg_temp_new_i32();
3767 tmp
= tcg_temp_new_i32();
3769 tcg_gen_shli_i32(rd
, t0
, 16);
3770 tcg_gen_andi_i32(tmp
, t1
, 0xffff);
3771 tcg_gen_or_i32(rd
, rd
, tmp
);
3772 tcg_gen_shri_i32(t1
, t1
, 16);
3773 tcg_gen_andi_i32(tmp
, t0
, 0xffff0000);
3774 tcg_gen_or_i32(t1
, t1
, tmp
);
3775 tcg_gen_mov_i32(t0
, rd
);
3777 tcg_temp_free_i32(tmp
);
3778 tcg_temp_free_i32(rd
);
3786 } neon_ls_element_type
[11] = {
3800 /* Translate a NEON load/store element instruction. Return nonzero if the
3801 instruction is invalid. */
3802 static int disas_neon_ls_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
3821 if (!s
->vfp_enabled
)
3823 VFP_DREG_D(rd
, insn
);
3824 rn
= (insn
>> 16) & 0xf;
3826 load
= (insn
& (1 << 21)) != 0;
3827 if ((insn
& (1 << 23)) == 0) {
3828 /* Load store all elements. */
3829 op
= (insn
>> 8) & 0xf;
3830 size
= (insn
>> 6) & 3;
3833 /* Catch UNDEF cases for bad values of align field */
3836 if (((insn
>> 5) & 1) == 1) {
3841 if (((insn
>> 4) & 3) == 3) {
3848 nregs
= neon_ls_element_type
[op
].nregs
;
3849 interleave
= neon_ls_element_type
[op
].interleave
;
3850 spacing
= neon_ls_element_type
[op
].spacing
;
3851 if (size
== 3 && (interleave
| spacing
) != 1)
3853 addr
= tcg_temp_new_i32();
3854 load_reg_var(s
, addr
, rn
);
3855 stride
= (1 << size
) * interleave
;
3856 for (reg
= 0; reg
< nregs
; reg
++) {
3857 if (interleave
> 2 || (interleave
== 2 && nregs
== 2)) {
3858 load_reg_var(s
, addr
, rn
);
3859 tcg_gen_addi_i32(addr
, addr
, (1 << size
) * reg
);
3860 } else if (interleave
== 2 && nregs
== 4 && reg
== 2) {
3861 load_reg_var(s
, addr
, rn
);
3862 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3866 tmp64
= gen_ld64(addr
, IS_USER(s
));
3867 neon_store_reg64(tmp64
, rd
);
3868 tcg_temp_free_i64(tmp64
);
3870 tmp64
= tcg_temp_new_i64();
3871 neon_load_reg64(tmp64
, rd
);
3872 gen_st64(tmp64
, addr
, IS_USER(s
));
3874 tcg_gen_addi_i32(addr
, addr
, stride
);
3876 for (pass
= 0; pass
< 2; pass
++) {
3879 tmp
= gen_ld32(addr
, IS_USER(s
));
3880 neon_store_reg(rd
, pass
, tmp
);
3882 tmp
= neon_load_reg(rd
, pass
);
3883 gen_st32(tmp
, addr
, IS_USER(s
));
3885 tcg_gen_addi_i32(addr
, addr
, stride
);
3886 } else if (size
== 1) {
3888 tmp
= gen_ld16u(addr
, IS_USER(s
));
3889 tcg_gen_addi_i32(addr
, addr
, stride
);
3890 tmp2
= gen_ld16u(addr
, IS_USER(s
));
3891 tcg_gen_addi_i32(addr
, addr
, stride
);
3892 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
3893 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
3894 tcg_temp_free_i32(tmp2
);
3895 neon_store_reg(rd
, pass
, tmp
);
3897 tmp
= neon_load_reg(rd
, pass
);
3898 tmp2
= tcg_temp_new_i32();
3899 tcg_gen_shri_i32(tmp2
, tmp
, 16);
3900 gen_st16(tmp
, addr
, IS_USER(s
));
3901 tcg_gen_addi_i32(addr
, addr
, stride
);
3902 gen_st16(tmp2
, addr
, IS_USER(s
));
3903 tcg_gen_addi_i32(addr
, addr
, stride
);
3905 } else /* size == 0 */ {
3908 for (n
= 0; n
< 4; n
++) {
3909 tmp
= gen_ld8u(addr
, IS_USER(s
));
3910 tcg_gen_addi_i32(addr
, addr
, stride
);
3914 tcg_gen_shli_i32(tmp
, tmp
, n
* 8);
3915 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
3916 tcg_temp_free_i32(tmp
);
3919 neon_store_reg(rd
, pass
, tmp2
);
3921 tmp2
= neon_load_reg(rd
, pass
);
3922 for (n
= 0; n
< 4; n
++) {
3923 tmp
= tcg_temp_new_i32();
3925 tcg_gen_mov_i32(tmp
, tmp2
);
3927 tcg_gen_shri_i32(tmp
, tmp2
, n
* 8);
3929 gen_st8(tmp
, addr
, IS_USER(s
));
3930 tcg_gen_addi_i32(addr
, addr
, stride
);
3932 tcg_temp_free_i32(tmp2
);
3939 tcg_temp_free_i32(addr
);
3942 size
= (insn
>> 10) & 3;
3944 /* Load single element to all lanes. */
3945 int a
= (insn
>> 4) & 1;
3949 size
= (insn
>> 6) & 3;
3950 nregs
= ((insn
>> 8) & 3) + 1;
3953 if (nregs
!= 4 || a
== 0) {
3956 /* For VLD4 size==3 a == 1 means 32 bits at 16 byte alignment */
3959 if (nregs
== 1 && a
== 1 && size
== 0) {
3962 if (nregs
== 3 && a
== 1) {
3965 addr
= tcg_temp_new_i32();
3966 load_reg_var(s
, addr
, rn
);
3968 /* VLD1 to all lanes: bit 5 indicates how many Dregs to write */
3969 tmp
= gen_load_and_replicate(s
, addr
, size
);
3970 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 0));
3971 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 1));
3972 if (insn
& (1 << 5)) {
3973 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
+ 1, 0));
3974 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
+ 1, 1));
3976 tcg_temp_free_i32(tmp
);
3978 /* VLD2/3/4 to all lanes: bit 5 indicates register stride */
3979 stride
= (insn
& (1 << 5)) ? 2 : 1;
3980 for (reg
= 0; reg
< nregs
; reg
++) {
3981 tmp
= gen_load_and_replicate(s
, addr
, size
);
3982 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 0));
3983 tcg_gen_st_i32(tmp
, cpu_env
, neon_reg_offset(rd
, 1));
3984 tcg_temp_free_i32(tmp
);
3985 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
3989 tcg_temp_free_i32(addr
);
3990 stride
= (1 << size
) * nregs
;
3992 /* Single element. */
3993 int idx
= (insn
>> 4) & 0xf;
3994 pass
= (insn
>> 7) & 1;
3997 shift
= ((insn
>> 5) & 3) * 8;
4001 shift
= ((insn
>> 6) & 1) * 16;
4002 stride
= (insn
& (1 << 5)) ? 2 : 1;
4006 stride
= (insn
& (1 << 6)) ? 2 : 1;
4011 nregs
= ((insn
>> 8) & 3) + 1;
4012 /* Catch the UNDEF cases. This is unavoidably a bit messy. */
4015 if (((idx
& (1 << size
)) != 0) ||
4016 (size
== 2 && ((idx
& 3) == 1 || (idx
& 3) == 2))) {
4021 if ((idx
& 1) != 0) {
4026 if (size
== 2 && (idx
& 2) != 0) {
4031 if ((size
== 2) && ((idx
& 3) == 3)) {
4038 if ((rd
+ stride
* (nregs
- 1)) > 31) {
4039 /* Attempts to write off the end of the register file
4040 * are UNPREDICTABLE; we choose to UNDEF because otherwise
4041 * the neon_load_reg() would write off the end of the array.
4045 addr
= tcg_temp_new_i32();
4046 load_reg_var(s
, addr
, rn
);
4047 for (reg
= 0; reg
< nregs
; reg
++) {
4051 tmp
= gen_ld8u(addr
, IS_USER(s
));
4054 tmp
= gen_ld16u(addr
, IS_USER(s
));
4057 tmp
= gen_ld32(addr
, IS_USER(s
));
4059 default: /* Avoid compiler warnings. */
4063 tmp2
= neon_load_reg(rd
, pass
);
4064 gen_bfi(tmp
, tmp2
, tmp
, shift
, size
? 0xffff : 0xff);
4065 tcg_temp_free_i32(tmp2
);
4067 neon_store_reg(rd
, pass
, tmp
);
4068 } else { /* Store */
4069 tmp
= neon_load_reg(rd
, pass
);
4071 tcg_gen_shri_i32(tmp
, tmp
, shift
);
4074 gen_st8(tmp
, addr
, IS_USER(s
));
4077 gen_st16(tmp
, addr
, IS_USER(s
));
4080 gen_st32(tmp
, addr
, IS_USER(s
));
4085 tcg_gen_addi_i32(addr
, addr
, 1 << size
);
4087 tcg_temp_free_i32(addr
);
4088 stride
= nregs
* (1 << size
);
4094 base
= load_reg(s
, rn
);
4096 tcg_gen_addi_i32(base
, base
, stride
);
4099 index
= load_reg(s
, rm
);
4100 tcg_gen_add_i32(base
, base
, index
);
4101 tcg_temp_free_i32(index
);
4103 store_reg(s
, rn
, base
);
4108 /* Bitwise select. dest = c ? t : f. Clobbers T and F. */
4109 static void gen_neon_bsl(TCGv dest
, TCGv t
, TCGv f
, TCGv c
)
4111 tcg_gen_and_i32(t
, t
, c
);
4112 tcg_gen_andc_i32(f
, f
, c
);
4113 tcg_gen_or_i32(dest
, t
, f
);
4116 static inline void gen_neon_narrow(int size
, TCGv dest
, TCGv_i64 src
)
4119 case 0: gen_helper_neon_narrow_u8(dest
, src
); break;
4120 case 1: gen_helper_neon_narrow_u16(dest
, src
); break;
4121 case 2: tcg_gen_trunc_i64_i32(dest
, src
); break;
4126 static inline void gen_neon_narrow_sats(int size
, TCGv dest
, TCGv_i64 src
)
4129 case 0: gen_helper_neon_narrow_sat_s8(dest
, src
); break;
4130 case 1: gen_helper_neon_narrow_sat_s16(dest
, src
); break;
4131 case 2: gen_helper_neon_narrow_sat_s32(dest
, src
); break;
4136 static inline void gen_neon_narrow_satu(int size
, TCGv dest
, TCGv_i64 src
)
4139 case 0: gen_helper_neon_narrow_sat_u8(dest
, src
); break;
4140 case 1: gen_helper_neon_narrow_sat_u16(dest
, src
); break;
4141 case 2: gen_helper_neon_narrow_sat_u32(dest
, src
); break;
4146 static inline void gen_neon_unarrow_sats(int size
, TCGv dest
, TCGv_i64 src
)
4149 case 0: gen_helper_neon_unarrow_sat8(dest
, src
); break;
4150 case 1: gen_helper_neon_unarrow_sat16(dest
, src
); break;
4151 case 2: gen_helper_neon_unarrow_sat32(dest
, src
); break;
4156 static inline void gen_neon_shift_narrow(int size
, TCGv var
, TCGv shift
,
4162 case 1: gen_helper_neon_rshl_u16(var
, var
, shift
); break;
4163 case 2: gen_helper_neon_rshl_u32(var
, var
, shift
); break;
4168 case 1: gen_helper_neon_rshl_s16(var
, var
, shift
); break;
4169 case 2: gen_helper_neon_rshl_s32(var
, var
, shift
); break;
4176 case 1: gen_helper_neon_shl_u16(var
, var
, shift
); break;
4177 case 2: gen_helper_neon_shl_u32(var
, var
, shift
); break;
4182 case 1: gen_helper_neon_shl_s16(var
, var
, shift
); break;
4183 case 2: gen_helper_neon_shl_s32(var
, var
, shift
); break;
4190 static inline void gen_neon_widen(TCGv_i64 dest
, TCGv src
, int size
, int u
)
4194 case 0: gen_helper_neon_widen_u8(dest
, src
); break;
4195 case 1: gen_helper_neon_widen_u16(dest
, src
); break;
4196 case 2: tcg_gen_extu_i32_i64(dest
, src
); break;
4201 case 0: gen_helper_neon_widen_s8(dest
, src
); break;
4202 case 1: gen_helper_neon_widen_s16(dest
, src
); break;
4203 case 2: tcg_gen_ext_i32_i64(dest
, src
); break;
4207 tcg_temp_free_i32(src
);
4210 static inline void gen_neon_addl(int size
)
4213 case 0: gen_helper_neon_addl_u16(CPU_V001
); break;
4214 case 1: gen_helper_neon_addl_u32(CPU_V001
); break;
4215 case 2: tcg_gen_add_i64(CPU_V001
); break;
4220 static inline void gen_neon_subl(int size
)
4223 case 0: gen_helper_neon_subl_u16(CPU_V001
); break;
4224 case 1: gen_helper_neon_subl_u32(CPU_V001
); break;
4225 case 2: tcg_gen_sub_i64(CPU_V001
); break;
4230 static inline void gen_neon_negl(TCGv_i64 var
, int size
)
4233 case 0: gen_helper_neon_negl_u16(var
, var
); break;
4234 case 1: gen_helper_neon_negl_u32(var
, var
); break;
4235 case 2: gen_helper_neon_negl_u64(var
, var
); break;
4240 static inline void gen_neon_addl_saturate(TCGv_i64 op0
, TCGv_i64 op1
, int size
)
4243 case 1: gen_helper_neon_addl_saturate_s32(op0
, op0
, op1
); break;
4244 case 2: gen_helper_neon_addl_saturate_s64(op0
, op0
, op1
); break;
4249 static inline void gen_neon_mull(TCGv_i64 dest
, TCGv a
, TCGv b
, int size
, int u
)
4253 switch ((size
<< 1) | u
) {
4254 case 0: gen_helper_neon_mull_s8(dest
, a
, b
); break;
4255 case 1: gen_helper_neon_mull_u8(dest
, a
, b
); break;
4256 case 2: gen_helper_neon_mull_s16(dest
, a
, b
); break;
4257 case 3: gen_helper_neon_mull_u16(dest
, a
, b
); break;
4259 tmp
= gen_muls_i64_i32(a
, b
);
4260 tcg_gen_mov_i64(dest
, tmp
);
4261 tcg_temp_free_i64(tmp
);
4264 tmp
= gen_mulu_i64_i32(a
, b
);
4265 tcg_gen_mov_i64(dest
, tmp
);
4266 tcg_temp_free_i64(tmp
);
4271 /* gen_helper_neon_mull_[su]{8|16} do not free their parameters.
4272 Don't forget to clean them now. */
4274 tcg_temp_free_i32(a
);
4275 tcg_temp_free_i32(b
);
4279 static void gen_neon_narrow_op(int op
, int u
, int size
, TCGv dest
, TCGv_i64 src
)
4283 gen_neon_unarrow_sats(size
, dest
, src
);
4285 gen_neon_narrow(size
, dest
, src
);
4289 gen_neon_narrow_satu(size
, dest
, src
);
4291 gen_neon_narrow_sats(size
, dest
, src
);
4296 /* Symbolic constants for op fields for Neon 3-register same-length.
4297 * The values correspond to bits [11:8,4]; see the ARM ARM DDI0406B
4300 #define NEON_3R_VHADD 0
4301 #define NEON_3R_VQADD 1
4302 #define NEON_3R_VRHADD 2
4303 #define NEON_3R_LOGIC 3 /* VAND,VBIC,VORR,VMOV,VORN,VEOR,VBIF,VBIT,VBSL */
4304 #define NEON_3R_VHSUB 4
4305 #define NEON_3R_VQSUB 5
4306 #define NEON_3R_VCGT 6
4307 #define NEON_3R_VCGE 7
4308 #define NEON_3R_VSHL 8
4309 #define NEON_3R_VQSHL 9
4310 #define NEON_3R_VRSHL 10
4311 #define NEON_3R_VQRSHL 11
4312 #define NEON_3R_VMAX 12
4313 #define NEON_3R_VMIN 13
4314 #define NEON_3R_VABD 14
4315 #define NEON_3R_VABA 15
4316 #define NEON_3R_VADD_VSUB 16
4317 #define NEON_3R_VTST_VCEQ 17
4318 #define NEON_3R_VML 18 /* VMLA, VMLAL, VMLS, VMLSL */
4319 #define NEON_3R_VMUL 19
4320 #define NEON_3R_VPMAX 20
4321 #define NEON_3R_VPMIN 21
4322 #define NEON_3R_VQDMULH_VQRDMULH 22
4323 #define NEON_3R_VPADD 23
4324 #define NEON_3R_FLOAT_ARITH 26 /* float VADD, VSUB, VPADD, VABD */
4325 #define NEON_3R_FLOAT_MULTIPLY 27 /* float VMLA, VMLS, VMUL */
4326 #define NEON_3R_FLOAT_CMP 28 /* float VCEQ, VCGE, VCGT */
4327 #define NEON_3R_FLOAT_ACMP 29 /* float VACGE, VACGT, VACLE, VACLT */
4328 #define NEON_3R_FLOAT_MINMAX 30 /* float VMIN, VMAX */
4329 #define NEON_3R_VRECPS_VRSQRTS 31 /* float VRECPS, VRSQRTS */
4331 static const uint8_t neon_3r_sizes
[] = {
4332 [NEON_3R_VHADD
] = 0x7,
4333 [NEON_3R_VQADD
] = 0xf,
4334 [NEON_3R_VRHADD
] = 0x7,
4335 [NEON_3R_LOGIC
] = 0xf, /* size field encodes op type */
4336 [NEON_3R_VHSUB
] = 0x7,
4337 [NEON_3R_VQSUB
] = 0xf,
4338 [NEON_3R_VCGT
] = 0x7,
4339 [NEON_3R_VCGE
] = 0x7,
4340 [NEON_3R_VSHL
] = 0xf,
4341 [NEON_3R_VQSHL
] = 0xf,
4342 [NEON_3R_VRSHL
] = 0xf,
4343 [NEON_3R_VQRSHL
] = 0xf,
4344 [NEON_3R_VMAX
] = 0x7,
4345 [NEON_3R_VMIN
] = 0x7,
4346 [NEON_3R_VABD
] = 0x7,
4347 [NEON_3R_VABA
] = 0x7,
4348 [NEON_3R_VADD_VSUB
] = 0xf,
4349 [NEON_3R_VTST_VCEQ
] = 0x7,
4350 [NEON_3R_VML
] = 0x7,
4351 [NEON_3R_VMUL
] = 0x7,
4352 [NEON_3R_VPMAX
] = 0x7,
4353 [NEON_3R_VPMIN
] = 0x7,
4354 [NEON_3R_VQDMULH_VQRDMULH
] = 0x6,
4355 [NEON_3R_VPADD
] = 0x7,
4356 [NEON_3R_FLOAT_ARITH
] = 0x5, /* size bit 1 encodes op */
4357 [NEON_3R_FLOAT_MULTIPLY
] = 0x5, /* size bit 1 encodes op */
4358 [NEON_3R_FLOAT_CMP
] = 0x5, /* size bit 1 encodes op */
4359 [NEON_3R_FLOAT_ACMP
] = 0x5, /* size bit 1 encodes op */
4360 [NEON_3R_FLOAT_MINMAX
] = 0x5, /* size bit 1 encodes op */
4361 [NEON_3R_VRECPS_VRSQRTS
] = 0x5, /* size bit 1 encodes op */
4364 /* Symbolic constants for op fields for Neon 2-register miscellaneous.
4365 * The values correspond to bits [17:16,10:7]; see the ARM ARM DDI0406B
4368 #define NEON_2RM_VREV64 0
4369 #define NEON_2RM_VREV32 1
4370 #define NEON_2RM_VREV16 2
4371 #define NEON_2RM_VPADDL 4
4372 #define NEON_2RM_VPADDL_U 5
4373 #define NEON_2RM_VCLS 8
4374 #define NEON_2RM_VCLZ 9
4375 #define NEON_2RM_VCNT 10
4376 #define NEON_2RM_VMVN 11
4377 #define NEON_2RM_VPADAL 12
4378 #define NEON_2RM_VPADAL_U 13
4379 #define NEON_2RM_VQABS 14
4380 #define NEON_2RM_VQNEG 15
4381 #define NEON_2RM_VCGT0 16
4382 #define NEON_2RM_VCGE0 17
4383 #define NEON_2RM_VCEQ0 18
4384 #define NEON_2RM_VCLE0 19
4385 #define NEON_2RM_VCLT0 20
4386 #define NEON_2RM_VABS 22
4387 #define NEON_2RM_VNEG 23
4388 #define NEON_2RM_VCGT0_F 24
4389 #define NEON_2RM_VCGE0_F 25
4390 #define NEON_2RM_VCEQ0_F 26
4391 #define NEON_2RM_VCLE0_F 27
4392 #define NEON_2RM_VCLT0_F 28
4393 #define NEON_2RM_VABS_F 30
4394 #define NEON_2RM_VNEG_F 31
4395 #define NEON_2RM_VSWP 32
4396 #define NEON_2RM_VTRN 33
4397 #define NEON_2RM_VUZP 34
4398 #define NEON_2RM_VZIP 35
4399 #define NEON_2RM_VMOVN 36 /* Includes VQMOVN, VQMOVUN */
4400 #define NEON_2RM_VQMOVN 37 /* Includes VQMOVUN */
4401 #define NEON_2RM_VSHLL 38
4402 #define NEON_2RM_VCVT_F16_F32 44
4403 #define NEON_2RM_VCVT_F32_F16 46
4404 #define NEON_2RM_VRECPE 56
4405 #define NEON_2RM_VRSQRTE 57
4406 #define NEON_2RM_VRECPE_F 58
4407 #define NEON_2RM_VRSQRTE_F 59
4408 #define NEON_2RM_VCVT_FS 60
4409 #define NEON_2RM_VCVT_FU 61
4410 #define NEON_2RM_VCVT_SF 62
4411 #define NEON_2RM_VCVT_UF 63
4413 static int neon_2rm_is_float_op(int op
)
4415 /* Return true if this neon 2reg-misc op is float-to-float */
4416 return (op
== NEON_2RM_VABS_F
|| op
== NEON_2RM_VNEG_F
||
4417 op
>= NEON_2RM_VRECPE_F
);
4420 /* Each entry in this array has bit n set if the insn allows
4421 * size value n (otherwise it will UNDEF). Since unallocated
4422 * op values will have no bits set they always UNDEF.
4424 static const uint8_t neon_2rm_sizes
[] = {
4425 [NEON_2RM_VREV64
] = 0x7,
4426 [NEON_2RM_VREV32
] = 0x3,
4427 [NEON_2RM_VREV16
] = 0x1,
4428 [NEON_2RM_VPADDL
] = 0x7,
4429 [NEON_2RM_VPADDL_U
] = 0x7,
4430 [NEON_2RM_VCLS
] = 0x7,
4431 [NEON_2RM_VCLZ
] = 0x7,
4432 [NEON_2RM_VCNT
] = 0x1,
4433 [NEON_2RM_VMVN
] = 0x1,
4434 [NEON_2RM_VPADAL
] = 0x7,
4435 [NEON_2RM_VPADAL_U
] = 0x7,
4436 [NEON_2RM_VQABS
] = 0x7,
4437 [NEON_2RM_VQNEG
] = 0x7,
4438 [NEON_2RM_VCGT0
] = 0x7,
4439 [NEON_2RM_VCGE0
] = 0x7,
4440 [NEON_2RM_VCEQ0
] = 0x7,
4441 [NEON_2RM_VCLE0
] = 0x7,
4442 [NEON_2RM_VCLT0
] = 0x7,
4443 [NEON_2RM_VABS
] = 0x7,
4444 [NEON_2RM_VNEG
] = 0x7,
4445 [NEON_2RM_VCGT0_F
] = 0x4,
4446 [NEON_2RM_VCGE0_F
] = 0x4,
4447 [NEON_2RM_VCEQ0_F
] = 0x4,
4448 [NEON_2RM_VCLE0_F
] = 0x4,
4449 [NEON_2RM_VCLT0_F
] = 0x4,
4450 [NEON_2RM_VABS_F
] = 0x4,
4451 [NEON_2RM_VNEG_F
] = 0x4,
4452 [NEON_2RM_VSWP
] = 0x1,
4453 [NEON_2RM_VTRN
] = 0x7,
4454 [NEON_2RM_VUZP
] = 0x7,
4455 [NEON_2RM_VZIP
] = 0x7,
4456 [NEON_2RM_VMOVN
] = 0x7,
4457 [NEON_2RM_VQMOVN
] = 0x7,
4458 [NEON_2RM_VSHLL
] = 0x7,
4459 [NEON_2RM_VCVT_F16_F32
] = 0x2,
4460 [NEON_2RM_VCVT_F32_F16
] = 0x2,
4461 [NEON_2RM_VRECPE
] = 0x4,
4462 [NEON_2RM_VRSQRTE
] = 0x4,
4463 [NEON_2RM_VRECPE_F
] = 0x4,
4464 [NEON_2RM_VRSQRTE_F
] = 0x4,
4465 [NEON_2RM_VCVT_FS
] = 0x4,
4466 [NEON_2RM_VCVT_FU
] = 0x4,
4467 [NEON_2RM_VCVT_SF
] = 0x4,
4468 [NEON_2RM_VCVT_UF
] = 0x4,
4471 /* Translate a NEON data processing instruction. Return nonzero if the
4472 instruction is invalid.
4473 We process data in a mixture of 32-bit and 64-bit chunks.
4474 Mostly we use 32-bit chunks so we can use normal scalar instructions. */
4476 static int disas_neon_data_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
4488 TCGv tmp
, tmp2
, tmp3
, tmp4
, tmp5
;
4491 if (!s
->vfp_enabled
)
4493 q
= (insn
& (1 << 6)) != 0;
4494 u
= (insn
>> 24) & 1;
4495 VFP_DREG_D(rd
, insn
);
4496 VFP_DREG_N(rn
, insn
);
4497 VFP_DREG_M(rm
, insn
);
4498 size
= (insn
>> 20) & 3;
4499 if ((insn
& (1 << 23)) == 0) {
4500 /* Three register same length. */
4501 op
= ((insn
>> 7) & 0x1e) | ((insn
>> 4) & 1);
4502 /* Catch invalid op and bad size combinations: UNDEF */
4503 if ((neon_3r_sizes
[op
] & (1 << size
)) == 0) {
4506 /* All insns of this form UNDEF for either this condition or the
4507 * superset of cases "Q==1"; we catch the latter later.
4509 if (q
&& ((rd
| rn
| rm
) & 1)) {
4512 if (size
== 3 && op
!= NEON_3R_LOGIC
) {
4513 /* 64-bit element instructions. */
4514 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
4515 neon_load_reg64(cpu_V0
, rn
+ pass
);
4516 neon_load_reg64(cpu_V1
, rm
+ pass
);
4520 gen_helper_neon_qadd_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4522 gen_helper_neon_qadd_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4527 gen_helper_neon_qsub_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4529 gen_helper_neon_qsub_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4534 gen_helper_neon_shl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4536 gen_helper_neon_shl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4541 gen_helper_neon_qshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4543 gen_helper_neon_qshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4548 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4550 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4553 case NEON_3R_VQRSHL
:
4555 gen_helper_neon_qrshl_u64(cpu_V0
, cpu_V1
, cpu_V0
);
4557 gen_helper_neon_qrshl_s64(cpu_V0
, cpu_V1
, cpu_V0
);
4560 case NEON_3R_VADD_VSUB
:
4562 tcg_gen_sub_i64(CPU_V001
);
4564 tcg_gen_add_i64(CPU_V001
);
4570 neon_store_reg64(cpu_V0
, rd
+ pass
);
4579 case NEON_3R_VQRSHL
:
4582 /* Shift instruction operands are reversed. */
4597 case NEON_3R_FLOAT_ARITH
:
4598 pairwise
= (u
&& size
< 2); /* if VPADD (float) */
4600 case NEON_3R_FLOAT_MINMAX
:
4601 pairwise
= u
; /* if VPMIN/VPMAX (float) */
4603 case NEON_3R_FLOAT_CMP
:
4605 /* no encoding for U=0 C=1x */
4609 case NEON_3R_FLOAT_ACMP
:
4614 case NEON_3R_VRECPS_VRSQRTS
:
4620 if (u
&& (size
!= 0)) {
4621 /* UNDEF on invalid size for polynomial subcase */
4629 if (pairwise
&& q
) {
4630 /* All the pairwise insns UNDEF if Q is set */
4634 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4639 tmp
= neon_load_reg(rn
, 0);
4640 tmp2
= neon_load_reg(rn
, 1);
4642 tmp
= neon_load_reg(rm
, 0);
4643 tmp2
= neon_load_reg(rm
, 1);
4647 tmp
= neon_load_reg(rn
, pass
);
4648 tmp2
= neon_load_reg(rm
, pass
);
4652 GEN_NEON_INTEGER_OP(hadd
);
4655 GEN_NEON_INTEGER_OP(qadd
);
4657 case NEON_3R_VRHADD
:
4658 GEN_NEON_INTEGER_OP(rhadd
);
4660 case NEON_3R_LOGIC
: /* Logic ops. */
4661 switch ((u
<< 2) | size
) {
4663 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
4666 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
4669 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
4672 tcg_gen_orc_i32(tmp
, tmp
, tmp2
);
4675 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
4678 tmp3
= neon_load_reg(rd
, pass
);
4679 gen_neon_bsl(tmp
, tmp
, tmp2
, tmp3
);
4680 tcg_temp_free_i32(tmp3
);
4683 tmp3
= neon_load_reg(rd
, pass
);
4684 gen_neon_bsl(tmp
, tmp
, tmp3
, tmp2
);
4685 tcg_temp_free_i32(tmp3
);
4688 tmp3
= neon_load_reg(rd
, pass
);
4689 gen_neon_bsl(tmp
, tmp3
, tmp
, tmp2
);
4690 tcg_temp_free_i32(tmp3
);
4695 GEN_NEON_INTEGER_OP(hsub
);
4698 GEN_NEON_INTEGER_OP(qsub
);
4701 GEN_NEON_INTEGER_OP(cgt
);
4704 GEN_NEON_INTEGER_OP(cge
);
4707 GEN_NEON_INTEGER_OP(shl
);
4710 GEN_NEON_INTEGER_OP(qshl
);
4713 GEN_NEON_INTEGER_OP(rshl
);
4715 case NEON_3R_VQRSHL
:
4716 GEN_NEON_INTEGER_OP(qrshl
);
4719 GEN_NEON_INTEGER_OP(max
);
4722 GEN_NEON_INTEGER_OP(min
);
4725 GEN_NEON_INTEGER_OP(abd
);
4728 GEN_NEON_INTEGER_OP(abd
);
4729 tcg_temp_free_i32(tmp2
);
4730 tmp2
= neon_load_reg(rd
, pass
);
4731 gen_neon_add(size
, tmp
, tmp2
);
4733 case NEON_3R_VADD_VSUB
:
4734 if (!u
) { /* VADD */
4735 gen_neon_add(size
, tmp
, tmp2
);
4738 case 0: gen_helper_neon_sub_u8(tmp
, tmp
, tmp2
); break;
4739 case 1: gen_helper_neon_sub_u16(tmp
, tmp
, tmp2
); break;
4740 case 2: tcg_gen_sub_i32(tmp
, tmp
, tmp2
); break;
4745 case NEON_3R_VTST_VCEQ
:
4746 if (!u
) { /* VTST */
4748 case 0: gen_helper_neon_tst_u8(tmp
, tmp
, tmp2
); break;
4749 case 1: gen_helper_neon_tst_u16(tmp
, tmp
, tmp2
); break;
4750 case 2: gen_helper_neon_tst_u32(tmp
, tmp
, tmp2
); break;
4755 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
4756 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
4757 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
4762 case NEON_3R_VML
: /* VMLA, VMLAL, VMLS,VMLSL */
4764 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
4765 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
4766 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
4769 tcg_temp_free_i32(tmp2
);
4770 tmp2
= neon_load_reg(rd
, pass
);
4772 gen_neon_rsb(size
, tmp
, tmp2
);
4774 gen_neon_add(size
, tmp
, tmp2
);
4778 if (u
) { /* polynomial */
4779 gen_helper_neon_mul_p8(tmp
, tmp
, tmp2
);
4780 } else { /* Integer */
4782 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
4783 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
4784 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
4790 GEN_NEON_INTEGER_OP(pmax
);
4793 GEN_NEON_INTEGER_OP(pmin
);
4795 case NEON_3R_VQDMULH_VQRDMULH
: /* Multiply high. */
4796 if (!u
) { /* VQDMULH */
4798 case 1: gen_helper_neon_qdmulh_s16(tmp
, tmp
, tmp2
); break;
4799 case 2: gen_helper_neon_qdmulh_s32(tmp
, tmp
, tmp2
); break;
4802 } else { /* VQRDMULH */
4804 case 1: gen_helper_neon_qrdmulh_s16(tmp
, tmp
, tmp2
); break;
4805 case 2: gen_helper_neon_qrdmulh_s32(tmp
, tmp
, tmp2
); break;
4812 case 0: gen_helper_neon_padd_u8(tmp
, tmp
, tmp2
); break;
4813 case 1: gen_helper_neon_padd_u16(tmp
, tmp
, tmp2
); break;
4814 case 2: tcg_gen_add_i32(tmp
, tmp
, tmp2
); break;
4818 case NEON_3R_FLOAT_ARITH
: /* Floating point arithmetic. */
4819 switch ((u
<< 2) | size
) {
4821 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4824 gen_helper_neon_sub_f32(tmp
, tmp
, tmp2
);
4827 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4830 gen_helper_neon_abd_f32(tmp
, tmp
, tmp2
);
4836 case NEON_3R_FLOAT_MULTIPLY
:
4837 gen_helper_neon_mul_f32(tmp
, tmp
, tmp2
);
4839 tcg_temp_free_i32(tmp2
);
4840 tmp2
= neon_load_reg(rd
, pass
);
4842 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
4844 gen_helper_neon_sub_f32(tmp
, tmp2
, tmp
);
4848 case NEON_3R_FLOAT_CMP
:
4850 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
);
4853 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
);
4855 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
);
4858 case NEON_3R_FLOAT_ACMP
:
4860 gen_helper_neon_acge_f32(tmp
, tmp
, tmp2
);
4862 gen_helper_neon_acgt_f32(tmp
, tmp
, tmp2
);
4864 case NEON_3R_FLOAT_MINMAX
:
4866 gen_helper_neon_max_f32(tmp
, tmp
, tmp2
);
4868 gen_helper_neon_min_f32(tmp
, tmp
, tmp2
);
4870 case NEON_3R_VRECPS_VRSQRTS
:
4872 gen_helper_recps_f32(tmp
, tmp
, tmp2
, cpu_env
);
4874 gen_helper_rsqrts_f32(tmp
, tmp
, tmp2
, cpu_env
);
4879 tcg_temp_free_i32(tmp2
);
4881 /* Save the result. For elementwise operations we can put it
4882 straight into the destination register. For pairwise operations
4883 we have to be careful to avoid clobbering the source operands. */
4884 if (pairwise
&& rd
== rm
) {
4885 neon_store_scratch(pass
, tmp
);
4887 neon_store_reg(rd
, pass
, tmp
);
4891 if (pairwise
&& rd
== rm
) {
4892 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
4893 tmp
= neon_load_scratch(pass
);
4894 neon_store_reg(rd
, pass
, tmp
);
4897 /* End of 3 register same size operations. */
4898 } else if (insn
& (1 << 4)) {
4899 if ((insn
& 0x00380080) != 0) {
4900 /* Two registers and shift. */
4901 op
= (insn
>> 8) & 0xf;
4902 if (insn
& (1 << 7)) {
4910 while ((insn
& (1 << (size
+ 19))) == 0)
4913 shift
= (insn
>> 16) & ((1 << (3 + size
)) - 1);
4914 /* To avoid excessive dumplication of ops we implement shift
4915 by immediate using the variable shift operations. */
4917 /* Shift by immediate:
4918 VSHR, VSRA, VRSHR, VRSRA, VSRI, VSHL, VQSHL, VQSHLU. */
4919 if (q
&& ((rd
| rm
) & 1)) {
4922 if (!u
&& (op
== 4 || op
== 6)) {
4925 /* Right shifts are encoded as N - shift, where N is the
4926 element size in bits. */
4928 shift
= shift
- (1 << (size
+ 3));
4936 imm
= (uint8_t) shift
;
4941 imm
= (uint16_t) shift
;
4952 for (pass
= 0; pass
< count
; pass
++) {
4954 neon_load_reg64(cpu_V0
, rm
+ pass
);
4955 tcg_gen_movi_i64(cpu_V1
, imm
);
4960 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4962 gen_helper_neon_shl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4967 gen_helper_neon_rshl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4969 gen_helper_neon_rshl_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4972 case 5: /* VSHL, VSLI */
4973 gen_helper_neon_shl_u64(cpu_V0
, cpu_V0
, cpu_V1
);
4975 case 6: /* VQSHLU */
4976 gen_helper_neon_qshlu_s64(cpu_V0
, cpu_V0
, cpu_V1
);
4980 gen_helper_neon_qshl_u64(cpu_V0
,
4983 gen_helper_neon_qshl_s64(cpu_V0
,
4988 if (op
== 1 || op
== 3) {
4990 neon_load_reg64(cpu_V1
, rd
+ pass
);
4991 tcg_gen_add_i64(cpu_V0
, cpu_V0
, cpu_V1
);
4992 } else if (op
== 4 || (op
== 5 && u
)) {
4994 neon_load_reg64(cpu_V1
, rd
+ pass
);
4996 if (shift
< -63 || shift
> 63) {
5000 mask
= 0xffffffffffffffffull
>> -shift
;
5002 mask
= 0xffffffffffffffffull
<< shift
;
5005 tcg_gen_andi_i64(cpu_V1
, cpu_V1
, ~mask
);
5006 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5008 neon_store_reg64(cpu_V0
, rd
+ pass
);
5009 } else { /* size < 3 */
5010 /* Operands in T0 and T1. */
5011 tmp
= neon_load_reg(rm
, pass
);
5012 tmp2
= tcg_temp_new_i32();
5013 tcg_gen_movi_i32(tmp2
, imm
);
5017 GEN_NEON_INTEGER_OP(shl
);
5021 GEN_NEON_INTEGER_OP(rshl
);
5024 case 5: /* VSHL, VSLI */
5026 case 0: gen_helper_neon_shl_u8(tmp
, tmp
, tmp2
); break;
5027 case 1: gen_helper_neon_shl_u16(tmp
, tmp
, tmp2
); break;
5028 case 2: gen_helper_neon_shl_u32(tmp
, tmp
, tmp2
); break;
5032 case 6: /* VQSHLU */
5035 gen_helper_neon_qshlu_s8(tmp
, tmp
, tmp2
);
5038 gen_helper_neon_qshlu_s16(tmp
, tmp
, tmp2
);
5041 gen_helper_neon_qshlu_s32(tmp
, tmp
, tmp2
);
5048 GEN_NEON_INTEGER_OP(qshl
);
5051 tcg_temp_free_i32(tmp2
);
5053 if (op
== 1 || op
== 3) {
5055 tmp2
= neon_load_reg(rd
, pass
);
5056 gen_neon_add(size
, tmp
, tmp2
);
5057 tcg_temp_free_i32(tmp2
);
5058 } else if (op
== 4 || (op
== 5 && u
)) {
5063 mask
= 0xff >> -shift
;
5065 mask
= (uint8_t)(0xff << shift
);
5071 mask
= 0xffff >> -shift
;
5073 mask
= (uint16_t)(0xffff << shift
);
5077 if (shift
< -31 || shift
> 31) {
5081 mask
= 0xffffffffu
>> -shift
;
5083 mask
= 0xffffffffu
<< shift
;
5089 tmp2
= neon_load_reg(rd
, pass
);
5090 tcg_gen_andi_i32(tmp
, tmp
, mask
);
5091 tcg_gen_andi_i32(tmp2
, tmp2
, ~mask
);
5092 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
5093 tcg_temp_free_i32(tmp2
);
5095 neon_store_reg(rd
, pass
, tmp
);
5098 } else if (op
< 10) {
5099 /* Shift by immediate and narrow:
5100 VSHRN, VRSHRN, VQSHRN, VQRSHRN. */
5101 int input_unsigned
= (op
== 8) ? !u
: u
;
5105 shift
= shift
- (1 << (size
+ 3));
5108 tmp64
= tcg_const_i64(shift
);
5109 neon_load_reg64(cpu_V0
, rm
);
5110 neon_load_reg64(cpu_V1
, rm
+ 1);
5111 for (pass
= 0; pass
< 2; pass
++) {
5119 if (input_unsigned
) {
5120 gen_helper_neon_rshl_u64(cpu_V0
, in
, tmp64
);
5122 gen_helper_neon_rshl_s64(cpu_V0
, in
, tmp64
);
5125 if (input_unsigned
) {
5126 gen_helper_neon_shl_u64(cpu_V0
, in
, tmp64
);
5128 gen_helper_neon_shl_s64(cpu_V0
, in
, tmp64
);
5131 tmp
= tcg_temp_new_i32();
5132 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
5133 neon_store_reg(rd
, pass
, tmp
);
5135 tcg_temp_free_i64(tmp64
);
5138 imm
= (uint16_t)shift
;
5142 imm
= (uint32_t)shift
;
5144 tmp2
= tcg_const_i32(imm
);
5145 tmp4
= neon_load_reg(rm
+ 1, 0);
5146 tmp5
= neon_load_reg(rm
+ 1, 1);
5147 for (pass
= 0; pass
< 2; pass
++) {
5149 tmp
= neon_load_reg(rm
, 0);
5153 gen_neon_shift_narrow(size
, tmp
, tmp2
, q
,
5156 tmp3
= neon_load_reg(rm
, 1);
5160 gen_neon_shift_narrow(size
, tmp3
, tmp2
, q
,
5162 tcg_gen_concat_i32_i64(cpu_V0
, tmp
, tmp3
);
5163 tcg_temp_free_i32(tmp
);
5164 tcg_temp_free_i32(tmp3
);
5165 tmp
= tcg_temp_new_i32();
5166 gen_neon_narrow_op(op
== 8, u
, size
- 1, tmp
, cpu_V0
);
5167 neon_store_reg(rd
, pass
, tmp
);
5169 tcg_temp_free_i32(tmp2
);
5171 } else if (op
== 10) {
5173 if (q
|| (rd
& 1)) {
5176 tmp
= neon_load_reg(rm
, 0);
5177 tmp2
= neon_load_reg(rm
, 1);
5178 for (pass
= 0; pass
< 2; pass
++) {
5182 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
5185 /* The shift is less than the width of the source
5186 type, so we can just shift the whole register. */
5187 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, shift
);
5188 /* Widen the result of shift: we need to clear
5189 * the potential overflow bits resulting from
5190 * left bits of the narrow input appearing as
5191 * right bits of left the neighbour narrow
5193 if (size
< 2 || !u
) {
5196 imm
= (0xffu
>> (8 - shift
));
5198 } else if (size
== 1) {
5199 imm
= 0xffff >> (16 - shift
);
5202 imm
= 0xffffffff >> (32 - shift
);
5205 imm64
= imm
| (((uint64_t)imm
) << 32);
5209 tcg_gen_andi_i64(cpu_V0
, cpu_V0
, ~imm64
);
5212 neon_store_reg64(cpu_V0
, rd
+ pass
);
5214 } else if (op
>= 14) {
5215 /* VCVT fixed-point. */
5216 if (!(insn
& (1 << 21)) || (q
&& ((rd
| rm
) & 1))) {
5219 /* We have already masked out the must-be-1 top bit of imm6,
5220 * hence this 32-shift where the ARM ARM has 64-imm6.
5223 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5224 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, pass
));
5227 gen_vfp_ulto(0, shift
);
5229 gen_vfp_slto(0, shift
);
5232 gen_vfp_toul(0, shift
);
5234 gen_vfp_tosl(0, shift
);
5236 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, pass
));
5241 } else { /* (insn & 0x00380080) == 0 */
5243 if (q
&& (rd
& 1)) {
5247 op
= (insn
>> 8) & 0xf;
5248 /* One register and immediate. */
5249 imm
= (u
<< 7) | ((insn
>> 12) & 0x70) | (insn
& 0xf);
5250 invert
= (insn
& (1 << 5)) != 0;
5251 /* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
5252 * We choose to not special-case this and will behave as if a
5253 * valid constant encoding of 0 had been given.
5272 imm
= (imm
<< 8) | (imm
<< 24);
5275 imm
= (imm
<< 8) | 0xff;
5278 imm
= (imm
<< 16) | 0xffff;
5281 imm
|= (imm
<< 8) | (imm
<< 16) | (imm
<< 24);
5289 imm
= ((imm
& 0x80) << 24) | ((imm
& 0x3f) << 19)
5290 | ((imm
& 0x40) ? (0x1f << 25) : (1 << 30));
5296 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5297 if (op
& 1 && op
< 12) {
5298 tmp
= neon_load_reg(rd
, pass
);
5300 /* The immediate value has already been inverted, so
5302 tcg_gen_andi_i32(tmp
, tmp
, imm
);
5304 tcg_gen_ori_i32(tmp
, tmp
, imm
);
5308 tmp
= tcg_temp_new_i32();
5309 if (op
== 14 && invert
) {
5313 for (n
= 0; n
< 4; n
++) {
5314 if (imm
& (1 << (n
+ (pass
& 1) * 4)))
5315 val
|= 0xff << (n
* 8);
5317 tcg_gen_movi_i32(tmp
, val
);
5319 tcg_gen_movi_i32(tmp
, imm
);
5322 neon_store_reg(rd
, pass
, tmp
);
5325 } else { /* (insn & 0x00800010 == 0x00800000) */
5327 op
= (insn
>> 8) & 0xf;
5328 if ((insn
& (1 << 6)) == 0) {
5329 /* Three registers of different lengths. */
5333 /* undefreq: bit 0 : UNDEF if size != 0
5334 * bit 1 : UNDEF if size == 0
5335 * bit 2 : UNDEF if U == 1
5336 * Note that [1:0] set implies 'always UNDEF'
5339 /* prewiden, src1_wide, src2_wide, undefreq */
5340 static const int neon_3reg_wide
[16][4] = {
5341 {1, 0, 0, 0}, /* VADDL */
5342 {1, 1, 0, 0}, /* VADDW */
5343 {1, 0, 0, 0}, /* VSUBL */
5344 {1, 1, 0, 0}, /* VSUBW */
5345 {0, 1, 1, 0}, /* VADDHN */
5346 {0, 0, 0, 0}, /* VABAL */
5347 {0, 1, 1, 0}, /* VSUBHN */
5348 {0, 0, 0, 0}, /* VABDL */
5349 {0, 0, 0, 0}, /* VMLAL */
5350 {0, 0, 0, 6}, /* VQDMLAL */
5351 {0, 0, 0, 0}, /* VMLSL */
5352 {0, 0, 0, 6}, /* VQDMLSL */
5353 {0, 0, 0, 0}, /* Integer VMULL */
5354 {0, 0, 0, 2}, /* VQDMULL */
5355 {0, 0, 0, 5}, /* Polynomial VMULL */
5356 {0, 0, 0, 3}, /* Reserved: always UNDEF */
5359 prewiden
= neon_3reg_wide
[op
][0];
5360 src1_wide
= neon_3reg_wide
[op
][1];
5361 src2_wide
= neon_3reg_wide
[op
][2];
5362 undefreq
= neon_3reg_wide
[op
][3];
5364 if (((undefreq
& 1) && (size
!= 0)) ||
5365 ((undefreq
& 2) && (size
== 0)) ||
5366 ((undefreq
& 4) && u
)) {
5369 if ((src1_wide
&& (rn
& 1)) ||
5370 (src2_wide
&& (rm
& 1)) ||
5371 (!src2_wide
&& (rd
& 1))) {
5375 /* Avoid overlapping operands. Wide source operands are
5376 always aligned so will never overlap with wide
5377 destinations in problematic ways. */
5378 if (rd
== rm
&& !src2_wide
) {
5379 tmp
= neon_load_reg(rm
, 1);
5380 neon_store_scratch(2, tmp
);
5381 } else if (rd
== rn
&& !src1_wide
) {
5382 tmp
= neon_load_reg(rn
, 1);
5383 neon_store_scratch(2, tmp
);
5386 for (pass
= 0; pass
< 2; pass
++) {
5388 neon_load_reg64(cpu_V0
, rn
+ pass
);
5391 if (pass
== 1 && rd
== rn
) {
5392 tmp
= neon_load_scratch(2);
5394 tmp
= neon_load_reg(rn
, pass
);
5397 gen_neon_widen(cpu_V0
, tmp
, size
, u
);
5401 neon_load_reg64(cpu_V1
, rm
+ pass
);
5404 if (pass
== 1 && rd
== rm
) {
5405 tmp2
= neon_load_scratch(2);
5407 tmp2
= neon_load_reg(rm
, pass
);
5410 gen_neon_widen(cpu_V1
, tmp2
, size
, u
);
5414 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
5415 gen_neon_addl(size
);
5417 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHN, VRSUBHN */
5418 gen_neon_subl(size
);
5420 case 5: case 7: /* VABAL, VABDL */
5421 switch ((size
<< 1) | u
) {
5423 gen_helper_neon_abdl_s16(cpu_V0
, tmp
, tmp2
);
5426 gen_helper_neon_abdl_u16(cpu_V0
, tmp
, tmp2
);
5429 gen_helper_neon_abdl_s32(cpu_V0
, tmp
, tmp2
);
5432 gen_helper_neon_abdl_u32(cpu_V0
, tmp
, tmp2
);
5435 gen_helper_neon_abdl_s64(cpu_V0
, tmp
, tmp2
);
5438 gen_helper_neon_abdl_u64(cpu_V0
, tmp
, tmp2
);
5442 tcg_temp_free_i32(tmp2
);
5443 tcg_temp_free_i32(tmp
);
5445 case 8: case 9: case 10: case 11: case 12: case 13:
5446 /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL */
5447 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
5449 case 14: /* Polynomial VMULL */
5450 gen_helper_neon_mull_p8(cpu_V0
, tmp
, tmp2
);
5451 tcg_temp_free_i32(tmp2
);
5452 tcg_temp_free_i32(tmp
);
5454 default: /* 15 is RESERVED: caught earlier */
5459 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5460 neon_store_reg64(cpu_V0
, rd
+ pass
);
5461 } else if (op
== 5 || (op
>= 8 && op
<= 11)) {
5463 neon_load_reg64(cpu_V1
, rd
+ pass
);
5465 case 10: /* VMLSL */
5466 gen_neon_negl(cpu_V0
, size
);
5468 case 5: case 8: /* VABAL, VMLAL */
5469 gen_neon_addl(size
);
5471 case 9: case 11: /* VQDMLAL, VQDMLSL */
5472 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5474 gen_neon_negl(cpu_V0
, size
);
5476 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
5481 neon_store_reg64(cpu_V0
, rd
+ pass
);
5482 } else if (op
== 4 || op
== 6) {
5483 /* Narrowing operation. */
5484 tmp
= tcg_temp_new_i32();
5488 gen_helper_neon_narrow_high_u8(tmp
, cpu_V0
);
5491 gen_helper_neon_narrow_high_u16(tmp
, cpu_V0
);
5494 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
5495 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
5502 gen_helper_neon_narrow_round_high_u8(tmp
, cpu_V0
);
5505 gen_helper_neon_narrow_round_high_u16(tmp
, cpu_V0
);
5508 tcg_gen_addi_i64(cpu_V0
, cpu_V0
, 1u << 31);
5509 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, 32);
5510 tcg_gen_trunc_i64_i32(tmp
, cpu_V0
);
5518 neon_store_reg(rd
, 0, tmp3
);
5519 neon_store_reg(rd
, 1, tmp
);
5522 /* Write back the result. */
5523 neon_store_reg64(cpu_V0
, rd
+ pass
);
5527 /* Two registers and a scalar. NB that for ops of this form
5528 * the ARM ARM labels bit 24 as Q, but it is in our variable
5535 case 1: /* Float VMLA scalar */
5536 case 5: /* Floating point VMLS scalar */
5537 case 9: /* Floating point VMUL scalar */
5542 case 0: /* Integer VMLA scalar */
5543 case 4: /* Integer VMLS scalar */
5544 case 8: /* Integer VMUL scalar */
5545 case 12: /* VQDMULH scalar */
5546 case 13: /* VQRDMULH scalar */
5547 if (u
&& ((rd
| rn
) & 1)) {
5550 tmp
= neon_get_scalar(size
, rm
);
5551 neon_store_scratch(0, tmp
);
5552 for (pass
= 0; pass
< (u
? 4 : 2); pass
++) {
5553 tmp
= neon_load_scratch(0);
5554 tmp2
= neon_load_reg(rn
, pass
);
5557 gen_helper_neon_qdmulh_s16(tmp
, tmp
, tmp2
);
5559 gen_helper_neon_qdmulh_s32(tmp
, tmp
, tmp2
);
5561 } else if (op
== 13) {
5563 gen_helper_neon_qrdmulh_s16(tmp
, tmp
, tmp2
);
5565 gen_helper_neon_qrdmulh_s32(tmp
, tmp
, tmp2
);
5567 } else if (op
& 1) {
5568 gen_helper_neon_mul_f32(tmp
, tmp
, tmp2
);
5571 case 0: gen_helper_neon_mul_u8(tmp
, tmp
, tmp2
); break;
5572 case 1: gen_helper_neon_mul_u16(tmp
, tmp
, tmp2
); break;
5573 case 2: tcg_gen_mul_i32(tmp
, tmp
, tmp2
); break;
5577 tcg_temp_free_i32(tmp2
);
5580 tmp2
= neon_load_reg(rd
, pass
);
5583 gen_neon_add(size
, tmp
, tmp2
);
5586 gen_helper_neon_add_f32(tmp
, tmp
, tmp2
);
5589 gen_neon_rsb(size
, tmp
, tmp2
);
5592 gen_helper_neon_sub_f32(tmp
, tmp2
, tmp
);
5597 tcg_temp_free_i32(tmp2
);
5599 neon_store_reg(rd
, pass
, tmp
);
5602 case 3: /* VQDMLAL scalar */
5603 case 7: /* VQDMLSL scalar */
5604 case 11: /* VQDMULL scalar */
5609 case 2: /* VMLAL sclar */
5610 case 6: /* VMLSL scalar */
5611 case 10: /* VMULL scalar */
5615 tmp2
= neon_get_scalar(size
, rm
);
5616 /* We need a copy of tmp2 because gen_neon_mull
5617 * deletes it during pass 0. */
5618 tmp4
= tcg_temp_new_i32();
5619 tcg_gen_mov_i32(tmp4
, tmp2
);
5620 tmp3
= neon_load_reg(rn
, 1);
5622 for (pass
= 0; pass
< 2; pass
++) {
5624 tmp
= neon_load_reg(rn
, 0);
5629 gen_neon_mull(cpu_V0
, tmp
, tmp2
, size
, u
);
5631 neon_load_reg64(cpu_V1
, rd
+ pass
);
5635 gen_neon_negl(cpu_V0
, size
);
5638 gen_neon_addl(size
);
5641 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5643 gen_neon_negl(cpu_V0
, size
);
5645 gen_neon_addl_saturate(cpu_V0
, cpu_V1
, size
);
5651 gen_neon_addl_saturate(cpu_V0
, cpu_V0
, size
);
5656 neon_store_reg64(cpu_V0
, rd
+ pass
);
5661 default: /* 14 and 15 are RESERVED */
5665 } else { /* size == 3 */
5668 imm
= (insn
>> 8) & 0xf;
5673 if (q
&& ((rd
| rn
| rm
) & 1)) {
5678 neon_load_reg64(cpu_V0
, rn
);
5680 neon_load_reg64(cpu_V1
, rn
+ 1);
5682 } else if (imm
== 8) {
5683 neon_load_reg64(cpu_V0
, rn
+ 1);
5685 neon_load_reg64(cpu_V1
, rm
);
5688 tmp64
= tcg_temp_new_i64();
5690 neon_load_reg64(cpu_V0
, rn
);
5691 neon_load_reg64(tmp64
, rn
+ 1);
5693 neon_load_reg64(cpu_V0
, rn
+ 1);
5694 neon_load_reg64(tmp64
, rm
);
5696 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, (imm
& 7) * 8);
5697 tcg_gen_shli_i64(cpu_V1
, tmp64
, 64 - ((imm
& 7) * 8));
5698 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5700 neon_load_reg64(cpu_V1
, rm
);
5702 neon_load_reg64(cpu_V1
, rm
+ 1);
5705 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
5706 tcg_gen_shri_i64(tmp64
, tmp64
, imm
* 8);
5707 tcg_gen_or_i64(cpu_V1
, cpu_V1
, tmp64
);
5708 tcg_temp_free_i64(tmp64
);
5711 neon_load_reg64(cpu_V0
, rn
);
5712 tcg_gen_shri_i64(cpu_V0
, cpu_V0
, imm
* 8);
5713 neon_load_reg64(cpu_V1
, rm
);
5714 tcg_gen_shli_i64(cpu_V1
, cpu_V1
, 64 - (imm
* 8));
5715 tcg_gen_or_i64(cpu_V0
, cpu_V0
, cpu_V1
);
5717 neon_store_reg64(cpu_V0
, rd
);
5719 neon_store_reg64(cpu_V1
, rd
+ 1);
5721 } else if ((insn
& (1 << 11)) == 0) {
5722 /* Two register misc. */
5723 op
= ((insn
>> 12) & 0x30) | ((insn
>> 7) & 0xf);
5724 size
= (insn
>> 18) & 3;
5725 /* UNDEF for unknown op values and bad op-size combinations */
5726 if ((neon_2rm_sizes
[op
] & (1 << size
)) == 0) {
5729 if ((op
!= NEON_2RM_VMOVN
&& op
!= NEON_2RM_VQMOVN
) &&
5730 q
&& ((rm
| rd
) & 1)) {
5734 case NEON_2RM_VREV64
:
5735 for (pass
= 0; pass
< (q
? 2 : 1); pass
++) {
5736 tmp
= neon_load_reg(rm
, pass
* 2);
5737 tmp2
= neon_load_reg(rm
, pass
* 2 + 1);
5739 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
5740 case 1: gen_swap_half(tmp
); break;
5741 case 2: /* no-op */ break;
5744 neon_store_reg(rd
, pass
* 2 + 1, tmp
);
5746 neon_store_reg(rd
, pass
* 2, tmp2
);
5749 case 0: tcg_gen_bswap32_i32(tmp2
, tmp2
); break;
5750 case 1: gen_swap_half(tmp2
); break;
5753 neon_store_reg(rd
, pass
* 2, tmp2
);
5757 case NEON_2RM_VPADDL
: case NEON_2RM_VPADDL_U
:
5758 case NEON_2RM_VPADAL
: case NEON_2RM_VPADAL_U
:
5759 for (pass
= 0; pass
< q
+ 1; pass
++) {
5760 tmp
= neon_load_reg(rm
, pass
* 2);
5761 gen_neon_widen(cpu_V0
, tmp
, size
, op
& 1);
5762 tmp
= neon_load_reg(rm
, pass
* 2 + 1);
5763 gen_neon_widen(cpu_V1
, tmp
, size
, op
& 1);
5765 case 0: gen_helper_neon_paddl_u16(CPU_V001
); break;
5766 case 1: gen_helper_neon_paddl_u32(CPU_V001
); break;
5767 case 2: tcg_gen_add_i64(CPU_V001
); break;
5770 if (op
>= NEON_2RM_VPADAL
) {
5772 neon_load_reg64(cpu_V1
, rd
+ pass
);
5773 gen_neon_addl(size
);
5775 neon_store_reg64(cpu_V0
, rd
+ pass
);
5781 for (n
= 0; n
< (q
? 4 : 2); n
+= 2) {
5782 tmp
= neon_load_reg(rm
, n
);
5783 tmp2
= neon_load_reg(rd
, n
+ 1);
5784 neon_store_reg(rm
, n
, tmp2
);
5785 neon_store_reg(rd
, n
+ 1, tmp
);
5792 if (gen_neon_unzip(rd
, rm
, size
, q
)) {
5797 if (gen_neon_zip(rd
, rm
, size
, q
)) {
5801 case NEON_2RM_VMOVN
: case NEON_2RM_VQMOVN
:
5802 /* also VQMOVUN; op field and mnemonics don't line up */
5807 for (pass
= 0; pass
< 2; pass
++) {
5808 neon_load_reg64(cpu_V0
, rm
+ pass
);
5809 tmp
= tcg_temp_new_i32();
5810 gen_neon_narrow_op(op
== NEON_2RM_VMOVN
, q
, size
,
5815 neon_store_reg(rd
, 0, tmp2
);
5816 neon_store_reg(rd
, 1, tmp
);
5820 case NEON_2RM_VSHLL
:
5821 if (q
|| (rd
& 1)) {
5824 tmp
= neon_load_reg(rm
, 0);
5825 tmp2
= neon_load_reg(rm
, 1);
5826 for (pass
= 0; pass
< 2; pass
++) {
5829 gen_neon_widen(cpu_V0
, tmp
, size
, 1);
5830 tcg_gen_shli_i64(cpu_V0
, cpu_V0
, 8 << size
);
5831 neon_store_reg64(cpu_V0
, rd
+ pass
);
5834 case NEON_2RM_VCVT_F16_F32
:
5835 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
) ||
5839 tmp
= tcg_temp_new_i32();
5840 tmp2
= tcg_temp_new_i32();
5841 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 0));
5842 gen_helper_neon_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
5843 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 1));
5844 gen_helper_neon_fcvt_f32_to_f16(tmp2
, cpu_F0s
, cpu_env
);
5845 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
5846 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
5847 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 2));
5848 gen_helper_neon_fcvt_f32_to_f16(tmp
, cpu_F0s
, cpu_env
);
5849 tcg_gen_ld_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rm
, 3));
5850 neon_store_reg(rd
, 0, tmp2
);
5851 tmp2
= tcg_temp_new_i32();
5852 gen_helper_neon_fcvt_f32_to_f16(tmp2
, cpu_F0s
, cpu_env
);
5853 tcg_gen_shli_i32(tmp2
, tmp2
, 16);
5854 tcg_gen_or_i32(tmp2
, tmp2
, tmp
);
5855 neon_store_reg(rd
, 1, tmp2
);
5856 tcg_temp_free_i32(tmp
);
5858 case NEON_2RM_VCVT_F32_F16
:
5859 if (!arm_feature(env
, ARM_FEATURE_VFP_FP16
) ||
5863 tmp3
= tcg_temp_new_i32();
5864 tmp
= neon_load_reg(rm
, 0);
5865 tmp2
= neon_load_reg(rm
, 1);
5866 tcg_gen_ext16u_i32(tmp3
, tmp
);
5867 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5868 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 0));
5869 tcg_gen_shri_i32(tmp3
, tmp
, 16);
5870 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5871 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 1));
5872 tcg_temp_free_i32(tmp
);
5873 tcg_gen_ext16u_i32(tmp3
, tmp2
);
5874 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5875 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 2));
5876 tcg_gen_shri_i32(tmp3
, tmp2
, 16);
5877 gen_helper_neon_fcvt_f16_to_f32(cpu_F0s
, tmp3
, cpu_env
);
5878 tcg_gen_st_f32(cpu_F0s
, cpu_env
, neon_reg_offset(rd
, 3));
5879 tcg_temp_free_i32(tmp2
);
5880 tcg_temp_free_i32(tmp3
);
5884 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
5885 if (neon_2rm_is_float_op(op
)) {
5886 tcg_gen_ld_f32(cpu_F0s
, cpu_env
,
5887 neon_reg_offset(rm
, pass
));
5890 tmp
= neon_load_reg(rm
, pass
);
5893 case NEON_2RM_VREV32
:
5895 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
5896 case 1: gen_swap_half(tmp
); break;
5900 case NEON_2RM_VREV16
:
5905 case 0: gen_helper_neon_cls_s8(tmp
, tmp
); break;
5906 case 1: gen_helper_neon_cls_s16(tmp
, tmp
); break;
5907 case 2: gen_helper_neon_cls_s32(tmp
, tmp
); break;
5913 case 0: gen_helper_neon_clz_u8(tmp
, tmp
); break;
5914 case 1: gen_helper_neon_clz_u16(tmp
, tmp
); break;
5915 case 2: gen_helper_clz(tmp
, tmp
); break;
5920 gen_helper_neon_cnt_u8(tmp
, tmp
);
5923 tcg_gen_not_i32(tmp
, tmp
);
5925 case NEON_2RM_VQABS
:
5927 case 0: gen_helper_neon_qabs_s8(tmp
, tmp
); break;
5928 case 1: gen_helper_neon_qabs_s16(tmp
, tmp
); break;
5929 case 2: gen_helper_neon_qabs_s32(tmp
, tmp
); break;
5933 case NEON_2RM_VQNEG
:
5935 case 0: gen_helper_neon_qneg_s8(tmp
, tmp
); break;
5936 case 1: gen_helper_neon_qneg_s16(tmp
, tmp
); break;
5937 case 2: gen_helper_neon_qneg_s32(tmp
, tmp
); break;
5941 case NEON_2RM_VCGT0
: case NEON_2RM_VCLE0
:
5942 tmp2
= tcg_const_i32(0);
5944 case 0: gen_helper_neon_cgt_s8(tmp
, tmp
, tmp2
); break;
5945 case 1: gen_helper_neon_cgt_s16(tmp
, tmp
, tmp2
); break;
5946 case 2: gen_helper_neon_cgt_s32(tmp
, tmp
, tmp2
); break;
5949 tcg_temp_free(tmp2
);
5950 if (op
== NEON_2RM_VCLE0
) {
5951 tcg_gen_not_i32(tmp
, tmp
);
5954 case NEON_2RM_VCGE0
: case NEON_2RM_VCLT0
:
5955 tmp2
= tcg_const_i32(0);
5957 case 0: gen_helper_neon_cge_s8(tmp
, tmp
, tmp2
); break;
5958 case 1: gen_helper_neon_cge_s16(tmp
, tmp
, tmp2
); break;
5959 case 2: gen_helper_neon_cge_s32(tmp
, tmp
, tmp2
); break;
5962 tcg_temp_free(tmp2
);
5963 if (op
== NEON_2RM_VCLT0
) {
5964 tcg_gen_not_i32(tmp
, tmp
);
5967 case NEON_2RM_VCEQ0
:
5968 tmp2
= tcg_const_i32(0);
5970 case 0: gen_helper_neon_ceq_u8(tmp
, tmp
, tmp2
); break;
5971 case 1: gen_helper_neon_ceq_u16(tmp
, tmp
, tmp2
); break;
5972 case 2: gen_helper_neon_ceq_u32(tmp
, tmp
, tmp2
); break;
5975 tcg_temp_free(tmp2
);
5979 case 0: gen_helper_neon_abs_s8(tmp
, tmp
); break;
5980 case 1: gen_helper_neon_abs_s16(tmp
, tmp
); break;
5981 case 2: tcg_gen_abs_i32(tmp
, tmp
); break;
5986 tmp2
= tcg_const_i32(0);
5987 gen_neon_rsb(size
, tmp
, tmp2
);
5988 tcg_temp_free(tmp2
);
5990 case NEON_2RM_VCGT0_F
:
5991 tmp2
= tcg_const_i32(0);
5992 gen_helper_neon_cgt_f32(tmp
, tmp
, tmp2
);
5993 tcg_temp_free(tmp2
);
5995 case NEON_2RM_VCGE0_F
:
5996 tmp2
= tcg_const_i32(0);
5997 gen_helper_neon_cge_f32(tmp
, tmp
, tmp2
);
5998 tcg_temp_free(tmp2
);
6000 case NEON_2RM_VCEQ0_F
:
6001 tmp2
= tcg_const_i32(0);
6002 gen_helper_neon_ceq_f32(tmp
, tmp
, tmp2
);
6003 tcg_temp_free(tmp2
);
6005 case NEON_2RM_VCLE0_F
:
6006 tmp2
= tcg_const_i32(0);
6007 gen_helper_neon_cge_f32(tmp
, tmp2
, tmp
);
6008 tcg_temp_free(tmp2
);
6010 case NEON_2RM_VCLT0_F
:
6011 tmp2
= tcg_const_i32(0);
6012 gen_helper_neon_cgt_f32(tmp
, tmp2
, tmp
);
6013 tcg_temp_free(tmp2
);
6015 case NEON_2RM_VABS_F
:
6018 case NEON_2RM_VNEG_F
:
6022 tmp2
= neon_load_reg(rd
, pass
);
6023 neon_store_reg(rm
, pass
, tmp2
);
6026 tmp2
= neon_load_reg(rd
, pass
);
6028 case 0: gen_neon_trn_u8(tmp
, tmp2
); break;
6029 case 1: gen_neon_trn_u16(tmp
, tmp2
); break;
6032 neon_store_reg(rm
, pass
, tmp2
);
6034 case NEON_2RM_VRECPE
:
6035 gen_helper_recpe_u32(tmp
, tmp
, cpu_env
);
6037 case NEON_2RM_VRSQRTE
:
6038 gen_helper_rsqrte_u32(tmp
, tmp
, cpu_env
);
6040 case NEON_2RM_VRECPE_F
:
6041 gen_helper_recpe_f32(cpu_F0s
, cpu_F0s
, cpu_env
);
6043 case NEON_2RM_VRSQRTE_F
:
6044 gen_helper_rsqrte_f32(cpu_F0s
, cpu_F0s
, cpu_env
);
6046 case NEON_2RM_VCVT_FS
: /* VCVT.F32.S32 */
6049 case NEON_2RM_VCVT_FU
: /* VCVT.F32.U32 */
6052 case NEON_2RM_VCVT_SF
: /* VCVT.S32.F32 */
6055 case NEON_2RM_VCVT_UF
: /* VCVT.U32.F32 */
6059 /* Reserved op values were caught by the
6060 * neon_2rm_sizes[] check earlier.
6064 if (neon_2rm_is_float_op(op
)) {
6065 tcg_gen_st_f32(cpu_F0s
, cpu_env
,
6066 neon_reg_offset(rd
, pass
));
6068 neon_store_reg(rd
, pass
, tmp
);
6073 } else if ((insn
& (1 << 10)) == 0) {
6075 int n
= ((insn
>> 8) & 3) + 1;
6076 if ((rn
+ n
) > 32) {
6077 /* This is UNPREDICTABLE; we choose to UNDEF to avoid the
6078 * helper function running off the end of the register file.
6083 if (insn
& (1 << 6)) {
6084 tmp
= neon_load_reg(rd
, 0);
6086 tmp
= tcg_temp_new_i32();
6087 tcg_gen_movi_i32(tmp
, 0);
6089 tmp2
= neon_load_reg(rm
, 0);
6090 tmp4
= tcg_const_i32(rn
);
6091 tmp5
= tcg_const_i32(n
);
6092 gen_helper_neon_tbl(tmp2
, tmp2
, tmp
, tmp4
, tmp5
);
6093 tcg_temp_free_i32(tmp
);
6094 if (insn
& (1 << 6)) {
6095 tmp
= neon_load_reg(rd
, 1);
6097 tmp
= tcg_temp_new_i32();
6098 tcg_gen_movi_i32(tmp
, 0);
6100 tmp3
= neon_load_reg(rm
, 1);
6101 gen_helper_neon_tbl(tmp3
, tmp3
, tmp
, tmp4
, tmp5
);
6102 tcg_temp_free_i32(tmp5
);
6103 tcg_temp_free_i32(tmp4
);
6104 neon_store_reg(rd
, 0, tmp2
);
6105 neon_store_reg(rd
, 1, tmp3
);
6106 tcg_temp_free_i32(tmp
);
6107 } else if ((insn
& 0x380) == 0) {
6109 if ((insn
& (7 << 16)) == 0 || (q
&& (rd
& 1))) {
6112 if (insn
& (1 << 19)) {
6113 tmp
= neon_load_reg(rm
, 1);
6115 tmp
= neon_load_reg(rm
, 0);
6117 if (insn
& (1 << 16)) {
6118 gen_neon_dup_u8(tmp
, ((insn
>> 17) & 3) * 8);
6119 } else if (insn
& (1 << 17)) {
6120 if ((insn
>> 18) & 1)
6121 gen_neon_dup_high16(tmp
);
6123 gen_neon_dup_low16(tmp
);
6125 for (pass
= 0; pass
< (q
? 4 : 2); pass
++) {
6126 tmp2
= tcg_temp_new_i32();
6127 tcg_gen_mov_i32(tmp2
, tmp
);
6128 neon_store_reg(rd
, pass
, tmp2
);
6130 tcg_temp_free_i32(tmp
);
6139 static int disas_cp14_read(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
6141 int crn
= (insn
>> 16) & 0xf;
6142 int crm
= insn
& 0xf;
6143 int op1
= (insn
>> 21) & 7;
6144 int op2
= (insn
>> 5) & 7;
6145 int rt
= (insn
>> 12) & 0xf;
6148 /* Minimal set of debug registers, since we don't support debug */
6149 if (op1
== 0 && crn
== 0 && op2
== 0) {
6152 /* DBGDIDR: just RAZ. In particular this means the
6153 * "debug architecture version" bits will read as
6154 * a reserved value, which should cause Linux to
6155 * not try to use the debug hardware.
6157 tmp
= tcg_const_i32(0);
6158 store_reg(s
, rt
, tmp
);
6162 /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
6163 * don't implement memory mapped debug components
6165 if (ENABLE_ARCH_7
) {
6166 tmp
= tcg_const_i32(0);
6167 store_reg(s
, rt
, tmp
);
6176 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
6177 if (op1
== 6 && crn
== 0 && crm
== 0 && op2
== 0) {
6181 tmp
= load_cpu_field(teecr
);
6182 store_reg(s
, rt
, tmp
);
6185 if (op1
== 6 && crn
== 1 && crm
== 0 && op2
== 0) {
6187 if (IS_USER(s
) && (env
->teecr
& 1))
6189 tmp
= load_cpu_field(teehbr
);
6190 store_reg(s
, rt
, tmp
);
6194 fprintf(stderr
, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
6195 op1
, crn
, crm
, op2
);
6199 static int disas_cp14_write(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
6201 int crn
= (insn
>> 16) & 0xf;
6202 int crm
= insn
& 0xf;
6203 int op1
= (insn
>> 21) & 7;
6204 int op2
= (insn
>> 5) & 7;
6205 int rt
= (insn
>> 12) & 0xf;
6208 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
6209 if (op1
== 6 && crn
== 0 && crm
== 0 && op2
== 0) {
6213 tmp
= load_reg(s
, rt
);
6214 gen_helper_set_teecr(cpu_env
, tmp
);
6215 tcg_temp_free_i32(tmp
);
6218 if (op1
== 6 && crn
== 1 && crm
== 0 && op2
== 0) {
6220 if (IS_USER(s
) && (env
->teecr
& 1))
6222 tmp
= load_reg(s
, rt
);
6223 store_cpu_field(tmp
, teehbr
);
6227 fprintf(stderr
, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
6228 op1
, crn
, crm
, op2
);
6232 static int disas_coproc_insn(CPUState
* env
, DisasContext
*s
, uint32_t insn
)
6236 cpnum
= (insn
>> 8) & 0xf;
6237 if (arm_feature(env
, ARM_FEATURE_XSCALE
)
6238 && ((env
->cp15
.c15_cpar
^ 0x3fff) & (1 << cpnum
)))
6244 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
6245 return disas_iwmmxt_insn(env
, s
, insn
);
6246 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
6247 return disas_dsp_insn(env
, s
, insn
);
6252 return disas_vfp_insn (env
, s
, insn
);
6254 /* Coprocessors 7-15 are architecturally reserved by ARM.
6255 Unfortunately Intel decided to ignore this. */
6256 if (arm_feature(env
, ARM_FEATURE_XSCALE
))
6258 if (insn
& (1 << 20))
6259 return disas_cp14_read(env
, s
, insn
);
6261 return disas_cp14_write(env
, s
, insn
);
6263 return disas_cp15_insn (env
, s
, insn
);
6266 /* Unknown coprocessor. See if the board has hooked it. */
6267 return disas_cp_insn (env
, s
, insn
);
6272 /* Store a 64-bit value to a register pair. Clobbers val. */
6273 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
6276 tmp
= tcg_temp_new_i32();
6277 tcg_gen_trunc_i64_i32(tmp
, val
);
6278 store_reg(s
, rlow
, tmp
);
6279 tmp
= tcg_temp_new_i32();
6280 tcg_gen_shri_i64(val
, val
, 32);
6281 tcg_gen_trunc_i64_i32(tmp
, val
);
6282 store_reg(s
, rhigh
, tmp
);
6285 /* load a 32-bit value from a register and perform a 64-bit accumulate. */
6286 static void gen_addq_lo(DisasContext
*s
, TCGv_i64 val
, int rlow
)
6291 /* Load value and extend to 64 bits. */
6292 tmp
= tcg_temp_new_i64();
6293 tmp2
= load_reg(s
, rlow
);
6294 tcg_gen_extu_i32_i64(tmp
, tmp2
);
6295 tcg_temp_free_i32(tmp2
);
6296 tcg_gen_add_i64(val
, val
, tmp
);
6297 tcg_temp_free_i64(tmp
);
6300 /* load and add a 64-bit value from a register pair. */
6301 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
6307 /* Load 64-bit value rd:rn. */
6308 tmpl
= load_reg(s
, rlow
);
6309 tmph
= load_reg(s
, rhigh
);
6310 tmp
= tcg_temp_new_i64();
6311 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
6312 tcg_temp_free_i32(tmpl
);
6313 tcg_temp_free_i32(tmph
);
6314 tcg_gen_add_i64(val
, val
, tmp
);
6315 tcg_temp_free_i64(tmp
);
6318 /* Set N and Z flags from a 64-bit value. */
6319 static void gen_logicq_cc(TCGv_i64 val
)
6321 TCGv tmp
= tcg_temp_new_i32();
6322 gen_helper_logicq_cc(tmp
, val
);
6324 tcg_temp_free_i32(tmp
);
6327 /* Load/Store exclusive instructions are implemented by remembering
6328 the value/address loaded, and seeing if these are the same
6329 when the store is performed. This should be is sufficient to implement
6330 the architecturally mandated semantics, and avoids having to monitor
6333 In system emulation mode only one CPU will be running at once, so
6334 this sequence is effectively atomic. In user emulation mode we
6335 throw an exception and handle the atomic operation elsewhere. */
6336 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
6337 TCGv addr
, int size
)
6343 tmp
= gen_ld8u(addr
, IS_USER(s
));
6346 tmp
= gen_ld16u(addr
, IS_USER(s
));
6350 tmp
= gen_ld32(addr
, IS_USER(s
));
6355 tcg_gen_mov_i32(cpu_exclusive_val
, tmp
);
6356 store_reg(s
, rt
, tmp
);
6358 TCGv tmp2
= tcg_temp_new_i32();
6359 tcg_gen_addi_i32(tmp2
, addr
, 4);
6360 tmp
= gen_ld32(tmp2
, IS_USER(s
));
6361 tcg_temp_free_i32(tmp2
);
6362 tcg_gen_mov_i32(cpu_exclusive_high
, tmp
);
6363 store_reg(s
, rt2
, tmp
);
6365 tcg_gen_mov_i32(cpu_exclusive_addr
, addr
);
6368 static void gen_clrex(DisasContext
*s
)
6370 tcg_gen_movi_i32(cpu_exclusive_addr
, -1);
6373 #ifdef CONFIG_USER_ONLY
6374 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
6375 TCGv addr
, int size
)
6377 tcg_gen_mov_i32(cpu_exclusive_test
, addr
);
6378 tcg_gen_movi_i32(cpu_exclusive_info
,
6379 size
| (rd
<< 4) | (rt
<< 8) | (rt2
<< 12));
6380 gen_exception_insn(s
, 4, EXCP_STREX
);
6383 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
6384 TCGv addr
, int size
)
6390 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
6396 fail_label
= gen_new_label();
6397 done_label
= gen_new_label();
6398 tcg_gen_brcond_i32(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
6401 tmp
= gen_ld8u(addr
, IS_USER(s
));
6404 tmp
= gen_ld16u(addr
, IS_USER(s
));
6408 tmp
= gen_ld32(addr
, IS_USER(s
));
6413 tcg_gen_brcond_i32(TCG_COND_NE
, tmp
, cpu_exclusive_val
, fail_label
);
6414 tcg_temp_free_i32(tmp
);
6416 TCGv tmp2
= tcg_temp_new_i32();
6417 tcg_gen_addi_i32(tmp2
, addr
, 4);
6418 tmp
= gen_ld32(tmp2
, IS_USER(s
));
6419 tcg_temp_free_i32(tmp2
);
6420 tcg_gen_brcond_i32(TCG_COND_NE
, tmp
, cpu_exclusive_high
, fail_label
);
6421 tcg_temp_free_i32(tmp
);
6423 tmp
= load_reg(s
, rt
);
6426 gen_st8(tmp
, addr
, IS_USER(s
));
6429 gen_st16(tmp
, addr
, IS_USER(s
));
6433 gen_st32(tmp
, addr
, IS_USER(s
));
6439 tcg_gen_addi_i32(addr
, addr
, 4);
6440 tmp
= load_reg(s
, rt2
);
6441 gen_st32(tmp
, addr
, IS_USER(s
));
6443 tcg_gen_movi_i32(cpu_R
[rd
], 0);
6444 tcg_gen_br(done_label
);
6445 gen_set_label(fail_label
);
6446 tcg_gen_movi_i32(cpu_R
[rd
], 1);
6447 gen_set_label(done_label
);
6448 tcg_gen_movi_i32(cpu_exclusive_addr
, -1);
6452 static void disas_arm_insn(CPUState
* env
, DisasContext
*s
)
6454 unsigned int cond
, insn
, val
, op1
, i
, shift
, rm
, rs
, rn
, rd
, sh
;
6461 insn
= ldl_code(s
->pc
);
6464 /* M variants do not implement ARM mode. */
6469 /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we
6470 * choose to UNDEF. In ARMv5 and above the space is used
6471 * for miscellaneous unconditional instructions.
6475 /* Unconditional instructions. */
6476 if (((insn
>> 25) & 7) == 1) {
6477 /* NEON Data processing. */
6478 if (!arm_feature(env
, ARM_FEATURE_NEON
))
6481 if (disas_neon_data_insn(env
, s
, insn
))
6485 if ((insn
& 0x0f100000) == 0x04000000) {
6486 /* NEON load/store. */
6487 if (!arm_feature(env
, ARM_FEATURE_NEON
))
6490 if (disas_neon_ls_insn(env
, s
, insn
))
6494 if (((insn
& 0x0f30f000) == 0x0510f000) ||
6495 ((insn
& 0x0f30f010) == 0x0710f000)) {
6496 if ((insn
& (1 << 22)) == 0) {
6498 if (!arm_feature(env
, ARM_FEATURE_V7MP
)) {
6502 /* Otherwise PLD; v5TE+ */
6506 if (((insn
& 0x0f70f000) == 0x0450f000) ||
6507 ((insn
& 0x0f70f010) == 0x0650f000)) {
6509 return; /* PLI; V7 */
6511 if (((insn
& 0x0f700000) == 0x04100000) ||
6512 ((insn
& 0x0f700010) == 0x06100000)) {
6513 if (!arm_feature(env
, ARM_FEATURE_V7MP
)) {
6516 return; /* v7MP: Unallocated memory hint: must NOP */
6519 if ((insn
& 0x0ffffdff) == 0x01010000) {
6522 if (insn
& (1 << 9)) {
6523 /* BE8 mode not implemented. */
6527 } else if ((insn
& 0x0fffff00) == 0x057ff000) {
6528 switch ((insn
>> 4) & 0xf) {
6537 /* We don't emulate caches so these are a no-op. */
6542 } else if ((insn
& 0x0e5fffe0) == 0x084d0500) {
6548 op1
= (insn
& 0x1f);
6549 addr
= tcg_temp_new_i32();
6550 tmp
= tcg_const_i32(op1
);
6551 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
6552 tcg_temp_free_i32(tmp
);
6553 i
= (insn
>> 23) & 3;
6555 case 0: offset
= -4; break; /* DA */
6556 case 1: offset
= 0; break; /* IA */
6557 case 2: offset
= -8; break; /* DB */
6558 case 3: offset
= 4; break; /* IB */
6562 tcg_gen_addi_i32(addr
, addr
, offset
);
6563 tmp
= load_reg(s
, 14);
6564 gen_st32(tmp
, addr
, 0);
6565 tmp
= load_cpu_field(spsr
);
6566 tcg_gen_addi_i32(addr
, addr
, 4);
6567 gen_st32(tmp
, addr
, 0);
6568 if (insn
& (1 << 21)) {
6569 /* Base writeback. */
6571 case 0: offset
= -8; break;
6572 case 1: offset
= 4; break;
6573 case 2: offset
= -4; break;
6574 case 3: offset
= 0; break;
6578 tcg_gen_addi_i32(addr
, addr
, offset
);
6579 tmp
= tcg_const_i32(op1
);
6580 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
6581 tcg_temp_free_i32(tmp
);
6582 tcg_temp_free_i32(addr
);
6584 tcg_temp_free_i32(addr
);
6587 } else if ((insn
& 0x0e50ffe0) == 0x08100a00) {
6593 rn
= (insn
>> 16) & 0xf;
6594 addr
= load_reg(s
, rn
);
6595 i
= (insn
>> 23) & 3;
6597 case 0: offset
= -4; break; /* DA */
6598 case 1: offset
= 0; break; /* IA */
6599 case 2: offset
= -8; break; /* DB */
6600 case 3: offset
= 4; break; /* IB */
6604 tcg_gen_addi_i32(addr
, addr
, offset
);
6605 /* Load PC into tmp and CPSR into tmp2. */
6606 tmp
= gen_ld32(addr
, 0);
6607 tcg_gen_addi_i32(addr
, addr
, 4);
6608 tmp2
= gen_ld32(addr
, 0);
6609 if (insn
& (1 << 21)) {
6610 /* Base writeback. */
6612 case 0: offset
= -8; break;
6613 case 1: offset
= 4; break;
6614 case 2: offset
= -4; break;
6615 case 3: offset
= 0; break;
6619 tcg_gen_addi_i32(addr
, addr
, offset
);
6620 store_reg(s
, rn
, addr
);
6622 tcg_temp_free_i32(addr
);
6624 gen_rfe(s
, tmp
, tmp2
);
6626 } else if ((insn
& 0x0e000000) == 0x0a000000) {
6627 /* branch link and change to thumb (blx <offset>) */
6630 val
= (uint32_t)s
->pc
;
6631 tmp
= tcg_temp_new_i32();
6632 tcg_gen_movi_i32(tmp
, val
);
6633 store_reg(s
, 14, tmp
);
6634 /* Sign-extend the 24-bit offset */
6635 offset
= (((int32_t)insn
) << 8) >> 8;
6636 /* offset * 4 + bit24 * 2 + (thumb bit) */
6637 val
+= (offset
<< 2) | ((insn
>> 23) & 2) | 1;
6638 /* pipeline offset */
6640 /* protected by ARCH(5); above, near the start of uncond block */
6643 } else if ((insn
& 0x0e000f00) == 0x0c000100) {
6644 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
6645 /* iWMMXt register transfer. */
6646 if (env
->cp15
.c15_cpar
& (1 << 1))
6647 if (!disas_iwmmxt_insn(env
, s
, insn
))
6650 } else if ((insn
& 0x0fe00000) == 0x0c400000) {
6651 /* Coprocessor double register transfer. */
6653 } else if ((insn
& 0x0f000010) == 0x0e000010) {
6654 /* Additional coprocessor register transfer. */
6655 } else if ((insn
& 0x0ff10020) == 0x01000000) {
6658 /* cps (privileged) */
6662 if (insn
& (1 << 19)) {
6663 if (insn
& (1 << 8))
6665 if (insn
& (1 << 7))
6667 if (insn
& (1 << 6))
6669 if (insn
& (1 << 18))
6672 if (insn
& (1 << 17)) {
6674 val
|= (insn
& 0x1f);
6677 gen_set_psr_im(s
, mask
, 0, val
);
6684 /* if not always execute, we generate a conditional jump to
6686 s
->condlabel
= gen_new_label();
6687 gen_test_cc(cond
^ 1, s
->condlabel
);
6690 if ((insn
& 0x0f900000) == 0x03000000) {
6691 if ((insn
& (1 << 21)) == 0) {
6693 rd
= (insn
>> 12) & 0xf;
6694 val
= ((insn
>> 4) & 0xf000) | (insn
& 0xfff);
6695 if ((insn
& (1 << 22)) == 0) {
6697 tmp
= tcg_temp_new_i32();
6698 tcg_gen_movi_i32(tmp
, val
);
6701 tmp
= load_reg(s
, rd
);
6702 tcg_gen_ext16u_i32(tmp
, tmp
);
6703 tcg_gen_ori_i32(tmp
, tmp
, val
<< 16);
6705 store_reg(s
, rd
, tmp
);
6707 if (((insn
>> 12) & 0xf) != 0xf)
6709 if (((insn
>> 16) & 0xf) == 0) {
6710 gen_nop_hint(s
, insn
& 0xff);
6712 /* CPSR = immediate */
6714 shift
= ((insn
>> 8) & 0xf) * 2;
6716 val
= (val
>> shift
) | (val
<< (32 - shift
));
6717 i
= ((insn
& (1 << 22)) != 0);
6718 if (gen_set_psr_im(s
, msr_mask(env
, s
, (insn
>> 16) & 0xf, i
), i
, val
))
6722 } else if ((insn
& 0x0f900000) == 0x01000000
6723 && (insn
& 0x00000090) != 0x00000090) {
6724 /* miscellaneous instructions */
6725 op1
= (insn
>> 21) & 3;
6726 sh
= (insn
>> 4) & 0xf;
6729 case 0x0: /* move program status register */
6732 tmp
= load_reg(s
, rm
);
6733 i
= ((op1
& 2) != 0);
6734 if (gen_set_psr(s
, msr_mask(env
, s
, (insn
>> 16) & 0xf, i
), i
, tmp
))
6738 rd
= (insn
>> 12) & 0xf;
6742 tmp
= load_cpu_field(spsr
);
6744 tmp
= tcg_temp_new_i32();
6745 gen_helper_cpsr_read(tmp
);
6747 store_reg(s
, rd
, tmp
);
6752 /* branch/exchange thumb (bx). */
6754 tmp
= load_reg(s
, rm
);
6756 } else if (op1
== 3) {
6759 rd
= (insn
>> 12) & 0xf;
6760 tmp
= load_reg(s
, rm
);
6761 gen_helper_clz(tmp
, tmp
);
6762 store_reg(s
, rd
, tmp
);
6770 /* Trivial implementation equivalent to bx. */
6771 tmp
= load_reg(s
, rm
);
6782 /* branch link/exchange thumb (blx) */
6783 tmp
= load_reg(s
, rm
);
6784 tmp2
= tcg_temp_new_i32();
6785 tcg_gen_movi_i32(tmp2
, s
->pc
);
6786 store_reg(s
, 14, tmp2
);
6789 case 0x5: /* saturating add/subtract */
6791 rd
= (insn
>> 12) & 0xf;
6792 rn
= (insn
>> 16) & 0xf;
6793 tmp
= load_reg(s
, rm
);
6794 tmp2
= load_reg(s
, rn
);
6796 gen_helper_double_saturate(tmp2
, tmp2
);
6798 gen_helper_sub_saturate(tmp
, tmp
, tmp2
);
6800 gen_helper_add_saturate(tmp
, tmp
, tmp2
);
6801 tcg_temp_free_i32(tmp2
);
6802 store_reg(s
, rd
, tmp
);
6805 /* SMC instruction (op1 == 3)
6806 and undefined instructions (op1 == 0 || op1 == 2)
6813 gen_exception_insn(s
, 4, EXCP_BKPT
);
6815 case 0x8: /* signed multiply */
6820 rs
= (insn
>> 8) & 0xf;
6821 rn
= (insn
>> 12) & 0xf;
6822 rd
= (insn
>> 16) & 0xf;
6824 /* (32 * 16) >> 16 */
6825 tmp
= load_reg(s
, rm
);
6826 tmp2
= load_reg(s
, rs
);
6828 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
6831 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
6832 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
6833 tmp
= tcg_temp_new_i32();
6834 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
6835 tcg_temp_free_i64(tmp64
);
6836 if ((sh
& 2) == 0) {
6837 tmp2
= load_reg(s
, rn
);
6838 gen_helper_add_setq(tmp
, tmp
, tmp2
);
6839 tcg_temp_free_i32(tmp2
);
6841 store_reg(s
, rd
, tmp
);
6844 tmp
= load_reg(s
, rm
);
6845 tmp2
= load_reg(s
, rs
);
6846 gen_mulxy(tmp
, tmp2
, sh
& 2, sh
& 4);
6847 tcg_temp_free_i32(tmp2
);
6849 tmp64
= tcg_temp_new_i64();
6850 tcg_gen_ext_i32_i64(tmp64
, tmp
);
6851 tcg_temp_free_i32(tmp
);
6852 gen_addq(s
, tmp64
, rn
, rd
);
6853 gen_storeq_reg(s
, rn
, rd
, tmp64
);
6854 tcg_temp_free_i64(tmp64
);
6857 tmp2
= load_reg(s
, rn
);
6858 gen_helper_add_setq(tmp
, tmp
, tmp2
);
6859 tcg_temp_free_i32(tmp2
);
6861 store_reg(s
, rd
, tmp
);
6868 } else if (((insn
& 0x0e000000) == 0 &&
6869 (insn
& 0x00000090) != 0x90) ||
6870 ((insn
& 0x0e000000) == (1 << 25))) {
6871 int set_cc
, logic_cc
, shiftop
;
6873 op1
= (insn
>> 21) & 0xf;
6874 set_cc
= (insn
>> 20) & 1;
6875 logic_cc
= table_logic_cc
[op1
] & set_cc
;
6877 /* data processing instruction */
6878 if (insn
& (1 << 25)) {
6879 /* immediate operand */
6881 shift
= ((insn
>> 8) & 0xf) * 2;
6883 val
= (val
>> shift
) | (val
<< (32 - shift
));
6885 tmp2
= tcg_temp_new_i32();
6886 tcg_gen_movi_i32(tmp2
, val
);
6887 if (logic_cc
&& shift
) {
6888 gen_set_CF_bit31(tmp2
);
6893 tmp2
= load_reg(s
, rm
);
6894 shiftop
= (insn
>> 5) & 3;
6895 if (!(insn
& (1 << 4))) {
6896 shift
= (insn
>> 7) & 0x1f;
6897 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
6899 rs
= (insn
>> 8) & 0xf;
6900 tmp
= load_reg(s
, rs
);
6901 gen_arm_shift_reg(tmp2
, shiftop
, tmp
, logic_cc
);
6904 if (op1
!= 0x0f && op1
!= 0x0d) {
6905 rn
= (insn
>> 16) & 0xf;
6906 tmp
= load_reg(s
, rn
);
6910 rd
= (insn
>> 12) & 0xf;
6913 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
6917 store_reg_bx(env
, s
, rd
, tmp
);
6920 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
6924 store_reg_bx(env
, s
, rd
, tmp
);
6927 if (set_cc
&& rd
== 15) {
6928 /* SUBS r15, ... is used for exception return. */
6932 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6933 gen_exception_return(s
, tmp
);
6936 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
6938 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
6940 store_reg_bx(env
, s
, rd
, tmp
);
6945 gen_helper_sub_cc(tmp
, tmp2
, tmp
);
6947 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
6949 store_reg_bx(env
, s
, rd
, tmp
);
6953 gen_helper_add_cc(tmp
, tmp
, tmp2
);
6955 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
6957 store_reg_bx(env
, s
, rd
, tmp
);
6961 gen_helper_adc_cc(tmp
, tmp
, tmp2
);
6963 gen_add_carry(tmp
, tmp
, tmp2
);
6965 store_reg_bx(env
, s
, rd
, tmp
);
6969 gen_helper_sbc_cc(tmp
, tmp
, tmp2
);
6971 gen_sub_carry(tmp
, tmp
, tmp2
);
6973 store_reg_bx(env
, s
, rd
, tmp
);
6977 gen_helper_sbc_cc(tmp
, tmp2
, tmp
);
6979 gen_sub_carry(tmp
, tmp2
, tmp
);
6981 store_reg_bx(env
, s
, rd
, tmp
);
6985 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
6988 tcg_temp_free_i32(tmp
);
6992 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
6995 tcg_temp_free_i32(tmp
);
6999 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
7001 tcg_temp_free_i32(tmp
);
7005 gen_helper_add_cc(tmp
, tmp
, tmp2
);
7007 tcg_temp_free_i32(tmp
);
7010 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
7014 store_reg_bx(env
, s
, rd
, tmp
);
7017 if (logic_cc
&& rd
== 15) {
7018 /* MOVS r15, ... is used for exception return. */
7022 gen_exception_return(s
, tmp2
);
7027 store_reg_bx(env
, s
, rd
, tmp2
);
7031 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
7035 store_reg_bx(env
, s
, rd
, tmp
);
7039 tcg_gen_not_i32(tmp2
, tmp2
);
7043 store_reg_bx(env
, s
, rd
, tmp2
);
7046 if (op1
!= 0x0f && op1
!= 0x0d) {
7047 tcg_temp_free_i32(tmp2
);
7050 /* other instructions */
7051 op1
= (insn
>> 24) & 0xf;
7055 /* multiplies, extra load/stores */
7056 sh
= (insn
>> 5) & 3;
7059 rd
= (insn
>> 16) & 0xf;
7060 rn
= (insn
>> 12) & 0xf;
7061 rs
= (insn
>> 8) & 0xf;
7063 op1
= (insn
>> 20) & 0xf;
7065 case 0: case 1: case 2: case 3: case 6:
7067 tmp
= load_reg(s
, rs
);
7068 tmp2
= load_reg(s
, rm
);
7069 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
7070 tcg_temp_free_i32(tmp2
);
7071 if (insn
& (1 << 22)) {
7072 /* Subtract (mls) */
7074 tmp2
= load_reg(s
, rn
);
7075 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
7076 tcg_temp_free_i32(tmp2
);
7077 } else if (insn
& (1 << 21)) {
7079 tmp2
= load_reg(s
, rn
);
7080 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7081 tcg_temp_free_i32(tmp2
);
7083 if (insn
& (1 << 20))
7085 store_reg(s
, rd
, tmp
);
7088 /* 64 bit mul double accumulate (UMAAL) */
7090 tmp
= load_reg(s
, rs
);
7091 tmp2
= load_reg(s
, rm
);
7092 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
7093 gen_addq_lo(s
, tmp64
, rn
);
7094 gen_addq_lo(s
, tmp64
, rd
);
7095 gen_storeq_reg(s
, rn
, rd
, tmp64
);
7096 tcg_temp_free_i64(tmp64
);
7098 case 8: case 9: case 10: case 11:
7099 case 12: case 13: case 14: case 15:
7100 /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */
7101 tmp
= load_reg(s
, rs
);
7102 tmp2
= load_reg(s
, rm
);
7103 if (insn
& (1 << 22)) {
7104 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7106 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
7108 if (insn
& (1 << 21)) { /* mult accumulate */
7109 gen_addq(s
, tmp64
, rn
, rd
);
7111 if (insn
& (1 << 20)) {
7112 gen_logicq_cc(tmp64
);
7114 gen_storeq_reg(s
, rn
, rd
, tmp64
);
7115 tcg_temp_free_i64(tmp64
);
7121 rn
= (insn
>> 16) & 0xf;
7122 rd
= (insn
>> 12) & 0xf;
7123 if (insn
& (1 << 23)) {
7124 /* load/store exclusive */
7125 op1
= (insn
>> 21) & 0x3;
7130 addr
= tcg_temp_local_new_i32();
7131 load_reg_var(s
, addr
, rn
);
7132 if (insn
& (1 << 20)) {
7135 gen_load_exclusive(s
, rd
, 15, addr
, 2);
7137 case 1: /* ldrexd */
7138 gen_load_exclusive(s
, rd
, rd
+ 1, addr
, 3);
7140 case 2: /* ldrexb */
7141 gen_load_exclusive(s
, rd
, 15, addr
, 0);
7143 case 3: /* ldrexh */
7144 gen_load_exclusive(s
, rd
, 15, addr
, 1);
7153 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 2);
7155 case 1: /* strexd */
7156 gen_store_exclusive(s
, rd
, rm
, rm
+ 1, addr
, 3);
7158 case 2: /* strexb */
7159 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 0);
7161 case 3: /* strexh */
7162 gen_store_exclusive(s
, rd
, rm
, 15, addr
, 1);
7168 tcg_temp_free(addr
);
7170 /* SWP instruction */
7173 /* ??? This is not really atomic. However we know
7174 we never have multiple CPUs running in parallel,
7175 so it is good enough. */
7176 addr
= load_reg(s
, rn
);
7177 tmp
= load_reg(s
, rm
);
7178 if (insn
& (1 << 22)) {
7179 tmp2
= gen_ld8u(addr
, IS_USER(s
));
7180 gen_st8(tmp
, addr
, IS_USER(s
));
7182 tmp2
= gen_ld32(addr
, IS_USER(s
));
7183 gen_st32(tmp
, addr
, IS_USER(s
));
7185 tcg_temp_free_i32(addr
);
7186 store_reg(s
, rd
, tmp2
);
7192 /* Misc load/store */
7193 rn
= (insn
>> 16) & 0xf;
7194 rd
= (insn
>> 12) & 0xf;
7195 addr
= load_reg(s
, rn
);
7196 if (insn
& (1 << 24))
7197 gen_add_datah_offset(s
, insn
, 0, addr
);
7199 if (insn
& (1 << 20)) {
7203 tmp
= gen_ld16u(addr
, IS_USER(s
));
7206 tmp
= gen_ld8s(addr
, IS_USER(s
));
7210 tmp
= gen_ld16s(addr
, IS_USER(s
));
7214 } else if (sh
& 2) {
7219 tmp
= load_reg(s
, rd
);
7220 gen_st32(tmp
, addr
, IS_USER(s
));
7221 tcg_gen_addi_i32(addr
, addr
, 4);
7222 tmp
= load_reg(s
, rd
+ 1);
7223 gen_st32(tmp
, addr
, IS_USER(s
));
7227 tmp
= gen_ld32(addr
, IS_USER(s
));
7228 store_reg(s
, rd
, tmp
);
7229 tcg_gen_addi_i32(addr
, addr
, 4);
7230 tmp
= gen_ld32(addr
, IS_USER(s
));
7234 address_offset
= -4;
7237 tmp
= load_reg(s
, rd
);
7238 gen_st16(tmp
, addr
, IS_USER(s
));
7241 /* Perform base writeback before the loaded value to
7242 ensure correct behavior with overlapping index registers.
7243 ldrd with base writeback is is undefined if the
7244 destination and index registers overlap. */
7245 if (!(insn
& (1 << 24))) {
7246 gen_add_datah_offset(s
, insn
, address_offset
, addr
);
7247 store_reg(s
, rn
, addr
);
7248 } else if (insn
& (1 << 21)) {
7250 tcg_gen_addi_i32(addr
, addr
, address_offset
);
7251 store_reg(s
, rn
, addr
);
7253 tcg_temp_free_i32(addr
);
7256 /* Complete the load. */
7257 store_reg(s
, rd
, tmp
);
7266 if (insn
& (1 << 4)) {
7268 /* Armv6 Media instructions. */
7270 rn
= (insn
>> 16) & 0xf;
7271 rd
= (insn
>> 12) & 0xf;
7272 rs
= (insn
>> 8) & 0xf;
7273 switch ((insn
>> 23) & 3) {
7274 case 0: /* Parallel add/subtract. */
7275 op1
= (insn
>> 20) & 7;
7276 tmp
= load_reg(s
, rn
);
7277 tmp2
= load_reg(s
, rm
);
7278 sh
= (insn
>> 5) & 7;
7279 if ((op1
& 3) == 0 || sh
== 5 || sh
== 6)
7281 gen_arm_parallel_addsub(op1
, sh
, tmp
, tmp2
);
7282 tcg_temp_free_i32(tmp2
);
7283 store_reg(s
, rd
, tmp
);
7286 if ((insn
& 0x00700020) == 0) {
7287 /* Halfword pack. */
7288 tmp
= load_reg(s
, rn
);
7289 tmp2
= load_reg(s
, rm
);
7290 shift
= (insn
>> 7) & 0x1f;
7291 if (insn
& (1 << 6)) {
7295 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
7296 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
7297 tcg_gen_ext16u_i32(tmp2
, tmp2
);
7301 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
7302 tcg_gen_ext16u_i32(tmp
, tmp
);
7303 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
7305 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
7306 tcg_temp_free_i32(tmp2
);
7307 store_reg(s
, rd
, tmp
);
7308 } else if ((insn
& 0x00200020) == 0x00200000) {
7310 tmp
= load_reg(s
, rm
);
7311 shift
= (insn
>> 7) & 0x1f;
7312 if (insn
& (1 << 6)) {
7315 tcg_gen_sari_i32(tmp
, tmp
, shift
);
7317 tcg_gen_shli_i32(tmp
, tmp
, shift
);
7319 sh
= (insn
>> 16) & 0x1f;
7320 tmp2
= tcg_const_i32(sh
);
7321 if (insn
& (1 << 22))
7322 gen_helper_usat(tmp
, tmp
, tmp2
);
7324 gen_helper_ssat(tmp
, tmp
, tmp2
);
7325 tcg_temp_free_i32(tmp2
);
7326 store_reg(s
, rd
, tmp
);
7327 } else if ((insn
& 0x00300fe0) == 0x00200f20) {
7329 tmp
= load_reg(s
, rm
);
7330 sh
= (insn
>> 16) & 0x1f;
7331 tmp2
= tcg_const_i32(sh
);
7332 if (insn
& (1 << 22))
7333 gen_helper_usat16(tmp
, tmp
, tmp2
);
7335 gen_helper_ssat16(tmp
, tmp
, tmp2
);
7336 tcg_temp_free_i32(tmp2
);
7337 store_reg(s
, rd
, tmp
);
7338 } else if ((insn
& 0x00700fe0) == 0x00000fa0) {
7340 tmp
= load_reg(s
, rn
);
7341 tmp2
= load_reg(s
, rm
);
7342 tmp3
= tcg_temp_new_i32();
7343 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUState
, GE
));
7344 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
7345 tcg_temp_free_i32(tmp3
);
7346 tcg_temp_free_i32(tmp2
);
7347 store_reg(s
, rd
, tmp
);
7348 } else if ((insn
& 0x000003e0) == 0x00000060) {
7349 tmp
= load_reg(s
, rm
);
7350 shift
= (insn
>> 10) & 3;
7351 /* ??? In many cases it's not neccessary to do a
7352 rotate, a shift is sufficient. */
7354 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
7355 op1
= (insn
>> 20) & 7;
7357 case 0: gen_sxtb16(tmp
); break;
7358 case 2: gen_sxtb(tmp
); break;
7359 case 3: gen_sxth(tmp
); break;
7360 case 4: gen_uxtb16(tmp
); break;
7361 case 6: gen_uxtb(tmp
); break;
7362 case 7: gen_uxth(tmp
); break;
7363 default: goto illegal_op
;
7366 tmp2
= load_reg(s
, rn
);
7367 if ((op1
& 3) == 0) {
7368 gen_add16(tmp
, tmp2
);
7370 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7371 tcg_temp_free_i32(tmp2
);
7374 store_reg(s
, rd
, tmp
);
7375 } else if ((insn
& 0x003f0f60) == 0x003f0f20) {
7377 tmp
= load_reg(s
, rm
);
7378 if (insn
& (1 << 22)) {
7379 if (insn
& (1 << 7)) {
7383 gen_helper_rbit(tmp
, tmp
);
7386 if (insn
& (1 << 7))
7389 tcg_gen_bswap32_i32(tmp
, tmp
);
7391 store_reg(s
, rd
, tmp
);
7396 case 2: /* Multiplies (Type 3). */
7397 tmp
= load_reg(s
, rm
);
7398 tmp2
= load_reg(s
, rs
);
7399 if (insn
& (1 << 20)) {
7400 /* Signed multiply most significant [accumulate].
7401 (SMMUL, SMMLA, SMMLS) */
7402 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
7405 tmp
= load_reg(s
, rd
);
7406 if (insn
& (1 << 6)) {
7407 tmp64
= gen_subq_msw(tmp64
, tmp
);
7409 tmp64
= gen_addq_msw(tmp64
, tmp
);
7412 if (insn
& (1 << 5)) {
7413 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
7415 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
7416 tmp
= tcg_temp_new_i32();
7417 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
7418 tcg_temp_free_i64(tmp64
);
7419 store_reg(s
, rn
, tmp
);
7421 if (insn
& (1 << 5))
7422 gen_swap_half(tmp2
);
7423 gen_smul_dual(tmp
, tmp2
);
7424 if (insn
& (1 << 6)) {
7425 /* This subtraction cannot overflow. */
7426 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
7428 /* This addition cannot overflow 32 bits;
7429 * however it may overflow considered as a signed
7430 * operation, in which case we must set the Q flag.
7432 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7434 tcg_temp_free_i32(tmp2
);
7435 if (insn
& (1 << 22)) {
7436 /* smlald, smlsld */
7437 tmp64
= tcg_temp_new_i64();
7438 tcg_gen_ext_i32_i64(tmp64
, tmp
);
7439 tcg_temp_free_i32(tmp
);
7440 gen_addq(s
, tmp64
, rd
, rn
);
7441 gen_storeq_reg(s
, rd
, rn
, tmp64
);
7442 tcg_temp_free_i64(tmp64
);
7444 /* smuad, smusd, smlad, smlsd */
7447 tmp2
= load_reg(s
, rd
);
7448 gen_helper_add_setq(tmp
, tmp
, tmp2
);
7449 tcg_temp_free_i32(tmp2
);
7451 store_reg(s
, rn
, tmp
);
7456 op1
= ((insn
>> 17) & 0x38) | ((insn
>> 5) & 7);
7458 case 0: /* Unsigned sum of absolute differences. */
7460 tmp
= load_reg(s
, rm
);
7461 tmp2
= load_reg(s
, rs
);
7462 gen_helper_usad8(tmp
, tmp
, tmp2
);
7463 tcg_temp_free_i32(tmp2
);
7465 tmp2
= load_reg(s
, rd
);
7466 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
7467 tcg_temp_free_i32(tmp2
);
7469 store_reg(s
, rn
, tmp
);
7471 case 0x20: case 0x24: case 0x28: case 0x2c:
7472 /* Bitfield insert/clear. */
7474 shift
= (insn
>> 7) & 0x1f;
7475 i
= (insn
>> 16) & 0x1f;
7478 tmp
= tcg_temp_new_i32();
7479 tcg_gen_movi_i32(tmp
, 0);
7481 tmp
= load_reg(s
, rm
);
7484 tmp2
= load_reg(s
, rd
);
7485 gen_bfi(tmp
, tmp2
, tmp
, shift
, (1u << i
) - 1);
7486 tcg_temp_free_i32(tmp2
);
7488 store_reg(s
, rd
, tmp
);
7490 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
7491 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
7493 tmp
= load_reg(s
, rm
);
7494 shift
= (insn
>> 7) & 0x1f;
7495 i
= ((insn
>> 16) & 0x1f) + 1;
7500 gen_ubfx(tmp
, shift
, (1u << i
) - 1);
7502 gen_sbfx(tmp
, shift
, i
);
7505 store_reg(s
, rd
, tmp
);
7515 /* Check for undefined extension instructions
7516 * per the ARM Bible IE:
7517 * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx
7519 sh
= (0xf << 20) | (0xf << 4);
7520 if (op1
== 0x7 && ((insn
& sh
) == sh
))
7524 /* load/store byte/word */
7525 rn
= (insn
>> 16) & 0xf;
7526 rd
= (insn
>> 12) & 0xf;
7527 tmp2
= load_reg(s
, rn
);
7528 i
= (IS_USER(s
) || (insn
& 0x01200000) == 0x00200000);
7529 if (insn
& (1 << 24))
7530 gen_add_data_offset(s
, insn
, tmp2
);
7531 if (insn
& (1 << 20)) {
7533 if (insn
& (1 << 22)) {
7534 tmp
= gen_ld8u(tmp2
, i
);
7536 tmp
= gen_ld32(tmp2
, i
);
7540 tmp
= load_reg(s
, rd
);
7541 if (insn
& (1 << 22))
7542 gen_st8(tmp
, tmp2
, i
);
7544 gen_st32(tmp
, tmp2
, i
);
7546 if (!(insn
& (1 << 24))) {
7547 gen_add_data_offset(s
, insn
, tmp2
);
7548 store_reg(s
, rn
, tmp2
);
7549 } else if (insn
& (1 << 21)) {
7550 store_reg(s
, rn
, tmp2
);
7552 tcg_temp_free_i32(tmp2
);
7554 if (insn
& (1 << 20)) {
7555 /* Complete the load. */
7556 store_reg_from_load(env
, s
, rd
, tmp
);
7562 int j
, n
, user
, loaded_base
;
7564 /* load/store multiple words */
7565 /* XXX: store correct base if write back */
7567 if (insn
& (1 << 22)) {
7569 goto illegal_op
; /* only usable in supervisor mode */
7571 if ((insn
& (1 << 15)) == 0)
7574 rn
= (insn
>> 16) & 0xf;
7575 addr
= load_reg(s
, rn
);
7577 /* compute total size */
7579 TCGV_UNUSED(loaded_var
);
7582 if (insn
& (1 << i
))
7585 /* XXX: test invalid n == 0 case ? */
7586 if (insn
& (1 << 23)) {
7587 if (insn
& (1 << 24)) {
7589 tcg_gen_addi_i32(addr
, addr
, 4);
7591 /* post increment */
7594 if (insn
& (1 << 24)) {
7596 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
7598 /* post decrement */
7600 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
7605 if (insn
& (1 << i
)) {
7606 if (insn
& (1 << 20)) {
7608 tmp
= gen_ld32(addr
, IS_USER(s
));
7610 tmp2
= tcg_const_i32(i
);
7611 gen_helper_set_user_reg(tmp2
, tmp
);
7612 tcg_temp_free_i32(tmp2
);
7613 tcg_temp_free_i32(tmp
);
7614 } else if (i
== rn
) {
7618 store_reg_from_load(env
, s
, i
, tmp
);
7623 /* special case: r15 = PC + 8 */
7624 val
= (long)s
->pc
+ 4;
7625 tmp
= tcg_temp_new_i32();
7626 tcg_gen_movi_i32(tmp
, val
);
7628 tmp
= tcg_temp_new_i32();
7629 tmp2
= tcg_const_i32(i
);
7630 gen_helper_get_user_reg(tmp
, tmp2
);
7631 tcg_temp_free_i32(tmp2
);
7633 tmp
= load_reg(s
, i
);
7635 gen_st32(tmp
, addr
, IS_USER(s
));
7638 /* no need to add after the last transfer */
7640 tcg_gen_addi_i32(addr
, addr
, 4);
7643 if (insn
& (1 << 21)) {
7645 if (insn
& (1 << 23)) {
7646 if (insn
& (1 << 24)) {
7649 /* post increment */
7650 tcg_gen_addi_i32(addr
, addr
, 4);
7653 if (insn
& (1 << 24)) {
7656 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
7658 /* post decrement */
7659 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
7662 store_reg(s
, rn
, addr
);
7664 tcg_temp_free_i32(addr
);
7667 store_reg(s
, rn
, loaded_var
);
7669 if ((insn
& (1 << 22)) && !user
) {
7670 /* Restore CPSR from SPSR. */
7671 tmp
= load_cpu_field(spsr
);
7672 gen_set_cpsr(tmp
, 0xffffffff);
7673 tcg_temp_free_i32(tmp
);
7674 s
->is_jmp
= DISAS_UPDATE
;
7683 /* branch (and link) */
7684 val
= (int32_t)s
->pc
;
7685 if (insn
& (1 << 24)) {
7686 tmp
= tcg_temp_new_i32();
7687 tcg_gen_movi_i32(tmp
, val
);
7688 store_reg(s
, 14, tmp
);
7690 offset
= (((int32_t)insn
<< 8) >> 8);
7691 val
+= (offset
<< 2) + 4;
7699 if (disas_coproc_insn(env
, s
, insn
))
7704 gen_set_pc_im(s
->pc
);
7705 s
->is_jmp
= DISAS_SWI
;
7709 gen_exception_insn(s
, 4, EXCP_UDEF
);
7715 /* Return true if this is a Thumb-2 logical op. */
7717 thumb2_logic_op(int op
)
7722 /* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero
7723 then set condition code flags based on the result of the operation.
7724 If SHIFTER_OUT is nonzero then set the carry flag for logical operations
7725 to the high bit of T1.
7726 Returns zero if the opcode is valid. */
7729 gen_thumb2_data_op(DisasContext
*s
, int op
, int conds
, uint32_t shifter_out
, TCGv t0
, TCGv t1
)
7736 tcg_gen_and_i32(t0
, t0
, t1
);
7740 tcg_gen_andc_i32(t0
, t0
, t1
);
7744 tcg_gen_or_i32(t0
, t0
, t1
);
7748 tcg_gen_orc_i32(t0
, t0
, t1
);
7752 tcg_gen_xor_i32(t0
, t0
, t1
);
7757 gen_helper_add_cc(t0
, t0
, t1
);
7759 tcg_gen_add_i32(t0
, t0
, t1
);
7763 gen_helper_adc_cc(t0
, t0
, t1
);
7769 gen_helper_sbc_cc(t0
, t0
, t1
);
7771 gen_sub_carry(t0
, t0
, t1
);
7775 gen_helper_sub_cc(t0
, t0
, t1
);
7777 tcg_gen_sub_i32(t0
, t0
, t1
);
7781 gen_helper_sub_cc(t0
, t1
, t0
);
7783 tcg_gen_sub_i32(t0
, t1
, t0
);
7785 default: /* 5, 6, 7, 9, 12, 15. */
7791 gen_set_CF_bit31(t1
);
7796 /* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
7798 static int disas_thumb2_insn(CPUState
*env
, DisasContext
*s
, uint16_t insn_hw1
)
7800 uint32_t insn
, imm
, shift
, offset
;
7801 uint32_t rd
, rn
, rm
, rs
;
7812 if (!(arm_feature(env
, ARM_FEATURE_THUMB2
)
7813 || arm_feature (env
, ARM_FEATURE_M
))) {
7814 /* Thumb-1 cores may need to treat bl and blx as a pair of
7815 16-bit instructions to get correct prefetch abort behavior. */
7817 if ((insn
& (1 << 12)) == 0) {
7819 /* Second half of blx. */
7820 offset
= ((insn
& 0x7ff) << 1);
7821 tmp
= load_reg(s
, 14);
7822 tcg_gen_addi_i32(tmp
, tmp
, offset
);
7823 tcg_gen_andi_i32(tmp
, tmp
, 0xfffffffc);
7825 tmp2
= tcg_temp_new_i32();
7826 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
7827 store_reg(s
, 14, tmp2
);
7831 if (insn
& (1 << 11)) {
7832 /* Second half of bl. */
7833 offset
= ((insn
& 0x7ff) << 1) | 1;
7834 tmp
= load_reg(s
, 14);
7835 tcg_gen_addi_i32(tmp
, tmp
, offset
);
7837 tmp2
= tcg_temp_new_i32();
7838 tcg_gen_movi_i32(tmp2
, s
->pc
| 1);
7839 store_reg(s
, 14, tmp2
);
7843 if ((s
->pc
& ~TARGET_PAGE_MASK
) == 0) {
7844 /* Instruction spans a page boundary. Implement it as two
7845 16-bit instructions in case the second half causes an
7847 offset
= ((int32_t)insn
<< 21) >> 9;
7848 tcg_gen_movi_i32(cpu_R
[14], s
->pc
+ 2 + offset
);
7851 /* Fall through to 32-bit decode. */
7854 insn
= lduw_code(s
->pc
);
7856 insn
|= (uint32_t)insn_hw1
<< 16;
7858 if ((insn
& 0xf800e800) != 0xf000e800) {
7862 rn
= (insn
>> 16) & 0xf;
7863 rs
= (insn
>> 12) & 0xf;
7864 rd
= (insn
>> 8) & 0xf;
7866 switch ((insn
>> 25) & 0xf) {
7867 case 0: case 1: case 2: case 3:
7868 /* 16-bit instructions. Should never happen. */
7871 if (insn
& (1 << 22)) {
7872 /* Other load/store, table branch. */
7873 if (insn
& 0x01200000) {
7874 /* Load/store doubleword. */
7876 addr
= tcg_temp_new_i32();
7877 tcg_gen_movi_i32(addr
, s
->pc
& ~3);
7879 addr
= load_reg(s
, rn
);
7881 offset
= (insn
& 0xff) * 4;
7882 if ((insn
& (1 << 23)) == 0)
7884 if (insn
& (1 << 24)) {
7885 tcg_gen_addi_i32(addr
, addr
, offset
);
7888 if (insn
& (1 << 20)) {
7890 tmp
= gen_ld32(addr
, IS_USER(s
));
7891 store_reg(s
, rs
, tmp
);
7892 tcg_gen_addi_i32(addr
, addr
, 4);
7893 tmp
= gen_ld32(addr
, IS_USER(s
));
7894 store_reg(s
, rd
, tmp
);
7897 tmp
= load_reg(s
, rs
);
7898 gen_st32(tmp
, addr
, IS_USER(s
));
7899 tcg_gen_addi_i32(addr
, addr
, 4);
7900 tmp
= load_reg(s
, rd
);
7901 gen_st32(tmp
, addr
, IS_USER(s
));
7903 if (insn
& (1 << 21)) {
7904 /* Base writeback. */
7907 tcg_gen_addi_i32(addr
, addr
, offset
- 4);
7908 store_reg(s
, rn
, addr
);
7910 tcg_temp_free_i32(addr
);
7912 } else if ((insn
& (1 << 23)) == 0) {
7913 /* Load/store exclusive word. */
7914 addr
= tcg_temp_local_new();
7915 load_reg_var(s
, addr
, rn
);
7916 tcg_gen_addi_i32(addr
, addr
, (insn
& 0xff) << 2);
7917 if (insn
& (1 << 20)) {
7918 gen_load_exclusive(s
, rs
, 15, addr
, 2);
7920 gen_store_exclusive(s
, rd
, rs
, 15, addr
, 2);
7922 tcg_temp_free(addr
);
7923 } else if ((insn
& (1 << 6)) == 0) {
7926 addr
= tcg_temp_new_i32();
7927 tcg_gen_movi_i32(addr
, s
->pc
);
7929 addr
= load_reg(s
, rn
);
7931 tmp
= load_reg(s
, rm
);
7932 tcg_gen_add_i32(addr
, addr
, tmp
);
7933 if (insn
& (1 << 4)) {
7935 tcg_gen_add_i32(addr
, addr
, tmp
);
7936 tcg_temp_free_i32(tmp
);
7937 tmp
= gen_ld16u(addr
, IS_USER(s
));
7939 tcg_temp_free_i32(tmp
);
7940 tmp
= gen_ld8u(addr
, IS_USER(s
));
7942 tcg_temp_free_i32(addr
);
7943 tcg_gen_shli_i32(tmp
, tmp
, 1);
7944 tcg_gen_addi_i32(tmp
, tmp
, s
->pc
);
7945 store_reg(s
, 15, tmp
);
7947 /* Load/store exclusive byte/halfword/doubleword. */
7949 op
= (insn
>> 4) & 0x3;
7953 addr
= tcg_temp_local_new();
7954 load_reg_var(s
, addr
, rn
);
7955 if (insn
& (1 << 20)) {
7956 gen_load_exclusive(s
, rs
, rd
, addr
, op
);
7958 gen_store_exclusive(s
, rm
, rs
, rd
, addr
, op
);
7960 tcg_temp_free(addr
);
7963 /* Load/store multiple, RFE, SRS. */
7964 if (((insn
>> 23) & 1) == ((insn
>> 24) & 1)) {
7965 /* Not available in user mode. */
7968 if (insn
& (1 << 20)) {
7970 addr
= load_reg(s
, rn
);
7971 if ((insn
& (1 << 24)) == 0)
7972 tcg_gen_addi_i32(addr
, addr
, -8);
7973 /* Load PC into tmp and CPSR into tmp2. */
7974 tmp
= gen_ld32(addr
, 0);
7975 tcg_gen_addi_i32(addr
, addr
, 4);
7976 tmp2
= gen_ld32(addr
, 0);
7977 if (insn
& (1 << 21)) {
7978 /* Base writeback. */
7979 if (insn
& (1 << 24)) {
7980 tcg_gen_addi_i32(addr
, addr
, 4);
7982 tcg_gen_addi_i32(addr
, addr
, -4);
7984 store_reg(s
, rn
, addr
);
7986 tcg_temp_free_i32(addr
);
7988 gen_rfe(s
, tmp
, tmp2
);
7992 addr
= tcg_temp_new_i32();
7993 tmp
= tcg_const_i32(op
);
7994 gen_helper_get_r13_banked(addr
, cpu_env
, tmp
);
7995 tcg_temp_free_i32(tmp
);
7996 if ((insn
& (1 << 24)) == 0) {
7997 tcg_gen_addi_i32(addr
, addr
, -8);
7999 tmp
= load_reg(s
, 14);
8000 gen_st32(tmp
, addr
, 0);
8001 tcg_gen_addi_i32(addr
, addr
, 4);
8002 tmp
= tcg_temp_new_i32();
8003 gen_helper_cpsr_read(tmp
);
8004 gen_st32(tmp
, addr
, 0);
8005 if (insn
& (1 << 21)) {
8006 if ((insn
& (1 << 24)) == 0) {
8007 tcg_gen_addi_i32(addr
, addr
, -4);
8009 tcg_gen_addi_i32(addr
, addr
, 4);
8011 tmp
= tcg_const_i32(op
);
8012 gen_helper_set_r13_banked(cpu_env
, tmp
, addr
);
8013 tcg_temp_free_i32(tmp
);
8015 tcg_temp_free_i32(addr
);
8020 /* Load/store multiple. */
8021 addr
= load_reg(s
, rn
);
8023 for (i
= 0; i
< 16; i
++) {
8024 if (insn
& (1 << i
))
8027 if (insn
& (1 << 24)) {
8028 tcg_gen_addi_i32(addr
, addr
, -offset
);
8031 for (i
= 0; i
< 16; i
++) {
8032 if ((insn
& (1 << i
)) == 0)
8034 if (insn
& (1 << 20)) {
8036 tmp
= gen_ld32(addr
, IS_USER(s
));
8040 store_reg(s
, i
, tmp
);
8044 tmp
= load_reg(s
, i
);
8045 gen_st32(tmp
, addr
, IS_USER(s
));
8047 tcg_gen_addi_i32(addr
, addr
, 4);
8049 if (insn
& (1 << 21)) {
8050 /* Base register writeback. */
8051 if (insn
& (1 << 24)) {
8052 tcg_gen_addi_i32(addr
, addr
, -offset
);
8054 /* Fault if writeback register is in register list. */
8055 if (insn
& (1 << rn
))
8057 store_reg(s
, rn
, addr
);
8059 tcg_temp_free_i32(addr
);
8066 op
= (insn
>> 21) & 0xf;
8068 /* Halfword pack. */
8069 tmp
= load_reg(s
, rn
);
8070 tmp2
= load_reg(s
, rm
);
8071 shift
= ((insn
>> 10) & 0x1c) | ((insn
>> 6) & 0x3);
8072 if (insn
& (1 << 5)) {
8076 tcg_gen_sari_i32(tmp2
, tmp2
, shift
);
8077 tcg_gen_andi_i32(tmp
, tmp
, 0xffff0000);
8078 tcg_gen_ext16u_i32(tmp2
, tmp2
);
8082 tcg_gen_shli_i32(tmp2
, tmp2
, shift
);
8083 tcg_gen_ext16u_i32(tmp
, tmp
);
8084 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffff0000);
8086 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
8087 tcg_temp_free_i32(tmp2
);
8088 store_reg(s
, rd
, tmp
);
8090 /* Data processing register constant shift. */
8092 tmp
= tcg_temp_new_i32();
8093 tcg_gen_movi_i32(tmp
, 0);
8095 tmp
= load_reg(s
, rn
);
8097 tmp2
= load_reg(s
, rm
);
8099 shiftop
= (insn
>> 4) & 3;
8100 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
8101 conds
= (insn
& (1 << 20)) != 0;
8102 logic_cc
= (conds
&& thumb2_logic_op(op
));
8103 gen_arm_shift_im(tmp2
, shiftop
, shift
, logic_cc
);
8104 if (gen_thumb2_data_op(s
, op
, conds
, 0, tmp
, tmp2
))
8106 tcg_temp_free_i32(tmp2
);
8108 store_reg(s
, rd
, tmp
);
8110 tcg_temp_free_i32(tmp
);
8114 case 13: /* Misc data processing. */
8115 op
= ((insn
>> 22) & 6) | ((insn
>> 7) & 1);
8116 if (op
< 4 && (insn
& 0xf000) != 0xf000)
8119 case 0: /* Register controlled shift. */
8120 tmp
= load_reg(s
, rn
);
8121 tmp2
= load_reg(s
, rm
);
8122 if ((insn
& 0x70) != 0)
8124 op
= (insn
>> 21) & 3;
8125 logic_cc
= (insn
& (1 << 20)) != 0;
8126 gen_arm_shift_reg(tmp
, op
, tmp2
, logic_cc
);
8129 store_reg_bx(env
, s
, rd
, tmp
);
8131 case 1: /* Sign/zero extend. */
8132 tmp
= load_reg(s
, rm
);
8133 shift
= (insn
>> 4) & 3;
8134 /* ??? In many cases it's not neccessary to do a
8135 rotate, a shift is sufficient. */
8137 tcg_gen_rotri_i32(tmp
, tmp
, shift
* 8);
8138 op
= (insn
>> 20) & 7;
8140 case 0: gen_sxth(tmp
); break;
8141 case 1: gen_uxth(tmp
); break;
8142 case 2: gen_sxtb16(tmp
); break;
8143 case 3: gen_uxtb16(tmp
); break;
8144 case 4: gen_sxtb(tmp
); break;
8145 case 5: gen_uxtb(tmp
); break;
8146 default: goto illegal_op
;
8149 tmp2
= load_reg(s
, rn
);
8150 if ((op
>> 1) == 1) {
8151 gen_add16(tmp
, tmp2
);
8153 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8154 tcg_temp_free_i32(tmp2
);
8157 store_reg(s
, rd
, tmp
);
8159 case 2: /* SIMD add/subtract. */
8160 op
= (insn
>> 20) & 7;
8161 shift
= (insn
>> 4) & 7;
8162 if ((op
& 3) == 3 || (shift
& 3) == 3)
8164 tmp
= load_reg(s
, rn
);
8165 tmp2
= load_reg(s
, rm
);
8166 gen_thumb2_parallel_addsub(op
, shift
, tmp
, tmp2
);
8167 tcg_temp_free_i32(tmp2
);
8168 store_reg(s
, rd
, tmp
);
8170 case 3: /* Other data processing. */
8171 op
= ((insn
>> 17) & 0x38) | ((insn
>> 4) & 7);
8173 /* Saturating add/subtract. */
8174 tmp
= load_reg(s
, rn
);
8175 tmp2
= load_reg(s
, rm
);
8177 gen_helper_double_saturate(tmp
, tmp
);
8179 gen_helper_sub_saturate(tmp
, tmp2
, tmp
);
8181 gen_helper_add_saturate(tmp
, tmp
, tmp2
);
8182 tcg_temp_free_i32(tmp2
);
8184 tmp
= load_reg(s
, rn
);
8186 case 0x0a: /* rbit */
8187 gen_helper_rbit(tmp
, tmp
);
8189 case 0x08: /* rev */
8190 tcg_gen_bswap32_i32(tmp
, tmp
);
8192 case 0x09: /* rev16 */
8195 case 0x0b: /* revsh */
8198 case 0x10: /* sel */
8199 tmp2
= load_reg(s
, rm
);
8200 tmp3
= tcg_temp_new_i32();
8201 tcg_gen_ld_i32(tmp3
, cpu_env
, offsetof(CPUState
, GE
));
8202 gen_helper_sel_flags(tmp
, tmp3
, tmp
, tmp2
);
8203 tcg_temp_free_i32(tmp3
);
8204 tcg_temp_free_i32(tmp2
);
8206 case 0x18: /* clz */
8207 gen_helper_clz(tmp
, tmp
);
8213 store_reg(s
, rd
, tmp
);
8215 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
8216 op
= (insn
>> 4) & 0xf;
8217 tmp
= load_reg(s
, rn
);
8218 tmp2
= load_reg(s
, rm
);
8219 switch ((insn
>> 20) & 7) {
8220 case 0: /* 32 x 32 -> 32 */
8221 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
8222 tcg_temp_free_i32(tmp2
);
8224 tmp2
= load_reg(s
, rs
);
8226 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
8228 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8229 tcg_temp_free_i32(tmp2
);
8232 case 1: /* 16 x 16 -> 32 */
8233 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
8234 tcg_temp_free_i32(tmp2
);
8236 tmp2
= load_reg(s
, rs
);
8237 gen_helper_add_setq(tmp
, tmp
, tmp2
);
8238 tcg_temp_free_i32(tmp2
);
8241 case 2: /* Dual multiply add. */
8242 case 4: /* Dual multiply subtract. */
8244 gen_swap_half(tmp2
);
8245 gen_smul_dual(tmp
, tmp2
);
8246 if (insn
& (1 << 22)) {
8247 /* This subtraction cannot overflow. */
8248 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8250 /* This addition cannot overflow 32 bits;
8251 * however it may overflow considered as a signed
8252 * operation, in which case we must set the Q flag.
8254 gen_helper_add_setq(tmp
, tmp
, tmp2
);
8256 tcg_temp_free_i32(tmp2
);
8259 tmp2
= load_reg(s
, rs
);
8260 gen_helper_add_setq(tmp
, tmp
, tmp2
);
8261 tcg_temp_free_i32(tmp2
);
8264 case 3: /* 32 * 16 -> 32msb */
8266 tcg_gen_sari_i32(tmp2
, tmp2
, 16);
8269 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
8270 tcg_gen_shri_i64(tmp64
, tmp64
, 16);
8271 tmp
= tcg_temp_new_i32();
8272 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
8273 tcg_temp_free_i64(tmp64
);
8276 tmp2
= load_reg(s
, rs
);
8277 gen_helper_add_setq(tmp
, tmp
, tmp2
);
8278 tcg_temp_free_i32(tmp2
);
8281 case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
8282 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
8284 tmp
= load_reg(s
, rs
);
8285 if (insn
& (1 << 20)) {
8286 tmp64
= gen_addq_msw(tmp64
, tmp
);
8288 tmp64
= gen_subq_msw(tmp64
, tmp
);
8291 if (insn
& (1 << 4)) {
8292 tcg_gen_addi_i64(tmp64
, tmp64
, 0x80000000u
);
8294 tcg_gen_shri_i64(tmp64
, tmp64
, 32);
8295 tmp
= tcg_temp_new_i32();
8296 tcg_gen_trunc_i64_i32(tmp
, tmp64
);
8297 tcg_temp_free_i64(tmp64
);
8299 case 7: /* Unsigned sum of absolute differences. */
8300 gen_helper_usad8(tmp
, tmp
, tmp2
);
8301 tcg_temp_free_i32(tmp2
);
8303 tmp2
= load_reg(s
, rs
);
8304 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8305 tcg_temp_free_i32(tmp2
);
8309 store_reg(s
, rd
, tmp
);
8311 case 6: case 7: /* 64-bit multiply, Divide. */
8312 op
= ((insn
>> 4) & 0xf) | ((insn
>> 16) & 0x70);
8313 tmp
= load_reg(s
, rn
);
8314 tmp2
= load_reg(s
, rm
);
8315 if ((op
& 0x50) == 0x10) {
8317 if (!arm_feature(env
, ARM_FEATURE_DIV
))
8320 gen_helper_udiv(tmp
, tmp
, tmp2
);
8322 gen_helper_sdiv(tmp
, tmp
, tmp2
);
8323 tcg_temp_free_i32(tmp2
);
8324 store_reg(s
, rd
, tmp
);
8325 } else if ((op
& 0xe) == 0xc) {
8326 /* Dual multiply accumulate long. */
8328 gen_swap_half(tmp2
);
8329 gen_smul_dual(tmp
, tmp2
);
8331 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8333 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8335 tcg_temp_free_i32(tmp2
);
8337 tmp64
= tcg_temp_new_i64();
8338 tcg_gen_ext_i32_i64(tmp64
, tmp
);
8339 tcg_temp_free_i32(tmp
);
8340 gen_addq(s
, tmp64
, rs
, rd
);
8341 gen_storeq_reg(s
, rs
, rd
, tmp64
);
8342 tcg_temp_free_i64(tmp64
);
8345 /* Unsigned 64-bit multiply */
8346 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
8350 gen_mulxy(tmp
, tmp2
, op
& 2, op
& 1);
8351 tcg_temp_free_i32(tmp2
);
8352 tmp64
= tcg_temp_new_i64();
8353 tcg_gen_ext_i32_i64(tmp64
, tmp
);
8354 tcg_temp_free_i32(tmp
);
8356 /* Signed 64-bit multiply */
8357 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
8362 gen_addq_lo(s
, tmp64
, rs
);
8363 gen_addq_lo(s
, tmp64
, rd
);
8364 } else if (op
& 0x40) {
8365 /* 64-bit accumulate. */
8366 gen_addq(s
, tmp64
, rs
, rd
);
8368 gen_storeq_reg(s
, rs
, rd
, tmp64
);
8369 tcg_temp_free_i64(tmp64
);
8374 case 6: case 7: case 14: case 15:
8376 if (((insn
>> 24) & 3) == 3) {
8377 /* Translate into the equivalent ARM encoding. */
8378 insn
= (insn
& 0xe2ffffff) | ((insn
& (1 << 28)) >> 4) | (1 << 28);
8379 if (disas_neon_data_insn(env
, s
, insn
))
8382 if (insn
& (1 << 28))
8384 if (disas_coproc_insn (env
, s
, insn
))
8388 case 8: case 9: case 10: case 11:
8389 if (insn
& (1 << 15)) {
8390 /* Branches, misc control. */
8391 if (insn
& 0x5000) {
8392 /* Unconditional branch. */
8393 /* signextend(hw1[10:0]) -> offset[:12]. */
8394 offset
= ((int32_t)insn
<< 5) >> 9 & ~(int32_t)0xfff;
8395 /* hw1[10:0] -> offset[11:1]. */
8396 offset
|= (insn
& 0x7ff) << 1;
8397 /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22]
8398 offset[24:22] already have the same value because of the
8399 sign extension above. */
8400 offset
^= ((~insn
) & (1 << 13)) << 10;
8401 offset
^= ((~insn
) & (1 << 11)) << 11;
8403 if (insn
& (1 << 14)) {
8404 /* Branch and link. */
8405 tcg_gen_movi_i32(cpu_R
[14], s
->pc
| 1);
8409 if (insn
& (1 << 12)) {
8414 offset
&= ~(uint32_t)2;
8415 /* thumb2 bx, no need to check */
8416 gen_bx_im(s
, offset
);
8418 } else if (((insn
>> 23) & 7) == 7) {
8420 if (insn
& (1 << 13))
8423 if (insn
& (1 << 26)) {
8424 /* Secure monitor call (v6Z) */
8425 goto illegal_op
; /* not implemented. */
8427 op
= (insn
>> 20) & 7;
8429 case 0: /* msr cpsr. */
8431 tmp
= load_reg(s
, rn
);
8432 addr
= tcg_const_i32(insn
& 0xff);
8433 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
8434 tcg_temp_free_i32(addr
);
8435 tcg_temp_free_i32(tmp
);
8440 case 1: /* msr spsr. */
8443 tmp
= load_reg(s
, rn
);
8445 msr_mask(env
, s
, (insn
>> 8) & 0xf, op
== 1),
8449 case 2: /* cps, nop-hint. */
8450 if (((insn
>> 8) & 7) == 0) {
8451 gen_nop_hint(s
, insn
& 0xff);
8453 /* Implemented as NOP in user mode. */
8458 if (insn
& (1 << 10)) {
8459 if (insn
& (1 << 7))
8461 if (insn
& (1 << 6))
8463 if (insn
& (1 << 5))
8465 if (insn
& (1 << 9))
8466 imm
= CPSR_A
| CPSR_I
| CPSR_F
;
8468 if (insn
& (1 << 8)) {
8470 imm
|= (insn
& 0x1f);
8473 gen_set_psr_im(s
, offset
, 0, imm
);
8476 case 3: /* Special control operations. */
8478 op
= (insn
>> 4) & 0xf;
8486 /* These execute as NOPs. */
8493 /* Trivial implementation equivalent to bx. */
8494 tmp
= load_reg(s
, rn
);
8497 case 5: /* Exception return. */
8501 if (rn
!= 14 || rd
!= 15) {
8504 tmp
= load_reg(s
, rn
);
8505 tcg_gen_subi_i32(tmp
, tmp
, insn
& 0xff);
8506 gen_exception_return(s
, tmp
);
8508 case 6: /* mrs cpsr. */
8509 tmp
= tcg_temp_new_i32();
8511 addr
= tcg_const_i32(insn
& 0xff);
8512 gen_helper_v7m_mrs(tmp
, cpu_env
, addr
);
8513 tcg_temp_free_i32(addr
);
8515 gen_helper_cpsr_read(tmp
);
8517 store_reg(s
, rd
, tmp
);
8519 case 7: /* mrs spsr. */
8520 /* Not accessible in user mode. */
8521 if (IS_USER(s
) || IS_M(env
))
8523 tmp
= load_cpu_field(spsr
);
8524 store_reg(s
, rd
, tmp
);
8529 /* Conditional branch. */
8530 op
= (insn
>> 22) & 0xf;
8531 /* Generate a conditional jump to next instruction. */
8532 s
->condlabel
= gen_new_label();
8533 gen_test_cc(op
^ 1, s
->condlabel
);
8536 /* offset[11:1] = insn[10:0] */
8537 offset
= (insn
& 0x7ff) << 1;
8538 /* offset[17:12] = insn[21:16]. */
8539 offset
|= (insn
& 0x003f0000) >> 4;
8540 /* offset[31:20] = insn[26]. */
8541 offset
|= ((int32_t)((insn
<< 5) & 0x80000000)) >> 11;
8542 /* offset[18] = insn[13]. */
8543 offset
|= (insn
& (1 << 13)) << 5;
8544 /* offset[19] = insn[11]. */
8545 offset
|= (insn
& (1 << 11)) << 8;
8547 /* jump to the offset */
8548 gen_jmp(s
, s
->pc
+ offset
);
8551 /* Data processing immediate. */
8552 if (insn
& (1 << 25)) {
8553 if (insn
& (1 << 24)) {
8554 if (insn
& (1 << 20))
8556 /* Bitfield/Saturate. */
8557 op
= (insn
>> 21) & 7;
8559 shift
= ((insn
>> 6) & 3) | ((insn
>> 10) & 0x1c);
8561 tmp
= tcg_temp_new_i32();
8562 tcg_gen_movi_i32(tmp
, 0);
8564 tmp
= load_reg(s
, rn
);
8567 case 2: /* Signed bitfield extract. */
8569 if (shift
+ imm
> 32)
8572 gen_sbfx(tmp
, shift
, imm
);
8574 case 6: /* Unsigned bitfield extract. */
8576 if (shift
+ imm
> 32)
8579 gen_ubfx(tmp
, shift
, (1u << imm
) - 1);
8581 case 3: /* Bitfield insert/clear. */
8584 imm
= imm
+ 1 - shift
;
8586 tmp2
= load_reg(s
, rd
);
8587 gen_bfi(tmp
, tmp2
, tmp
, shift
, (1u << imm
) - 1);
8588 tcg_temp_free_i32(tmp2
);
8593 default: /* Saturate. */
8596 tcg_gen_sari_i32(tmp
, tmp
, shift
);
8598 tcg_gen_shli_i32(tmp
, tmp
, shift
);
8600 tmp2
= tcg_const_i32(imm
);
8603 if ((op
& 1) && shift
== 0)
8604 gen_helper_usat16(tmp
, tmp
, tmp2
);
8606 gen_helper_usat(tmp
, tmp
, tmp2
);
8609 if ((op
& 1) && shift
== 0)
8610 gen_helper_ssat16(tmp
, tmp
, tmp2
);
8612 gen_helper_ssat(tmp
, tmp
, tmp2
);
8614 tcg_temp_free_i32(tmp2
);
8617 store_reg(s
, rd
, tmp
);
8619 imm
= ((insn
& 0x04000000) >> 15)
8620 | ((insn
& 0x7000) >> 4) | (insn
& 0xff);
8621 if (insn
& (1 << 22)) {
8622 /* 16-bit immediate. */
8623 imm
|= (insn
>> 4) & 0xf000;
8624 if (insn
& (1 << 23)) {
8626 tmp
= load_reg(s
, rd
);
8627 tcg_gen_ext16u_i32(tmp
, tmp
);
8628 tcg_gen_ori_i32(tmp
, tmp
, imm
<< 16);
8631 tmp
= tcg_temp_new_i32();
8632 tcg_gen_movi_i32(tmp
, imm
);
8635 /* Add/sub 12-bit immediate. */
8637 offset
= s
->pc
& ~(uint32_t)3;
8638 if (insn
& (1 << 23))
8642 tmp
= tcg_temp_new_i32();
8643 tcg_gen_movi_i32(tmp
, offset
);
8645 tmp
= load_reg(s
, rn
);
8646 if (insn
& (1 << 23))
8647 tcg_gen_subi_i32(tmp
, tmp
, imm
);
8649 tcg_gen_addi_i32(tmp
, tmp
, imm
);
8652 store_reg(s
, rd
, tmp
);
8655 int shifter_out
= 0;
8656 /* modified 12-bit immediate. */
8657 shift
= ((insn
& 0x04000000) >> 23) | ((insn
& 0x7000) >> 12);
8658 imm
= (insn
& 0xff);
8661 /* Nothing to do. */
8663 case 1: /* 00XY00XY */
8666 case 2: /* XY00XY00 */
8670 case 3: /* XYXYXYXY */
8674 default: /* Rotated constant. */
8675 shift
= (shift
<< 1) | (imm
>> 7);
8677 imm
= imm
<< (32 - shift
);
8681 tmp2
= tcg_temp_new_i32();
8682 tcg_gen_movi_i32(tmp2
, imm
);
8683 rn
= (insn
>> 16) & 0xf;
8685 tmp
= tcg_temp_new_i32();
8686 tcg_gen_movi_i32(tmp
, 0);
8688 tmp
= load_reg(s
, rn
);
8690 op
= (insn
>> 21) & 0xf;
8691 if (gen_thumb2_data_op(s
, op
, (insn
& (1 << 20)) != 0,
8692 shifter_out
, tmp
, tmp2
))
8694 tcg_temp_free_i32(tmp2
);
8695 rd
= (insn
>> 8) & 0xf;
8697 store_reg(s
, rd
, tmp
);
8699 tcg_temp_free_i32(tmp
);
8704 case 12: /* Load/store single data item. */
8709 if ((insn
& 0x01100000) == 0x01000000) {
8710 if (disas_neon_ls_insn(env
, s
, insn
))
8714 op
= ((insn
>> 21) & 3) | ((insn
>> 22) & 4);
8716 if (!(insn
& (1 << 20))) {
8720 /* Byte or halfword load space with dest == r15 : memory hints.
8721 * Catch them early so we don't emit pointless addressing code.
8722 * This space is a mix of:
8723 * PLD/PLDW/PLI, which we implement as NOPs (note that unlike
8724 * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP
8726 * unallocated hints, which must be treated as NOPs
8727 * UNPREDICTABLE space, which we NOP or UNDEF depending on
8728 * which is easiest for the decoding logic
8729 * Some space which must UNDEF
8731 int op1
= (insn
>> 23) & 3;
8732 int op2
= (insn
>> 6) & 0x3f;
8737 /* UNPREDICTABLE or unallocated hint */
8741 return 0; /* PLD* or unallocated hint */
8743 if ((op2
== 0) || ((op2
& 0x3c) == 0x30)) {
8744 return 0; /* PLD* or unallocated hint */
8746 /* UNDEF space, or an UNPREDICTABLE */
8752 addr
= tcg_temp_new_i32();
8754 /* s->pc has already been incremented by 4. */
8755 imm
= s
->pc
& 0xfffffffc;
8756 if (insn
& (1 << 23))
8757 imm
+= insn
& 0xfff;
8759 imm
-= insn
& 0xfff;
8760 tcg_gen_movi_i32(addr
, imm
);
8762 addr
= load_reg(s
, rn
);
8763 if (insn
& (1 << 23)) {
8764 /* Positive offset. */
8766 tcg_gen_addi_i32(addr
, addr
, imm
);
8769 switch ((insn
>> 8) & 0xf) {
8770 case 0x0: /* Shifted Register. */
8771 shift
= (insn
>> 4) & 0xf;
8773 tcg_temp_free_i32(addr
);
8776 tmp
= load_reg(s
, rm
);
8778 tcg_gen_shli_i32(tmp
, tmp
, shift
);
8779 tcg_gen_add_i32(addr
, addr
, tmp
);
8780 tcg_temp_free_i32(tmp
);
8782 case 0xc: /* Negative offset. */
8783 tcg_gen_addi_i32(addr
, addr
, -imm
);
8785 case 0xe: /* User privilege. */
8786 tcg_gen_addi_i32(addr
, addr
, imm
);
8789 case 0x9: /* Post-decrement. */
8792 case 0xb: /* Post-increment. */
8796 case 0xd: /* Pre-decrement. */
8799 case 0xf: /* Pre-increment. */
8800 tcg_gen_addi_i32(addr
, addr
, imm
);
8804 tcg_temp_free_i32(addr
);
8809 if (insn
& (1 << 20)) {
8812 case 0: tmp
= gen_ld8u(addr
, user
); break;
8813 case 4: tmp
= gen_ld8s(addr
, user
); break;
8814 case 1: tmp
= gen_ld16u(addr
, user
); break;
8815 case 5: tmp
= gen_ld16s(addr
, user
); break;
8816 case 2: tmp
= gen_ld32(addr
, user
); break;
8818 tcg_temp_free_i32(addr
);
8824 store_reg(s
, rs
, tmp
);
8828 tmp
= load_reg(s
, rs
);
8830 case 0: gen_st8(tmp
, addr
, user
); break;
8831 case 1: gen_st16(tmp
, addr
, user
); break;
8832 case 2: gen_st32(tmp
, addr
, user
); break;
8834 tcg_temp_free_i32(addr
);
8839 tcg_gen_addi_i32(addr
, addr
, imm
);
8841 store_reg(s
, rn
, addr
);
8843 tcg_temp_free_i32(addr
);
8855 static void disas_thumb_insn(CPUState
*env
, DisasContext
*s
)
8857 uint32_t val
, insn
, op
, rm
, rn
, rd
, shift
, cond
;
8864 if (s
->condexec_mask
) {
8865 cond
= s
->condexec_cond
;
8866 if (cond
!= 0x0e) { /* Skip conditional when condition is AL. */
8867 s
->condlabel
= gen_new_label();
8868 gen_test_cc(cond
^ 1, s
->condlabel
);
8873 insn
= lduw_code(s
->pc
);
8876 switch (insn
>> 12) {
8880 op
= (insn
>> 11) & 3;
8883 rn
= (insn
>> 3) & 7;
8884 tmp
= load_reg(s
, rn
);
8885 if (insn
& (1 << 10)) {
8887 tmp2
= tcg_temp_new_i32();
8888 tcg_gen_movi_i32(tmp2
, (insn
>> 6) & 7);
8891 rm
= (insn
>> 6) & 7;
8892 tmp2
= load_reg(s
, rm
);
8894 if (insn
& (1 << 9)) {
8895 if (s
->condexec_mask
)
8896 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8898 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8900 if (s
->condexec_mask
)
8901 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8903 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8905 tcg_temp_free_i32(tmp2
);
8906 store_reg(s
, rd
, tmp
);
8908 /* shift immediate */
8909 rm
= (insn
>> 3) & 7;
8910 shift
= (insn
>> 6) & 0x1f;
8911 tmp
= load_reg(s
, rm
);
8912 gen_arm_shift_im(tmp
, op
, shift
, s
->condexec_mask
== 0);
8913 if (!s
->condexec_mask
)
8915 store_reg(s
, rd
, tmp
);
8919 /* arithmetic large immediate */
8920 op
= (insn
>> 11) & 3;
8921 rd
= (insn
>> 8) & 0x7;
8922 if (op
== 0) { /* mov */
8923 tmp
= tcg_temp_new_i32();
8924 tcg_gen_movi_i32(tmp
, insn
& 0xff);
8925 if (!s
->condexec_mask
)
8927 store_reg(s
, rd
, tmp
);
8929 tmp
= load_reg(s
, rd
);
8930 tmp2
= tcg_temp_new_i32();
8931 tcg_gen_movi_i32(tmp2
, insn
& 0xff);
8934 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8935 tcg_temp_free_i32(tmp
);
8936 tcg_temp_free_i32(tmp2
);
8939 if (s
->condexec_mask
)
8940 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8942 gen_helper_add_cc(tmp
, tmp
, tmp2
);
8943 tcg_temp_free_i32(tmp2
);
8944 store_reg(s
, rd
, tmp
);
8947 if (s
->condexec_mask
)
8948 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
8950 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8951 tcg_temp_free_i32(tmp2
);
8952 store_reg(s
, rd
, tmp
);
8958 if (insn
& (1 << 11)) {
8959 rd
= (insn
>> 8) & 7;
8960 /* load pc-relative. Bit 1 of PC is ignored. */
8961 val
= s
->pc
+ 2 + ((insn
& 0xff) * 4);
8962 val
&= ~(uint32_t)2;
8963 addr
= tcg_temp_new_i32();
8964 tcg_gen_movi_i32(addr
, val
);
8965 tmp
= gen_ld32(addr
, IS_USER(s
));
8966 tcg_temp_free_i32(addr
);
8967 store_reg(s
, rd
, tmp
);
8970 if (insn
& (1 << 10)) {
8971 /* data processing extended or blx */
8972 rd
= (insn
& 7) | ((insn
>> 4) & 8);
8973 rm
= (insn
>> 3) & 0xf;
8974 op
= (insn
>> 8) & 3;
8977 tmp
= load_reg(s
, rd
);
8978 tmp2
= load_reg(s
, rm
);
8979 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
8980 tcg_temp_free_i32(tmp2
);
8981 store_reg(s
, rd
, tmp
);
8984 tmp
= load_reg(s
, rd
);
8985 tmp2
= load_reg(s
, rm
);
8986 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
8987 tcg_temp_free_i32(tmp2
);
8988 tcg_temp_free_i32(tmp
);
8990 case 2: /* mov/cpy */
8991 tmp
= load_reg(s
, rm
);
8992 store_reg(s
, rd
, tmp
);
8994 case 3:/* branch [and link] exchange thumb register */
8995 tmp
= load_reg(s
, rm
);
8996 if (insn
& (1 << 7)) {
8998 val
= (uint32_t)s
->pc
| 1;
8999 tmp2
= tcg_temp_new_i32();
9000 tcg_gen_movi_i32(tmp2
, val
);
9001 store_reg(s
, 14, tmp2
);
9003 /* already thumb, no need to check */
9010 /* data processing register */
9012 rm
= (insn
>> 3) & 7;
9013 op
= (insn
>> 6) & 0xf;
9014 if (op
== 2 || op
== 3 || op
== 4 || op
== 7) {
9015 /* the shift/rotate ops want the operands backwards */
9024 if (op
== 9) { /* neg */
9025 tmp
= tcg_temp_new_i32();
9026 tcg_gen_movi_i32(tmp
, 0);
9027 } else if (op
!= 0xf) { /* mvn doesn't read its first operand */
9028 tmp
= load_reg(s
, rd
);
9033 tmp2
= load_reg(s
, rm
);
9036 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
9037 if (!s
->condexec_mask
)
9041 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
9042 if (!s
->condexec_mask
)
9046 if (s
->condexec_mask
) {
9047 gen_helper_shl(tmp2
, tmp2
, tmp
);
9049 gen_helper_shl_cc(tmp2
, tmp2
, tmp
);
9054 if (s
->condexec_mask
) {
9055 gen_helper_shr(tmp2
, tmp2
, tmp
);
9057 gen_helper_shr_cc(tmp2
, tmp2
, tmp
);
9062 if (s
->condexec_mask
) {
9063 gen_helper_sar(tmp2
, tmp2
, tmp
);
9065 gen_helper_sar_cc(tmp2
, tmp2
, tmp
);
9070 if (s
->condexec_mask
)
9073 gen_helper_adc_cc(tmp
, tmp
, tmp2
);
9076 if (s
->condexec_mask
)
9077 gen_sub_carry(tmp
, tmp
, tmp2
);
9079 gen_helper_sbc_cc(tmp
, tmp
, tmp2
);
9082 if (s
->condexec_mask
) {
9083 tcg_gen_andi_i32(tmp
, tmp
, 0x1f);
9084 tcg_gen_rotr_i32(tmp2
, tmp2
, tmp
);
9086 gen_helper_ror_cc(tmp2
, tmp2
, tmp
);
9091 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
9096 if (s
->condexec_mask
)
9097 tcg_gen_neg_i32(tmp
, tmp2
);
9099 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
9102 gen_helper_sub_cc(tmp
, tmp
, tmp2
);
9106 gen_helper_add_cc(tmp
, tmp
, tmp2
);
9110 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
9111 if (!s
->condexec_mask
)
9115 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
9116 if (!s
->condexec_mask
)
9120 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
9121 if (!s
->condexec_mask
)
9125 tcg_gen_not_i32(tmp2
, tmp2
);
9126 if (!s
->condexec_mask
)
9134 store_reg(s
, rm
, tmp2
);
9136 tcg_temp_free_i32(tmp
);
9138 store_reg(s
, rd
, tmp
);
9139 tcg_temp_free_i32(tmp2
);
9142 tcg_temp_free_i32(tmp
);
9143 tcg_temp_free_i32(tmp2
);
9148 /* load/store register offset. */
9150 rn
= (insn
>> 3) & 7;
9151 rm
= (insn
>> 6) & 7;
9152 op
= (insn
>> 9) & 7;
9153 addr
= load_reg(s
, rn
);
9154 tmp
= load_reg(s
, rm
);
9155 tcg_gen_add_i32(addr
, addr
, tmp
);
9156 tcg_temp_free_i32(tmp
);
9158 if (op
< 3) /* store */
9159 tmp
= load_reg(s
, rd
);
9163 gen_st32(tmp
, addr
, IS_USER(s
));
9166 gen_st16(tmp
, addr
, IS_USER(s
));
9169 gen_st8(tmp
, addr
, IS_USER(s
));
9172 tmp
= gen_ld8s(addr
, IS_USER(s
));
9175 tmp
= gen_ld32(addr
, IS_USER(s
));
9178 tmp
= gen_ld16u(addr
, IS_USER(s
));
9181 tmp
= gen_ld8u(addr
, IS_USER(s
));
9184 tmp
= gen_ld16s(addr
, IS_USER(s
));
9187 if (op
>= 3) /* load */
9188 store_reg(s
, rd
, tmp
);
9189 tcg_temp_free_i32(addr
);
9193 /* load/store word immediate offset */
9195 rn
= (insn
>> 3) & 7;
9196 addr
= load_reg(s
, rn
);
9197 val
= (insn
>> 4) & 0x7c;
9198 tcg_gen_addi_i32(addr
, addr
, val
);
9200 if (insn
& (1 << 11)) {
9202 tmp
= gen_ld32(addr
, IS_USER(s
));
9203 store_reg(s
, rd
, tmp
);
9206 tmp
= load_reg(s
, rd
);
9207 gen_st32(tmp
, addr
, IS_USER(s
));
9209 tcg_temp_free_i32(addr
);
9213 /* load/store byte immediate offset */
9215 rn
= (insn
>> 3) & 7;
9216 addr
= load_reg(s
, rn
);
9217 val
= (insn
>> 6) & 0x1f;
9218 tcg_gen_addi_i32(addr
, addr
, val
);
9220 if (insn
& (1 << 11)) {
9222 tmp
= gen_ld8u(addr
, IS_USER(s
));
9223 store_reg(s
, rd
, tmp
);
9226 tmp
= load_reg(s
, rd
);
9227 gen_st8(tmp
, addr
, IS_USER(s
));
9229 tcg_temp_free_i32(addr
);
9233 /* load/store halfword immediate offset */
9235 rn
= (insn
>> 3) & 7;
9236 addr
= load_reg(s
, rn
);
9237 val
= (insn
>> 5) & 0x3e;
9238 tcg_gen_addi_i32(addr
, addr
, val
);
9240 if (insn
& (1 << 11)) {
9242 tmp
= gen_ld16u(addr
, IS_USER(s
));
9243 store_reg(s
, rd
, tmp
);
9246 tmp
= load_reg(s
, rd
);
9247 gen_st16(tmp
, addr
, IS_USER(s
));
9249 tcg_temp_free_i32(addr
);
9253 /* load/store from stack */
9254 rd
= (insn
>> 8) & 7;
9255 addr
= load_reg(s
, 13);
9256 val
= (insn
& 0xff) * 4;
9257 tcg_gen_addi_i32(addr
, addr
, val
);
9259 if (insn
& (1 << 11)) {
9261 tmp
= gen_ld32(addr
, IS_USER(s
));
9262 store_reg(s
, rd
, tmp
);
9265 tmp
= load_reg(s
, rd
);
9266 gen_st32(tmp
, addr
, IS_USER(s
));
9268 tcg_temp_free_i32(addr
);
9272 /* add to high reg */
9273 rd
= (insn
>> 8) & 7;
9274 if (insn
& (1 << 11)) {
9276 tmp
= load_reg(s
, 13);
9278 /* PC. bit 1 is ignored. */
9279 tmp
= tcg_temp_new_i32();
9280 tcg_gen_movi_i32(tmp
, (s
->pc
+ 2) & ~(uint32_t)2);
9282 val
= (insn
& 0xff) * 4;
9283 tcg_gen_addi_i32(tmp
, tmp
, val
);
9284 store_reg(s
, rd
, tmp
);
9289 op
= (insn
>> 8) & 0xf;
9292 /* adjust stack pointer */
9293 tmp
= load_reg(s
, 13);
9294 val
= (insn
& 0x7f) * 4;
9295 if (insn
& (1 << 7))
9296 val
= -(int32_t)val
;
9297 tcg_gen_addi_i32(tmp
, tmp
, val
);
9298 store_reg(s
, 13, tmp
);
9301 case 2: /* sign/zero extend. */
9304 rm
= (insn
>> 3) & 7;
9305 tmp
= load_reg(s
, rm
);
9306 switch ((insn
>> 6) & 3) {
9307 case 0: gen_sxth(tmp
); break;
9308 case 1: gen_sxtb(tmp
); break;
9309 case 2: gen_uxth(tmp
); break;
9310 case 3: gen_uxtb(tmp
); break;
9312 store_reg(s
, rd
, tmp
);
9314 case 4: case 5: case 0xc: case 0xd:
9316 addr
= load_reg(s
, 13);
9317 if (insn
& (1 << 8))
9321 for (i
= 0; i
< 8; i
++) {
9322 if (insn
& (1 << i
))
9325 if ((insn
& (1 << 11)) == 0) {
9326 tcg_gen_addi_i32(addr
, addr
, -offset
);
9328 for (i
= 0; i
< 8; i
++) {
9329 if (insn
& (1 << i
)) {
9330 if (insn
& (1 << 11)) {
9332 tmp
= gen_ld32(addr
, IS_USER(s
));
9333 store_reg(s
, i
, tmp
);
9336 tmp
= load_reg(s
, i
);
9337 gen_st32(tmp
, addr
, IS_USER(s
));
9339 /* advance to the next address. */
9340 tcg_gen_addi_i32(addr
, addr
, 4);
9344 if (insn
& (1 << 8)) {
9345 if (insn
& (1 << 11)) {
9347 tmp
= gen_ld32(addr
, IS_USER(s
));
9348 /* don't set the pc until the rest of the instruction
9352 tmp
= load_reg(s
, 14);
9353 gen_st32(tmp
, addr
, IS_USER(s
));
9355 tcg_gen_addi_i32(addr
, addr
, 4);
9357 if ((insn
& (1 << 11)) == 0) {
9358 tcg_gen_addi_i32(addr
, addr
, -offset
);
9360 /* write back the new stack pointer */
9361 store_reg(s
, 13, addr
);
9362 /* set the new PC value */
9363 if ((insn
& 0x0900) == 0x0900) {
9364 store_reg_from_load(env
, s
, 15, tmp
);
9368 case 1: case 3: case 9: case 11: /* czb */
9370 tmp
= load_reg(s
, rm
);
9371 s
->condlabel
= gen_new_label();
9373 if (insn
& (1 << 11))
9374 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, s
->condlabel
);
9376 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, s
->condlabel
);
9377 tcg_temp_free_i32(tmp
);
9378 offset
= ((insn
& 0xf8) >> 2) | (insn
& 0x200) >> 3;
9379 val
= (uint32_t)s
->pc
+ 2;
9384 case 15: /* IT, nop-hint. */
9385 if ((insn
& 0xf) == 0) {
9386 gen_nop_hint(s
, (insn
>> 4) & 0xf);
9390 s
->condexec_cond
= (insn
>> 4) & 0xe;
9391 s
->condexec_mask
= insn
& 0x1f;
9392 /* No actual code generated for this insn, just setup state. */
9395 case 0xe: /* bkpt */
9397 gen_exception_insn(s
, 2, EXCP_BKPT
);
9402 rn
= (insn
>> 3) & 0x7;
9404 tmp
= load_reg(s
, rn
);
9405 switch ((insn
>> 6) & 3) {
9406 case 0: tcg_gen_bswap32_i32(tmp
, tmp
); break;
9407 case 1: gen_rev16(tmp
); break;
9408 case 3: gen_revsh(tmp
); break;
9409 default: goto illegal_op
;
9411 store_reg(s
, rd
, tmp
);
9419 tmp
= tcg_const_i32((insn
& (1 << 4)) != 0);
9422 addr
= tcg_const_i32(16);
9423 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
9424 tcg_temp_free_i32(addr
);
9428 addr
= tcg_const_i32(17);
9429 gen_helper_v7m_msr(cpu_env
, addr
, tmp
);
9430 tcg_temp_free_i32(addr
);
9432 tcg_temp_free_i32(tmp
);
9435 if (insn
& (1 << 4))
9436 shift
= CPSR_A
| CPSR_I
| CPSR_F
;
9439 gen_set_psr_im(s
, ((insn
& 7) << 6), 0, shift
);
9449 /* load/store multiple */
9450 rn
= (insn
>> 8) & 0x7;
9451 addr
= load_reg(s
, rn
);
9452 for (i
= 0; i
< 8; i
++) {
9453 if (insn
& (1 << i
)) {
9454 if (insn
& (1 << 11)) {
9456 tmp
= gen_ld32(addr
, IS_USER(s
));
9457 store_reg(s
, i
, tmp
);
9460 tmp
= load_reg(s
, i
);
9461 gen_st32(tmp
, addr
, IS_USER(s
));
9463 /* advance to the next address */
9464 tcg_gen_addi_i32(addr
, addr
, 4);
9467 /* Base register writeback. */
9468 if ((insn
& (1 << rn
)) == 0) {
9469 store_reg(s
, rn
, addr
);
9471 tcg_temp_free_i32(addr
);
9476 /* conditional branch or swi */
9477 cond
= (insn
>> 8) & 0xf;
9483 gen_set_pc_im(s
->pc
);
9484 s
->is_jmp
= DISAS_SWI
;
9487 /* generate a conditional jump to next instruction */
9488 s
->condlabel
= gen_new_label();
9489 gen_test_cc(cond
^ 1, s
->condlabel
);
9492 /* jump to the offset */
9493 val
= (uint32_t)s
->pc
+ 2;
9494 offset
= ((int32_t)insn
<< 24) >> 24;
9500 if (insn
& (1 << 11)) {
9501 if (disas_thumb2_insn(env
, s
, insn
))
9505 /* unconditional branch */
9506 val
= (uint32_t)s
->pc
;
9507 offset
= ((int32_t)insn
<< 21) >> 21;
9508 val
+= (offset
<< 1) + 2;
9513 if (disas_thumb2_insn(env
, s
, insn
))
9519 gen_exception_insn(s
, 4, EXCP_UDEF
);
9523 gen_exception_insn(s
, 2, EXCP_UDEF
);
9526 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
9527 basic block 'tb'. If search_pc is TRUE, also generate PC
9528 information for each intermediate instruction. */
9529 static inline void gen_intermediate_code_internal(CPUState
*env
,
9530 TranslationBlock
*tb
,
9533 DisasContext dc1
, *dc
= &dc1
;
9535 uint16_t *gen_opc_end
;
9537 target_ulong pc_start
;
9538 uint32_t next_page_start
;
9542 /* generate intermediate code */
9547 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
9549 dc
->is_jmp
= DISAS_NEXT
;
9551 dc
->singlestep_enabled
= env
->singlestep_enabled
;
9553 dc
->thumb
= ARM_TBFLAG_THUMB(tb
->flags
);
9554 dc
->condexec_mask
= (ARM_TBFLAG_CONDEXEC(tb
->flags
) & 0xf) << 1;
9555 dc
->condexec_cond
= ARM_TBFLAG_CONDEXEC(tb
->flags
) >> 4;
9556 #if !defined(CONFIG_USER_ONLY)
9557 dc
->user
= (ARM_TBFLAG_PRIV(tb
->flags
) == 0);
9559 dc
->vfp_enabled
= ARM_TBFLAG_VFPEN(tb
->flags
);
9560 dc
->vec_len
= ARM_TBFLAG_VECLEN(tb
->flags
);
9561 dc
->vec_stride
= ARM_TBFLAG_VECSTRIDE(tb
->flags
);
9562 cpu_F0s
= tcg_temp_new_i32();
9563 cpu_F1s
= tcg_temp_new_i32();
9564 cpu_F0d
= tcg_temp_new_i64();
9565 cpu_F1d
= tcg_temp_new_i64();
9568 /* FIXME: cpu_M0 can probably be the same as cpu_V0. */
9569 cpu_M0
= tcg_temp_new_i64();
9570 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
9573 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
9575 max_insns
= CF_COUNT_MASK
;
9579 tcg_clear_temp_count();
9581 /* A note on handling of the condexec (IT) bits:
9583 * We want to avoid the overhead of having to write the updated condexec
9584 * bits back to the CPUState for every instruction in an IT block. So:
9585 * (1) if the condexec bits are not already zero then we write
9586 * zero back into the CPUState now. This avoids complications trying
9587 * to do it at the end of the block. (For example if we don't do this
9588 * it's hard to identify whether we can safely skip writing condexec
9589 * at the end of the TB, which we definitely want to do for the case
9590 * where a TB doesn't do anything with the IT state at all.)
9591 * (2) if we are going to leave the TB then we call gen_set_condexec()
9592 * which will write the correct value into CPUState if zero is wrong.
9593 * This is done both for leaving the TB at the end, and for leaving
9594 * it because of an exception we know will happen, which is done in
9595 * gen_exception_insn(). The latter is necessary because we need to
9596 * leave the TB with the PC/IT state just prior to execution of the
9597 * instruction which caused the exception.
9598 * (3) if we leave the TB unexpectedly (eg a data abort on a load)
9599 * then the CPUState will be wrong and we need to reset it.
9600 * This is handled in the same way as restoration of the
9601 * PC in these situations: we will be called again with search_pc=1
9602 * and generate a mapping of the condexec bits for each PC in
9603 * gen_opc_condexec_bits[]. restore_state_to_opc() then uses
9604 * this to restore the condexec bits.
9606 * Note that there are no instructions which can read the condexec
9607 * bits, and none which can write non-static values to them, so
9608 * we don't need to care about whether CPUState is correct in the
9612 /* Reset the conditional execution bits immediately. This avoids
9613 complications trying to do it at the end of the block. */
9614 if (dc
->condexec_mask
|| dc
->condexec_cond
)
9616 TCGv tmp
= tcg_temp_new_i32();
9617 tcg_gen_movi_i32(tmp
, 0);
9618 store_cpu_field(tmp
, condexec_bits
);
9621 #ifdef CONFIG_USER_ONLY
9622 /* Intercept jump to the magic kernel page. */
9623 if (dc
->pc
>= 0xffff0000) {
9624 /* We always get here via a jump, so know we are not in a
9625 conditional execution block. */
9626 gen_exception(EXCP_KERNEL_TRAP
);
9627 dc
->is_jmp
= DISAS_UPDATE
;
9631 if (dc
->pc
>= 0xfffffff0 && IS_M(env
)) {
9632 /* We always get here via a jump, so know we are not in a
9633 conditional execution block. */
9634 gen_exception(EXCP_EXCEPTION_EXIT
);
9635 dc
->is_jmp
= DISAS_UPDATE
;
9640 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
9641 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
9642 if (bp
->pc
== dc
->pc
) {
9643 gen_exception_insn(dc
, 0, EXCP_DEBUG
);
9644 /* Advance PC so that clearing the breakpoint will
9645 invalidate this TB. */
9647 goto done_generating
;
9653 j
= gen_opc_ptr
- gen_opc_buf
;
9657 gen_opc_instr_start
[lj
++] = 0;
9659 gen_opc_pc
[lj
] = dc
->pc
;
9660 gen_opc_condexec_bits
[lj
] = (dc
->condexec_cond
<< 4) | (dc
->condexec_mask
>> 1);
9661 gen_opc_instr_start
[lj
] = 1;
9662 gen_opc_icount
[lj
] = num_insns
;
9665 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
9668 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
9669 tcg_gen_debug_insn_start(dc
->pc
);
9673 disas_thumb_insn(env
, dc
);
9674 if (dc
->condexec_mask
) {
9675 dc
->condexec_cond
= (dc
->condexec_cond
& 0xe)
9676 | ((dc
->condexec_mask
>> 4) & 1);
9677 dc
->condexec_mask
= (dc
->condexec_mask
<< 1) & 0x1f;
9678 if (dc
->condexec_mask
== 0) {
9679 dc
->condexec_cond
= 0;
9683 disas_arm_insn(env
, dc
);
9686 if (dc
->condjmp
&& !dc
->is_jmp
) {
9687 gen_set_label(dc
->condlabel
);
9691 if (tcg_check_temp_count()) {
9692 fprintf(stderr
, "TCG temporary leak before %08x\n", dc
->pc
);
9695 /* Translation stops when a conditional branch is encountered.
9696 * Otherwise the subsequent code could get translated several times.
9697 * Also stop translation when a page boundary is reached. This
9698 * ensures prefetch aborts occur at the right place. */
9700 } while (!dc
->is_jmp
&& gen_opc_ptr
< gen_opc_end
&&
9701 !env
->singlestep_enabled
&&
9703 dc
->pc
< next_page_start
&&
9704 num_insns
< max_insns
);
9706 if (tb
->cflags
& CF_LAST_IO
) {
9708 /* FIXME: This can theoretically happen with self-modifying
9710 cpu_abort(env
, "IO on conditional branch instruction");
9715 /* At this stage dc->condjmp will only be set when the skipped
9716 instruction was a conditional branch or trap, and the PC has
9717 already been written. */
9718 if (unlikely(env
->singlestep_enabled
)) {
9719 /* Make sure the pc is updated, and raise a debug exception. */
9721 gen_set_condexec(dc
);
9722 if (dc
->is_jmp
== DISAS_SWI
) {
9723 gen_exception(EXCP_SWI
);
9725 gen_exception(EXCP_DEBUG
);
9727 gen_set_label(dc
->condlabel
);
9729 if (dc
->condjmp
|| !dc
->is_jmp
) {
9730 gen_set_pc_im(dc
->pc
);
9733 gen_set_condexec(dc
);
9734 if (dc
->is_jmp
== DISAS_SWI
&& !dc
->condjmp
) {
9735 gen_exception(EXCP_SWI
);
9737 /* FIXME: Single stepping a WFI insn will not halt
9739 gen_exception(EXCP_DEBUG
);
9742 /* While branches must always occur at the end of an IT block,
9743 there are a few other things that can cause us to terminate
9744 the TB in the middel of an IT block:
9745 - Exception generating instructions (bkpt, swi, undefined).
9747 - Hardware watchpoints.
9748 Hardware breakpoints have already been handled and skip this code.
9750 gen_set_condexec(dc
);
9751 switch(dc
->is_jmp
) {
9753 gen_goto_tb(dc
, 1, dc
->pc
);
9758 /* indicate that the hash table must be used to find the next TB */
9762 /* nothing more to generate */
9768 gen_exception(EXCP_SWI
);
9772 gen_set_label(dc
->condlabel
);
9773 gen_set_condexec(dc
);
9774 gen_goto_tb(dc
, 1, dc
->pc
);
9780 gen_icount_end(tb
, num_insns
);
9781 *gen_opc_ptr
= INDEX_op_end
;
9784 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
9785 qemu_log("----------------\n");
9786 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
9787 log_target_disas(pc_start
, dc
->pc
- pc_start
, dc
->thumb
);
9792 j
= gen_opc_ptr
- gen_opc_buf
;
9795 gen_opc_instr_start
[lj
++] = 0;
9797 tb
->size
= dc
->pc
- pc_start
;
9798 tb
->icount
= num_insns
;
9802 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
9804 gen_intermediate_code_internal(env
, tb
, 0);
9807 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
9809 gen_intermediate_code_internal(env
, tb
, 1);
9812 static const char *cpu_mode_names
[16] = {
9813 "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
9814 "???", "???", "???", "und", "???", "???", "???", "sys"
9817 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
9827 /* ??? This assumes float64 and double have the same layout.
9828 Oh well, it's only debug dumps. */
9837 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
9839 cpu_fprintf(f
, "\n");
9841 cpu_fprintf(f
, " ");
9843 psr
= cpsr_read(env
);
9844 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%d\n",
9846 psr
& (1 << 31) ? 'N' : '-',
9847 psr
& (1 << 30) ? 'Z' : '-',
9848 psr
& (1 << 29) ? 'C' : '-',
9849 psr
& (1 << 28) ? 'V' : '-',
9850 psr
& CPSR_T
? 'T' : 'A',
9851 cpu_mode_names
[psr
& 0xf], (psr
& 0x10) ? 32 : 26);
9854 for (i
= 0; i
< 16; i
++) {
9855 d
.d
= env
->vfp
.regs
[i
];
9859 cpu_fprintf(f
, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n",
9860 i
* 2, (int)s0
.i
, s0
.s
,
9861 i
* 2 + 1, (int)s1
.i
, s1
.s
,
9862 i
, (int)(uint32_t)d
.l
.upper
, (int)(uint32_t)d
.l
.lower
,
9865 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->vfp
.xregs
[ARM_VFP_FPSCR
]);
9869 void restore_state_to_opc(CPUState
*env
, TranslationBlock
*tb
, int pc_pos
)
9871 env
->regs
[15] = gen_opc_pc
[pc_pos
];
9872 env
->condexec_bits
= gen_opc_condexec_bits
[pc_pos
];