target-sparc/win_helper.c

   1 /*
   2  * Helpers for CWP and PSTATE handling
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "trace.h"
  23
  24 static inline void memcpy32(target_ulong *dst, const target_ulong *src)
  25 {
  26     dst[0] = src[0];
  27     dst[1] = src[1];
  28     dst[2] = src[2];
  29     dst[3] = src[3];
  30     dst[4] = src[4];
  31     dst[5] = src[5];
  32     dst[6] = src[6];
  33     dst[7] = src[7];
  34 }
  35
  36 void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
  37 {
  38     /* put the modified wrap registers at their proper location */
  39     if (env->cwp == env->nwindows - 1) {
  40         memcpy32(env->regbase, env->regbase + env->nwindows * 16);
  41     }
  42     env->cwp = new_cwp;
  43
  44     /* put the wrap registers at their temporary location */
  45     if (new_cwp == env->nwindows - 1) {
  46         memcpy32(env->regbase + env->nwindows * 16, env->regbase);
  47     }
  48     env->regwptr = env->regbase + (new_cwp * 16);
  49 }
  50
  51 target_ulong cpu_get_psr(CPUSPARCState *env)
  52 {
  53     helper_compute_psr(env);
  54
  55 #if !defined(TARGET_SPARC64)
  56     return env->version | (env->psr & PSR_ICC) |
  57         (env->psref ? PSR_EF : 0) |
  58         (env->psrpil << 8) |
  59         (env->psrs ? PSR_S : 0) |
  60         (env->psrps ? PSR_PS : 0) |
  61         (env->psret ? PSR_ET : 0) | env->cwp;
  62 #else
  63     return env->psr & PSR_ICC;
  64 #endif
  65 }
  66
  67 void cpu_put_psr_raw(CPUSPARCState *env, target_ulong val)
  68 {
  69     env->psr = val & PSR_ICC;
  70 #if !defined(TARGET_SPARC64)
  71     env->psref = (val & PSR_EF) ? 1 : 0;
  72     env->psrpil = (val & PSR_PIL) >> 8;
  73     env->psrs = (val & PSR_S) ? 1 : 0;
  74     env->psrps = (val & PSR_PS) ? 1 : 0;
  75     env->psret = (val & PSR_ET) ? 1 : 0;
  76 #endif
  77     env->cc_op = CC_OP_FLAGS;
  78 #if !defined(TARGET_SPARC64)
  79     cpu_set_cwp(env, val & PSR_CWP);
  80 #endif
  81 }
  82
  83 void cpu_put_psr(CPUSPARCState *env, target_ulong val)
  84 {
  85     cpu_put_psr_raw(env, val);
  86 #if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
  87     cpu_check_irqs(env);
  88 #endif
  89 }
  90
  91 int cpu_cwp_inc(CPUSPARCState *env, int cwp)
  92 {
  93     if (unlikely(cwp >= env->nwindows)) {
  94         cwp -= env->nwindows;
  95     }
  96     return cwp;
  97 }
  98
  99 int cpu_cwp_dec(CPUSPARCState *env, int cwp)
 100 {
 101     if (unlikely(cwp < 0)) {
 102         cwp += env->nwindows;
 103     }
 104     return cwp;
 105 }
 106
 107 #ifndef TARGET_SPARC64
 108 void helper_rett(CPUSPARCState *env)
 109 {
 110     unsigned int cwp;
 111
 112     if (env->psret == 1) {
 113         helper_raise_exception(env, TT_ILL_INSN);
 114     }
 115
 116     env->psret = 1;
 117     cwp = cpu_cwp_inc(env, env->cwp + 1) ;
 118     if (env->wim & (1 << cwp)) {
 119         helper_raise_exception(env, TT_WIN_UNF);
 120     }
 121     cpu_set_cwp(env, cwp);
 122     env->psrs = env->psrps;
 123 }
 124
 125 /* XXX: use another pointer for %iN registers to avoid slow wrapping
 126    handling ? */
 127 void helper_save(CPUSPARCState *env)
 128 {
 129     uint32_t cwp;
 130
 131     cwp = cpu_cwp_dec(env, env->cwp - 1);
 132     if (env->wim & (1 << cwp)) {
 133         helper_raise_exception(env, TT_WIN_OVF);
 134     }
 135     cpu_set_cwp(env, cwp);
 136 }
 137
 138 void helper_restore(CPUSPARCState *env)
 139 {
 140     uint32_t cwp;
 141
 142     cwp = cpu_cwp_inc(env, env->cwp + 1);
 143     if (env->wim & (1 << cwp)) {
 144         helper_raise_exception(env, TT_WIN_UNF);
 145     }
 146     cpu_set_cwp(env, cwp);
 147 }
 148
 149 void helper_wrpsr(CPUSPARCState *env, target_ulong new_psr)
 150 {
 151     if ((new_psr & PSR_CWP) >= env->nwindows) {
 152         helper_raise_exception(env, TT_ILL_INSN);
 153     } else {
 154         cpu_put_psr(env, new_psr);
 155     }
 156 }
 157
 158 target_ulong helper_rdpsr(CPUSPARCState *env)
 159 {
 160     return cpu_get_psr(env);
 161 }
 162
 163 #else
 164 /* XXX: use another pointer for %iN registers to avoid slow wrapping
 165    handling ? */
 166 void helper_save(CPUSPARCState *env)
 167 {
 168     uint32_t cwp;
 169
 170     cwp = cpu_cwp_dec(env, env->cwp - 1);
 171     if (env->cansave == 0) {
 172         helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
 173                                                 (TT_WOTHER |
 174                                                  ((env->wstate & 0x38) >> 1)) :
 175                                                 ((env->wstate & 0x7) << 2)));
 176     } else {
 177         if (env->cleanwin - env->canrestore == 0) {
 178             /* XXX Clean windows without trap */
 179             helper_raise_exception(env, TT_CLRWIN);
 180         } else {
 181             env->cansave--;
 182             env->canrestore++;
 183             cpu_set_cwp(env, cwp);
 184         }
 185     }
 186 }
 187
 188 void helper_restore(CPUSPARCState *env)
 189 {
 190     uint32_t cwp;
 191
 192     cwp = cpu_cwp_inc(env, env->cwp + 1);
 193     if (env->canrestore == 0) {
 194         helper_raise_exception(env, TT_FILL | (env->otherwin != 0 ?
 195                                                (TT_WOTHER |
 196                                                 ((env->wstate & 0x38) >> 1)) :
 197                                                ((env->wstate & 0x7) << 2)));
 198     } else {
 199         env->cansave++;
 200         env->canrestore--;
 201         cpu_set_cwp(env, cwp);
 202     }
 203 }
 204
 205 void helper_flushw(CPUSPARCState *env)
 206 {
 207     if (env->cansave != env->nwindows - 2) {
 208         helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
 209                                                 (TT_WOTHER |
 210                                                  ((env->wstate & 0x38) >> 1)) :
 211                                                 ((env->wstate & 0x7) << 2)));
 212     }
 213 }
 214
 215 void helper_saved(CPUSPARCState *env)
 216 {
 217     env->cansave++;
 218     if (env->otherwin == 0) {
 219         env->canrestore--;
 220     } else {
 221         env->otherwin--;
 222     }
 223 }
 224
 225 void helper_restored(CPUSPARCState *env)
 226 {
 227     env->canrestore++;
 228     if (env->cleanwin < env->nwindows - 1) {
 229         env->cleanwin++;
 230     }
 231     if (env->otherwin == 0) {
 232         env->cansave--;
 233     } else {
 234         env->otherwin--;
 235     }
 236 }
 237
 238 target_ulong cpu_get_ccr(CPUSPARCState *env)
 239 {
 240     target_ulong psr;
 241
 242     psr = cpu_get_psr(env);
 243
 244     return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
 245 }
 246
 247 void cpu_put_ccr(CPUSPARCState *env, target_ulong val)
 248 {
 249     env->xcc = (val >> 4) << 20;
 250     env->psr = (val & 0xf) << 20;
 251     CC_OP = CC_OP_FLAGS;
 252 }
 253
 254 target_ulong cpu_get_cwp64(CPUSPARCState *env)
 255 {
 256     return env->nwindows - 1 - env->cwp;
 257 }
 258
 259 void cpu_put_cwp64(CPUSPARCState *env, int cwp)
 260 {
 261     if (unlikely(cwp >= env->nwindows || cwp < 0)) {
 262         cwp %= env->nwindows;
 263     }
 264     cpu_set_cwp(env, env->nwindows - 1 - cwp);
 265 }
 266
 267 target_ulong helper_rdccr(CPUSPARCState *env)
 268 {
 269     return cpu_get_ccr(env);
 270 }
 271
 272 void helper_wrccr(CPUSPARCState *env, target_ulong new_ccr)
 273 {
 274     cpu_put_ccr(env, new_ccr);
 275 }
 276
 277 /* CWP handling is reversed in V9, but we still use the V8 register
 278    order. */
 279 target_ulong helper_rdcwp(CPUSPARCState *env)
 280 {
 281     return cpu_get_cwp64(env);
 282 }
 283
 284 void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
 285 {
 286     cpu_put_cwp64(env, new_cwp);
 287 }
 288
 289 static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
 290 {
 291     switch (pstate) {
 292     default:
 293         trace_win_helper_gregset_error(pstate);
 294         /* pass through to normal set of global registers */
 295     case 0:
 296         return env->bgregs;
 297     case PS_AG:
 298         return env->agregs;
 299     case PS_MG:
 300         return env->mgregs;
 301     case PS_IG:
 302         return env->igregs;
 303     }
 304 }
 305
 306 void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
 307 {
 308     uint32_t pstate_regs, new_pstate_regs;
 309     uint64_t *src, *dst;
 310
 311     if (env->def->features & CPU_FEATURE_GL) {
 312         /* PS_AG is not implemented in this case */
 313         new_pstate &= ~PS_AG;
 314     }
 315
 316     pstate_regs = env->pstate & 0xc01;
 317     new_pstate_regs = new_pstate & 0xc01;
 318
 319     if (new_pstate_regs != pstate_regs) {
 320         trace_win_helper_switch_pstate(pstate_regs, new_pstate_regs);
 321
 322         /* Switch global register bank */
 323         src = get_gregset(env, new_pstate_regs);
 324         dst = get_gregset(env, pstate_regs);
 325         memcpy32(dst, env->gregs);
 326         memcpy32(env->gregs, src);
 327     } else {
 328         trace_win_helper_no_switch_pstate(new_pstate_regs);
 329     }
 330     env->pstate = new_pstate;
 331 }
 332
 333 void helper_wrpstate(CPUSPARCState *env, target_ulong new_state)
 334 {
 335     cpu_change_pstate(env, new_state & 0xf3f);
 336
 337 #if !defined(CONFIG_USER_ONLY)
 338     if (cpu_interrupts_enabled(env)) {
 339         cpu_check_irqs(env);
 340     }
 341 #endif
 342 }
 343
 344 void helper_wrpil(CPUSPARCState *env, target_ulong new_pil)
 345 {
 346 #if !defined(CONFIG_USER_ONLY)
 347     trace_win_helper_wrpil(env->psrpil, (uint32_t)new_pil);
 348
 349     env->psrpil = new_pil;
 350
 351     if (cpu_interrupts_enabled(env)) {
 352         cpu_check_irqs(env);
 353     }
 354 #endif
 355 }
 356
 357 void helper_done(CPUSPARCState *env)
 358 {
 359     trap_state *tsptr = cpu_tsptr(env);
 360
 361     env->pc = tsptr->tnpc;
 362     env->npc = tsptr->tnpc + 4;
 363     cpu_put_ccr(env, tsptr->tstate >> 32);
 364     env->asi = (tsptr->tstate >> 24) & 0xff;
 365     cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
 366     cpu_put_cwp64(env, tsptr->tstate & 0xff);
 367     env->tl--;
 368
 369     trace_win_helper_done(env->tl);
 370
 371 #if !defined(CONFIG_USER_ONLY)
 372     if (cpu_interrupts_enabled(env)) {
 373         cpu_check_irqs(env);
 374     }
 375 #endif
 376 }
 377
 378 void helper_retry(CPUSPARCState *env)
 379 {
 380     trap_state *tsptr = cpu_tsptr(env);
 381
 382     env->pc = tsptr->tpc;
 383     env->npc = tsptr->tnpc;
 384     cpu_put_ccr(env, tsptr->tstate >> 32);
 385     env->asi = (tsptr->tstate >> 24) & 0xff;
 386     cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
 387     cpu_put_cwp64(env, tsptr->tstate & 0xff);
 388     env->tl--;
 389
 390     trace_win_helper_retry(env->tl);
 391
 392 #if !defined(CONFIG_USER_ONLY)
 393     if (cpu_interrupts_enabled(env)) {
 394         cpu_check_irqs(env);
 395     }
 396 #endif
 397 }
 398 #endif