?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge remote-tracking branch 'qmp/queue/qmp' into staging
[qemu.git] / hw / fdc.c
bloba0236b7295d05ccdefc0ad2074302269411daa30
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "qemu-error.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37 #include "blockdev.h"
38 #include "sysemu.h"
39
40 /********************************************************/
41 /* debug Floppy devices */
42 //#define DEBUG_FLOPPY
43
44 #ifdef DEBUG_FLOPPY
45 #define FLOPPY_DPRINTF(fmt, ...) \
46 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
47 #else
48 #define FLOPPY_DPRINTF(fmt, ...)
49 #endif
50
51 #define FLOPPY_ERROR(fmt, ...) \
52 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54 /********************************************************/
55 /* Floppy drive emulation */
56
57 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
58 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
59
60 /* Will always be a fixed parameter for us */
61 #define FD_SECTOR_LEN 512
62 #define FD_SECTOR_SC 2 /* Sector size code */
63 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
64
65 typedef struct FDCtrl FDCtrl;
66
67 /* Floppy disk drive emulation */
68 typedef enum FDiskFlags {
69 FDISK_DBL_SIDES = 0x01,
70 } FDiskFlags;
71
72 typedef struct FDrive {
73 FDCtrl *fdctrl;
74 BlockDriverState *bs;
75 /* Drive status */
76 FDriveType drive;
77 uint8_t perpendicular; /* 2.88 MB access mode */
78 /* Position */
79 uint8_t head;
80 uint8_t track;
81 uint8_t sect;
82 /* Media */
83 FDiskFlags flags;
84 uint8_t last_sect; /* Nb sector per track */
85 uint8_t max_track; /* Nb of tracks */
86 uint16_t bps; /* Bytes per sector */
87 uint8_t ro; /* Is read-only */
88 uint8_t media_changed; /* Is media changed */
89 uint8_t media_rate; /* Data rate of medium */
90 } FDrive;
91
92 static void fd_init(FDrive *drv)
93 {
94 /* Drive */
95 drv->drive = FDRIVE_DRV_NONE;
96 drv->perpendicular = 0;
97 /* Disk */
98 drv->last_sect = 0;
99 drv->max_track = 0;
100 }
101
102 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
103
104 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
105 uint8_t last_sect, uint8_t num_sides)
106 {
107 return (((track * num_sides) + head) * last_sect) + sect - 1;
108 }
109
110 /* Returns current position, in sectors, for given drive */
111 static int fd_sector(FDrive *drv)
112 {
113 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
114 NUM_SIDES(drv));
115 }
116
117 /* Seek to a new position:
118 * returns 0 if already on right track
119 * returns 1 if track changed
120 * returns 2 if track is invalid
121 * returns 3 if sector is invalid
122 * returns 4 if seek is disabled
123 */
124 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
125 int enable_seek)
126 {
127 uint32_t sector;
128 int ret;
129
130 if (track > drv->max_track ||
131 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
132 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
133 head, track, sect, 1,
134 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
135 drv->max_track, drv->last_sect);
136 return 2;
137 }
138 if (sect > drv->last_sect) {
139 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
140 head, track, sect, 1,
141 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
142 drv->max_track, drv->last_sect);
143 return 3;
144 }
145 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
146 ret = 0;
147 if (sector != fd_sector(drv)) {
148 #if 0
149 if (!enable_seek) {
150 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
151 head, track, sect, 1, drv->max_track, drv->last_sect);
152 return 4;
153 }
154 #endif
155 drv->head = head;
156 if (drv->track != track)
157 ret = 1;
158 drv->track = track;
159 drv->sect = sect;
160 }
161
162 return ret;
163 }
164
165 /* Set drive back to track 0 */
166 static void fd_recalibrate(FDrive *drv)
167 {
168 FLOPPY_DPRINTF("recalibrate\n");
169 drv->head = 0;
170 drv->track = 0;
171 drv->sect = 1;
172 }
173
174 /* Revalidate a disk drive after a disk change */
175 static void fd_revalidate(FDrive *drv)
176 {
177 int nb_heads, max_track, last_sect, ro;
178 FDriveType drive;
179 FDriveRate rate;
180
181 FLOPPY_DPRINTF("revalidate\n");
182 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
183 ro = bdrv_is_read_only(drv->bs);
184 bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,
185 &last_sect, drv->drive, &drive, &rate);
186 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
187 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
188 nb_heads - 1, max_track, last_sect);
189 } else {
190 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,
191 max_track, last_sect, ro ? "ro" : "rw");
192 }
193 if (nb_heads == 1) {
194 drv->flags &= ~FDISK_DBL_SIDES;
195 } else {
196 drv->flags |= FDISK_DBL_SIDES;
197 }
198 drv->max_track = max_track;
199 drv->last_sect = last_sect;
200 drv->ro = ro;
201 drv->drive = drive;
202 drv->media_rate = rate;
203 } else {
204 FLOPPY_DPRINTF("No disk in drive\n");
205 drv->last_sect = 0;
206 drv->max_track = 0;
207 drv->flags &= ~FDISK_DBL_SIDES;
208 }
209 }
210
211 /********************************************************/
212 /* Intel 82078 floppy disk controller emulation */
213
214 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
215 static void fdctrl_reset_fifo(FDCtrl *fdctrl);
216 static int fdctrl_transfer_handler (void *opaque, int nchan,
217 int dma_pos, int dma_len);
218 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);
219 static FDrive *get_cur_drv(FDCtrl *fdctrl);
220
221 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
222 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
223 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
224 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
225 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
226 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
227 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
228 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
229 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
230 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
231 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
232 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
233
234 enum {
235 FD_DIR_WRITE = 0,
236 FD_DIR_READ = 1,
237 FD_DIR_SCANE = 2,
238 FD_DIR_SCANL = 3,
239 FD_DIR_SCANH = 4,
240 };
241
242 enum {
243 FD_STATE_MULTI = 0x01, /* multi track flag */
244 FD_STATE_FORMAT = 0x02, /* format flag */
245 FD_STATE_SEEK = 0x04, /* seek flag */
246 };
247
248 enum {
249 FD_REG_SRA = 0x00,
250 FD_REG_SRB = 0x01,
251 FD_REG_DOR = 0x02,
252 FD_REG_TDR = 0x03,
253 FD_REG_MSR = 0x04,
254 FD_REG_DSR = 0x04,
255 FD_REG_FIFO = 0x05,
256 FD_REG_DIR = 0x07,
257 FD_REG_CCR = 0x07,
258 };
259
260 enum {
261 FD_CMD_READ_TRACK = 0x02,
262 FD_CMD_SPECIFY = 0x03,
263 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
264 FD_CMD_WRITE = 0x05,
265 FD_CMD_READ = 0x06,
266 FD_CMD_RECALIBRATE = 0x07,
267 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
268 FD_CMD_WRITE_DELETED = 0x09,
269 FD_CMD_READ_ID = 0x0a,
270 FD_CMD_READ_DELETED = 0x0c,
271 FD_CMD_FORMAT_TRACK = 0x0d,
272 FD_CMD_DUMPREG = 0x0e,
273 FD_CMD_SEEK = 0x0f,
274 FD_CMD_VERSION = 0x10,
275 FD_CMD_SCAN_EQUAL = 0x11,
276 FD_CMD_PERPENDICULAR_MODE = 0x12,
277 FD_CMD_CONFIGURE = 0x13,
278 FD_CMD_LOCK = 0x14,
279 FD_CMD_VERIFY = 0x16,
280 FD_CMD_POWERDOWN_MODE = 0x17,
281 FD_CMD_PART_ID = 0x18,
282 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
283 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
284 FD_CMD_SAVE = 0x2e,
285 FD_CMD_OPTION = 0x33,
286 FD_CMD_RESTORE = 0x4e,
287 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
288 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
289 FD_CMD_FORMAT_AND_WRITE = 0xcd,
290 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
291 };
292
293 enum {
294 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
295 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
296 FD_CONFIG_POLL = 0x10, /* Poll enabled */
297 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
298 FD_CONFIG_EIS = 0x40, /* No implied seeks */
299 };
300
301 enum {
302 FD_SR0_EQPMT = 0x10,
303 FD_SR0_SEEK = 0x20,
304 FD_SR0_ABNTERM = 0x40,
305 FD_SR0_INVCMD = 0x80,
306 FD_SR0_RDYCHG = 0xc0,
307 };
308
309 enum {
310 FD_SR1_MA = 0x01, /* Missing address mark */
311 FD_SR1_NW = 0x02, /* Not writable */
312 FD_SR1_EC = 0x80, /* End of cylinder */
313 };
314
315 enum {
316 FD_SR2_SNS = 0x04, /* Scan not satisfied */
317 FD_SR2_SEH = 0x08, /* Scan equal hit */
318 };
319
320 enum {
321 FD_SRA_DIR = 0x01,
322 FD_SRA_nWP = 0x02,
323 FD_SRA_nINDX = 0x04,
324 FD_SRA_HDSEL = 0x08,
325 FD_SRA_nTRK0 = 0x10,
326 FD_SRA_STEP = 0x20,
327 FD_SRA_nDRV2 = 0x40,
328 FD_SRA_INTPEND = 0x80,
329 };
330
331 enum {
332 FD_SRB_MTR0 = 0x01,
333 FD_SRB_MTR1 = 0x02,
334 FD_SRB_WGATE = 0x04,
335 FD_SRB_RDATA = 0x08,
336 FD_SRB_WDATA = 0x10,
337 FD_SRB_DR0 = 0x20,
338 };
339
340 enum {
341 #if MAX_FD == 4
342 FD_DOR_SELMASK = 0x03,
343 #else
344 FD_DOR_SELMASK = 0x01,
345 #endif
346 FD_DOR_nRESET = 0x04,
347 FD_DOR_DMAEN = 0x08,
348 FD_DOR_MOTEN0 = 0x10,
349 FD_DOR_MOTEN1 = 0x20,
350 FD_DOR_MOTEN2 = 0x40,
351 FD_DOR_MOTEN3 = 0x80,
352 };
353
354 enum {
355 #if MAX_FD == 4
356 FD_TDR_BOOTSEL = 0x0c,
357 #else
358 FD_TDR_BOOTSEL = 0x04,
359 #endif
360 };
361
362 enum {
363 FD_DSR_DRATEMASK= 0x03,
364 FD_DSR_PWRDOWN = 0x40,
365 FD_DSR_SWRESET = 0x80,
366 };
367
368 enum {
369 FD_MSR_DRV0BUSY = 0x01,
370 FD_MSR_DRV1BUSY = 0x02,
371 FD_MSR_DRV2BUSY = 0x04,
372 FD_MSR_DRV3BUSY = 0x08,
373 FD_MSR_CMDBUSY = 0x10,
374 FD_MSR_NONDMA = 0x20,
375 FD_MSR_DIO = 0x40,
376 FD_MSR_RQM = 0x80,
377 };
378
379 enum {
380 FD_DIR_DSKCHG = 0x80,
381 };
382
383 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
384 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
385 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
386
387 struct FDCtrl {
388 MemoryRegion iomem;
389 qemu_irq irq;
390 /* Controller state */
391 QEMUTimer *result_timer;
392 int dma_chann;
393 /* Controller's identification */
394 uint8_t version;
395 /* HW */
396 uint8_t sra;
397 uint8_t srb;
398 uint8_t dor;
399 uint8_t dor_vmstate; /* only used as temp during vmstate */
400 uint8_t tdr;
401 uint8_t dsr;
402 uint8_t msr;
403 uint8_t cur_drv;
404 uint8_t status0;
405 uint8_t status1;
406 uint8_t status2;
407 /* Command FIFO */
408 uint8_t *fifo;
409 int32_t fifo_size;
410 uint32_t data_pos;
411 uint32_t data_len;
412 uint8_t data_state;
413 uint8_t data_dir;
414 uint8_t eot; /* last wanted sector */
415 /* States kept only to be returned back */
416 /* precompensation */
417 uint8_t precomp_trk;
418 uint8_t config;
419 uint8_t lock;
420 /* Power down config (also with status regB access mode */
421 uint8_t pwrd;
422 /* Floppy drives */
423 uint8_t num_floppies;
424 /* Sun4m quirks? */
425 int sun4m;
426 FDrive drives[MAX_FD];
427 int reset_sensei;
428 uint32_t check_media_rate;
429 /* Timers state */
430 uint8_t timer0;
431 uint8_t timer1;
432 };
433
434 typedef struct FDCtrlSysBus {
435 SysBusDevice busdev;
436 struct FDCtrl state;
437 } FDCtrlSysBus;
438
439 typedef struct FDCtrlISABus {
440 ISADevice busdev;
441 struct FDCtrl state;
442 int32_t bootindexA;
443 int32_t bootindexB;
444 } FDCtrlISABus;
445
446 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
447 {
448 FDCtrl *fdctrl = opaque;
449 uint32_t retval;
450
451 reg &= 7;
452 switch (reg) {
453 case FD_REG_SRA:
454 retval = fdctrl_read_statusA(fdctrl);
455 break;
456 case FD_REG_SRB:
457 retval = fdctrl_read_statusB(fdctrl);
458 break;
459 case FD_REG_DOR:
460 retval = fdctrl_read_dor(fdctrl);
461 break;
462 case FD_REG_TDR:
463 retval = fdctrl_read_tape(fdctrl);
464 break;
465 case FD_REG_MSR:
466 retval = fdctrl_read_main_status(fdctrl);
467 break;
468 case FD_REG_FIFO:
469 retval = fdctrl_read_data(fdctrl);
470 break;
471 case FD_REG_DIR:
472 retval = fdctrl_read_dir(fdctrl);
473 break;
474 default:
475 retval = (uint32_t)(-1);
476 break;
477 }
478 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
479
480 return retval;
481 }
482
483 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
484 {
485 FDCtrl *fdctrl = opaque;
486
487 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
488
489 reg &= 7;
490 switch (reg) {
491 case FD_REG_DOR:
492 fdctrl_write_dor(fdctrl, value);
493 break;
494 case FD_REG_TDR:
495 fdctrl_write_tape(fdctrl, value);
496 break;
497 case FD_REG_DSR:
498 fdctrl_write_rate(fdctrl, value);
499 break;
500 case FD_REG_FIFO:
501 fdctrl_write_data(fdctrl, value);
502 break;
503 case FD_REG_CCR:
504 fdctrl_write_ccr(fdctrl, value);
505 break;
506 default:
507 break;
508 }
509 }
510
511 static uint64_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg,
512 unsigned ize)
513 {
514 return fdctrl_read(opaque, (uint32_t)reg);
515 }
516
517 static void fdctrl_write_mem (void *opaque, target_phys_addr_t reg,
518 uint64_t value, unsigned size)
519 {
520 fdctrl_write(opaque, (uint32_t)reg, value);
521 }
522
523 static const MemoryRegionOps fdctrl_mem_ops = {
524 .read = fdctrl_read_mem,
525 .write = fdctrl_write_mem,
526 .endianness = DEVICE_NATIVE_ENDIAN,
527 };
528
529 static const MemoryRegionOps fdctrl_mem_strict_ops = {
530 .read = fdctrl_read_mem,
531 .write = fdctrl_write_mem,
532 .endianness = DEVICE_NATIVE_ENDIAN,
533 .valid = {
534 .min_access_size = 1,
535 .max_access_size = 1,
536 },
537 };
538
539 static bool fdrive_media_changed_needed(void *opaque)
540 {
541 FDrive *drive = opaque;
542
543 return (drive->bs != NULL && drive->media_changed != 1);
544 }
545
546 static const VMStateDescription vmstate_fdrive_media_changed = {
547 .name = "fdrive/media_changed",
548 .version_id = 1,
549 .minimum_version_id = 1,
550 .minimum_version_id_old = 1,
551 .fields = (VMStateField[]) {
552 VMSTATE_UINT8(media_changed, FDrive),
553 VMSTATE_END_OF_LIST()
554 }
555 };
556
557 static bool fdrive_media_rate_needed(void *opaque)
558 {
559 FDrive *drive = opaque;
560
561 return drive->fdctrl->check_media_rate;
562 }
563
564 static const VMStateDescription vmstate_fdrive_media_rate = {
565 .name = "fdrive/media_rate",
566 .version_id = 1,
567 .minimum_version_id = 1,
568 .minimum_version_id_old = 1,
569 .fields = (VMStateField[]) {
570 VMSTATE_UINT8(media_rate, FDrive),
571 VMSTATE_END_OF_LIST()
572 }
573 };
574
575 static const VMStateDescription vmstate_fdrive = {
576 .name = "fdrive",
577 .version_id = 1,
578 .minimum_version_id = 1,
579 .minimum_version_id_old = 1,
580 .fields = (VMStateField[]) {
581 VMSTATE_UINT8(head, FDrive),
582 VMSTATE_UINT8(track, FDrive),
583 VMSTATE_UINT8(sect, FDrive),
584 VMSTATE_END_OF_LIST()
585 },
586 .subsections = (VMStateSubsection[]) {
587 {
588 .vmsd = &vmstate_fdrive_media_changed,
589 .needed = &fdrive_media_changed_needed,
590 } , {
591 .vmsd = &vmstate_fdrive_media_rate,
592 .needed = &fdrive_media_rate_needed,
593 } , {
594 /* empty */
595 }
596 }
597 };
598
599 static void fdc_pre_save(void *opaque)
600 {
601 FDCtrl *s = opaque;
602
603 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
604 }
605
606 static int fdc_post_load(void *opaque, int version_id)
607 {
608 FDCtrl *s = opaque;
609
610 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
611 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
612 return 0;
613 }
614
615 static const VMStateDescription vmstate_fdc = {
616 .name = "fdc",
617 .version_id = 2,
618 .minimum_version_id = 2,
619 .minimum_version_id_old = 2,
620 .pre_save = fdc_pre_save,
621 .post_load = fdc_post_load,
622 .fields = (VMStateField []) {
623 /* Controller State */
624 VMSTATE_UINT8(sra, FDCtrl),
625 VMSTATE_UINT8(srb, FDCtrl),
626 VMSTATE_UINT8(dor_vmstate, FDCtrl),
627 VMSTATE_UINT8(tdr, FDCtrl),
628 VMSTATE_UINT8(dsr, FDCtrl),
629 VMSTATE_UINT8(msr, FDCtrl),
630 VMSTATE_UINT8(status0, FDCtrl),
631 VMSTATE_UINT8(status1, FDCtrl),
632 VMSTATE_UINT8(status2, FDCtrl),
633 /* Command FIFO */
634 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
635 uint8_t),
636 VMSTATE_UINT32(data_pos, FDCtrl),
637 VMSTATE_UINT32(data_len, FDCtrl),
638 VMSTATE_UINT8(data_state, FDCtrl),
639 VMSTATE_UINT8(data_dir, FDCtrl),
640 VMSTATE_UINT8(eot, FDCtrl),
641 /* States kept only to be returned back */
642 VMSTATE_UINT8(timer0, FDCtrl),
643 VMSTATE_UINT8(timer1, FDCtrl),
644 VMSTATE_UINT8(precomp_trk, FDCtrl),
645 VMSTATE_UINT8(config, FDCtrl),
646 VMSTATE_UINT8(lock, FDCtrl),
647 VMSTATE_UINT8(pwrd, FDCtrl),
648 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),
649 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
650 vmstate_fdrive, FDrive),
651 VMSTATE_END_OF_LIST()
652 }
653 };
654
655 static void fdctrl_external_reset_sysbus(DeviceState *d)
656 {
657 FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);
658 FDCtrl *s = &sys->state;
659
660 fdctrl_reset(s, 0);
661 }
662
663 static void fdctrl_external_reset_isa(DeviceState *d)
664 {
665 FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);
666 FDCtrl *s = &isa->state;
667
668 fdctrl_reset(s, 0);
669 }
670
671 static void fdctrl_handle_tc(void *opaque, int irq, int level)
672 {
673 //FDCtrl *s = opaque;
674
675 if (level) {
676 // XXX
677 FLOPPY_DPRINTF("TC pulsed\n");
678 }
679 }
680
681 /* Change IRQ state */
682 static void fdctrl_reset_irq(FDCtrl *fdctrl)
683 {
684 if (!(fdctrl->sra & FD_SRA_INTPEND))
685 return;
686 FLOPPY_DPRINTF("Reset interrupt\n");
687 qemu_set_irq(fdctrl->irq, 0);
688 fdctrl->sra &= ~FD_SRA_INTPEND;
689 }
690
691 static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)
692 {
693 /* Sparc mutation */
694 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
695 /* XXX: not sure */
696 fdctrl->msr &= ~FD_MSR_CMDBUSY;
697 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
698 fdctrl->status0 = status0;
699 return;
700 }
701 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
702 qemu_set_irq(fdctrl->irq, 1);
703 fdctrl->sra |= FD_SRA_INTPEND;
704 }
705 fdctrl->reset_sensei = 0;
706 fdctrl->status0 = status0;
707 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
708 }
709
710 /* Reset controller */
711 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
712 {
713 int i;
714
715 FLOPPY_DPRINTF("reset controller\n");
716 fdctrl_reset_irq(fdctrl);
717 /* Initialise controller */
718 fdctrl->sra = 0;
719 fdctrl->srb = 0xc0;
720 if (!fdctrl->drives[1].bs)
721 fdctrl->sra |= FD_SRA_nDRV2;
722 fdctrl->cur_drv = 0;
723 fdctrl->dor = FD_DOR_nRESET;
724 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
725 fdctrl->msr = FD_MSR_RQM;
726 /* FIFO state */
727 fdctrl->data_pos = 0;
728 fdctrl->data_len = 0;
729 fdctrl->data_state = 0;
730 fdctrl->data_dir = FD_DIR_WRITE;
731 for (i = 0; i < MAX_FD; i++)
732 fd_recalibrate(&fdctrl->drives[i]);
733 fdctrl_reset_fifo(fdctrl);
734 if (do_irq) {
735 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
736 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
737 }
738 }
739
740 static inline FDrive *drv0(FDCtrl *fdctrl)
741 {
742 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
743 }
744
745 static inline FDrive *drv1(FDCtrl *fdctrl)
746 {
747 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
748 return &fdctrl->drives[1];
749 else
750 return &fdctrl->drives[0];
751 }
752
753 #if MAX_FD == 4
754 static inline FDrive *drv2(FDCtrl *fdctrl)
755 {
756 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
757 return &fdctrl->drives[2];
758 else
759 return &fdctrl->drives[1];
760 }
761
762 static inline FDrive *drv3(FDCtrl *fdctrl)
763 {
764 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
765 return &fdctrl->drives[3];
766 else
767 return &fdctrl->drives[2];
768 }
769 #endif
770
771 static FDrive *get_cur_drv(FDCtrl *fdctrl)
772 {
773 switch (fdctrl->cur_drv) {
774 case 0: return drv0(fdctrl);
775 case 1: return drv1(fdctrl);
776 #if MAX_FD == 4
777 case 2: return drv2(fdctrl);
778 case 3: return drv3(fdctrl);
779 #endif
780 default: return NULL;
781 }
782 }
783
784 /* Status A register : 0x00 (read-only) */
785 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
786 {
787 uint32_t retval = fdctrl->sra;
788
789 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
790
791 return retval;
792 }
793
794 /* Status B register : 0x01 (read-only) */
795 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
796 {
797 uint32_t retval = fdctrl->srb;
798
799 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
800
801 return retval;
802 }
803
804 /* Digital output register : 0x02 */
805 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
806 {
807 uint32_t retval = fdctrl->dor;
808
809 /* Selected drive */
810 retval |= fdctrl->cur_drv;
811 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
812
813 return retval;
814 }
815
816 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
817 {
818 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
819
820 /* Motors */
821 if (value & FD_DOR_MOTEN0)
822 fdctrl->srb |= FD_SRB_MTR0;
823 else
824 fdctrl->srb &= ~FD_SRB_MTR0;
825 if (value & FD_DOR_MOTEN1)
826 fdctrl->srb |= FD_SRB_MTR1;
827 else
828 fdctrl->srb &= ~FD_SRB_MTR1;
829
830 /* Drive */
831 if (value & 1)
832 fdctrl->srb |= FD_SRB_DR0;
833 else
834 fdctrl->srb &= ~FD_SRB_DR0;
835
836 /* Reset */
837 if (!(value & FD_DOR_nRESET)) {
838 if (fdctrl->dor & FD_DOR_nRESET) {
839 FLOPPY_DPRINTF("controller enter RESET state\n");
840 }
841 } else {
842 if (!(fdctrl->dor & FD_DOR_nRESET)) {
843 FLOPPY_DPRINTF("controller out of RESET state\n");
844 fdctrl_reset(fdctrl, 1);
845 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
846 }
847 }
848 /* Selected drive */
849 fdctrl->cur_drv = value & FD_DOR_SELMASK;
850
851 fdctrl->dor = value;
852 }
853
854 /* Tape drive register : 0x03 */
855 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
856 {
857 uint32_t retval = fdctrl->tdr;
858
859 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
860
861 return retval;
862 }
863
864 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
865 {
866 /* Reset mode */
867 if (!(fdctrl->dor & FD_DOR_nRESET)) {
868 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
869 return;
870 }
871 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
872 /* Disk boot selection indicator */
873 fdctrl->tdr = value & FD_TDR_BOOTSEL;
874 /* Tape indicators: never allow */
875 }
876
877 /* Main status register : 0x04 (read) */
878 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
879 {
880 uint32_t retval = fdctrl->msr;
881
882 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
883 fdctrl->dor |= FD_DOR_nRESET;
884
885 /* Sparc mutation */
886 if (fdctrl->sun4m) {
887 retval |= FD_MSR_DIO;
888 fdctrl_reset_irq(fdctrl);
889 };
890
891 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
892
893 return retval;
894 }
895
896 /* Data select rate register : 0x04 (write) */
897 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
898 {
899 /* Reset mode */
900 if (!(fdctrl->dor & FD_DOR_nRESET)) {
901 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
902 return;
903 }
904 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
905 /* Reset: autoclear */
906 if (value & FD_DSR_SWRESET) {
907 fdctrl->dor &= ~FD_DOR_nRESET;
908 fdctrl_reset(fdctrl, 1);
909 fdctrl->dor |= FD_DOR_nRESET;
910 }
911 if (value & FD_DSR_PWRDOWN) {
912 fdctrl_reset(fdctrl, 1);
913 }
914 fdctrl->dsr = value;
915 }
916
917 /* Configuration control register: 0x07 (write) */
918 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
919 {
920 /* Reset mode */
921 if (!(fdctrl->dor & FD_DOR_nRESET)) {
922 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
923 return;
924 }
925 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
926
927 /* Only the rate selection bits used in AT mode, and we
928 * store those in the DSR.
929 */
930 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
931 (value & FD_DSR_DRATEMASK);
932 }
933
934 static int fdctrl_media_changed(FDrive *drv)
935 {
936 int ret;
937
938 if (!drv->bs)
939 return 0;
940 if (drv->media_changed) {
941 drv->media_changed = 0;
942 ret = 1;
943 } else {
944 ret = bdrv_media_changed(drv->bs);
945 if (ret < 0) {
946 ret = 0; /* we don't know, assume no */
947 }
948 }
949 if (ret) {
950 fd_revalidate(drv);
951 }
952 return ret;
953 }
954
955 /* Digital input register : 0x07 (read-only) */
956 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
957 {
958 uint32_t retval = 0;
959
960 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
961 retval |= FD_DIR_DSKCHG;
962 }
963 if (retval != 0) {
964 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
965 }
966
967 return retval;
968 }
969
970 /* FIFO state control */
971 static void fdctrl_reset_fifo(FDCtrl *fdctrl)
972 {
973 fdctrl->data_dir = FD_DIR_WRITE;
974 fdctrl->data_pos = 0;
975 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
976 }
977
978 /* Set FIFO status for the host to read */
979 static void fdctrl_set_fifo(FDCtrl *fdctrl, int fifo_len, int do_irq)
980 {
981 fdctrl->data_dir = FD_DIR_READ;
982 fdctrl->data_len = fifo_len;
983 fdctrl->data_pos = 0;
984 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
985 if (do_irq)
986 fdctrl_raise_irq(fdctrl, 0x00);
987 }
988
989 /* Set an error: unimplemented/unknown command */
990 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
991 {
992 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
993 fdctrl->fifo[0] = FD_SR0_INVCMD;
994 fdctrl_set_fifo(fdctrl, 1, 0);
995 }
996
997 /* Seek to next sector */
998 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
999 {
1000 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1001 cur_drv->head, cur_drv->track, cur_drv->sect,
1002 fd_sector(cur_drv));
1003 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1004 error in fact */
1005 if (cur_drv->sect >= cur_drv->last_sect ||
1006 cur_drv->sect == fdctrl->eot) {
1007 cur_drv->sect = 1;
1008 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1009 if (cur_drv->head == 0 &&
1010 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1011 cur_drv->head = 1;
1012 } else {
1013 cur_drv->head = 0;
1014 cur_drv->track++;
1015 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1016 return 0;
1017 }
1018 } else {
1019 cur_drv->track++;
1020 return 0;
1021 }
1022 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1023 cur_drv->head, cur_drv->track,
1024 cur_drv->sect, fd_sector(cur_drv));
1025 } else {
1026 cur_drv->sect++;
1027 }
1028 return 1;
1029 }
1030
1031 /* Callback for transfer end (stop or abort) */
1032 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1033 uint8_t status1, uint8_t status2)
1034 {
1035 FDrive *cur_drv;
1036
1037 cur_drv = get_cur_drv(fdctrl);
1038 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1039 status0, status1, status2,
1040 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1041 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1042 fdctrl->fifo[1] = status1;
1043 fdctrl->fifo[2] = status2;
1044 fdctrl->fifo[3] = cur_drv->track;
1045 fdctrl->fifo[4] = cur_drv->head;
1046 fdctrl->fifo[5] = cur_drv->sect;
1047 fdctrl->fifo[6] = FD_SECTOR_SC;
1048 fdctrl->data_dir = FD_DIR_READ;
1049 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1050 DMA_release_DREQ(fdctrl->dma_chann);
1051 }
1052 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1053 fdctrl->msr &= ~FD_MSR_NONDMA;
1054 fdctrl_set_fifo(fdctrl, 7, 1);
1055 }
1056
1057 /* Prepare a data transfer (either DMA or FIFO) */
1058 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1059 {
1060 FDrive *cur_drv;
1061 uint8_t kh, kt, ks;
1062 int did_seek = 0;
1063
1064 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1065 cur_drv = get_cur_drv(fdctrl);
1066 kt = fdctrl->fifo[2];
1067 kh = fdctrl->fifo[3];
1068 ks = fdctrl->fifo[4];
1069 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1070 GET_CUR_DRV(fdctrl), kh, kt, ks,
1071 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1072 NUM_SIDES(cur_drv)));
1073 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1074 case 2:
1075 /* sect too big */
1076 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1077 fdctrl->fifo[3] = kt;
1078 fdctrl->fifo[4] = kh;
1079 fdctrl->fifo[5] = ks;
1080 return;
1081 case 3:
1082 /* track too big */
1083 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1084 fdctrl->fifo[3] = kt;
1085 fdctrl->fifo[4] = kh;
1086 fdctrl->fifo[5] = ks;
1087 return;
1088 case 4:
1089 /* No seek enabled */
1090 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1091 fdctrl->fifo[3] = kt;
1092 fdctrl->fifo[4] = kh;
1093 fdctrl->fifo[5] = ks;
1094 return;
1095 case 1:
1096 did_seek = 1;
1097 break;
1098 default:
1099 break;
1100 }
1101
1102 /* Check the data rate. If the programmed data rate does not match
1103 * the currently inserted medium, the operation has to fail. */
1104 if (fdctrl->check_media_rate &&
1105 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1106 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1107 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1108 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1109 fdctrl->fifo[3] = kt;
1110 fdctrl->fifo[4] = kh;
1111 fdctrl->fifo[5] = ks;
1112 return;
1113 }
1114
1115 /* Set the FIFO state */
1116 fdctrl->data_dir = direction;
1117 fdctrl->data_pos = 0;
1118 fdctrl->msr |= FD_MSR_CMDBUSY;
1119 if (fdctrl->fifo[0] & 0x80)
1120 fdctrl->data_state |= FD_STATE_MULTI;
1121 else
1122 fdctrl->data_state &= ~FD_STATE_MULTI;
1123 if (did_seek)
1124 fdctrl->data_state |= FD_STATE_SEEK;
1125 else
1126 fdctrl->data_state &= ~FD_STATE_SEEK;
1127 if (fdctrl->fifo[5] == 00) {
1128 fdctrl->data_len = fdctrl->fifo[8];
1129 } else {
1130 int tmp;
1131 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1132 tmp = (fdctrl->fifo[6] - ks + 1);
1133 if (fdctrl->fifo[0] & 0x80)
1134 tmp += fdctrl->fifo[6];
1135 fdctrl->data_len *= tmp;
1136 }
1137 fdctrl->eot = fdctrl->fifo[6];
1138 if (fdctrl->dor & FD_DOR_DMAEN) {
1139 int dma_mode;
1140 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1141 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1142 dma_mode = (dma_mode >> 2) & 3;
1143 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1144 dma_mode, direction,
1145 (128 << fdctrl->fifo[5]) *
1146 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1147 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1148 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1149 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1150 (direction == FD_DIR_READ && dma_mode == 1)) {
1151 /* No access is allowed until DMA transfer has completed */
1152 fdctrl->msr &= ~FD_MSR_RQM;
1153 /* Now, we just have to wait for the DMA controller to
1154 * recall us...
1155 */
1156 DMA_hold_DREQ(fdctrl->dma_chann);
1157 DMA_schedule(fdctrl->dma_chann);
1158 return;
1159 } else {
1160 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1161 }
1162 }
1163 FLOPPY_DPRINTF("start non-DMA transfer\n");
1164 fdctrl->msr |= FD_MSR_NONDMA;
1165 if (direction != FD_DIR_WRITE)
1166 fdctrl->msr |= FD_MSR_DIO;
1167 /* IO based transfer: calculate len */
1168 fdctrl_raise_irq(fdctrl, 0x00);
1169
1170 return;
1171 }
1172
1173 /* Prepare a transfer of deleted data */
1174 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1175 {
1176 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1177
1178 /* We don't handle deleted data,
1179 * so we don't return *ANYTHING*
1180 */
1181 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1182 }
1183
1184 /* handlers for DMA transfers */
1185 static int fdctrl_transfer_handler (void *opaque, int nchan,
1186 int dma_pos, int dma_len)
1187 {
1188 FDCtrl *fdctrl;
1189 FDrive *cur_drv;
1190 int len, start_pos, rel_pos;
1191 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1192
1193 fdctrl = opaque;
1194 if (fdctrl->msr & FD_MSR_RQM) {
1195 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1196 return 0;
1197 }
1198 cur_drv = get_cur_drv(fdctrl);
1199 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1200 fdctrl->data_dir == FD_DIR_SCANH)
1201 status2 = FD_SR2_SNS;
1202 if (dma_len > fdctrl->data_len)
1203 dma_len = fdctrl->data_len;
1204 if (cur_drv->bs == NULL) {
1205 if (fdctrl->data_dir == FD_DIR_WRITE)
1206 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1207 else
1208 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1209 len = 0;
1210 goto transfer_error;
1211 }
1212 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1213 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1214 len = dma_len - fdctrl->data_pos;
1215 if (len + rel_pos > FD_SECTOR_LEN)
1216 len = FD_SECTOR_LEN - rel_pos;
1217 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1218 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1219 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1220 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1221 fd_sector(cur_drv) * FD_SECTOR_LEN);
1222 if (fdctrl->data_dir != FD_DIR_WRITE ||
1223 len < FD_SECTOR_LEN || rel_pos != 0) {
1224 /* READ & SCAN commands and realign to a sector for WRITE */
1225 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1226 fdctrl->fifo, 1) < 0) {
1227 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1228 fd_sector(cur_drv));
1229 /* Sure, image size is too small... */
1230 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1231 }
1232 }
1233 switch (fdctrl->data_dir) {
1234 case FD_DIR_READ:
1235 /* READ commands */
1236 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1237 fdctrl->data_pos, len);
1238 break;
1239 case FD_DIR_WRITE:
1240 /* WRITE commands */
1241 if (cur_drv->ro) {
1242 /* Handle readonly medium early, no need to do DMA, touch the
1243 * LED or attempt any writes. A real floppy doesn't attempt
1244 * to write to readonly media either. */
1245 fdctrl_stop_transfer(fdctrl,
1246 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1247 0x00);
1248 goto transfer_error;
1249 }
1250
1251 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1252 fdctrl->data_pos, len);
1253 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1254 fdctrl->fifo, 1) < 0) {
1255 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1256 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1257 goto transfer_error;
1258 }
1259 break;
1260 default:
1261 /* SCAN commands */
1262 {
1263 uint8_t tmpbuf[FD_SECTOR_LEN];
1264 int ret;
1265 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1266 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1267 if (ret == 0) {
1268 status2 = FD_SR2_SEH;
1269 goto end_transfer;
1270 }
1271 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1272 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1273 status2 = 0x00;
1274 goto end_transfer;
1275 }
1276 }
1277 break;
1278 }
1279 fdctrl->data_pos += len;
1280 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1281 if (rel_pos == 0) {
1282 /* Seek to next sector */
1283 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1284 break;
1285 }
1286 }
1287 end_transfer:
1288 len = fdctrl->data_pos - start_pos;
1289 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1290 fdctrl->data_pos, len, fdctrl->data_len);
1291 if (fdctrl->data_dir == FD_DIR_SCANE ||
1292 fdctrl->data_dir == FD_DIR_SCANL ||
1293 fdctrl->data_dir == FD_DIR_SCANH)
1294 status2 = FD_SR2_SEH;
1295 if (FD_DID_SEEK(fdctrl->data_state))
1296 status0 |= FD_SR0_SEEK;
1297 fdctrl->data_len -= len;
1298 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1299 transfer_error:
1300
1301 return len;
1302 }
1303
1304 /* Data register : 0x05 */
1305 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1306 {
1307 FDrive *cur_drv;
1308 uint32_t retval = 0;
1309 int pos;
1310
1311 cur_drv = get_cur_drv(fdctrl);
1312 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1313 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1314 FLOPPY_ERROR("controller not ready for reading\n");
1315 return 0;
1316 }
1317 pos = fdctrl->data_pos;
1318 if (fdctrl->msr & FD_MSR_NONDMA) {
1319 pos %= FD_SECTOR_LEN;
1320 if (pos == 0) {
1321 if (fdctrl->data_pos != 0)
1322 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1323 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1324 fd_sector(cur_drv));
1325 return 0;
1326 }
1327 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1328 FLOPPY_DPRINTF("error getting sector %d\n",
1329 fd_sector(cur_drv));
1330 /* Sure, image size is too small... */
1331 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1332 }
1333 }
1334 }
1335 retval = fdctrl->fifo[pos];
1336 if (++fdctrl->data_pos == fdctrl->data_len) {
1337 fdctrl->data_pos = 0;
1338 /* Switch from transfer mode to status mode
1339 * then from status mode to command mode
1340 */
1341 if (fdctrl->msr & FD_MSR_NONDMA) {
1342 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1343 } else {
1344 fdctrl_reset_fifo(fdctrl);
1345 fdctrl_reset_irq(fdctrl);
1346 }
1347 }
1348 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1349
1350 return retval;
1351 }
1352
1353 static void fdctrl_format_sector(FDCtrl *fdctrl)
1354 {
1355 FDrive *cur_drv;
1356 uint8_t kh, kt, ks;
1357
1358 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1359 cur_drv = get_cur_drv(fdctrl);
1360 kt = fdctrl->fifo[6];
1361 kh = fdctrl->fifo[7];
1362 ks = fdctrl->fifo[8];
1363 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1364 GET_CUR_DRV(fdctrl), kh, kt, ks,
1365 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1366 NUM_SIDES(cur_drv)));
1367 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1368 case 2:
1369 /* sect too big */
1370 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1371 fdctrl->fifo[3] = kt;
1372 fdctrl->fifo[4] = kh;
1373 fdctrl->fifo[5] = ks;
1374 return;
1375 case 3:
1376 /* track too big */
1377 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1378 fdctrl->fifo[3] = kt;
1379 fdctrl->fifo[4] = kh;
1380 fdctrl->fifo[5] = ks;
1381 return;
1382 case 4:
1383 /* No seek enabled */
1384 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1385 fdctrl->fifo[3] = kt;
1386 fdctrl->fifo[4] = kh;
1387 fdctrl->fifo[5] = ks;
1388 return;
1389 case 1:
1390 fdctrl->data_state |= FD_STATE_SEEK;
1391 break;
1392 default:
1393 break;
1394 }
1395 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1396 if (cur_drv->bs == NULL ||
1397 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1398 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1399 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1400 } else {
1401 if (cur_drv->sect == cur_drv->last_sect) {
1402 fdctrl->data_state &= ~FD_STATE_FORMAT;
1403 /* Last sector done */
1404 if (FD_DID_SEEK(fdctrl->data_state))
1405 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1406 else
1407 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1408 } else {
1409 /* More to do */
1410 fdctrl->data_pos = 0;
1411 fdctrl->data_len = 4;
1412 }
1413 }
1414 }
1415
1416 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
1417 {
1418 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1419 fdctrl->fifo[0] = fdctrl->lock << 4;
1420 fdctrl_set_fifo(fdctrl, 1, 0);
1421 }
1422
1423 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
1424 {
1425 FDrive *cur_drv = get_cur_drv(fdctrl);
1426
1427 /* Drives position */
1428 fdctrl->fifo[0] = drv0(fdctrl)->track;
1429 fdctrl->fifo[1] = drv1(fdctrl)->track;
1430 #if MAX_FD == 4
1431 fdctrl->fifo[2] = drv2(fdctrl)->track;
1432 fdctrl->fifo[3] = drv3(fdctrl)->track;
1433 #else
1434 fdctrl->fifo[2] = 0;
1435 fdctrl->fifo[3] = 0;
1436 #endif
1437 /* timers */
1438 fdctrl->fifo[4] = fdctrl->timer0;
1439 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1440 fdctrl->fifo[6] = cur_drv->last_sect;
1441 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1442 (cur_drv->perpendicular << 2);
1443 fdctrl->fifo[8] = fdctrl->config;
1444 fdctrl->fifo[9] = fdctrl->precomp_trk;
1445 fdctrl_set_fifo(fdctrl, 10, 0);
1446 }
1447
1448 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
1449 {
1450 /* Controller's version */
1451 fdctrl->fifo[0] = fdctrl->version;
1452 fdctrl_set_fifo(fdctrl, 1, 0);
1453 }
1454
1455 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
1456 {
1457 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1458 fdctrl_set_fifo(fdctrl, 1, 0);
1459 }
1460
1461 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
1462 {
1463 FDrive *cur_drv = get_cur_drv(fdctrl);
1464
1465 /* Drives position */
1466 drv0(fdctrl)->track = fdctrl->fifo[3];
1467 drv1(fdctrl)->track = fdctrl->fifo[4];
1468 #if MAX_FD == 4
1469 drv2(fdctrl)->track = fdctrl->fifo[5];
1470 drv3(fdctrl)->track = fdctrl->fifo[6];
1471 #endif
1472 /* timers */
1473 fdctrl->timer0 = fdctrl->fifo[7];
1474 fdctrl->timer1 = fdctrl->fifo[8];
1475 cur_drv->last_sect = fdctrl->fifo[9];
1476 fdctrl->lock = fdctrl->fifo[10] >> 7;
1477 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1478 fdctrl->config = fdctrl->fifo[11];
1479 fdctrl->precomp_trk = fdctrl->fifo[12];
1480 fdctrl->pwrd = fdctrl->fifo[13];
1481 fdctrl_reset_fifo(fdctrl);
1482 }
1483
1484 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
1485 {
1486 FDrive *cur_drv = get_cur_drv(fdctrl);
1487
1488 fdctrl->fifo[0] = 0;
1489 fdctrl->fifo[1] = 0;
1490 /* Drives position */
1491 fdctrl->fifo[2] = drv0(fdctrl)->track;
1492 fdctrl->fifo[3] = drv1(fdctrl)->track;
1493 #if MAX_FD == 4
1494 fdctrl->fifo[4] = drv2(fdctrl)->track;
1495 fdctrl->fifo[5] = drv3(fdctrl)->track;
1496 #else
1497 fdctrl->fifo[4] = 0;
1498 fdctrl->fifo[5] = 0;
1499 #endif
1500 /* timers */
1501 fdctrl->fifo[6] = fdctrl->timer0;
1502 fdctrl->fifo[7] = fdctrl->timer1;
1503 fdctrl->fifo[8] = cur_drv->last_sect;
1504 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1505 (cur_drv->perpendicular << 2);
1506 fdctrl->fifo[10] = fdctrl->config;
1507 fdctrl->fifo[11] = fdctrl->precomp_trk;
1508 fdctrl->fifo[12] = fdctrl->pwrd;
1509 fdctrl->fifo[13] = 0;
1510 fdctrl->fifo[14] = 0;
1511 fdctrl_set_fifo(fdctrl, 15, 0);
1512 }
1513
1514 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
1515 {
1516 FDrive *cur_drv = get_cur_drv(fdctrl);
1517
1518 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1519 qemu_mod_timer(fdctrl->result_timer,
1520 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 50));
1521 }
1522
1523 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
1524 {
1525 FDrive *cur_drv;
1526
1527 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1528 cur_drv = get_cur_drv(fdctrl);
1529 fdctrl->data_state |= FD_STATE_FORMAT;
1530 if (fdctrl->fifo[0] & 0x80)
1531 fdctrl->data_state |= FD_STATE_MULTI;
1532 else
1533 fdctrl->data_state &= ~FD_STATE_MULTI;
1534 fdctrl->data_state &= ~FD_STATE_SEEK;
1535 cur_drv->bps =
1536 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1537 #if 0
1538 cur_drv->last_sect =
1539 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1540 fdctrl->fifo[3] / 2;
1541 #else
1542 cur_drv->last_sect = fdctrl->fifo[3];
1543 #endif
1544 /* TODO: implement format using DMA expected by the Bochs BIOS
1545 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1546 * the sector with the specified fill byte
1547 */
1548 fdctrl->data_state &= ~FD_STATE_FORMAT;
1549 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1550 }
1551
1552 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
1553 {
1554 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1555 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1556 if (fdctrl->fifo[2] & 1)
1557 fdctrl->dor &= ~FD_DOR_DMAEN;
1558 else
1559 fdctrl->dor |= FD_DOR_DMAEN;
1560 /* No result back */
1561 fdctrl_reset_fifo(fdctrl);
1562 }
1563
1564 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
1565 {
1566 FDrive *cur_drv;
1567
1568 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1569 cur_drv = get_cur_drv(fdctrl);
1570 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1571 /* 1 Byte status back */
1572 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1573 (cur_drv->track == 0 ? 0x10 : 0x00) |
1574 (cur_drv->head << 2) |
1575 GET_CUR_DRV(fdctrl) |
1576 0x28;
1577 fdctrl_set_fifo(fdctrl, 1, 0);
1578 }
1579
1580 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
1581 {
1582 FDrive *cur_drv;
1583
1584 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1585 cur_drv = get_cur_drv(fdctrl);
1586 fd_recalibrate(cur_drv);
1587 fdctrl_reset_fifo(fdctrl);
1588 /* Raise Interrupt */
1589 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1590 }
1591
1592 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
1593 {
1594 FDrive *cur_drv = get_cur_drv(fdctrl);
1595
1596 if(fdctrl->reset_sensei > 0) {
1597 fdctrl->fifo[0] =
1598 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1599 fdctrl->reset_sensei--;
1600 } else {
1601 /* XXX: status0 handling is broken for read/write
1602 commands, so we do this hack. It should be suppressed
1603 ASAP */
1604 fdctrl->fifo[0] =
1605 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1606 }
1607
1608 fdctrl->fifo[1] = cur_drv->track;
1609 fdctrl_set_fifo(fdctrl, 2, 0);
1610 fdctrl_reset_irq(fdctrl);
1611 fdctrl->status0 = FD_SR0_RDYCHG;
1612 }
1613
1614 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
1615 {
1616 FDrive *cur_drv;
1617
1618 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1619 cur_drv = get_cur_drv(fdctrl);
1620 fdctrl_reset_fifo(fdctrl);
1621 /* The seek command just sends step pulses to the drive and doesn't care if
1622 * there is a medium inserted of if it's banging the head against the drive.
1623 */
1624 if (fdctrl->fifo[2] > cur_drv->max_track) {
1625 cur_drv->track = cur_drv->max_track;
1626 } else {
1627 cur_drv->track = fdctrl->fifo[2];
1628 }
1629 /* Raise Interrupt */
1630 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1631 }
1632
1633 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
1634 {
1635 FDrive *cur_drv = get_cur_drv(fdctrl);
1636
1637 if (fdctrl->fifo[1] & 0x80)
1638 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1639 /* No result back */
1640 fdctrl_reset_fifo(fdctrl);
1641 }
1642
1643 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
1644 {
1645 fdctrl->config = fdctrl->fifo[2];
1646 fdctrl->precomp_trk = fdctrl->fifo[3];
1647 /* No result back */
1648 fdctrl_reset_fifo(fdctrl);
1649 }
1650
1651 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
1652 {
1653 fdctrl->pwrd = fdctrl->fifo[1];
1654 fdctrl->fifo[0] = fdctrl->fifo[1];
1655 fdctrl_set_fifo(fdctrl, 1, 0);
1656 }
1657
1658 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
1659 {
1660 /* No result back */
1661 fdctrl_reset_fifo(fdctrl);
1662 }
1663
1664 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
1665 {
1666 FDrive *cur_drv = get_cur_drv(fdctrl);
1667
1668 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1669 /* Command parameters done */
1670 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1671 fdctrl->fifo[0] = fdctrl->fifo[1];
1672 fdctrl->fifo[2] = 0;
1673 fdctrl->fifo[3] = 0;
1674 fdctrl_set_fifo(fdctrl, 4, 0);
1675 } else {
1676 fdctrl_reset_fifo(fdctrl);
1677 }
1678 } else if (fdctrl->data_len > 7) {
1679 /* ERROR */
1680 fdctrl->fifo[0] = 0x80 |
1681 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1682 fdctrl_set_fifo(fdctrl, 1, 0);
1683 }
1684 }
1685
1686 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
1687 {
1688 FDrive *cur_drv;
1689
1690 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1691 cur_drv = get_cur_drv(fdctrl);
1692 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1693 cur_drv->track = cur_drv->max_track - 1;
1694 } else {
1695 cur_drv->track += fdctrl->fifo[2];
1696 }
1697 fdctrl_reset_fifo(fdctrl);
1698 /* Raise Interrupt */
1699 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1700 }
1701
1702 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
1703 {
1704 FDrive *cur_drv;
1705
1706 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1707 cur_drv = get_cur_drv(fdctrl);
1708 if (fdctrl->fifo[2] > cur_drv->track) {
1709 cur_drv->track = 0;
1710 } else {
1711 cur_drv->track -= fdctrl->fifo[2];
1712 }
1713 fdctrl_reset_fifo(fdctrl);
1714 /* Raise Interrupt */
1715 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1716 }
1717
1718 static const struct {
1719 uint8_t value;
1720 uint8_t mask;
1721 const char* name;
1722 int parameters;
1723 void (*handler)(FDCtrl *fdctrl, int direction);
1724 int direction;
1725 } handlers[] = {
1726 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1727 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1728 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1729 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1730 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1731 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1732 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1733 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1734 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1735 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1736 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1737 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1738 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1739 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1740 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1741 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1742 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1743 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1744 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1745 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1746 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1747 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1748 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1749 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1750 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1751 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1752 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1753 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1754 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1755 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1756 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1757 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1758 };
1759 /* Associate command to an index in the 'handlers' array */
1760 static uint8_t command_to_handler[256];
1761
1762 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
1763 {
1764 FDrive *cur_drv;
1765 int pos;
1766
1767 /* Reset mode */
1768 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1769 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1770 return;
1771 }
1772 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1773 FLOPPY_ERROR("controller not ready for writing\n");
1774 return;
1775 }
1776 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1777 /* Is it write command time ? */
1778 if (fdctrl->msr & FD_MSR_NONDMA) {
1779 /* FIFO data write */
1780 pos = fdctrl->data_pos++;
1781 pos %= FD_SECTOR_LEN;
1782 fdctrl->fifo[pos] = value;
1783 if (pos == FD_SECTOR_LEN - 1 ||
1784 fdctrl->data_pos == fdctrl->data_len) {
1785 cur_drv = get_cur_drv(fdctrl);
1786 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1787 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1788 return;
1789 }
1790 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1791 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1792 fd_sector(cur_drv));
1793 return;
1794 }
1795 }
1796 /* Switch from transfer mode to status mode
1797 * then from status mode to command mode
1798 */
1799 if (fdctrl->data_pos == fdctrl->data_len)
1800 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1801 return;
1802 }
1803 if (fdctrl->data_pos == 0) {
1804 /* Command */
1805 pos = command_to_handler[value & 0xff];
1806 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1807 fdctrl->data_len = handlers[pos].parameters + 1;
1808 fdctrl->msr |= FD_MSR_CMDBUSY;
1809 }
1810
1811 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1812 fdctrl->fifo[fdctrl->data_pos++] = value;
1813 if (fdctrl->data_pos == fdctrl->data_len) {
1814 /* We now have all parameters
1815 * and will be able to treat the command
1816 */
1817 if (fdctrl->data_state & FD_STATE_FORMAT) {
1818 fdctrl_format_sector(fdctrl);
1819 return;
1820 }
1821
1822 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1823 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1824 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1825 }
1826 }
1827
1828 static void fdctrl_result_timer(void *opaque)
1829 {
1830 FDCtrl *fdctrl = opaque;
1831 FDrive *cur_drv = get_cur_drv(fdctrl);
1832
1833 /* Pretend we are spinning.
1834 * This is needed for Coherent, which uses READ ID to check for
1835 * sector interleaving.
1836 */
1837 if (cur_drv->last_sect != 0) {
1838 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1839 }
1840 /* READ_ID can't automatically succeed! */
1841 if (fdctrl->check_media_rate &&
1842 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1843 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
1844 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1845 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1846 } else {
1847 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1848 }
1849 }
1850
1851 static void fdctrl_change_cb(void *opaque, bool load)
1852 {
1853 FDrive *drive = opaque;
1854
1855 drive->media_changed = 1;
1856 }
1857
1858 static const BlockDevOps fdctrl_block_ops = {
1859 .change_media_cb = fdctrl_change_cb,
1860 };
1861
1862 /* Init functions */
1863 static int fdctrl_connect_drives(FDCtrl *fdctrl)
1864 {
1865 unsigned int i;
1866 FDrive *drive;
1867
1868 for (i = 0; i < MAX_FD; i++) {
1869 drive = &fdctrl->drives[i];
1870 drive->fdctrl = fdctrl;
1871
1872 if (drive->bs) {
1873 if (bdrv_get_on_error(drive->bs, 0) != BLOCK_ERR_STOP_ENOSPC) {
1874 error_report("fdc doesn't support drive option werror");
1875 return -1;
1876 }
1877 if (bdrv_get_on_error(drive->bs, 1) != BLOCK_ERR_REPORT) {
1878 error_report("fdc doesn't support drive option rerror");
1879 return -1;
1880 }
1881 }
1882
1883 fd_init(drive);
1884 fd_revalidate(drive);
1885 if (drive->bs) {
1886 drive->media_changed = 1;
1887 bdrv_set_dev_ops(drive->bs, &fdctrl_block_ops, drive);
1888 }
1889 }
1890 return 0;
1891 }
1892
1893 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1894 target_phys_addr_t mmio_base, DriveInfo **fds)
1895 {
1896 FDCtrl *fdctrl;
1897 DeviceState *dev;
1898 FDCtrlSysBus *sys;
1899
1900 dev = qdev_create(NULL, "sysbus-fdc");
1901 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1902 fdctrl = &sys->state;
1903 fdctrl->dma_chann = dma_chann; /* FIXME */
1904 if (fds[0]) {
1905 qdev_prop_set_drive_nofail(dev, "driveA", fds[0]->bdrv);
1906 }
1907 if (fds[1]) {
1908 qdev_prop_set_drive_nofail(dev, "driveB", fds[1]->bdrv);
1909 }
1910 qdev_init_nofail(dev);
1911 sysbus_connect_irq(&sys->busdev, 0, irq);
1912 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1913 }
1914
1915 void sun4m_fdctrl_init(qemu_irq irq, target_phys_addr_t io_base,
1916 DriveInfo **fds, qemu_irq *fdc_tc)
1917 {
1918 DeviceState *dev;
1919 FDCtrlSysBus *sys;
1920
1921 dev = qdev_create(NULL, "SUNW,fdtwo");
1922 if (fds[0]) {
1923 qdev_prop_set_drive_nofail(dev, "drive", fds[0]->bdrv);
1924 }
1925 qdev_init_nofail(dev);
1926 sys = DO_UPCAST(FDCtrlSysBus, busdev.qdev, dev);
1927 sysbus_connect_irq(&sys->busdev, 0, irq);
1928 sysbus_mmio_map(&sys->busdev, 0, io_base);
1929 *fdc_tc = qdev_get_gpio_in(dev, 0);
1930 }
1931
1932 static int fdctrl_init_common(FDCtrl *fdctrl)
1933 {
1934 int i, j;
1935 static int command_tables_inited = 0;
1936
1937 /* Fill 'command_to_handler' lookup table */
1938 if (!command_tables_inited) {
1939 command_tables_inited = 1;
1940 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1941 for (j = 0; j < sizeof(command_to_handler); j++) {
1942 if ((j & handlers[i].mask) == handlers[i].value) {
1943 command_to_handler[j] = i;
1944 }
1945 }
1946 }
1947 }
1948
1949 FLOPPY_DPRINTF("init controller\n");
1950 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1951 fdctrl->fifo_size = 512;
1952 fdctrl->result_timer = qemu_new_timer_ns(vm_clock,
1953 fdctrl_result_timer, fdctrl);
1954
1955 fdctrl->version = 0x90; /* Intel 82078 controller */
1956 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1957 fdctrl->num_floppies = MAX_FD;
1958
1959 if (fdctrl->dma_chann != -1)
1960 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1961 return fdctrl_connect_drives(fdctrl);
1962 }
1963
1964 static const MemoryRegionPortio fdc_portio_list[] = {
1965 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
1966 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
1967 PORTIO_END_OF_LIST(),
1968 };
1969
1970 static int isabus_fdc_init1(ISADevice *dev)
1971 {
1972 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
1973 FDCtrl *fdctrl = &isa->state;
1974 int iobase = 0x3f0;
1975 int isairq = 6;
1976 int dma_chann = 2;
1977 int ret;
1978
1979 isa_register_portio_list(dev, iobase, fdc_portio_list, fdctrl, "fdc");
1980
1981 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1982 fdctrl->dma_chann = dma_chann;
1983
1984 qdev_set_legacy_instance_id(&dev->qdev, iobase, 2);
1985 ret = fdctrl_init_common(fdctrl);
1986
1987 add_boot_device_path(isa->bootindexA, &dev->qdev, "/floppy@0");
1988 add_boot_device_path(isa->bootindexB, &dev->qdev, "/floppy@1");
1989
1990 return ret;
1991 }
1992
1993 static int sysbus_fdc_init1(SysBusDevice *dev)
1994 {
1995 FDCtrlSysBus *sys = DO_UPCAST(FDCtrlSysBus, busdev, dev);
1996 FDCtrl *fdctrl = &sys->state;
1997 int ret;
1998
1999 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_ops, fdctrl, "fdc", 0x08);
2000 sysbus_init_mmio(dev, &fdctrl->iomem);
2001 sysbus_init_irq(dev, &fdctrl->irq);
2002 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2003 fdctrl->dma_chann = -1;
2004
2005 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2006 ret = fdctrl_init_common(fdctrl);
2007
2008 return ret;
2009 }
2010
2011 static int sun4m_fdc_init1(SysBusDevice *dev)
2012 {
2013 FDCtrl *fdctrl = &(FROM_SYSBUS(FDCtrlSysBus, dev)->state);
2014
2015 memory_region_init_io(&fdctrl->iomem, &fdctrl_mem_strict_ops, fdctrl,
2016 "fdctrl", 0x08);
2017 sysbus_init_mmio(dev, &fdctrl->iomem);
2018 sysbus_init_irq(dev, &fdctrl->irq);
2019 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2020
2021 fdctrl->sun4m = 1;
2022 qdev_set_legacy_instance_id(&dev->qdev, 0 /* io */, 2); /* FIXME */
2023 return fdctrl_init_common(fdctrl);
2024 }
2025
2026 void fdc_get_bs(BlockDriverState *bs[], ISADevice *dev)
2027 {
2028 FDCtrlISABus *isa = DO_UPCAST(FDCtrlISABus, busdev, dev);
2029 FDCtrl *fdctrl = &isa->state;
2030 int i;
2031
2032 for (i = 0; i < MAX_FD; i++) {
2033 bs[i] = fdctrl->drives[i].bs;
2034 }
2035 }
2036
2037
2038 static const VMStateDescription vmstate_isa_fdc ={
2039 .name = "fdc",
2040 .version_id = 2,
2041 .minimum_version_id = 2,
2042 .fields = (VMStateField []) {
2043 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2044 VMSTATE_END_OF_LIST()
2045 }
2046 };
2047
2048 static Property isa_fdc_properties[] = {
2049 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.drives[0].bs),
2050 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.drives[1].bs),
2051 DEFINE_PROP_INT32("bootindexA", FDCtrlISABus, bootindexA, -1),
2052 DEFINE_PROP_INT32("bootindexB", FDCtrlISABus, bootindexB, -1),
2053 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2054 0, true),
2055 DEFINE_PROP_END_OF_LIST(),
2056 };
2057
2058 static void isabus_fdc_class_init1(ObjectClass *klass, void *data)
2059 {
2060 DeviceClass *dc = DEVICE_CLASS(klass);
2061 ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
2062 ic->init = isabus_fdc_init1;
2063 dc->fw_name = "fdc";
2064 dc->no_user = 1;
2065 dc->reset = fdctrl_external_reset_isa;
2066 dc->vmsd = &vmstate_isa_fdc;
2067 dc->props = isa_fdc_properties;
2068 }
2069
2070 static TypeInfo isa_fdc_info = {
2071 .name = "isa-fdc",
2072 .parent = TYPE_ISA_DEVICE,
2073 .instance_size = sizeof(FDCtrlISABus),
2074 .class_init = isabus_fdc_class_init1,
2075 };
2076
2077 static const VMStateDescription vmstate_sysbus_fdc ={
2078 .name = "fdc",
2079 .version_id = 2,
2080 .minimum_version_id = 2,
2081 .fields = (VMStateField []) {
2082 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2083 VMSTATE_END_OF_LIST()
2084 }
2085 };
2086
2087 static Property sysbus_fdc_properties[] = {
2088 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.drives[0].bs),
2089 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.drives[1].bs),
2090 DEFINE_PROP_END_OF_LIST(),
2091 };
2092
2093 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2094 {
2095 DeviceClass *dc = DEVICE_CLASS(klass);
2096 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2097
2098 k->init = sysbus_fdc_init1;
2099 dc->reset = fdctrl_external_reset_sysbus;
2100 dc->vmsd = &vmstate_sysbus_fdc;
2101 dc->props = sysbus_fdc_properties;
2102 }
2103
2104 static TypeInfo sysbus_fdc_info = {
2105 .name = "sysbus-fdc",
2106 .parent = TYPE_SYS_BUS_DEVICE,
2107 .instance_size = sizeof(FDCtrlSysBus),
2108 .class_init = sysbus_fdc_class_init,
2109 };
2110
2111 static Property sun4m_fdc_properties[] = {
2112 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.drives[0].bs),
2113 DEFINE_PROP_END_OF_LIST(),
2114 };
2115
2116 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2117 {
2118 DeviceClass *dc = DEVICE_CLASS(klass);
2119 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
2120
2121 k->init = sun4m_fdc_init1;
2122 dc->reset = fdctrl_external_reset_sysbus;
2123 dc->vmsd = &vmstate_sysbus_fdc;
2124 dc->props = sun4m_fdc_properties;
2125 }
2126
2127 static TypeInfo sun4m_fdc_info = {
2128 .name = "SUNW,fdtwo",
2129 .parent = TYPE_SYS_BUS_DEVICE,
2130 .instance_size = sizeof(FDCtrlSysBus),
2131 .class_init = sun4m_fdc_class_init,
2132 };
2133
2134 static void fdc_register_types(void)
2135 {
2136 type_register_static(&isa_fdc_info);
2137 type_register_static(&sysbus_fdc_info);
2138 type_register_static(&sun4m_fdc_info);
2139 }
2140
2141 type_init(fdc_register_types)
QEmu