2 * Model of Petalogix linux reference design targeting Xilinx Spartan ml605
5 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
6 * Copyright (c) 2011 PetaLogix
7 * Copyright (c) 2009 Edgar E. Iglesias.
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "hw/sysbus.h"
31 #include "hw/block/flash.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/devices.h"
34 #include "hw/boards.h"
35 #include "sysemu/block-backend.h"
36 #include "hw/char/serial.h"
37 #include "exec/address-spaces.h"
42 #include "hw/stream.h"
44 #define LMB_BRAM_SIZE (128 * 1024)
45 #define FLASH_SIZE (32 * 1024 * 1024)
47 #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"
49 #define NUM_SPI_FLASHES 4
51 #define SPI_BASEADDR 0x40a00000
52 #define MEMORY_BASEADDR 0x50000000
53 #define FLASH_BASEADDR 0x86000000
54 #define INTC_BASEADDR 0x81800000
55 #define TIMER_BASEADDR 0x83c00000
56 #define UART16550_BASEADDR 0x83e00000
57 #define AXIENET_BASEADDR 0x82780000
58 #define AXIDMA_BASEADDR 0x84600000
65 #define UART16550_IRQ 5
67 static void machine_cpu_reset(MicroBlazeCPU
*cpu
)
69 CPUMBState
*env
= &cpu
->env
;
71 env
->pvr
.regs
[10] = 0x0e000000; /* virtex 6 */
72 /* setup pvr to match kernel setting */
73 env
->pvr
.regs
[0] = (env
->pvr
.regs
[0] & ~PVR0_VERSION_MASK
) | (0x14 << 8);
74 env
->pvr
.regs
[4] = 0xc56b8000;
75 env
->pvr
.regs
[5] = 0xc56be000;
79 petalogix_ml605_init(MachineState
*machine
)
81 ram_addr_t ram_size
= machine
->ram_size
;
82 MemoryRegion
*address_space_mem
= get_system_memory();
83 DeviceState
*dev
, *dma
, *eth0
;
89 MemoryRegion
*phys_lmb_bram
= g_new(MemoryRegion
, 1);
90 MemoryRegion
*phys_ram
= g_new(MemoryRegion
, 1);
94 cpu
= MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU
));
95 /* Use FPU but don't use floating point conversion and square
98 object_property_set_int(OBJECT(cpu
), 1, "use-fpu", &error_abort
);
99 object_property_set_bool(OBJECT(cpu
), true, "dcache-writeback",
101 object_property_set_bool(OBJECT(cpu
), true, "endianness", &error_abort
);
102 object_property_set_bool(OBJECT(cpu
), true, "realized", &error_abort
);
104 /* Attach emulated BRAM through the LMB. */
105 memory_region_init_ram(phys_lmb_bram
, NULL
, "petalogix_ml605.lmb_bram",
106 LMB_BRAM_SIZE
, &error_abort
);
107 vmstate_register_ram_global(phys_lmb_bram
);
108 memory_region_add_subregion(address_space_mem
, 0x00000000, phys_lmb_bram
);
110 memory_region_init_ram(phys_ram
, NULL
, "petalogix_ml605.ram", ram_size
,
112 vmstate_register_ram_global(phys_ram
);
113 memory_region_add_subregion(address_space_mem
, MEMORY_BASEADDR
, phys_ram
);
115 dinfo
= drive_get(IF_PFLASH
, 0, 0);
116 /* 5th parameter 2 means bank-width
117 * 10th paremeter 0 means little-endian */
118 pflash_cfi01_register(FLASH_BASEADDR
,
119 NULL
, "petalogix_ml605.flash", FLASH_SIZE
,
120 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
121 (64 * 1024), FLASH_SIZE
>> 16,
122 2, 0x89, 0x18, 0x0000, 0x0, 0);
125 dev
= qdev_create(NULL
, "xlnx.xps-intc");
126 qdev_prop_set_uint32(dev
, "kind-of-intr", 1 << TIMER_IRQ
);
127 qdev_init_nofail(dev
);
128 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, INTC_BASEADDR
);
129 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0,
130 qdev_get_gpio_in(DEVICE(cpu
), MB_CPU_IRQ
));
131 for (i
= 0; i
< 32; i
++) {
132 irq
[i
] = qdev_get_gpio_in(dev
, i
);
135 serial_mm_init(address_space_mem
, UART16550_BASEADDR
+ 0x1000, 2,
136 irq
[UART16550_IRQ
], 115200, serial_hds
[0],
137 DEVICE_LITTLE_ENDIAN
);
139 /* 2 timers at irq 2 @ 100 Mhz. */
140 dev
= qdev_create(NULL
, "xlnx.xps-timer");
141 qdev_prop_set_uint32(dev
, "one-timer-only", 0);
142 qdev_prop_set_uint32(dev
, "clock-frequency", 100 * 1000000);
143 qdev_init_nofail(dev
);
144 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, TIMER_BASEADDR
);
145 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0, irq
[TIMER_IRQ
]);
147 /* axi ethernet and dma initialization. */
148 qemu_check_nic_model(&nd_table
[0], "xlnx.axi-ethernet");
149 eth0
= qdev_create(NULL
, "xlnx.axi-ethernet");
150 dma
= qdev_create(NULL
, "xlnx.axi-dma");
152 /* FIXME: attach to the sysbus instead */
153 object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0
),
155 object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma
),
158 ds
= object_property_get_link(OBJECT(dma
),
159 "axistream-connected-target", NULL
);
160 cs
= object_property_get_link(OBJECT(dma
),
161 "axistream-control-connected-target", NULL
);
162 qdev_set_nic_properties(eth0
, &nd_table
[0]);
163 qdev_prop_set_uint32(eth0
, "rxmem", 0x1000);
164 qdev_prop_set_uint32(eth0
, "txmem", 0x1000);
165 object_property_set_link(OBJECT(eth0
), OBJECT(ds
),
166 "axistream-connected", &error_abort
);
167 object_property_set_link(OBJECT(eth0
), OBJECT(cs
),
168 "axistream-control-connected", &error_abort
);
169 qdev_init_nofail(eth0
);
170 sysbus_mmio_map(SYS_BUS_DEVICE(eth0
), 0, AXIENET_BASEADDR
);
171 sysbus_connect_irq(SYS_BUS_DEVICE(eth0
), 0, irq
[AXIENET_IRQ
]);
173 ds
= object_property_get_link(OBJECT(eth0
),
174 "axistream-connected-target", NULL
);
175 cs
= object_property_get_link(OBJECT(eth0
),
176 "axistream-control-connected-target", NULL
);
177 qdev_prop_set_uint32(dma
, "freqhz", 100 * 1000000);
178 object_property_set_link(OBJECT(dma
), OBJECT(ds
),
179 "axistream-connected", &error_abort
);
180 object_property_set_link(OBJECT(dma
), OBJECT(cs
),
181 "axistream-control-connected", &error_abort
);
182 qdev_init_nofail(dma
);
183 sysbus_mmio_map(SYS_BUS_DEVICE(dma
), 0, AXIDMA_BASEADDR
);
184 sysbus_connect_irq(SYS_BUS_DEVICE(dma
), 0, irq
[AXIDMA_IRQ0
]);
185 sysbus_connect_irq(SYS_BUS_DEVICE(dma
), 1, irq
[AXIDMA_IRQ1
]);
190 dev
= qdev_create(NULL
, "xlnx.xps-spi");
191 qdev_prop_set_uint8(dev
, "num-ss-bits", NUM_SPI_FLASHES
);
192 qdev_init_nofail(dev
);
193 busdev
= SYS_BUS_DEVICE(dev
);
194 sysbus_mmio_map(busdev
, 0, SPI_BASEADDR
);
195 sysbus_connect_irq(busdev
, 0, irq
[SPI_IRQ
]);
197 spi
= (SSIBus
*)qdev_get_child_bus(dev
, "spi");
199 for (i
= 0; i
< NUM_SPI_FLASHES
; i
++) {
202 dev
= ssi_create_slave(spi
, "n25q128");
203 cs_line
= qdev_get_gpio_in_named(dev
, SSI_GPIO_CS
, 0);
204 sysbus_connect_irq(busdev
, i
+1, cs_line
);
208 microblaze_load_kernel(cpu
, MEMORY_BASEADDR
, ram_size
,
209 machine
->initrd_filename
,
210 BINARY_DEVICE_TREE_FILE
,
215 static QEMUMachine petalogix_ml605_machine
= {
216 .name
= "petalogix-ml605",
217 .desc
= "PetaLogix linux refdesign for xilinx ml605 little endian",
218 .init
= petalogix_ml605_init
,
222 static void petalogix_ml605_machine_init(void)
224 qemu_register_machine(&petalogix_ml605_machine
);
227 machine_init(petalogix_ml605_machine_init
);