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i386: introduce hv_cpuid_cache
[qemu.git] / target / i386 / kvm / kvm.c
blob2dd60fcaacf7cfe9572364e7252d3027f76662a9
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/qapi-events-run-state.h"
17 #include "qapi/error.h"
18 #include <sys/ioctl.h>
19 #include <sys/utsname.h>
20
21 #include <linux/kvm.h>
22 #include "standard-headers/asm-x86/kvm_para.h"
23
24 #include "cpu.h"
25 #include "host-cpu.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/hw_accel.h"
28 #include "sysemu/kvm_int.h"
29 #include "sysemu/runstate.h"
30 #include "kvm_i386.h"
31 #include "sev_i386.h"
32 #include "hyperv.h"
33 #include "hyperv-proto.h"
34
35 #include "exec/gdbstub.h"
36 #include "qemu/host-utils.h"
37 #include "qemu/main-loop.h"
38 #include "qemu/config-file.h"
39 #include "qemu/error-report.h"
40 #include "hw/i386/x86.h"
41 #include "hw/i386/apic.h"
42 #include "hw/i386/apic_internal.h"
43 #include "hw/i386/apic-msidef.h"
44 #include "hw/i386/intel_iommu.h"
45 #include "hw/i386/x86-iommu.h"
46 #include "hw/i386/e820_memory_layout.h"
47 #include "sysemu/sev.h"
48
49 #include "hw/pci/pci.h"
50 #include "hw/pci/msi.h"
51 #include "hw/pci/msix.h"
52 #include "migration/blocker.h"
53 #include "exec/memattrs.h"
54 #include "trace.h"
55
56 //#define DEBUG_KVM
57
58 #ifdef DEBUG_KVM
59 #define DPRINTF(fmt, ...) \
60 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
61 #else
62 #define DPRINTF(fmt, ...) \
63 do { } while (0)
64 #endif
65
66 /* From arch/x86/kvm/lapic.h */
67 #define KVM_APIC_BUS_CYCLE_NS 1
68 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
69
70 #define MSR_KVM_WALL_CLOCK 0x11
71 #define MSR_KVM_SYSTEM_TIME 0x12
72
73 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
74 * 255 kvm_msr_entry structs */
75 #define MSR_BUF_SIZE 4096
76
77 static void kvm_init_msrs(X86CPU *cpu);
78
79 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
80 KVM_CAP_INFO(SET_TSS_ADDR),
81 KVM_CAP_INFO(EXT_CPUID),
82 KVM_CAP_INFO(MP_STATE),
83 KVM_CAP_LAST_INFO
84 };
85
86 static bool has_msr_star;
87 static bool has_msr_hsave_pa;
88 static bool has_msr_tsc_aux;
89 static bool has_msr_tsc_adjust;
90 static bool has_msr_tsc_deadline;
91 static bool has_msr_feature_control;
92 static bool has_msr_misc_enable;
93 static bool has_msr_smbase;
94 static bool has_msr_bndcfgs;
95 static int lm_capable_kernel;
96 static bool has_msr_hv_hypercall;
97 static bool has_msr_hv_crash;
98 static bool has_msr_hv_reset;
99 static bool has_msr_hv_vpindex;
100 static bool hv_vpindex_settable;
101 static bool has_msr_hv_runtime;
102 static bool has_msr_hv_synic;
103 static bool has_msr_hv_stimer;
104 static bool has_msr_hv_frequencies;
105 static bool has_msr_hv_reenlightenment;
106 static bool has_msr_xss;
107 static bool has_msr_umwait;
108 static bool has_msr_spec_ctrl;
109 static bool has_msr_tsx_ctrl;
110 static bool has_msr_virt_ssbd;
111 static bool has_msr_smi_count;
112 static bool has_msr_arch_capabs;
113 static bool has_msr_core_capabs;
114 static bool has_msr_vmx_vmfunc;
115 static bool has_msr_ucode_rev;
116 static bool has_msr_vmx_procbased_ctls2;
117 static bool has_msr_perf_capabs;
118 static bool has_msr_pkrs;
119
120 static uint32_t has_architectural_pmu_version;
121 static uint32_t num_architectural_pmu_gp_counters;
122 static uint32_t num_architectural_pmu_fixed_counters;
123
124 static int has_xsave;
125 static int has_xcrs;
126 static int has_pit_state2;
127 static int has_exception_payload;
128
129 static bool has_msr_mcg_ext_ctl;
130
131 static struct kvm_cpuid2 *cpuid_cache;
132 static struct kvm_cpuid2 *hv_cpuid_cache;
133 static struct kvm_msr_list *kvm_feature_msrs;
134
135 int kvm_has_pit_state2(void)
136 {
137 return has_pit_state2;
138 }
139
140 bool kvm_has_smm(void)
141 {
142 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
143 }
144
145 bool kvm_has_adjust_clock_stable(void)
146 {
147 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
148
149 return (ret == KVM_CLOCK_TSC_STABLE);
150 }
151
152 bool kvm_has_adjust_clock(void)
153 {
154 return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
155 }
156
157 bool kvm_has_exception_payload(void)
158 {
159 return has_exception_payload;
160 }
161
162 static bool kvm_x2apic_api_set_flags(uint64_t flags)
163 {
164 KVMState *s = KVM_STATE(current_accel());
165
166 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
167 }
168
169 #define MEMORIZE(fn, _result) \
170 ({ \
171 static bool _memorized; \
172 \
173 if (_memorized) { \
174 return _result; \
175 } \
176 _memorized = true; \
177 _result = fn; \
178 })
179
180 static bool has_x2apic_api;
181
182 bool kvm_has_x2apic_api(void)
183 {
184 return has_x2apic_api;
185 }
186
187 bool kvm_enable_x2apic(void)
188 {
189 return MEMORIZE(
190 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
191 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
192 has_x2apic_api);
193 }
194
195 bool kvm_hv_vpindex_settable(void)
196 {
197 return hv_vpindex_settable;
198 }
199
200 static int kvm_get_tsc(CPUState *cs)
201 {
202 X86CPU *cpu = X86_CPU(cs);
203 CPUX86State *env = &cpu->env;
204 struct {
205 struct kvm_msrs info;
206 struct kvm_msr_entry entries[1];
207 } msr_data = {};
208 int ret;
209
210 if (env->tsc_valid) {
211 return 0;
212 }
213
214 memset(&msr_data, 0, sizeof(msr_data));
215 msr_data.info.nmsrs = 1;
216 msr_data.entries[0].index = MSR_IA32_TSC;
217 env->tsc_valid = !runstate_is_running();
218
219 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
220 if (ret < 0) {
221 return ret;
222 }
223
224 assert(ret == 1);
225 env->tsc = msr_data.entries[0].data;
226 return 0;
227 }
228
229 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
230 {
231 kvm_get_tsc(cpu);
232 }
233
234 void kvm_synchronize_all_tsc(void)
235 {
236 CPUState *cpu;
237
238 if (kvm_enabled()) {
239 CPU_FOREACH(cpu) {
240 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
241 }
242 }
243 }
244
245 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
246 {
247 struct kvm_cpuid2 *cpuid;
248 int r, size;
249
250 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
251 cpuid = g_malloc0(size);
252 cpuid->nent = max;
253 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
254 if (r == 0 && cpuid->nent >= max) {
255 r = -E2BIG;
256 }
257 if (r < 0) {
258 if (r == -E2BIG) {
259 g_free(cpuid);
260 return NULL;
261 } else {
262 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
263 strerror(-r));
264 exit(1);
265 }
266 }
267 return cpuid;
268 }
269
270 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
271 * for all entries.
272 */
273 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
274 {
275 struct kvm_cpuid2 *cpuid;
276 int max = 1;
277
278 if (cpuid_cache != NULL) {
279 return cpuid_cache;
280 }
281 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
282 max *= 2;
283 }
284 cpuid_cache = cpuid;
285 return cpuid;
286 }
287
288 static bool host_tsx_broken(void)
289 {
290 int family, model, stepping;\
291 char vendor[CPUID_VENDOR_SZ + 1];
292
293 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
294
295 /* Check if we are running on a Haswell host known to have broken TSX */
296 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
297 (family == 6) &&
298 ((model == 63 && stepping < 4) ||
299 model == 60 || model == 69 || model == 70);
300 }
301
302 /* Returns the value for a specific register on the cpuid entry
303 */
304 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
305 {
306 uint32_t ret = 0;
307 switch (reg) {
308 case R_EAX:
309 ret = entry->eax;
310 break;
311 case R_EBX:
312 ret = entry->ebx;
313 break;
314 case R_ECX:
315 ret = entry->ecx;
316 break;
317 case R_EDX:
318 ret = entry->edx;
319 break;
320 }
321 return ret;
322 }
323
324 /* Find matching entry for function/index on kvm_cpuid2 struct
325 */
326 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
327 uint32_t function,
328 uint32_t index)
329 {
330 int i;
331 for (i = 0; i < cpuid->nent; ++i) {
332 if (cpuid->entries[i].function == function &&
333 cpuid->entries[i].index == index) {
334 return &cpuid->entries[i];
335 }
336 }
337 /* not found: */
338 return NULL;
339 }
340
341 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
342 uint32_t index, int reg)
343 {
344 struct kvm_cpuid2 *cpuid;
345 uint32_t ret = 0;
346 uint32_t cpuid_1_edx;
347
348 cpuid = get_supported_cpuid(s);
349
350 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
351 if (entry) {
352 ret = cpuid_entry_get_reg(entry, reg);
353 }
354
355 /* Fixups for the data returned by KVM, below */
356
357 if (function == 1 && reg == R_EDX) {
358 /* KVM before 2.6.30 misreports the following features */
359 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
360 } else if (function == 1 && reg == R_ECX) {
361 /* We can set the hypervisor flag, even if KVM does not return it on
362 * GET_SUPPORTED_CPUID
363 */
364 ret |= CPUID_EXT_HYPERVISOR;
365 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
366 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
367 * and the irqchip is in the kernel.
368 */
369 if (kvm_irqchip_in_kernel() &&
370 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
371 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
372 }
373
374 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
375 * without the in-kernel irqchip
376 */
377 if (!kvm_irqchip_in_kernel()) {
378 ret &= ~CPUID_EXT_X2APIC;
379 }
380
381 if (enable_cpu_pm) {
382 int disable_exits = kvm_check_extension(s,
383 KVM_CAP_X86_DISABLE_EXITS);
384
385 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
386 ret |= CPUID_EXT_MONITOR;
387 }
388 }
389 } else if (function == 6 && reg == R_EAX) {
390 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
391 } else if (function == 7 && index == 0 && reg == R_EBX) {
392 if (host_tsx_broken()) {
393 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
394 }
395 } else if (function == 7 && index == 0 && reg == R_EDX) {
396 /*
397 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
398 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
399 * returned by KVM_GET_MSR_INDEX_LIST.
400 */
401 if (!has_msr_arch_capabs) {
402 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
403 }
404 } else if (function == 0x80000001 && reg == R_ECX) {
405 /*
406 * It's safe to enable TOPOEXT even if it's not returned by
407 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
408 * us to keep CPU models including TOPOEXT runnable on older kernels.
409 */
410 ret |= CPUID_EXT3_TOPOEXT;
411 } else if (function == 0x80000001 && reg == R_EDX) {
412 /* On Intel, kvm returns cpuid according to the Intel spec,
413 * so add missing bits according to the AMD spec:
414 */
415 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
416 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
417 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
418 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
419 * be enabled without the in-kernel irqchip
420 */
421 if (!kvm_irqchip_in_kernel()) {
422 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
423 }
424 if (kvm_irqchip_is_split()) {
425 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID;
426 }
427 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
428 ret |= 1U << KVM_HINTS_REALTIME;
429 }
430
431 return ret;
432 }
433
434 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
435 {
436 struct {
437 struct kvm_msrs info;
438 struct kvm_msr_entry entries[1];
439 } msr_data = {};
440 uint64_t value;
441 uint32_t ret, can_be_one, must_be_one;
442
443 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
444 return 0;
445 }
446
447 /* Check if requested MSR is supported feature MSR */
448 int i;
449 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
450 if (kvm_feature_msrs->indices[i] == index) {
451 break;
452 }
453 if (i == kvm_feature_msrs->nmsrs) {
454 return 0; /* if the feature MSR is not supported, simply return 0 */
455 }
456
457 msr_data.info.nmsrs = 1;
458 msr_data.entries[0].index = index;
459
460 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
461 if (ret != 1) {
462 error_report("KVM get MSR (index=0x%x) feature failed, %s",
463 index, strerror(-ret));
464 exit(1);
465 }
466
467 value = msr_data.entries[0].data;
468 switch (index) {
469 case MSR_IA32_VMX_PROCBASED_CTLS2:
470 if (!has_msr_vmx_procbased_ctls2) {
471 /* KVM forgot to add these bits for some time, do this ourselves. */
472 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
473 CPUID_XSAVE_XSAVES) {
474 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
475 }
476 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
477 CPUID_EXT_RDRAND) {
478 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
479 }
480 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
481 CPUID_7_0_EBX_INVPCID) {
482 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
483 }
484 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
485 CPUID_7_0_EBX_RDSEED) {
486 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
487 }
488 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
489 CPUID_EXT2_RDTSCP) {
490 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
491 }
492 }
493 /* fall through */
494 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
495 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
496 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
497 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
498 /*
499 * Return true for bits that can be one, but do not have to be one.
500 * The SDM tells us which bits could have a "must be one" setting,
501 * so we can do the opposite transformation in make_vmx_msr_value.
502 */
503 must_be_one = (uint32_t)value;
504 can_be_one = (uint32_t)(value >> 32);
505 return can_be_one & ~must_be_one;
506
507 default:
508 return value;
509 }
510 }
511
512 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
513 int *max_banks)
514 {
515 int r;
516
517 r = kvm_check_extension(s, KVM_CAP_MCE);
518 if (r > 0) {
519 *max_banks = r;
520 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
521 }
522 return -ENOSYS;
523 }
524
525 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
526 {
527 CPUState *cs = CPU(cpu);
528 CPUX86State *env = &cpu->env;
529 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
530 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
531 uint64_t mcg_status = MCG_STATUS_MCIP;
532 int flags = 0;
533
534 if (code == BUS_MCEERR_AR) {
535 status |= MCI_STATUS_AR | 0x134;
536 mcg_status |= MCG_STATUS_EIPV;
537 } else {
538 status |= 0xc0;
539 mcg_status |= MCG_STATUS_RIPV;
540 }
541
542 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
543 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
544 * guest kernel back into env->mcg_ext_ctl.
545 */
546 cpu_synchronize_state(cs);
547 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
548 mcg_status |= MCG_STATUS_LMCE;
549 flags = 0;
550 }
551
552 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
553 (MCM_ADDR_PHYS << 6) | 0xc, flags);
554 }
555
556 static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
557 {
558 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
559
560 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
561 &mff);
562 }
563
564 static void hardware_memory_error(void *host_addr)
565 {
566 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
567 error_report("QEMU got Hardware memory error at addr %p", host_addr);
568 exit(1);
569 }
570
571 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
572 {
573 X86CPU *cpu = X86_CPU(c);
574 CPUX86State *env = &cpu->env;
575 ram_addr_t ram_addr;
576 hwaddr paddr;
577
578 /* If we get an action required MCE, it has been injected by KVM
579 * while the VM was running. An action optional MCE instead should
580 * be coming from the main thread, which qemu_init_sigbus identifies
581 * as the "early kill" thread.
582 */
583 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
584
585 if ((env->mcg_cap & MCG_SER_P) && addr) {
586 ram_addr = qemu_ram_addr_from_host(addr);
587 if (ram_addr != RAM_ADDR_INVALID &&
588 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
589 kvm_hwpoison_page_add(ram_addr);
590 kvm_mce_inject(cpu, paddr, code);
591
592 /*
593 * Use different logging severity based on error type.
594 * If there is additional MCE reporting on the hypervisor, QEMU VA
595 * could be another source to identify the PA and MCE details.
596 */
597 if (code == BUS_MCEERR_AR) {
598 error_report("Guest MCE Memory Error at QEMU addr %p and "
599 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
600 addr, paddr, "BUS_MCEERR_AR");
601 } else {
602 warn_report("Guest MCE Memory Error at QEMU addr %p and "
603 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
604 addr, paddr, "BUS_MCEERR_AO");
605 }
606
607 return;
608 }
609
610 if (code == BUS_MCEERR_AO) {
611 warn_report("Hardware memory error at addr %p of type %s "
612 "for memory used by QEMU itself instead of guest system!",
613 addr, "BUS_MCEERR_AO");
614 }
615 }
616
617 if (code == BUS_MCEERR_AR) {
618 hardware_memory_error(addr);
619 }
620
621 /* Hope we are lucky for AO MCE, just notify a event */
622 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
623 }
624
625 static void kvm_reset_exception(CPUX86State *env)
626 {
627 env->exception_nr = -1;
628 env->exception_pending = 0;
629 env->exception_injected = 0;
630 env->exception_has_payload = false;
631 env->exception_payload = 0;
632 }
633
634 static void kvm_queue_exception(CPUX86State *env,
635 int32_t exception_nr,
636 uint8_t exception_has_payload,
637 uint64_t exception_payload)
638 {
639 assert(env->exception_nr == -1);
640 assert(!env->exception_pending);
641 assert(!env->exception_injected);
642 assert(!env->exception_has_payload);
643
644 env->exception_nr = exception_nr;
645
646 if (has_exception_payload) {
647 env->exception_pending = 1;
648
649 env->exception_has_payload = exception_has_payload;
650 env->exception_payload = exception_payload;
651 } else {
652 env->exception_injected = 1;
653
654 if (exception_nr == EXCP01_DB) {
655 assert(exception_has_payload);
656 env->dr[6] = exception_payload;
657 } else if (exception_nr == EXCP0E_PAGE) {
658 assert(exception_has_payload);
659 env->cr[2] = exception_payload;
660 } else {
661 assert(!exception_has_payload);
662 }
663 }
664 }
665
666 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
667 {
668 CPUX86State *env = &cpu->env;
669
670 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
671 unsigned int bank, bank_num = env->mcg_cap & 0xff;
672 struct kvm_x86_mce mce;
673
674 kvm_reset_exception(env);
675
676 /*
677 * There must be at least one bank in use if an MCE is pending.
678 * Find it and use its values for the event injection.
679 */
680 for (bank = 0; bank < bank_num; bank++) {
681 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
682 break;
683 }
684 }
685 assert(bank < bank_num);
686
687 mce.bank = bank;
688 mce.status = env->mce_banks[bank * 4 + 1];
689 mce.mcg_status = env->mcg_status;
690 mce.addr = env->mce_banks[bank * 4 + 2];
691 mce.misc = env->mce_banks[bank * 4 + 3];
692
693 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
694 }
695 return 0;
696 }
697
698 static void cpu_update_state(void *opaque, bool running, RunState state)
699 {
700 CPUX86State *env = opaque;
701
702 if (running) {
703 env->tsc_valid = false;
704 }
705 }
706
707 unsigned long kvm_arch_vcpu_id(CPUState *cs)
708 {
709 X86CPU *cpu = X86_CPU(cs);
710 return cpu->apic_id;
711 }
712
713 #ifndef KVM_CPUID_SIGNATURE_NEXT
714 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
715 #endif
716
717 static bool hyperv_enabled(X86CPU *cpu)
718 {
719 CPUState *cs = CPU(cpu);
720 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
721 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
722 cpu->hyperv_features || cpu->hyperv_passthrough);
723 }
724
725 /*
726 * Check whether target_freq is within conservative
727 * ntp correctable bounds (250ppm) of freq
728 */
729 static inline bool freq_within_bounds(int freq, int target_freq)
730 {
731 int max_freq = freq + (freq * 250 / 1000000);
732 int min_freq = freq - (freq * 250 / 1000000);
733
734 if (target_freq >= min_freq && target_freq <= max_freq) {
735 return true;
736 }
737
738 return false;
739 }
740
741 static int kvm_arch_set_tsc_khz(CPUState *cs)
742 {
743 X86CPU *cpu = X86_CPU(cs);
744 CPUX86State *env = &cpu->env;
745 int r, cur_freq;
746 bool set_ioctl = false;
747
748 if (!env->tsc_khz) {
749 return 0;
750 }
751
752 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
753 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
754
755 /*
756 * If TSC scaling is supported, attempt to set TSC frequency.
757 */
758 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
759 set_ioctl = true;
760 }
761
762 /*
763 * If desired TSC frequency is within bounds of NTP correction,
764 * attempt to set TSC frequency.
765 */
766 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
767 set_ioctl = true;
768 }
769
770 r = set_ioctl ?
771 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
772 -ENOTSUP;
773
774 if (r < 0) {
775 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
776 * TSC frequency doesn't match the one we want.
777 */
778 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
779 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
780 -ENOTSUP;
781 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
782 warn_report("TSC frequency mismatch between "
783 "VM (%" PRId64 " kHz) and host (%d kHz), "
784 "and TSC scaling unavailable",
785 env->tsc_khz, cur_freq);
786 return r;
787 }
788 }
789
790 return 0;
791 }
792
793 static bool tsc_is_stable_and_known(CPUX86State *env)
794 {
795 if (!env->tsc_khz) {
796 return false;
797 }
798 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
799 || env->user_tsc_khz;
800 }
801
802 static struct {
803 const char *desc;
804 struct {
805 uint32_t func;
806 int reg;
807 uint32_t bits;
808 } flags[2];
809 uint64_t dependencies;
810 } kvm_hyperv_properties[] = {
811 [HYPERV_FEAT_RELAXED] = {
812 .desc = "relaxed timing (hv-relaxed)",
813 .flags = {
814 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
815 .bits = HV_HYPERCALL_AVAILABLE},
816 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
817 .bits = HV_RELAXED_TIMING_RECOMMENDED}
818 }
819 },
820 [HYPERV_FEAT_VAPIC] = {
821 .desc = "virtual APIC (hv-vapic)",
822 .flags = {
823 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
824 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
825 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
826 .bits = HV_APIC_ACCESS_RECOMMENDED}
827 }
828 },
829 [HYPERV_FEAT_TIME] = {
830 .desc = "clocksources (hv-time)",
831 .flags = {
832 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
833 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
834 HV_REFERENCE_TSC_AVAILABLE}
835 }
836 },
837 [HYPERV_FEAT_CRASH] = {
838 .desc = "crash MSRs (hv-crash)",
839 .flags = {
840 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
841 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
842 }
843 },
844 [HYPERV_FEAT_RESET] = {
845 .desc = "reset MSR (hv-reset)",
846 .flags = {
847 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
848 .bits = HV_RESET_AVAILABLE}
849 }
850 },
851 [HYPERV_FEAT_VPINDEX] = {
852 .desc = "VP_INDEX MSR (hv-vpindex)",
853 .flags = {
854 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
855 .bits = HV_VP_INDEX_AVAILABLE}
856 }
857 },
858 [HYPERV_FEAT_RUNTIME] = {
859 .desc = "VP_RUNTIME MSR (hv-runtime)",
860 .flags = {
861 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
862 .bits = HV_VP_RUNTIME_AVAILABLE}
863 }
864 },
865 [HYPERV_FEAT_SYNIC] = {
866 .desc = "synthetic interrupt controller (hv-synic)",
867 .flags = {
868 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
869 .bits = HV_SYNIC_AVAILABLE}
870 }
871 },
872 [HYPERV_FEAT_STIMER] = {
873 .desc = "synthetic timers (hv-stimer)",
874 .flags = {
875 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
876 .bits = HV_SYNTIMERS_AVAILABLE}
877 },
878 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
879 },
880 [HYPERV_FEAT_FREQUENCIES] = {
881 .desc = "frequency MSRs (hv-frequencies)",
882 .flags = {
883 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
884 .bits = HV_ACCESS_FREQUENCY_MSRS},
885 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
886 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
887 }
888 },
889 [HYPERV_FEAT_REENLIGHTENMENT] = {
890 .desc = "reenlightenment MSRs (hv-reenlightenment)",
891 .flags = {
892 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
893 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
894 }
895 },
896 [HYPERV_FEAT_TLBFLUSH] = {
897 .desc = "paravirtualized TLB flush (hv-tlbflush)",
898 .flags = {
899 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
900 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
901 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
902 },
903 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
904 },
905 [HYPERV_FEAT_EVMCS] = {
906 .desc = "enlightened VMCS (hv-evmcs)",
907 .flags = {
908 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
909 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
910 },
911 .dependencies = BIT(HYPERV_FEAT_VAPIC)
912 },
913 [HYPERV_FEAT_IPI] = {
914 .desc = "paravirtualized IPI (hv-ipi)",
915 .flags = {
916 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
917 .bits = HV_CLUSTER_IPI_RECOMMENDED |
918 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
919 },
920 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
921 },
922 [HYPERV_FEAT_STIMER_DIRECT] = {
923 .desc = "direct mode synthetic timers (hv-stimer-direct)",
924 .flags = {
925 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
926 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
927 },
928 .dependencies = BIT(HYPERV_FEAT_STIMER)
929 },
930 };
931
932 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
933 {
934 struct kvm_cpuid2 *cpuid;
935 int r, size;
936
937 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
938 cpuid = g_malloc0(size);
939 cpuid->nent = max;
940
941 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
942 if (r == 0 && cpuid->nent >= max) {
943 r = -E2BIG;
944 }
945 if (r < 0) {
946 if (r == -E2BIG) {
947 g_free(cpuid);
948 return NULL;
949 } else {
950 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
951 strerror(-r));
952 exit(1);
953 }
954 }
955 return cpuid;
956 }
957
958 /*
959 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
960 * for all entries.
961 */
962 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
963 {
964 struct kvm_cpuid2 *cpuid;
965 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
966
967 /*
968 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
969 * -E2BIG, however, it doesn't report back the right size. Keep increasing
970 * it and re-trying until we succeed.
971 */
972 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
973 max++;
974 }
975 return cpuid;
976 }
977
978 /*
979 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
980 * leaves from KVM_CAP_HYPERV* and present MSRs data.
981 */
982 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
983 {
984 X86CPU *cpu = X86_CPU(cs);
985 struct kvm_cpuid2 *cpuid;
986 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
987
988 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
989 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
990 cpuid->nent = 2;
991
992 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
993 entry_feat = &cpuid->entries[0];
994 entry_feat->function = HV_CPUID_FEATURES;
995
996 entry_recomm = &cpuid->entries[1];
997 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
998 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
999
1000 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1001 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1002 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1003 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1004 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1005 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1006 }
1007
1008 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1009 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1010 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1011 }
1012
1013 if (has_msr_hv_frequencies) {
1014 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1015 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1016 }
1017
1018 if (has_msr_hv_crash) {
1019 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1020 }
1021
1022 if (has_msr_hv_reenlightenment) {
1023 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1024 }
1025
1026 if (has_msr_hv_reset) {
1027 entry_feat->eax |= HV_RESET_AVAILABLE;
1028 }
1029
1030 if (has_msr_hv_vpindex) {
1031 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1032 }
1033
1034 if (has_msr_hv_runtime) {
1035 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1036 }
1037
1038 if (has_msr_hv_synic) {
1039 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1040 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1041
1042 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1043 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1044 }
1045 }
1046
1047 if (has_msr_hv_stimer) {
1048 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1049 }
1050
1051 if (kvm_check_extension(cs->kvm_state,
1052 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1053 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1054 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1055 }
1056
1057 if (kvm_check_extension(cs->kvm_state,
1058 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1059 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1060 }
1061
1062 if (kvm_check_extension(cs->kvm_state,
1063 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1064 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1065 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1066 }
1067
1068 return cpuid;
1069 }
1070
1071 static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
1072 {
1073 struct kvm_cpuid_entry2 *entry;
1074 struct kvm_cpuid2 *cpuid;
1075
1076 if (hv_cpuid_cache) {
1077 cpuid = hv_cpuid_cache;
1078 } else {
1079 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1080 cpuid = get_supported_hv_cpuid(cs);
1081 } else {
1082 cpuid = get_supported_hv_cpuid_legacy(cs);
1083 }
1084 hv_cpuid_cache = cpuid;
1085 }
1086
1087 if (!cpuid) {
1088 return 0;
1089 }
1090
1091 entry = cpuid_find_entry(cpuid, func, 0);
1092 if (!entry) {
1093 return 0;
1094 }
1095
1096 return cpuid_entry_get_reg(entry, reg);
1097 }
1098
1099 static bool hyperv_feature_supported(CPUState *cs, int feature)
1100 {
1101 uint32_t func, bits;
1102 int i, reg;
1103
1104 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1105
1106 func = kvm_hyperv_properties[feature].flags[i].func;
1107 reg = kvm_hyperv_properties[feature].flags[i].reg;
1108 bits = kvm_hyperv_properties[feature].flags[i].bits;
1109
1110 if (!func) {
1111 continue;
1112 }
1113
1114 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
1115 return false;
1116 }
1117 }
1118
1119 return true;
1120 }
1121
1122 static int hv_cpuid_check_and_set(CPUState *cs, int feature)
1123 {
1124 X86CPU *cpu = X86_CPU(cs);
1125 uint64_t deps;
1126 int dep_feat;
1127
1128 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
1129 return 0;
1130 }
1131
1132 deps = kvm_hyperv_properties[feature].dependencies;
1133 while (deps) {
1134 dep_feat = ctz64(deps);
1135 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1136 fprintf(stderr,
1137 "Hyper-V %s requires Hyper-V %s\n",
1138 kvm_hyperv_properties[feature].desc,
1139 kvm_hyperv_properties[dep_feat].desc);
1140 return 1;
1141 }
1142 deps &= ~(1ull << dep_feat);
1143 }
1144
1145 if (!hyperv_feature_supported(cs, feature)) {
1146 if (hyperv_feat_enabled(cpu, feature)) {
1147 fprintf(stderr,
1148 "Hyper-V %s is not supported by kernel\n",
1149 kvm_hyperv_properties[feature].desc);
1150 return 1;
1151 } else {
1152 return 0;
1153 }
1154 }
1155
1156 if (cpu->hyperv_passthrough) {
1157 cpu->hyperv_features |= BIT(feature);
1158 }
1159
1160 return 0;
1161 }
1162
1163 static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
1164 {
1165 X86CPU *cpu = X86_CPU(cs);
1166 uint32_t r = 0;
1167 int i, j;
1168
1169 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1170 if (!hyperv_feat_enabled(cpu, i)) {
1171 continue;
1172 }
1173
1174 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
1175 if (kvm_hyperv_properties[i].flags[j].func != func) {
1176 continue;
1177 }
1178 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
1179 continue;
1180 }
1181
1182 r |= kvm_hyperv_properties[i].flags[j].bits;
1183 }
1184 }
1185
1186 return r;
1187 }
1188
1189 /*
1190 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1191 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1192 * extentions are enabled.
1193 */
1194 static int hyperv_handle_properties(CPUState *cs,
1195 struct kvm_cpuid_entry2 *cpuid_ent)
1196 {
1197 X86CPU *cpu = X86_CPU(cs);
1198 struct kvm_cpuid_entry2 *c;
1199 uint32_t cpuid_i = 0;
1200 int r;
1201
1202 if (!hyperv_enabled(cpu))
1203 return 0;
1204
1205 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1206 cpu->hyperv_passthrough) {
1207 uint16_t evmcs_version;
1208
1209 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1210 (uintptr_t)&evmcs_version);
1211
1212 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
1213 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1214 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1215 return -ENOSYS;
1216 }
1217
1218 if (!r) {
1219 cpu->hyperv_nested[0] = evmcs_version;
1220 }
1221 }
1222
1223 if (cpu->hyperv_passthrough) {
1224 cpu->hyperv_vendor_id[0] =
1225 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
1226 cpu->hyperv_vendor_id[1] =
1227 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
1228 cpu->hyperv_vendor_id[2] =
1229 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
1230 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1231 sizeof(cpu->hyperv_vendor_id) + 1);
1232 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1233 sizeof(cpu->hyperv_vendor_id));
1234 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1235
1236 cpu->hyperv_interface_id[0] =
1237 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
1238 cpu->hyperv_interface_id[1] =
1239 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
1240 cpu->hyperv_interface_id[2] =
1241 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
1242 cpu->hyperv_interface_id[3] =
1243 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
1244
1245 cpu->hyperv_version_id[0] =
1246 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
1247 cpu->hyperv_version_id[1] =
1248 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX);
1249 cpu->hyperv_version_id[2] =
1250 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
1251 cpu->hyperv_version_id[3] =
1252 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX);
1253
1254 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
1255 R_EAX);
1256 cpu->hyperv_limits[0] =
1257 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
1258 cpu->hyperv_limits[1] =
1259 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
1260 cpu->hyperv_limits[2] =
1261 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
1262
1263 cpu->hyperv_spinlock_attempts =
1264 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
1265 }
1266
1267 /* Features */
1268 r = hv_cpuid_check_and_set(cs, HYPERV_FEAT_RELAXED);
1269 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_VAPIC);
1270 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_TIME);
1271 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_CRASH);
1272 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_RESET);
1273 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_VPINDEX);
1274 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_RUNTIME);
1275 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_SYNIC);
1276 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_STIMER);
1277 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_FREQUENCIES);
1278 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_REENLIGHTENMENT);
1279 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_TLBFLUSH);
1280 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_EVMCS);
1281 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_IPI);
1282 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_STIMER_DIRECT);
1283
1284 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1285 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1286 !cpu->hyperv_synic_kvm_only &&
1287 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1288 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
1289 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1290 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1291 r |= 1;
1292 }
1293
1294 if (r) {
1295 return -ENOSYS;
1296 }
1297
1298 c = &cpuid_ent[cpuid_i++];
1299 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1300 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1301 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1302 c->ebx = cpu->hyperv_vendor_id[0];
1303 c->ecx = cpu->hyperv_vendor_id[1];
1304 c->edx = cpu->hyperv_vendor_id[2];
1305
1306 c = &cpuid_ent[cpuid_i++];
1307 c->function = HV_CPUID_INTERFACE;
1308 c->eax = cpu->hyperv_interface_id[0];
1309 c->ebx = cpu->hyperv_interface_id[1];
1310 c->ecx = cpu->hyperv_interface_id[2];
1311 c->edx = cpu->hyperv_interface_id[3];
1312
1313 c = &cpuid_ent[cpuid_i++];
1314 c->function = HV_CPUID_VERSION;
1315 c->eax = cpu->hyperv_version_id[0];
1316 c->ebx = cpu->hyperv_version_id[1];
1317 c->ecx = cpu->hyperv_version_id[2];
1318 c->edx = cpu->hyperv_version_id[3];
1319
1320 c = &cpuid_ent[cpuid_i++];
1321 c->function = HV_CPUID_FEATURES;
1322 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1323 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1324 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
1325
1326 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1327 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1328
1329 c = &cpuid_ent[cpuid_i++];
1330 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1331 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
1332 c->ebx = cpu->hyperv_spinlock_attempts;
1333
1334 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1335 c->eax |= HV_NO_NONARCH_CORESHARING;
1336 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1337 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
1338 HV_NO_NONARCH_CORESHARING;
1339 }
1340
1341 c = &cpuid_ent[cpuid_i++];
1342 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1343 c->eax = cpu->hv_max_vps;
1344 c->ebx = cpu->hyperv_limits[0];
1345 c->ecx = cpu->hyperv_limits[1];
1346 c->edx = cpu->hyperv_limits[2];
1347
1348 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1349 __u32 function;
1350
1351 /* Create zeroed 0x40000006..0x40000009 leaves */
1352 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1353 function < HV_CPUID_NESTED_FEATURES; function++) {
1354 c = &cpuid_ent[cpuid_i++];
1355 c->function = function;
1356 }
1357
1358 c = &cpuid_ent[cpuid_i++];
1359 c->function = HV_CPUID_NESTED_FEATURES;
1360 c->eax = cpu->hyperv_nested[0];
1361 }
1362
1363 return cpuid_i;
1364 }
1365
1366 static Error *hv_passthrough_mig_blocker;
1367 static Error *hv_no_nonarch_cs_mig_blocker;
1368
1369 static int hyperv_init_vcpu(X86CPU *cpu)
1370 {
1371 CPUState *cs = CPU(cpu);
1372 Error *local_err = NULL;
1373 int ret;
1374
1375 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1376 error_setg(&hv_passthrough_mig_blocker,
1377 "'hv-passthrough' CPU flag prevents migration, use explicit"
1378 " set of hv-* flags instead");
1379 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1380 if (local_err) {
1381 error_report_err(local_err);
1382 error_free(hv_passthrough_mig_blocker);
1383 return ret;
1384 }
1385 }
1386
1387 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1388 hv_no_nonarch_cs_mig_blocker == NULL) {
1389 error_setg(&hv_no_nonarch_cs_mig_blocker,
1390 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1391 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1392 " make sure SMT is disabled and/or that vCPUs are properly"
1393 " pinned)");
1394 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
1395 if (local_err) {
1396 error_report_err(local_err);
1397 error_free(hv_no_nonarch_cs_mig_blocker);
1398 return ret;
1399 }
1400 }
1401
1402 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1403 /*
1404 * the kernel doesn't support setting vp_index; assert that its value
1405 * is in sync
1406 */
1407 struct {
1408 struct kvm_msrs info;
1409 struct kvm_msr_entry entries[1];
1410 } msr_data = {
1411 .info.nmsrs = 1,
1412 .entries[0].index = HV_X64_MSR_VP_INDEX,
1413 };
1414
1415 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
1416 if (ret < 0) {
1417 return ret;
1418 }
1419 assert(ret == 1);
1420
1421 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
1422 error_report("kernel's vp_index != QEMU's vp_index");
1423 return -ENXIO;
1424 }
1425 }
1426
1427 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1428 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1429 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1430 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1431 if (ret < 0) {
1432 error_report("failed to turn on HyperV SynIC in KVM: %s",
1433 strerror(-ret));
1434 return ret;
1435 }
1436
1437 if (!cpu->hyperv_synic_kvm_only) {
1438 ret = hyperv_x86_synic_add(cpu);
1439 if (ret < 0) {
1440 error_report("failed to create HyperV SynIC: %s",
1441 strerror(-ret));
1442 return ret;
1443 }
1444 }
1445 }
1446
1447 return 0;
1448 }
1449
1450 static Error *invtsc_mig_blocker;
1451
1452 #define KVM_MAX_CPUID_ENTRIES 100
1453
1454 int kvm_arch_init_vcpu(CPUState *cs)
1455 {
1456 struct {
1457 struct kvm_cpuid2 cpuid;
1458 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
1459 } cpuid_data;
1460 /*
1461 * The kernel defines these structs with padding fields so there
1462 * should be no extra padding in our cpuid_data struct.
1463 */
1464 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1465 sizeof(struct kvm_cpuid2) +
1466 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1467
1468 X86CPU *cpu = X86_CPU(cs);
1469 CPUX86State *env = &cpu->env;
1470 uint32_t limit, i, j, cpuid_i;
1471 uint32_t unused;
1472 struct kvm_cpuid_entry2 *c;
1473 uint32_t signature[3];
1474 int kvm_base = KVM_CPUID_SIGNATURE;
1475 int max_nested_state_len;
1476 int r;
1477 Error *local_err = NULL;
1478
1479 memset(&cpuid_data, 0, sizeof(cpuid_data));
1480
1481 cpuid_i = 0;
1482
1483 r = kvm_arch_set_tsc_khz(cs);
1484 if (r < 0) {
1485 return r;
1486 }
1487
1488 /* vcpu's TSC frequency is either specified by user, or following
1489 * the value used by KVM if the former is not present. In the
1490 * latter case, we query it from KVM and record in env->tsc_khz,
1491 * so that vcpu's TSC frequency can be migrated later via this field.
1492 */
1493 if (!env->tsc_khz) {
1494 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1495 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1496 -ENOTSUP;
1497 if (r > 0) {
1498 env->tsc_khz = r;
1499 }
1500 }
1501
1502 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1503
1504 /* Paravirtualization CPUIDs */
1505 r = hyperv_handle_properties(cs, cpuid_data.entries);
1506 if (r < 0) {
1507 return r;
1508 } else if (r > 0) {
1509 cpuid_i = r;
1510 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
1511 has_msr_hv_hypercall = true;
1512 }
1513
1514 if (cpu->expose_kvm) {
1515 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1516 c = &cpuid_data.entries[cpuid_i++];
1517 c->function = KVM_CPUID_SIGNATURE | kvm_base;
1518 c->eax = KVM_CPUID_FEATURES | kvm_base;
1519 c->ebx = signature[0];
1520 c->ecx = signature[1];
1521 c->edx = signature[2];
1522
1523 c = &cpuid_data.entries[cpuid_i++];
1524 c->function = KVM_CPUID_FEATURES | kvm_base;
1525 c->eax = env->features[FEAT_KVM];
1526 c->edx = env->features[FEAT_KVM_HINTS];
1527 }
1528
1529 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1530
1531 for (i = 0; i <= limit; i++) {
1532 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1533 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1534 abort();
1535 }
1536 c = &cpuid_data.entries[cpuid_i++];
1537
1538 switch (i) {
1539 case 2: {
1540 /* Keep reading function 2 till all the input is received */
1541 int times;
1542
1543 c->function = i;
1544 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1545 KVM_CPUID_FLAG_STATE_READ_NEXT;
1546 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1547 times = c->eax & 0xff;
1548
1549 for (j = 1; j < times; ++j) {
1550 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1551 fprintf(stderr, "cpuid_data is full, no space for "
1552 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1553 abort();
1554 }
1555 c = &cpuid_data.entries[cpuid_i++];
1556 c->function = i;
1557 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1558 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1559 }
1560 break;
1561 }
1562 case 0x1f:
1563 if (env->nr_dies < 2) {
1564 break;
1565 }
1566 /* fallthrough */
1567 case 4:
1568 case 0xb:
1569 case 0xd:
1570 for (j = 0; ; j++) {
1571 if (i == 0xd && j == 64) {
1572 break;
1573 }
1574
1575 if (i == 0x1f && j == 64) {
1576 break;
1577 }
1578
1579 c->function = i;
1580 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1581 c->index = j;
1582 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1583
1584 if (i == 4 && c->eax == 0) {
1585 break;
1586 }
1587 if (i == 0xb && !(c->ecx & 0xff00)) {
1588 break;
1589 }
1590 if (i == 0x1f && !(c->ecx & 0xff00)) {
1591 break;
1592 }
1593 if (i == 0xd && c->eax == 0) {
1594 continue;
1595 }
1596 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1597 fprintf(stderr, "cpuid_data is full, no space for "
1598 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1599 abort();
1600 }
1601 c = &cpuid_data.entries[cpuid_i++];
1602 }
1603 break;
1604 case 0x7:
1605 case 0x14: {
1606 uint32_t times;
1607
1608 c->function = i;
1609 c->index = 0;
1610 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1611 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1612 times = c->eax;
1613
1614 for (j = 1; j <= times; ++j) {
1615 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1616 fprintf(stderr, "cpuid_data is full, no space for "
1617 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1618 abort();
1619 }
1620 c = &cpuid_data.entries[cpuid_i++];
1621 c->function = i;
1622 c->index = j;
1623 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1624 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1625 }
1626 break;
1627 }
1628 default:
1629 c->function = i;
1630 c->flags = 0;
1631 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1632 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1633 /*
1634 * KVM already returns all zeroes if a CPUID entry is missing,
1635 * so we can omit it and avoid hitting KVM's 80-entry limit.
1636 */
1637 cpuid_i--;
1638 }
1639 break;
1640 }
1641 }
1642
1643 if (limit >= 0x0a) {
1644 uint32_t eax, edx;
1645
1646 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1647
1648 has_architectural_pmu_version = eax & 0xff;
1649 if (has_architectural_pmu_version > 0) {
1650 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1651
1652 /* Shouldn't be more than 32, since that's the number of bits
1653 * available in EBX to tell us _which_ counters are available.
1654 * Play it safe.
1655 */
1656 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1657 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1658 }
1659
1660 if (has_architectural_pmu_version > 1) {
1661 num_architectural_pmu_fixed_counters = edx & 0x1f;
1662
1663 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1664 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1665 }
1666 }
1667 }
1668 }
1669
1670 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1671
1672 for (i = 0x80000000; i <= limit; i++) {
1673 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1674 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1675 abort();
1676 }
1677 c = &cpuid_data.entries[cpuid_i++];
1678
1679 switch (i) {
1680 case 0x8000001d:
1681 /* Query for all AMD cache information leaves */
1682 for (j = 0; ; j++) {
1683 c->function = i;
1684 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1685 c->index = j;
1686 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1687
1688 if (c->eax == 0) {
1689 break;
1690 }
1691 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1692 fprintf(stderr, "cpuid_data is full, no space for "
1693 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1694 abort();
1695 }
1696 c = &cpuid_data.entries[cpuid_i++];
1697 }
1698 break;
1699 default:
1700 c->function = i;
1701 c->flags = 0;
1702 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1703 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1704 /*
1705 * KVM already returns all zeroes if a CPUID entry is missing,
1706 * so we can omit it and avoid hitting KVM's 80-entry limit.
1707 */
1708 cpuid_i--;
1709 }
1710 break;
1711 }
1712 }
1713
1714 /* Call Centaur's CPUID instructions they are supported. */
1715 if (env->cpuid_xlevel2 > 0) {
1716 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1717
1718 for (i = 0xC0000000; i <= limit; i++) {
1719 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1720 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1721 abort();
1722 }
1723 c = &cpuid_data.entries[cpuid_i++];
1724
1725 c->function = i;
1726 c->flags = 0;
1727 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1728 }
1729 }
1730
1731 cpuid_data.cpuid.nent = cpuid_i;
1732
1733 if (((env->cpuid_version >> 8)&0xF) >= 6
1734 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1735 (CPUID_MCE | CPUID_MCA)
1736 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1737 uint64_t mcg_cap, unsupported_caps;
1738 int banks;
1739 int ret;
1740
1741 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1742 if (ret < 0) {
1743 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1744 return ret;
1745 }
1746
1747 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1748 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1749 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1750 return -ENOTSUP;
1751 }
1752
1753 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1754 if (unsupported_caps) {
1755 if (unsupported_caps & MCG_LMCE_P) {
1756 error_report("kvm: LMCE not supported");
1757 return -ENOTSUP;
1758 }
1759 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1760 unsupported_caps);
1761 }
1762
1763 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1764 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1765 if (ret < 0) {
1766 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1767 return ret;
1768 }
1769 }
1770
1771 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
1772
1773 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1774 if (c) {
1775 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1776 !!(c->ecx & CPUID_EXT_SMX);
1777 }
1778
1779 if (env->mcg_cap & MCG_LMCE_P) {
1780 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1781 }
1782
1783 if (!env->user_tsc_khz) {
1784 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1785 invtsc_mig_blocker == NULL) {
1786 error_setg(&invtsc_mig_blocker,
1787 "State blocked by non-migratable CPU device"
1788 " (invtsc flag)");
1789 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1790 if (local_err) {
1791 error_report_err(local_err);
1792 error_free(invtsc_mig_blocker);
1793 return r;
1794 }
1795 }
1796 }
1797
1798 if (cpu->vmware_cpuid_freq
1799 /* Guests depend on 0x40000000 to detect this feature, so only expose
1800 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1801 && cpu->expose_kvm
1802 && kvm_base == KVM_CPUID_SIGNATURE
1803 /* TSC clock must be stable and known for this feature. */
1804 && tsc_is_stable_and_known(env)) {
1805
1806 c = &cpuid_data.entries[cpuid_i++];
1807 c->function = KVM_CPUID_SIGNATURE | 0x10;
1808 c->eax = env->tsc_khz;
1809 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
1810 c->ecx = c->edx = 0;
1811
1812 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1813 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1814 }
1815
1816 cpuid_data.cpuid.nent = cpuid_i;
1817
1818 cpuid_data.cpuid.padding = 0;
1819 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1820 if (r) {
1821 goto fail;
1822 }
1823
1824 if (has_xsave) {
1825 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1826 memset(env->xsave_buf, 0, sizeof(struct kvm_xsave));
1827 }
1828
1829 max_nested_state_len = kvm_max_nested_state_length();
1830 if (max_nested_state_len > 0) {
1831 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
1832
1833 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
1834 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1835
1836 env->nested_state = g_malloc0(max_nested_state_len);
1837 env->nested_state->size = max_nested_state_len;
1838
1839 if (cpu_has_vmx(env)) {
1840 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1841 vmx_hdr = &env->nested_state->hdr.vmx;
1842 vmx_hdr->vmxon_pa = -1ull;
1843 vmx_hdr->vmcs12_pa = -1ull;
1844 } else {
1845 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1846 }
1847 }
1848 }
1849
1850 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1851
1852 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1853 has_msr_tsc_aux = false;
1854 }
1855
1856 kvm_init_msrs(cpu);
1857
1858 r = hyperv_init_vcpu(cpu);
1859 if (r) {
1860 goto fail;
1861 }
1862
1863 return 0;
1864
1865 fail:
1866 migrate_del_blocker(invtsc_mig_blocker);
1867
1868 return r;
1869 }
1870
1871 int kvm_arch_destroy_vcpu(CPUState *cs)
1872 {
1873 X86CPU *cpu = X86_CPU(cs);
1874 CPUX86State *env = &cpu->env;
1875
1876 if (cpu->kvm_msr_buf) {
1877 g_free(cpu->kvm_msr_buf);
1878 cpu->kvm_msr_buf = NULL;
1879 }
1880
1881 if (env->nested_state) {
1882 g_free(env->nested_state);
1883 env->nested_state = NULL;
1884 }
1885
1886 qemu_del_vm_change_state_handler(cpu->vmsentry);
1887
1888 return 0;
1889 }
1890
1891 void kvm_arch_reset_vcpu(X86CPU *cpu)
1892 {
1893 CPUX86State *env = &cpu->env;
1894
1895 env->xcr0 = 1;
1896 if (kvm_irqchip_in_kernel()) {
1897 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1898 KVM_MP_STATE_UNINITIALIZED;
1899 } else {
1900 env->mp_state = KVM_MP_STATE_RUNNABLE;
1901 }
1902
1903 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1904 int i;
1905 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1906 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1907 }
1908
1909 hyperv_x86_synic_reset(cpu);
1910 }
1911 /* enabled by default */
1912 env->poll_control_msr = 1;
1913
1914 sev_es_set_reset_vector(CPU(cpu));
1915 }
1916
1917 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1918 {
1919 CPUX86State *env = &cpu->env;
1920
1921 /* APs get directly into wait-for-SIPI state. */
1922 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1923 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1924 }
1925 }
1926
1927 static int kvm_get_supported_feature_msrs(KVMState *s)
1928 {
1929 int ret = 0;
1930
1931 if (kvm_feature_msrs != NULL) {
1932 return 0;
1933 }
1934
1935 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1936 return 0;
1937 }
1938
1939 struct kvm_msr_list msr_list;
1940
1941 msr_list.nmsrs = 0;
1942 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1943 if (ret < 0 && ret != -E2BIG) {
1944 error_report("Fetch KVM feature MSR list failed: %s",
1945 strerror(-ret));
1946 return ret;
1947 }
1948
1949 assert(msr_list.nmsrs > 0);
1950 kvm_feature_msrs = (struct kvm_msr_list *) \
1951 g_malloc0(sizeof(msr_list) +
1952 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1953
1954 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1955 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1956
1957 if (ret < 0) {
1958 error_report("Fetch KVM feature MSR list failed: %s",
1959 strerror(-ret));
1960 g_free(kvm_feature_msrs);
1961 kvm_feature_msrs = NULL;
1962 return ret;
1963 }
1964
1965 return 0;
1966 }
1967
1968 static int kvm_get_supported_msrs(KVMState *s)
1969 {
1970 int ret = 0;
1971 struct kvm_msr_list msr_list, *kvm_msr_list;
1972
1973 /*
1974 * Obtain MSR list from KVM. These are the MSRs that we must
1975 * save/restore.
1976 */
1977 msr_list.nmsrs = 0;
1978 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1979 if (ret < 0 && ret != -E2BIG) {
1980 return ret;
1981 }
1982 /*
1983 * Old kernel modules had a bug and could write beyond the provided
1984 * memory. Allocate at least a safe amount of 1K.
1985 */
1986 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1987 msr_list.nmsrs *
1988 sizeof(msr_list.indices[0])));
1989
1990 kvm_msr_list->nmsrs = msr_list.nmsrs;
1991 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1992 if (ret >= 0) {
1993 int i;
1994
1995 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1996 switch (kvm_msr_list->indices[i]) {
1997 case MSR_STAR:
1998 has_msr_star = true;
1999 break;
2000 case MSR_VM_HSAVE_PA:
2001 has_msr_hsave_pa = true;
2002 break;
2003 case MSR_TSC_AUX:
2004 has_msr_tsc_aux = true;
2005 break;
2006 case MSR_TSC_ADJUST:
2007 has_msr_tsc_adjust = true;
2008 break;
2009 case MSR_IA32_TSCDEADLINE:
2010 has_msr_tsc_deadline = true;
2011 break;
2012 case MSR_IA32_SMBASE:
2013 has_msr_smbase = true;
2014 break;
2015 case MSR_SMI_COUNT:
2016 has_msr_smi_count = true;
2017 break;
2018 case MSR_IA32_MISC_ENABLE:
2019 has_msr_misc_enable = true;
2020 break;
2021 case MSR_IA32_BNDCFGS:
2022 has_msr_bndcfgs = true;
2023 break;
2024 case MSR_IA32_XSS:
2025 has_msr_xss = true;
2026 break;
2027 case MSR_IA32_UMWAIT_CONTROL:
2028 has_msr_umwait = true;
2029 break;
2030 case HV_X64_MSR_CRASH_CTL:
2031 has_msr_hv_crash = true;
2032 break;
2033 case HV_X64_MSR_RESET:
2034 has_msr_hv_reset = true;
2035 break;
2036 case HV_X64_MSR_VP_INDEX:
2037 has_msr_hv_vpindex = true;
2038 break;
2039 case HV_X64_MSR_VP_RUNTIME:
2040 has_msr_hv_runtime = true;
2041 break;
2042 case HV_X64_MSR_SCONTROL:
2043 has_msr_hv_synic = true;
2044 break;
2045 case HV_X64_MSR_STIMER0_CONFIG:
2046 has_msr_hv_stimer = true;
2047 break;
2048 case HV_X64_MSR_TSC_FREQUENCY:
2049 has_msr_hv_frequencies = true;
2050 break;
2051 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2052 has_msr_hv_reenlightenment = true;
2053 break;
2054 case MSR_IA32_SPEC_CTRL:
2055 has_msr_spec_ctrl = true;
2056 break;
2057 case MSR_IA32_TSX_CTRL:
2058 has_msr_tsx_ctrl = true;
2059 break;
2060 case MSR_VIRT_SSBD:
2061 has_msr_virt_ssbd = true;
2062 break;
2063 case MSR_IA32_ARCH_CAPABILITIES:
2064 has_msr_arch_capabs = true;
2065 break;
2066 case MSR_IA32_CORE_CAPABILITY:
2067 has_msr_core_capabs = true;
2068 break;
2069 case MSR_IA32_PERF_CAPABILITIES:
2070 has_msr_perf_capabs = true;
2071 break;
2072 case MSR_IA32_VMX_VMFUNC:
2073 has_msr_vmx_vmfunc = true;
2074 break;
2075 case MSR_IA32_UCODE_REV:
2076 has_msr_ucode_rev = true;
2077 break;
2078 case MSR_IA32_VMX_PROCBASED_CTLS2:
2079 has_msr_vmx_procbased_ctls2 = true;
2080 break;
2081 case MSR_IA32_PKRS:
2082 has_msr_pkrs = true;
2083 break;
2084 }
2085 }
2086 }
2087
2088 g_free(kvm_msr_list);
2089
2090 return ret;
2091 }
2092
2093 static Notifier smram_machine_done;
2094 static KVMMemoryListener smram_listener;
2095 static AddressSpace smram_address_space;
2096 static MemoryRegion smram_as_root;
2097 static MemoryRegion smram_as_mem;
2098
2099 static void register_smram_listener(Notifier *n, void *unused)
2100 {
2101 MemoryRegion *smram =
2102 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2103
2104 /* Outer container... */
2105 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2106 memory_region_set_enabled(&smram_as_root, true);
2107
2108 /* ... with two regions inside: normal system memory with low
2109 * priority, and...
2110 */
2111 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2112 get_system_memory(), 0, ~0ull);
2113 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2114 memory_region_set_enabled(&smram_as_mem, true);
2115
2116 if (smram) {
2117 /* ... SMRAM with higher priority */
2118 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2119 memory_region_set_enabled(smram, true);
2120 }
2121
2122 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2123 kvm_memory_listener_register(kvm_state, &smram_listener,
2124 &smram_address_space, 1);
2125 }
2126
2127 int kvm_arch_init(MachineState *ms, KVMState *s)
2128 {
2129 uint64_t identity_base = 0xfffbc000;
2130 uint64_t shadow_mem;
2131 int ret;
2132 struct utsname utsname;
2133 Error *local_err = NULL;
2134
2135 /*
2136 * Initialize SEV context, if required
2137 *
2138 * If no memory encryption is requested (ms->cgs == NULL) this is
2139 * a no-op.
2140 *
2141 * It's also a no-op if a non-SEV confidential guest support
2142 * mechanism is selected. SEV is the only mechanism available to
2143 * select on x86 at present, so this doesn't arise, but if new
2144 * mechanisms are supported in future (e.g. TDX), they'll need
2145 * their own initialization either here or elsewhere.
2146 */
2147 ret = sev_kvm_init(ms->cgs, &local_err);
2148 if (ret < 0) {
2149 error_report_err(local_err);
2150 return ret;
2151 }
2152
2153 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2154 error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM");
2155 return -ENOTSUP;
2156 }
2157
2158 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
2159 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
2160 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
2161
2162 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2163
2164 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2165 if (has_exception_payload) {
2166 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2167 if (ret < 0) {
2168 error_report("kvm: Failed to enable exception payload cap: %s",
2169 strerror(-ret));
2170 return ret;
2171 }
2172 }
2173
2174 ret = kvm_get_supported_msrs(s);
2175 if (ret < 0) {
2176 return ret;
2177 }
2178
2179 kvm_get_supported_feature_msrs(s);
2180
2181 uname(&utsname);
2182 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2183
2184 /*
2185 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2186 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2187 * Since these must be part of guest physical memory, we need to allocate
2188 * them, both by setting their start addresses in the kernel and by
2189 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2190 *
2191 * Older KVM versions may not support setting the identity map base. In
2192 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2193 * size.
2194 */
2195 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2196 /* Allows up to 16M BIOSes. */
2197 identity_base = 0xfeffc000;
2198
2199 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2200 if (ret < 0) {
2201 return ret;
2202 }
2203 }
2204
2205 /* Set TSS base one page after EPT identity map. */
2206 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
2207 if (ret < 0) {
2208 return ret;
2209 }
2210
2211 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2212 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
2213 if (ret < 0) {
2214 fprintf(stderr, "e820_add_entry() table is full\n");
2215 return ret;
2216 }
2217
2218 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
2219 if (shadow_mem != -1) {
2220 shadow_mem /= 4096;
2221 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2222 if (ret < 0) {
2223 return ret;
2224 }
2225 }
2226
2227 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2228 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
2229 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
2230 smram_machine_done.notify = register_smram_listener;
2231 qemu_add_machine_init_done_notifier(&smram_machine_done);
2232 }
2233
2234 if (enable_cpu_pm) {
2235 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2236 int ret;
2237
2238 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2239 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2240 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2241 #endif
2242 if (disable_exits) {
2243 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2244 KVM_X86_DISABLE_EXITS_HLT |
2245 KVM_X86_DISABLE_EXITS_PAUSE |
2246 KVM_X86_DISABLE_EXITS_CSTATE);
2247 }
2248
2249 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2250 disable_exits);
2251 if (ret < 0) {
2252 error_report("kvm: guest stopping CPU not supported: %s",
2253 strerror(-ret));
2254 }
2255 }
2256
2257 return 0;
2258 }
2259
2260 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2261 {
2262 lhs->selector = rhs->selector;
2263 lhs->base = rhs->base;
2264 lhs->limit = rhs->limit;
2265 lhs->type = 3;
2266 lhs->present = 1;
2267 lhs->dpl = 3;
2268 lhs->db = 0;
2269 lhs->s = 1;
2270 lhs->l = 0;
2271 lhs->g = 0;
2272 lhs->avl = 0;
2273 lhs->unusable = 0;
2274 }
2275
2276 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2277 {
2278 unsigned flags = rhs->flags;
2279 lhs->selector = rhs->selector;
2280 lhs->base = rhs->base;
2281 lhs->limit = rhs->limit;
2282 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2283 lhs->present = (flags & DESC_P_MASK) != 0;
2284 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
2285 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2286 lhs->s = (flags & DESC_S_MASK) != 0;
2287 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2288 lhs->g = (flags & DESC_G_MASK) != 0;
2289 lhs->avl = (flags & DESC_AVL_MASK) != 0;
2290 lhs->unusable = !lhs->present;
2291 lhs->padding = 0;
2292 }
2293
2294 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2295 {
2296 lhs->selector = rhs->selector;
2297 lhs->base = rhs->base;
2298 lhs->limit = rhs->limit;
2299 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2300 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2301 (rhs->dpl << DESC_DPL_SHIFT) |
2302 (rhs->db << DESC_B_SHIFT) |
2303 (rhs->s * DESC_S_MASK) |
2304 (rhs->l << DESC_L_SHIFT) |
2305 (rhs->g * DESC_G_MASK) |
2306 (rhs->avl * DESC_AVL_MASK);
2307 }
2308
2309 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2310 {
2311 if (set) {
2312 *kvm_reg = *qemu_reg;
2313 } else {
2314 *qemu_reg = *kvm_reg;
2315 }
2316 }
2317
2318 static int kvm_getput_regs(X86CPU *cpu, int set)
2319 {
2320 CPUX86State *env = &cpu->env;
2321 struct kvm_regs regs;
2322 int ret = 0;
2323
2324 if (!set) {
2325 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
2326 if (ret < 0) {
2327 return ret;
2328 }
2329 }
2330
2331 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2332 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2333 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2334 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2335 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2336 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2337 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2338 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2339 #ifdef TARGET_X86_64
2340 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2341 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2342 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2343 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2344 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2345 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2346 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2347 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2348 #endif
2349
2350 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2351 kvm_getput_reg(&regs.rip, &env->eip, set);
2352
2353 if (set) {
2354 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
2355 }
2356
2357 return ret;
2358 }
2359
2360 static int kvm_put_fpu(X86CPU *cpu)
2361 {
2362 CPUX86State *env = &cpu->env;
2363 struct kvm_fpu fpu;
2364 int i;
2365
2366 memset(&fpu, 0, sizeof fpu);
2367 fpu.fsw = env->fpus & ~(7 << 11);
2368 fpu.fsw |= (env->fpstt & 7) << 11;
2369 fpu.fcw = env->fpuc;
2370 fpu.last_opcode = env->fpop;
2371 fpu.last_ip = env->fpip;
2372 fpu.last_dp = env->fpdp;
2373 for (i = 0; i < 8; ++i) {
2374 fpu.ftwx |= (!env->fptags[i]) << i;
2375 }
2376 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
2377 for (i = 0; i < CPU_NB_REGS; i++) {
2378 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2379 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
2380 }
2381 fpu.mxcsr = env->mxcsr;
2382
2383 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
2384 }
2385
2386 #define XSAVE_FCW_FSW 0
2387 #define XSAVE_FTW_FOP 1
2388 #define XSAVE_CWD_RIP 2
2389 #define XSAVE_CWD_RDP 4
2390 #define XSAVE_MXCSR 6
2391 #define XSAVE_ST_SPACE 8
2392 #define XSAVE_XMM_SPACE 40
2393 #define XSAVE_XSTATE_BV 128
2394 #define XSAVE_YMMH_SPACE 144
2395 #define XSAVE_BNDREGS 240
2396 #define XSAVE_BNDCSR 256
2397 #define XSAVE_OPMASK 272
2398 #define XSAVE_ZMM_Hi256 288
2399 #define XSAVE_Hi16_ZMM 416
2400 #define XSAVE_PKRU 672
2401
2402 #define XSAVE_BYTE_OFFSET(word_offset) \
2403 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
2404
2405 #define ASSERT_OFFSET(word_offset, field) \
2406 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2407 offsetof(X86XSaveArea, field))
2408
2409 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2410 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2411 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2412 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2413 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2414 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2415 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2416 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2417 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2418 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2419 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2420 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2421 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2422 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2423 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2424
2425 static int kvm_put_xsave(X86CPU *cpu)
2426 {
2427 CPUX86State *env = &cpu->env;
2428 X86XSaveArea *xsave = env->xsave_buf;
2429
2430 if (!has_xsave) {
2431 return kvm_put_fpu(cpu);
2432 }
2433 x86_cpu_xsave_all_areas(cpu, xsave);
2434
2435 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
2436 }
2437
2438 static int kvm_put_xcrs(X86CPU *cpu)
2439 {
2440 CPUX86State *env = &cpu->env;
2441 struct kvm_xcrs xcrs = {};
2442
2443 if (!has_xcrs) {
2444 return 0;
2445 }
2446
2447 xcrs.nr_xcrs = 1;
2448 xcrs.flags = 0;
2449 xcrs.xcrs[0].xcr = 0;
2450 xcrs.xcrs[0].value = env->xcr0;
2451 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
2452 }
2453
2454 static int kvm_put_sregs(X86CPU *cpu)
2455 {
2456 CPUX86State *env = &cpu->env;
2457 struct kvm_sregs sregs;
2458
2459 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2460 if (env->interrupt_injected >= 0) {
2461 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2462 (uint64_t)1 << (env->interrupt_injected % 64);
2463 }
2464
2465 if ((env->eflags & VM_MASK)) {
2466 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2467 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2468 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2469 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2470 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2471 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2472 } else {
2473 set_seg(&sregs.cs, &env->segs[R_CS]);
2474 set_seg(&sregs.ds, &env->segs[R_DS]);
2475 set_seg(&sregs.es, &env->segs[R_ES]);
2476 set_seg(&sregs.fs, &env->segs[R_FS]);
2477 set_seg(&sregs.gs, &env->segs[R_GS]);
2478 set_seg(&sregs.ss, &env->segs[R_SS]);
2479 }
2480
2481 set_seg(&sregs.tr, &env->tr);
2482 set_seg(&sregs.ldt, &env->ldt);
2483
2484 sregs.idt.limit = env->idt.limit;
2485 sregs.idt.base = env->idt.base;
2486 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2487 sregs.gdt.limit = env->gdt.limit;
2488 sregs.gdt.base = env->gdt.base;
2489 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2490
2491 sregs.cr0 = env->cr[0];
2492 sregs.cr2 = env->cr[2];
2493 sregs.cr3 = env->cr[3];
2494 sregs.cr4 = env->cr[4];
2495
2496 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2497 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2498
2499 sregs.efer = env->efer;
2500
2501 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
2502 }
2503
2504 static void kvm_msr_buf_reset(X86CPU *cpu)
2505 {
2506 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2507 }
2508
2509 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2510 {
2511 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2512 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2513 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2514
2515 assert((void *)(entry + 1) <= limit);
2516
2517 entry->index = index;
2518 entry->reserved = 0;
2519 entry->data = value;
2520 msrs->nmsrs++;
2521 }
2522
2523 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2524 {
2525 kvm_msr_buf_reset(cpu);
2526 kvm_msr_entry_add(cpu, index, value);
2527
2528 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2529 }
2530
2531 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2532 {
2533 int ret;
2534
2535 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2536 assert(ret == 1);
2537 }
2538
2539 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2540 {
2541 CPUX86State *env = &cpu->env;
2542 int ret;
2543
2544 if (!has_msr_tsc_deadline) {
2545 return 0;
2546 }
2547
2548 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
2549 if (ret < 0) {
2550 return ret;
2551 }
2552
2553 assert(ret == 1);
2554 return 0;
2555 }
2556
2557 /*
2558 * Provide a separate write service for the feature control MSR in order to
2559 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2560 * before writing any other state because forcibly leaving nested mode
2561 * invalidates the VCPU state.
2562 */
2563 static int kvm_put_msr_feature_control(X86CPU *cpu)
2564 {
2565 int ret;
2566
2567 if (!has_msr_feature_control) {
2568 return 0;
2569 }
2570
2571 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2572 cpu->env.msr_ia32_feature_control);
2573 if (ret < 0) {
2574 return ret;
2575 }
2576
2577 assert(ret == 1);
2578 return 0;
2579 }
2580
2581 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2582 {
2583 uint32_t default1, can_be_one, can_be_zero;
2584 uint32_t must_be_one;
2585
2586 switch (index) {
2587 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2588 default1 = 0x00000016;
2589 break;
2590 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2591 default1 = 0x0401e172;
2592 break;
2593 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2594 default1 = 0x000011ff;
2595 break;
2596 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2597 default1 = 0x00036dff;
2598 break;
2599 case MSR_IA32_VMX_PROCBASED_CTLS2:
2600 default1 = 0;
2601 break;
2602 default:
2603 abort();
2604 }
2605
2606 /* If a feature bit is set, the control can be either set or clear.
2607 * Otherwise the value is limited to either 0 or 1 by default1.
2608 */
2609 can_be_one = features | default1;
2610 can_be_zero = features | ~default1;
2611 must_be_one = ~can_be_zero;
2612
2613 /*
2614 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2615 * Bit 32:63 -> 1 if the control bit can be one.
2616 */
2617 return must_be_one | (((uint64_t)can_be_one) << 32);
2618 }
2619
2620 #define VMCS12_MAX_FIELD_INDEX (0x17)
2621
2622 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2623 {
2624 uint64_t kvm_vmx_basic =
2625 kvm_arch_get_supported_msr_feature(kvm_state,
2626 MSR_IA32_VMX_BASIC);
2627
2628 if (!kvm_vmx_basic) {
2629 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2630 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2631 */
2632 return;
2633 }
2634
2635 uint64_t kvm_vmx_misc =
2636 kvm_arch_get_supported_msr_feature(kvm_state,
2637 MSR_IA32_VMX_MISC);
2638 uint64_t kvm_vmx_ept_vpid =
2639 kvm_arch_get_supported_msr_feature(kvm_state,
2640 MSR_IA32_VMX_EPT_VPID_CAP);
2641
2642 /*
2643 * If the guest is 64-bit, a value of 1 is allowed for the host address
2644 * space size vmexit control.
2645 */
2646 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
2647 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
2648
2649 /*
2650 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2651 * not change them for backwards compatibility.
2652 */
2653 uint64_t fixed_vmx_basic = kvm_vmx_basic &
2654 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
2655 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
2656 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
2657
2658 /*
2659 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2660 * change in the future but are always zero for now, clear them to be
2661 * future proof. Bits 32-63 in theory could change, though KVM does
2662 * not support dual-monitor treatment and probably never will; mask
2663 * them out as well.
2664 */
2665 uint64_t fixed_vmx_misc = kvm_vmx_misc &
2666 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
2667 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
2668
2669 /*
2670 * EPT memory types should not change either, so we do not bother
2671 * adding features for them.
2672 */
2673 uint64_t fixed_vmx_ept_mask =
2674 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
2675 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
2676 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
2677
2678 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2679 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2680 f[FEAT_VMX_PROCBASED_CTLS]));
2681 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2682 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2683 f[FEAT_VMX_PINBASED_CTLS]));
2684 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
2685 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
2686 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
2687 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2688 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2689 f[FEAT_VMX_ENTRY_CTLS]));
2690 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
2691 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
2692 f[FEAT_VMX_SECONDARY_CTLS]));
2693 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
2694 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
2695 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
2696 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
2697 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
2698 f[FEAT_VMX_MISC] | fixed_vmx_misc);
2699 if (has_msr_vmx_vmfunc) {
2700 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
2701 }
2702
2703 /*
2704 * Just to be safe, write these with constant values. The CRn_FIXED1
2705 * MSRs are generated by KVM based on the vCPU's CPUID.
2706 */
2707 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
2708 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
2709 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
2710 CR4_VMXE_MASK);
2711 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM,
2712 VMCS12_MAX_FIELD_INDEX << 1);
2713 }
2714
2715 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
2716 {
2717 uint64_t kvm_perf_cap =
2718 kvm_arch_get_supported_msr_feature(kvm_state,
2719 MSR_IA32_PERF_CAPABILITIES);
2720
2721 if (kvm_perf_cap) {
2722 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
2723 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
2724 }
2725 }
2726
2727 static int kvm_buf_set_msrs(X86CPU *cpu)
2728 {
2729 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2730 if (ret < 0) {
2731 return ret;
2732 }
2733
2734 if (ret < cpu->kvm_msr_buf->nmsrs) {
2735 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2736 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2737 (uint32_t)e->index, (uint64_t)e->data);
2738 }
2739
2740 assert(ret == cpu->kvm_msr_buf->nmsrs);
2741 return 0;
2742 }
2743
2744 static void kvm_init_msrs(X86CPU *cpu)
2745 {
2746 CPUX86State *env = &cpu->env;
2747
2748 kvm_msr_buf_reset(cpu);
2749 if (has_msr_arch_capabs) {
2750 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2751 env->features[FEAT_ARCH_CAPABILITIES]);
2752 }
2753
2754 if (has_msr_core_capabs) {
2755 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2756 env->features[FEAT_CORE_CAPABILITY]);
2757 }
2758
2759 if (has_msr_perf_capabs && cpu->enable_pmu) {
2760 kvm_msr_entry_add_perf(cpu, env->features);
2761 }
2762
2763 if (has_msr_ucode_rev) {
2764 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
2765 }
2766
2767 /*
2768 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2769 * all kernels with MSR features should have them.
2770 */
2771 if (kvm_feature_msrs && cpu_has_vmx(env)) {
2772 kvm_msr_entry_add_vmx(cpu, env->features);
2773 }
2774
2775 assert(kvm_buf_set_msrs(cpu) == 0);
2776 }
2777
2778 static int kvm_put_msrs(X86CPU *cpu, int level)
2779 {
2780 CPUX86State *env = &cpu->env;
2781 int i;
2782
2783 kvm_msr_buf_reset(cpu);
2784
2785 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2786 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2787 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2788 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
2789 if (has_msr_star) {
2790 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
2791 }
2792 if (has_msr_hsave_pa) {
2793 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
2794 }
2795 if (has_msr_tsc_aux) {
2796 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
2797 }
2798 if (has_msr_tsc_adjust) {
2799 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
2800 }
2801 if (has_msr_misc_enable) {
2802 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
2803 env->msr_ia32_misc_enable);
2804 }
2805 if (has_msr_smbase) {
2806 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
2807 }
2808 if (has_msr_smi_count) {
2809 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2810 }
2811 if (has_msr_pkrs) {
2812 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
2813 }
2814 if (has_msr_bndcfgs) {
2815 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
2816 }
2817 if (has_msr_xss) {
2818 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2819 }
2820 if (has_msr_umwait) {
2821 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
2822 }
2823 if (has_msr_spec_ctrl) {
2824 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2825 }
2826 if (has_msr_tsx_ctrl) {
2827 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
2828 }
2829 if (has_msr_virt_ssbd) {
2830 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2831 }
2832
2833 #ifdef TARGET_X86_64
2834 if (lm_capable_kernel) {
2835 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2836 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2837 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2838 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2839 }
2840 #endif
2841
2842 /*
2843 * The following MSRs have side effects on the guest or are too heavy
2844 * for normal writeback. Limit them to reset or full state updates.
2845 */
2846 if (level >= KVM_PUT_RESET_STATE) {
2847 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2848 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2849 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2850 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
2851 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
2852 }
2853 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2854 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2855 }
2856 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2857 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2858 }
2859 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2860 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2861 }
2862
2863 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2864 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2865 }
2866
2867 if (has_architectural_pmu_version > 0) {
2868 if (has_architectural_pmu_version > 1) {
2869 /* Stop the counter. */
2870 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2871 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2872 }
2873
2874 /* Set the counter values. */
2875 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2876 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2877 env->msr_fixed_counters[i]);
2878 }
2879 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2880 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2881 env->msr_gp_counters[i]);
2882 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2883 env->msr_gp_evtsel[i]);
2884 }
2885 if (has_architectural_pmu_version > 1) {
2886 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2887 env->msr_global_status);
2888 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2889 env->msr_global_ovf_ctrl);
2890
2891 /* Now start the PMU. */
2892 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2893 env->msr_fixed_ctr_ctrl);
2894 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2895 env->msr_global_ctrl);
2896 }
2897 }
2898 /*
2899 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2900 * only sync them to KVM on the first cpu
2901 */
2902 if (current_cpu == first_cpu) {
2903 if (has_msr_hv_hypercall) {
2904 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2905 env->msr_hv_guest_os_id);
2906 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2907 env->msr_hv_hypercall);
2908 }
2909 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
2910 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2911 env->msr_hv_tsc);
2912 }
2913 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
2914 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2915 env->msr_hv_reenlightenment_control);
2916 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2917 env->msr_hv_tsc_emulation_control);
2918 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2919 env->msr_hv_tsc_emulation_status);
2920 }
2921 }
2922 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
2923 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2924 env->msr_hv_vapic);
2925 }
2926 if (has_msr_hv_crash) {
2927 int j;
2928
2929 for (j = 0; j < HV_CRASH_PARAMS; j++)
2930 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2931 env->msr_hv_crash_params[j]);
2932
2933 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2934 }
2935 if (has_msr_hv_runtime) {
2936 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2937 }
2938 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2939 && hv_vpindex_settable) {
2940 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2941 hyperv_vp_index(CPU(cpu)));
2942 }
2943 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2944 int j;
2945
2946 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2947
2948 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2949 env->msr_hv_synic_control);
2950 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2951 env->msr_hv_synic_evt_page);
2952 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2953 env->msr_hv_synic_msg_page);
2954
2955 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2956 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2957 env->msr_hv_synic_sint[j]);
2958 }
2959 }
2960 if (has_msr_hv_stimer) {
2961 int j;
2962
2963 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2964 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2965 env->msr_hv_stimer_config[j]);
2966 }
2967
2968 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2969 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2970 env->msr_hv_stimer_count[j]);
2971 }
2972 }
2973 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2974 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2975
2976 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2977 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2978 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2979 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2980 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2981 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2982 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2983 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2984 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2985 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2986 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2987 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2988 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2989 /* The CPU GPs if we write to a bit above the physical limit of
2990 * the host CPU (and KVM emulates that)
2991 */
2992 uint64_t mask = env->mtrr_var[i].mask;
2993 mask &= phys_mask;
2994
2995 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2996 env->mtrr_var[i].base);
2997 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2998 }
2999 }
3000 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3001 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
3002 0x14, 1, R_EAX) & 0x7;
3003
3004 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
3005 env->msr_rtit_ctrl);
3006 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
3007 env->msr_rtit_status);
3008 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
3009 env->msr_rtit_output_base);
3010 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
3011 env->msr_rtit_output_mask);
3012 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
3013 env->msr_rtit_cr3_match);
3014 for (i = 0; i < addr_num; i++) {
3015 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
3016 env->msr_rtit_addrs[i]);
3017 }
3018 }
3019
3020 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
3021 * kvm_put_msr_feature_control. */
3022 }
3023
3024 if (env->mcg_cap) {
3025 int i;
3026
3027 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
3028 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
3029 if (has_msr_mcg_ext_ctl) {
3030 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
3031 }
3032 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
3033 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
3034 }
3035 }
3036
3037 return kvm_buf_set_msrs(cpu);
3038 }
3039
3040
3041 static int kvm_get_fpu(X86CPU *cpu)
3042 {
3043 CPUX86State *env = &cpu->env;
3044 struct kvm_fpu fpu;
3045 int i, ret;
3046
3047 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
3048 if (ret < 0) {
3049 return ret;
3050 }
3051
3052 env->fpstt = (fpu.fsw >> 11) & 7;
3053 env->fpus = fpu.fsw;
3054 env->fpuc = fpu.fcw;
3055 env->fpop = fpu.last_opcode;
3056 env->fpip = fpu.last_ip;
3057 env->fpdp = fpu.last_dp;
3058 for (i = 0; i < 8; ++i) {
3059 env->fptags[i] = !((fpu.ftwx >> i) & 1);
3060 }
3061 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
3062 for (i = 0; i < CPU_NB_REGS; i++) {
3063 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
3064 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
3065 }
3066 env->mxcsr = fpu.mxcsr;
3067
3068 return 0;
3069 }
3070
3071 static int kvm_get_xsave(X86CPU *cpu)
3072 {
3073 CPUX86State *env = &cpu->env;
3074 X86XSaveArea *xsave = env->xsave_buf;
3075 int ret;
3076
3077 if (!has_xsave) {
3078 return kvm_get_fpu(cpu);
3079 }
3080
3081 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
3082 if (ret < 0) {
3083 return ret;
3084 }
3085 x86_cpu_xrstor_all_areas(cpu, xsave);
3086
3087 return 0;
3088 }
3089
3090 static int kvm_get_xcrs(X86CPU *cpu)
3091 {
3092 CPUX86State *env = &cpu->env;
3093 int i, ret;
3094 struct kvm_xcrs xcrs;
3095
3096 if (!has_xcrs) {
3097 return 0;
3098 }
3099
3100 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
3101 if (ret < 0) {
3102 return ret;
3103 }
3104
3105 for (i = 0; i < xcrs.nr_xcrs; i++) {
3106 /* Only support xcr0 now */
3107 if (xcrs.xcrs[i].xcr == 0) {
3108 env->xcr0 = xcrs.xcrs[i].value;
3109 break;
3110 }
3111 }
3112 return 0;
3113 }
3114
3115 static int kvm_get_sregs(X86CPU *cpu)
3116 {
3117 CPUX86State *env = &cpu->env;
3118 struct kvm_sregs sregs;
3119 int bit, i, ret;
3120
3121 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
3122 if (ret < 0) {
3123 return ret;
3124 }
3125
3126 /* There can only be one pending IRQ set in the bitmap at a time, so try
3127 to find it and save its number instead (-1 for none). */
3128 env->interrupt_injected = -1;
3129 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
3130 if (sregs.interrupt_bitmap[i]) {
3131 bit = ctz64(sregs.interrupt_bitmap[i]);
3132 env->interrupt_injected = i * 64 + bit;
3133 break;
3134 }
3135 }
3136
3137 get_seg(&env->segs[R_CS], &sregs.cs);
3138 get_seg(&env->segs[R_DS], &sregs.ds);
3139 get_seg(&env->segs[R_ES], &sregs.es);
3140 get_seg(&env->segs[R_FS], &sregs.fs);
3141 get_seg(&env->segs[R_GS], &sregs.gs);
3142 get_seg(&env->segs[R_SS], &sregs.ss);
3143
3144 get_seg(&env->tr, &sregs.tr);
3145 get_seg(&env->ldt, &sregs.ldt);
3146
3147 env->idt.limit = sregs.idt.limit;
3148 env->idt.base = sregs.idt.base;
3149 env->gdt.limit = sregs.gdt.limit;
3150 env->gdt.base = sregs.gdt.base;
3151
3152 env->cr[0] = sregs.cr0;
3153 env->cr[2] = sregs.cr2;
3154 env->cr[3] = sregs.cr3;
3155 env->cr[4] = sregs.cr4;
3156
3157 env->efer = sregs.efer;
3158
3159 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3160 x86_update_hflags(env);
3161
3162 return 0;
3163 }
3164
3165 static int kvm_get_msrs(X86CPU *cpu)
3166 {
3167 CPUX86State *env = &cpu->env;
3168 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
3169 int ret, i;
3170 uint64_t mtrr_top_bits;
3171
3172 kvm_msr_buf_reset(cpu);
3173
3174 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3175 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3176 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3177 kvm_msr_entry_add(cpu, MSR_PAT, 0);
3178 if (has_msr_star) {
3179 kvm_msr_entry_add(cpu, MSR_STAR, 0);
3180 }
3181 if (has_msr_hsave_pa) {
3182 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
3183 }
3184 if (has_msr_tsc_aux) {
3185 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
3186 }
3187 if (has_msr_tsc_adjust) {
3188 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
3189 }
3190 if (has_msr_tsc_deadline) {
3191 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
3192 }
3193 if (has_msr_misc_enable) {
3194 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
3195 }
3196 if (has_msr_smbase) {
3197 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
3198 }
3199 if (has_msr_smi_count) {
3200 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3201 }
3202 if (has_msr_feature_control) {
3203 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
3204 }
3205 if (has_msr_pkrs) {
3206 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
3207 }
3208 if (has_msr_bndcfgs) {
3209 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
3210 }
3211 if (has_msr_xss) {
3212 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
3213 }
3214 if (has_msr_umwait) {
3215 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3216 }
3217 if (has_msr_spec_ctrl) {
3218 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3219 }
3220 if (has_msr_tsx_ctrl) {
3221 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3222 }
3223 if (has_msr_virt_ssbd) {
3224 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3225 }
3226 if (!env->tsc_valid) {
3227 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
3228 env->tsc_valid = !runstate_is_running();
3229 }
3230
3231 #ifdef TARGET_X86_64
3232 if (lm_capable_kernel) {
3233 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3234 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3235 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3236 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
3237 }
3238 #endif
3239 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3240 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
3241 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3242 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
3243 }
3244 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3245 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3246 }
3247 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
3248 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
3249 }
3250 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
3251 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
3252 }
3253 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3254 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3255 }
3256 if (has_architectural_pmu_version > 0) {
3257 if (has_architectural_pmu_version > 1) {
3258 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3259 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3260 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3261 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3262 }
3263 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
3264 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
3265 }
3266 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
3267 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3268 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
3269 }
3270 }
3271
3272 if (env->mcg_cap) {
3273 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3274 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
3275 if (has_msr_mcg_ext_ctl) {
3276 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3277 }
3278 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
3279 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
3280 }
3281 }
3282
3283 if (has_msr_hv_hypercall) {
3284 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3285 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
3286 }
3287 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
3288 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
3289 }
3290 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
3291 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
3292 }
3293 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
3294 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3295 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3296 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3297 }
3298 if (has_msr_hv_crash) {
3299 int j;
3300
3301 for (j = 0; j < HV_CRASH_PARAMS; j++) {
3302 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
3303 }
3304 }
3305 if (has_msr_hv_runtime) {
3306 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
3307 }
3308 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
3309 uint32_t msr;
3310
3311 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
3312 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3313 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
3314 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
3315 kvm_msr_entry_add(cpu, msr, 0);
3316 }
3317 }
3318 if (has_msr_hv_stimer) {
3319 uint32_t msr;
3320
3321 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3322 msr++) {
3323 kvm_msr_entry_add(cpu, msr, 0);
3324 }
3325 }
3326 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
3327 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3328 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3329 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3330 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3331 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3332 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3333 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3334 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3335 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3336 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3337 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3338 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
3339 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
3340 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3341 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
3342 }
3343 }
3344
3345 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3346 int addr_num =
3347 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3348
3349 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3350 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3351 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3352 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3353 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3354 for (i = 0; i < addr_num; i++) {
3355 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3356 }
3357 }
3358
3359 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
3360 if (ret < 0) {
3361 return ret;
3362 }
3363
3364 if (ret < cpu->kvm_msr_buf->nmsrs) {
3365 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3366 error_report("error: failed to get MSR 0x%" PRIx32,
3367 (uint32_t)e->index);
3368 }
3369
3370 assert(ret == cpu->kvm_msr_buf->nmsrs);
3371 /*
3372 * MTRR masks: Each mask consists of 5 parts
3373 * a 10..0: must be zero
3374 * b 11 : valid bit
3375 * c n-1.12: actual mask bits
3376 * d 51..n: reserved must be zero
3377 * e 63.52: reserved must be zero
3378 *
3379 * 'n' is the number of physical bits supported by the CPU and is
3380 * apparently always <= 52. We know our 'n' but don't know what
3381 * the destinations 'n' is; it might be smaller, in which case
3382 * it masks (c) on loading. It might be larger, in which case
3383 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3384 * we're migrating to.
3385 */
3386
3387 if (cpu->fill_mtrr_mask) {
3388 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3389 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3390 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3391 } else {
3392 mtrr_top_bits = 0;
3393 }
3394
3395 for (i = 0; i < ret; i++) {
3396 uint32_t index = msrs[i].index;
3397 switch (index) {
3398 case MSR_IA32_SYSENTER_CS:
3399 env->sysenter_cs = msrs[i].data;
3400 break;
3401 case MSR_IA32_SYSENTER_ESP:
3402 env->sysenter_esp = msrs[i].data;
3403 break;
3404 case MSR_IA32_SYSENTER_EIP:
3405 env->sysenter_eip = msrs[i].data;
3406 break;
3407 case MSR_PAT:
3408 env->pat = msrs[i].data;
3409 break;
3410 case MSR_STAR:
3411 env->star = msrs[i].data;
3412 break;
3413 #ifdef TARGET_X86_64
3414 case MSR_CSTAR:
3415 env->cstar = msrs[i].data;
3416 break;
3417 case MSR_KERNELGSBASE:
3418 env->kernelgsbase = msrs[i].data;
3419 break;
3420 case MSR_FMASK:
3421 env->fmask = msrs[i].data;
3422 break;
3423 case MSR_LSTAR:
3424 env->lstar = msrs[i].data;
3425 break;
3426 #endif
3427 case MSR_IA32_TSC:
3428 env->tsc = msrs[i].data;
3429 break;
3430 case MSR_TSC_AUX:
3431 env->tsc_aux = msrs[i].data;
3432 break;
3433 case MSR_TSC_ADJUST:
3434 env->tsc_adjust = msrs[i].data;
3435 break;
3436 case MSR_IA32_TSCDEADLINE:
3437 env->tsc_deadline = msrs[i].data;
3438 break;
3439 case MSR_VM_HSAVE_PA:
3440 env->vm_hsave = msrs[i].data;
3441 break;
3442 case MSR_KVM_SYSTEM_TIME:
3443 env->system_time_msr = msrs[i].data;
3444 break;
3445 case MSR_KVM_WALL_CLOCK:
3446 env->wall_clock_msr = msrs[i].data;
3447 break;
3448 case MSR_MCG_STATUS:
3449 env->mcg_status = msrs[i].data;
3450 break;
3451 case MSR_MCG_CTL:
3452 env->mcg_ctl = msrs[i].data;
3453 break;
3454 case MSR_MCG_EXT_CTL:
3455 env->mcg_ext_ctl = msrs[i].data;
3456 break;
3457 case MSR_IA32_MISC_ENABLE:
3458 env->msr_ia32_misc_enable = msrs[i].data;
3459 break;
3460 case MSR_IA32_SMBASE:
3461 env->smbase = msrs[i].data;
3462 break;
3463 case MSR_SMI_COUNT:
3464 env->msr_smi_count = msrs[i].data;
3465 break;
3466 case MSR_IA32_FEATURE_CONTROL:
3467 env->msr_ia32_feature_control = msrs[i].data;
3468 break;
3469 case MSR_IA32_BNDCFGS:
3470 env->msr_bndcfgs = msrs[i].data;
3471 break;
3472 case MSR_IA32_XSS:
3473 env->xss = msrs[i].data;
3474 break;
3475 case MSR_IA32_UMWAIT_CONTROL:
3476 env->umwait = msrs[i].data;
3477 break;
3478 case MSR_IA32_PKRS:
3479 env->pkrs = msrs[i].data;
3480 break;
3481 default:
3482 if (msrs[i].index >= MSR_MC0_CTL &&
3483 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3484 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
3485 }
3486 break;
3487 case MSR_KVM_ASYNC_PF_EN:
3488 env->async_pf_en_msr = msrs[i].data;
3489 break;
3490 case MSR_KVM_ASYNC_PF_INT:
3491 env->async_pf_int_msr = msrs[i].data;
3492 break;
3493 case MSR_KVM_PV_EOI_EN:
3494 env->pv_eoi_en_msr = msrs[i].data;
3495 break;
3496 case MSR_KVM_STEAL_TIME:
3497 env->steal_time_msr = msrs[i].data;
3498 break;
3499 case MSR_KVM_POLL_CONTROL: {
3500 env->poll_control_msr = msrs[i].data;
3501 break;
3502 }
3503 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3504 env->msr_fixed_ctr_ctrl = msrs[i].data;
3505 break;
3506 case MSR_CORE_PERF_GLOBAL_CTRL:
3507 env->msr_global_ctrl = msrs[i].data;
3508 break;
3509 case MSR_CORE_PERF_GLOBAL_STATUS:
3510 env->msr_global_status = msrs[i].data;
3511 break;
3512 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3513 env->msr_global_ovf_ctrl = msrs[i].data;
3514 break;
3515 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3516 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3517 break;
3518 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3519 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3520 break;
3521 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3522 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3523 break;
3524 case HV_X64_MSR_HYPERCALL:
3525 env->msr_hv_hypercall = msrs[i].data;
3526 break;
3527 case HV_X64_MSR_GUEST_OS_ID:
3528 env->msr_hv_guest_os_id = msrs[i].data;
3529 break;
3530 case HV_X64_MSR_APIC_ASSIST_PAGE:
3531 env->msr_hv_vapic = msrs[i].data;
3532 break;
3533 case HV_X64_MSR_REFERENCE_TSC:
3534 env->msr_hv_tsc = msrs[i].data;
3535 break;
3536 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3537 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3538 break;
3539 case HV_X64_MSR_VP_RUNTIME:
3540 env->msr_hv_runtime = msrs[i].data;
3541 break;
3542 case HV_X64_MSR_SCONTROL:
3543 env->msr_hv_synic_control = msrs[i].data;
3544 break;
3545 case HV_X64_MSR_SIEFP:
3546 env->msr_hv_synic_evt_page = msrs[i].data;
3547 break;
3548 case HV_X64_MSR_SIMP:
3549 env->msr_hv_synic_msg_page = msrs[i].data;
3550 break;
3551 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3552 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
3553 break;
3554 case HV_X64_MSR_STIMER0_CONFIG:
3555 case HV_X64_MSR_STIMER1_CONFIG:
3556 case HV_X64_MSR_STIMER2_CONFIG:
3557 case HV_X64_MSR_STIMER3_CONFIG:
3558 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3559 msrs[i].data;
3560 break;
3561 case HV_X64_MSR_STIMER0_COUNT:
3562 case HV_X64_MSR_STIMER1_COUNT:
3563 case HV_X64_MSR_STIMER2_COUNT:
3564 case HV_X64_MSR_STIMER3_COUNT:
3565 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3566 msrs[i].data;
3567 break;
3568 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3569 env->msr_hv_reenlightenment_control = msrs[i].data;
3570 break;
3571 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3572 env->msr_hv_tsc_emulation_control = msrs[i].data;
3573 break;
3574 case HV_X64_MSR_TSC_EMULATION_STATUS:
3575 env->msr_hv_tsc_emulation_status = msrs[i].data;
3576 break;
3577 case MSR_MTRRdefType:
3578 env->mtrr_deftype = msrs[i].data;
3579 break;
3580 case MSR_MTRRfix64K_00000:
3581 env->mtrr_fixed[0] = msrs[i].data;
3582 break;
3583 case MSR_MTRRfix16K_80000:
3584 env->mtrr_fixed[1] = msrs[i].data;
3585 break;
3586 case MSR_MTRRfix16K_A0000:
3587 env->mtrr_fixed[2] = msrs[i].data;
3588 break;
3589 case MSR_MTRRfix4K_C0000:
3590 env->mtrr_fixed[3] = msrs[i].data;
3591 break;
3592 case MSR_MTRRfix4K_C8000:
3593 env->mtrr_fixed[4] = msrs[i].data;
3594 break;
3595 case MSR_MTRRfix4K_D0000:
3596 env->mtrr_fixed[5] = msrs[i].data;
3597 break;
3598 case MSR_MTRRfix4K_D8000:
3599 env->mtrr_fixed[6] = msrs[i].data;
3600 break;
3601 case MSR_MTRRfix4K_E0000:
3602 env->mtrr_fixed[7] = msrs[i].data;
3603 break;
3604 case MSR_MTRRfix4K_E8000:
3605 env->mtrr_fixed[8] = msrs[i].data;
3606 break;
3607 case MSR_MTRRfix4K_F0000:
3608 env->mtrr_fixed[9] = msrs[i].data;
3609 break;
3610 case MSR_MTRRfix4K_F8000:
3611 env->mtrr_fixed[10] = msrs[i].data;
3612 break;
3613 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3614 if (index & 1) {
3615 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3616 mtrr_top_bits;
3617 } else {
3618 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3619 }
3620 break;
3621 case MSR_IA32_SPEC_CTRL:
3622 env->spec_ctrl = msrs[i].data;
3623 break;
3624 case MSR_IA32_TSX_CTRL:
3625 env->tsx_ctrl = msrs[i].data;
3626 break;
3627 case MSR_VIRT_SSBD:
3628 env->virt_ssbd = msrs[i].data;
3629 break;
3630 case MSR_IA32_RTIT_CTL:
3631 env->msr_rtit_ctrl = msrs[i].data;
3632 break;
3633 case MSR_IA32_RTIT_STATUS:
3634 env->msr_rtit_status = msrs[i].data;
3635 break;
3636 case MSR_IA32_RTIT_OUTPUT_BASE:
3637 env->msr_rtit_output_base = msrs[i].data;
3638 break;
3639 case MSR_IA32_RTIT_OUTPUT_MASK:
3640 env->msr_rtit_output_mask = msrs[i].data;
3641 break;
3642 case MSR_IA32_RTIT_CR3_MATCH:
3643 env->msr_rtit_cr3_match = msrs[i].data;
3644 break;
3645 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3646 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3647 break;
3648 }
3649 }
3650
3651 return 0;
3652 }
3653
3654 static int kvm_put_mp_state(X86CPU *cpu)
3655 {
3656 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
3657
3658 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
3659 }
3660
3661 static int kvm_get_mp_state(X86CPU *cpu)
3662 {
3663 CPUState *cs = CPU(cpu);
3664 CPUX86State *env = &cpu->env;
3665 struct kvm_mp_state mp_state;
3666 int ret;
3667
3668 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
3669 if (ret < 0) {
3670 return ret;
3671 }
3672 env->mp_state = mp_state.mp_state;
3673 if (kvm_irqchip_in_kernel()) {
3674 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
3675 }
3676 return 0;
3677 }
3678
3679 static int kvm_get_apic(X86CPU *cpu)
3680 {
3681 DeviceState *apic = cpu->apic_state;
3682 struct kvm_lapic_state kapic;
3683 int ret;
3684
3685 if (apic && kvm_irqchip_in_kernel()) {
3686 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
3687 if (ret < 0) {
3688 return ret;
3689 }
3690
3691 kvm_get_apic_state(apic, &kapic);
3692 }
3693 return 0;
3694 }
3695
3696 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
3697 {
3698 CPUState *cs = CPU(cpu);
3699 CPUX86State *env = &cpu->env;
3700 struct kvm_vcpu_events events = {};
3701
3702 if (!kvm_has_vcpu_events()) {
3703 return 0;
3704 }
3705
3706 events.flags = 0;
3707
3708 if (has_exception_payload) {
3709 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3710 events.exception.pending = env->exception_pending;
3711 events.exception_has_payload = env->exception_has_payload;
3712 events.exception_payload = env->exception_payload;
3713 }
3714 events.exception.nr = env->exception_nr;
3715 events.exception.injected = env->exception_injected;
3716 events.exception.has_error_code = env->has_error_code;
3717 events.exception.error_code = env->error_code;
3718
3719 events.interrupt.injected = (env->interrupt_injected >= 0);
3720 events.interrupt.nr = env->interrupt_injected;
3721 events.interrupt.soft = env->soft_interrupt;
3722
3723 events.nmi.injected = env->nmi_injected;
3724 events.nmi.pending = env->nmi_pending;
3725 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3726
3727 events.sipi_vector = env->sipi_vector;
3728
3729 if (has_msr_smbase) {
3730 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3731 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3732 if (kvm_irqchip_in_kernel()) {
3733 /* As soon as these are moved to the kernel, remove them
3734 * from cs->interrupt_request.
3735 */
3736 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3737 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3738 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3739 } else {
3740 /* Keep these in cs->interrupt_request. */
3741 events.smi.pending = 0;
3742 events.smi.latched_init = 0;
3743 }
3744 /* Stop SMI delivery on old machine types to avoid a reboot
3745 * on an inward migration of an old VM.
3746 */
3747 if (!cpu->kvm_no_smi_migration) {
3748 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3749 }
3750 }
3751
3752 if (level >= KVM_PUT_RESET_STATE) {
3753 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3754 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3755 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3756 }
3757 }
3758
3759 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
3760 }
3761
3762 static int kvm_get_vcpu_events(X86CPU *cpu)
3763 {
3764 CPUX86State *env = &cpu->env;
3765 struct kvm_vcpu_events events;
3766 int ret;
3767
3768 if (!kvm_has_vcpu_events()) {
3769 return 0;
3770 }
3771
3772 memset(&events, 0, sizeof(events));
3773 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
3774 if (ret < 0) {
3775 return ret;
3776 }
3777
3778 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3779 env->exception_pending = events.exception.pending;
3780 env->exception_has_payload = events.exception_has_payload;
3781 env->exception_payload = events.exception_payload;
3782 } else {
3783 env->exception_pending = 0;
3784 env->exception_has_payload = false;
3785 }
3786 env->exception_injected = events.exception.injected;
3787 env->exception_nr =
3788 (env->exception_pending || env->exception_injected) ?
3789 events.exception.nr : -1;
3790 env->has_error_code = events.exception.has_error_code;
3791 env->error_code = events.exception.error_code;
3792
3793 env->interrupt_injected =
3794 events.interrupt.injected ? events.interrupt.nr : -1;
3795 env->soft_interrupt = events.interrupt.soft;
3796
3797 env->nmi_injected = events.nmi.injected;
3798 env->nmi_pending = events.nmi.pending;
3799 if (events.nmi.masked) {
3800 env->hflags2 |= HF2_NMI_MASK;
3801 } else {
3802 env->hflags2 &= ~HF2_NMI_MASK;
3803 }
3804
3805 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3806 if (events.smi.smm) {
3807 env->hflags |= HF_SMM_MASK;
3808 } else {
3809 env->hflags &= ~HF_SMM_MASK;
3810 }
3811 if (events.smi.pending) {
3812 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3813 } else {
3814 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3815 }
3816 if (events.smi.smm_inside_nmi) {
3817 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3818 } else {
3819 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3820 }
3821 if (events.smi.latched_init) {
3822 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3823 } else {
3824 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3825 }
3826 }
3827
3828 env->sipi_vector = events.sipi_vector;
3829
3830 return 0;
3831 }
3832
3833 static int kvm_guest_debug_workarounds(X86CPU *cpu)
3834 {
3835 CPUState *cs = CPU(cpu);
3836 CPUX86State *env = &cpu->env;
3837 int ret = 0;
3838 unsigned long reinject_trap = 0;
3839
3840 if (!kvm_has_vcpu_events()) {
3841 if (env->exception_nr == EXCP01_DB) {
3842 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3843 } else if (env->exception_injected == EXCP03_INT3) {
3844 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3845 }
3846 kvm_reset_exception(env);
3847 }
3848
3849 /*
3850 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3851 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3852 * by updating the debug state once again if single-stepping is on.
3853 * Another reason to call kvm_update_guest_debug here is a pending debug
3854 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3855 * reinject them via SET_GUEST_DEBUG.
3856 */
3857 if (reinject_trap ||
3858 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
3859 ret = kvm_update_guest_debug(cs, reinject_trap);
3860 }
3861 return ret;
3862 }
3863
3864 static int kvm_put_debugregs(X86CPU *cpu)
3865 {
3866 CPUX86State *env = &cpu->env;
3867 struct kvm_debugregs dbgregs;
3868 int i;
3869
3870 if (!kvm_has_debugregs()) {
3871 return 0;
3872 }
3873
3874 memset(&dbgregs, 0, sizeof(dbgregs));
3875 for (i = 0; i < 4; i++) {
3876 dbgregs.db[i] = env->dr[i];
3877 }
3878 dbgregs.dr6 = env->dr[6];
3879 dbgregs.dr7 = env->dr[7];
3880 dbgregs.flags = 0;
3881
3882 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3883 }
3884
3885 static int kvm_get_debugregs(X86CPU *cpu)
3886 {
3887 CPUX86State *env = &cpu->env;
3888 struct kvm_debugregs dbgregs;
3889 int i, ret;
3890
3891 if (!kvm_has_debugregs()) {
3892 return 0;
3893 }
3894
3895 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3896 if (ret < 0) {
3897 return ret;
3898 }
3899 for (i = 0; i < 4; i++) {
3900 env->dr[i] = dbgregs.db[i];
3901 }
3902 env->dr[4] = env->dr[6] = dbgregs.dr6;
3903 env->dr[5] = env->dr[7] = dbgregs.dr7;
3904
3905 return 0;
3906 }
3907
3908 static int kvm_put_nested_state(X86CPU *cpu)
3909 {
3910 CPUX86State *env = &cpu->env;
3911 int max_nested_state_len = kvm_max_nested_state_length();
3912
3913 if (!env->nested_state) {
3914 return 0;
3915 }
3916
3917 /*
3918 * Copy flags that are affected by reset from env->hflags and env->hflags2.
3919 */
3920 if (env->hflags & HF_GUEST_MASK) {
3921 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
3922 } else {
3923 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
3924 }
3925
3926 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
3927 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
3928 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
3929 } else {
3930 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
3931 }
3932
3933 assert(env->nested_state->size <= max_nested_state_len);
3934 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3935 }
3936
3937 static int kvm_get_nested_state(X86CPU *cpu)
3938 {
3939 CPUX86State *env = &cpu->env;
3940 int max_nested_state_len = kvm_max_nested_state_length();
3941 int ret;
3942
3943 if (!env->nested_state) {
3944 return 0;
3945 }
3946
3947 /*
3948 * It is possible that migration restored a smaller size into
3949 * nested_state->hdr.size than what our kernel support.
3950 * We preserve migration origin nested_state->hdr.size for
3951 * call to KVM_SET_NESTED_STATE but wish that our next call
3952 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3953 */
3954 env->nested_state->size = max_nested_state_len;
3955
3956 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3957 if (ret < 0) {
3958 return ret;
3959 }
3960
3961 /*
3962 * Copy flags that are affected by reset to env->hflags and env->hflags2.
3963 */
3964 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3965 env->hflags |= HF_GUEST_MASK;
3966 } else {
3967 env->hflags &= ~HF_GUEST_MASK;
3968 }
3969
3970 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
3971 if (cpu_has_svm(env)) {
3972 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
3973 env->hflags2 |= HF2_GIF_MASK;
3974 } else {
3975 env->hflags2 &= ~HF2_GIF_MASK;
3976 }
3977 }
3978
3979 return ret;
3980 }
3981
3982 int kvm_arch_put_registers(CPUState *cpu, int level)
3983 {
3984 X86CPU *x86_cpu = X86_CPU(cpu);
3985 int ret;
3986
3987 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3988
3989 /* must be before kvm_put_nested_state so that EFER.SVME is set */
3990 ret = kvm_put_sregs(x86_cpu);
3991 if (ret < 0) {
3992 return ret;
3993 }
3994
3995 if (level >= KVM_PUT_RESET_STATE) {
3996 ret = kvm_put_nested_state(x86_cpu);
3997 if (ret < 0) {
3998 return ret;
3999 }
4000
4001 ret = kvm_put_msr_feature_control(x86_cpu);
4002 if (ret < 0) {
4003 return ret;
4004 }
4005 }
4006
4007 if (level == KVM_PUT_FULL_STATE) {
4008 /* We don't check for kvm_arch_set_tsc_khz() errors here,
4009 * because TSC frequency mismatch shouldn't abort migration,
4010 * unless the user explicitly asked for a more strict TSC
4011 * setting (e.g. using an explicit "tsc-freq" option).
4012 */
4013 kvm_arch_set_tsc_khz(cpu);
4014 }
4015
4016 ret = kvm_getput_regs(x86_cpu, 1);
4017 if (ret < 0) {
4018 return ret;
4019 }
4020 ret = kvm_put_xsave(x86_cpu);
4021 if (ret < 0) {
4022 return ret;
4023 }
4024 ret = kvm_put_xcrs(x86_cpu);
4025 if (ret < 0) {
4026 return ret;
4027 }
4028 /* must be before kvm_put_msrs */
4029 ret = kvm_inject_mce_oldstyle(x86_cpu);
4030 if (ret < 0) {
4031 return ret;
4032 }
4033 ret = kvm_put_msrs(x86_cpu, level);
4034 if (ret < 0) {
4035 return ret;
4036 }
4037 ret = kvm_put_vcpu_events(x86_cpu, level);
4038 if (ret < 0) {
4039 return ret;
4040 }
4041 if (level >= KVM_PUT_RESET_STATE) {
4042 ret = kvm_put_mp_state(x86_cpu);
4043 if (ret < 0) {
4044 return ret;
4045 }
4046 }
4047
4048 ret = kvm_put_tscdeadline_msr(x86_cpu);
4049 if (ret < 0) {
4050 return ret;
4051 }
4052 ret = kvm_put_debugregs(x86_cpu);
4053 if (ret < 0) {
4054 return ret;
4055 }
4056 /* must be last */
4057 ret = kvm_guest_debug_workarounds(x86_cpu);
4058 if (ret < 0) {
4059 return ret;
4060 }
4061 return 0;
4062 }
4063
4064 int kvm_arch_get_registers(CPUState *cs)
4065 {
4066 X86CPU *cpu = X86_CPU(cs);
4067 int ret;
4068
4069 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
4070
4071 ret = kvm_get_vcpu_events(cpu);
4072 if (ret < 0) {
4073 goto out;
4074 }
4075 /*
4076 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4077 * KVM_GET_REGS and KVM_GET_SREGS.
4078 */
4079 ret = kvm_get_mp_state(cpu);
4080 if (ret < 0) {
4081 goto out;
4082 }
4083 ret = kvm_getput_regs(cpu, 0);
4084 if (ret < 0) {
4085 goto out;
4086 }
4087 ret = kvm_get_xsave(cpu);
4088 if (ret < 0) {
4089 goto out;
4090 }
4091 ret = kvm_get_xcrs(cpu);
4092 if (ret < 0) {
4093 goto out;
4094 }
4095 ret = kvm_get_sregs(cpu);
4096 if (ret < 0) {
4097 goto out;
4098 }
4099 ret = kvm_get_msrs(cpu);
4100 if (ret < 0) {
4101 goto out;
4102 }
4103 ret = kvm_get_apic(cpu);
4104 if (ret < 0) {
4105 goto out;
4106 }
4107 ret = kvm_get_debugregs(cpu);
4108 if (ret < 0) {
4109 goto out;
4110 }
4111 ret = kvm_get_nested_state(cpu);
4112 if (ret < 0) {
4113 goto out;
4114 }
4115 ret = 0;
4116 out:
4117 cpu_sync_bndcs_hflags(&cpu->env);
4118 return ret;
4119 }
4120
4121 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
4122 {
4123 X86CPU *x86_cpu = X86_CPU(cpu);
4124 CPUX86State *env = &x86_cpu->env;
4125 int ret;
4126
4127 /* Inject NMI */
4128 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4129 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4130 qemu_mutex_lock_iothread();
4131 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4132 qemu_mutex_unlock_iothread();
4133 DPRINTF("injected NMI\n");
4134 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4135 if (ret < 0) {
4136 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4137 strerror(-ret));
4138 }
4139 }
4140 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4141 qemu_mutex_lock_iothread();
4142 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4143 qemu_mutex_unlock_iothread();
4144 DPRINTF("injected SMI\n");
4145 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4146 if (ret < 0) {
4147 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4148 strerror(-ret));
4149 }
4150 }
4151 }
4152
4153 if (!kvm_pic_in_kernel()) {
4154 qemu_mutex_lock_iothread();
4155 }
4156
4157 /* Force the VCPU out of its inner loop to process any INIT requests
4158 * or (for userspace APIC, but it is cheap to combine the checks here)
4159 * pending TPR access reports.
4160 */
4161 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
4162 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4163 !(env->hflags & HF_SMM_MASK)) {
4164 cpu->exit_request = 1;
4165 }
4166 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4167 cpu->exit_request = 1;
4168 }
4169 }
4170
4171 if (!kvm_pic_in_kernel()) {
4172 /* Try to inject an interrupt if the guest can accept it */
4173 if (run->ready_for_interrupt_injection &&
4174 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
4175 (env->eflags & IF_MASK)) {
4176 int irq;
4177
4178 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
4179 irq = cpu_get_pic_interrupt(env);
4180 if (irq >= 0) {
4181 struct kvm_interrupt intr;
4182
4183 intr.irq = irq;
4184 DPRINTF("injected interrupt %d\n", irq);
4185 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
4186 if (ret < 0) {
4187 fprintf(stderr,
4188 "KVM: injection failed, interrupt lost (%s)\n",
4189 strerror(-ret));
4190 }
4191 }
4192 }
4193
4194 /* If we have an interrupt but the guest is not ready to receive an
4195 * interrupt, request an interrupt window exit. This will
4196 * cause a return to userspace as soon as the guest is ready to
4197 * receive interrupts. */
4198 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
4199 run->request_interrupt_window = 1;
4200 } else {
4201 run->request_interrupt_window = 0;
4202 }
4203
4204 DPRINTF("setting tpr\n");
4205 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4206
4207 qemu_mutex_unlock_iothread();
4208 }
4209 }
4210
4211 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
4212 {
4213 X86CPU *x86_cpu = X86_CPU(cpu);
4214 CPUX86State *env = &x86_cpu->env;
4215
4216 if (run->flags & KVM_RUN_X86_SMM) {
4217 env->hflags |= HF_SMM_MASK;
4218 } else {
4219 env->hflags &= ~HF_SMM_MASK;
4220 }
4221 if (run->if_flag) {
4222 env->eflags |= IF_MASK;
4223 } else {
4224 env->eflags &= ~IF_MASK;
4225 }
4226
4227 /* We need to protect the apic state against concurrent accesses from
4228 * different threads in case the userspace irqchip is used. */
4229 if (!kvm_irqchip_in_kernel()) {
4230 qemu_mutex_lock_iothread();
4231 }
4232 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4233 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4234 if (!kvm_irqchip_in_kernel()) {
4235 qemu_mutex_unlock_iothread();
4236 }
4237 return cpu_get_mem_attrs(env);
4238 }
4239
4240 int kvm_arch_process_async_events(CPUState *cs)
4241 {
4242 X86CPU *cpu = X86_CPU(cs);
4243 CPUX86State *env = &cpu->env;
4244
4245 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
4246 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4247 assert(env->mcg_cap);
4248
4249 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
4250
4251 kvm_cpu_synchronize_state(cs);
4252
4253 if (env->exception_nr == EXCP08_DBLE) {
4254 /* this means triple fault */
4255 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4256 cs->exit_request = 1;
4257 return 0;
4258 }
4259 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
4260 env->has_error_code = 0;
4261
4262 cs->halted = 0;
4263 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4264 env->mp_state = KVM_MP_STATE_RUNNABLE;
4265 }
4266 }
4267
4268 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4269 !(env->hflags & HF_SMM_MASK)) {
4270 kvm_cpu_synchronize_state(cs);
4271 do_cpu_init(cpu);
4272 }
4273
4274 if (kvm_irqchip_in_kernel()) {
4275 return 0;
4276 }
4277
4278 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4279 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
4280 apic_poll_irq(cpu->apic_state);
4281 }
4282 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4283 (env->eflags & IF_MASK)) ||
4284 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4285 cs->halted = 0;
4286 }
4287 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
4288 kvm_cpu_synchronize_state(cs);
4289 do_cpu_sipi(cpu);
4290 }
4291 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4292 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
4293 kvm_cpu_synchronize_state(cs);
4294 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
4295 env->tpr_access_type);
4296 }
4297
4298 return cs->halted;
4299 }
4300
4301 static int kvm_handle_halt(X86CPU *cpu)
4302 {
4303 CPUState *cs = CPU(cpu);
4304 CPUX86State *env = &cpu->env;
4305
4306 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4307 (env->eflags & IF_MASK)) &&
4308 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4309 cs->halted = 1;
4310 return EXCP_HLT;
4311 }
4312
4313 return 0;
4314 }
4315
4316 static int kvm_handle_tpr_access(X86CPU *cpu)
4317 {
4318 CPUState *cs = CPU(cpu);
4319 struct kvm_run *run = cs->kvm_run;
4320
4321 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
4322 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4323 : TPR_ACCESS_READ);
4324 return 1;
4325 }
4326
4327 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4328 {
4329 static const uint8_t int3 = 0xcc;
4330
4331 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4332 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
4333 return -EINVAL;
4334 }
4335 return 0;
4336 }
4337
4338 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4339 {
4340 uint8_t int3;
4341
4342 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
4343 return -EINVAL;
4344 }
4345 if (int3 != 0xcc) {
4346 return 0;
4347 }
4348 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
4349 return -EINVAL;
4350 }
4351 return 0;
4352 }
4353
4354 static struct {
4355 target_ulong addr;
4356 int len;
4357 int type;
4358 } hw_breakpoint[4];
4359
4360 static int nb_hw_breakpoint;
4361
4362 static int find_hw_breakpoint(target_ulong addr, int len, int type)
4363 {
4364 int n;
4365
4366 for (n = 0; n < nb_hw_breakpoint; n++) {
4367 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
4368 (hw_breakpoint[n].len == len || len == -1)) {
4369 return n;
4370 }
4371 }
4372 return -1;
4373 }
4374
4375 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4376 target_ulong len, int type)
4377 {
4378 switch (type) {
4379 case GDB_BREAKPOINT_HW:
4380 len = 1;
4381 break;
4382 case GDB_WATCHPOINT_WRITE:
4383 case GDB_WATCHPOINT_ACCESS:
4384 switch (len) {
4385 case 1:
4386 break;
4387 case 2:
4388 case 4:
4389 case 8:
4390 if (addr & (len - 1)) {
4391 return -EINVAL;
4392 }
4393 break;
4394 default:
4395 return -EINVAL;
4396 }
4397 break;
4398 default:
4399 return -ENOSYS;
4400 }
4401
4402 if (nb_hw_breakpoint == 4) {
4403 return -ENOBUFS;
4404 }
4405 if (find_hw_breakpoint(addr, len, type) >= 0) {
4406 return -EEXIST;
4407 }
4408 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4409 hw_breakpoint[nb_hw_breakpoint].len = len;
4410 hw_breakpoint[nb_hw_breakpoint].type = type;
4411 nb_hw_breakpoint++;
4412
4413 return 0;
4414 }
4415
4416 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4417 target_ulong len, int type)
4418 {
4419 int n;
4420
4421 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
4422 if (n < 0) {
4423 return -ENOENT;
4424 }
4425 nb_hw_breakpoint--;
4426 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4427
4428 return 0;
4429 }
4430
4431 void kvm_arch_remove_all_hw_breakpoints(void)
4432 {
4433 nb_hw_breakpoint = 0;
4434 }
4435
4436 static CPUWatchpoint hw_watchpoint;
4437
4438 static int kvm_handle_debug(X86CPU *cpu,
4439 struct kvm_debug_exit_arch *arch_info)
4440 {
4441 CPUState *cs = CPU(cpu);
4442 CPUX86State *env = &cpu->env;
4443 int ret = 0;
4444 int n;
4445
4446 if (arch_info->exception == EXCP01_DB) {
4447 if (arch_info->dr6 & DR6_BS) {
4448 if (cs->singlestep_enabled) {
4449 ret = EXCP_DEBUG;
4450 }
4451 } else {
4452 for (n = 0; n < 4; n++) {
4453 if (arch_info->dr6 & (1 << n)) {
4454 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4455 case 0x0:
4456 ret = EXCP_DEBUG;
4457 break;
4458 case 0x1:
4459 ret = EXCP_DEBUG;
4460 cs->watchpoint_hit = &hw_watchpoint;
4461 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4462 hw_watchpoint.flags = BP_MEM_WRITE;
4463 break;
4464 case 0x3:
4465 ret = EXCP_DEBUG;
4466 cs->watchpoint_hit = &hw_watchpoint;
4467 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4468 hw_watchpoint.flags = BP_MEM_ACCESS;
4469 break;
4470 }
4471 }
4472 }
4473 }
4474 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
4475 ret = EXCP_DEBUG;
4476 }
4477 if (ret == 0) {
4478 cpu_synchronize_state(cs);
4479 assert(env->exception_nr == -1);
4480
4481 /* pass to guest */
4482 kvm_queue_exception(env, arch_info->exception,
4483 arch_info->exception == EXCP01_DB,
4484 arch_info->dr6);
4485 env->has_error_code = 0;
4486 }
4487
4488 return ret;
4489 }
4490
4491 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
4492 {
4493 const uint8_t type_code[] = {
4494 [GDB_BREAKPOINT_HW] = 0x0,
4495 [GDB_WATCHPOINT_WRITE] = 0x1,
4496 [GDB_WATCHPOINT_ACCESS] = 0x3
4497 };
4498 const uint8_t len_code[] = {
4499 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4500 };
4501 int n;
4502
4503 if (kvm_sw_breakpoints_active(cpu)) {
4504 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
4505 }
4506 if (nb_hw_breakpoint > 0) {
4507 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4508 dbg->arch.debugreg[7] = 0x0600;
4509 for (n = 0; n < nb_hw_breakpoint; n++) {
4510 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4511 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4512 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
4513 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
4514 }
4515 }
4516 }
4517
4518 static bool host_supports_vmx(void)
4519 {
4520 uint32_t ecx, unused;
4521
4522 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4523 return ecx & CPUID_EXT_VMX;
4524 }
4525
4526 #define VMX_INVALID_GUEST_STATE 0x80000021
4527
4528 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
4529 {
4530 X86CPU *cpu = X86_CPU(cs);
4531 uint64_t code;
4532 int ret;
4533
4534 switch (run->exit_reason) {
4535 case KVM_EXIT_HLT:
4536 DPRINTF("handle_hlt\n");
4537 qemu_mutex_lock_iothread();
4538 ret = kvm_handle_halt(cpu);
4539 qemu_mutex_unlock_iothread();
4540 break;
4541 case KVM_EXIT_SET_TPR:
4542 ret = 0;
4543 break;
4544 case KVM_EXIT_TPR_ACCESS:
4545 qemu_mutex_lock_iothread();
4546 ret = kvm_handle_tpr_access(cpu);
4547 qemu_mutex_unlock_iothread();
4548 break;
4549 case KVM_EXIT_FAIL_ENTRY:
4550 code = run->fail_entry.hardware_entry_failure_reason;
4551 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4552 code);
4553 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4554 fprintf(stderr,
4555 "\nIf you're running a guest on an Intel machine without "
4556 "unrestricted mode\n"
4557 "support, the failure can be most likely due to the guest "
4558 "entering an invalid\n"
4559 "state for Intel VT. For example, the guest maybe running "
4560 "in big real mode\n"
4561 "which is not supported on less recent Intel processors."
4562 "\n\n");
4563 }
4564 ret = -1;
4565 break;
4566 case KVM_EXIT_EXCEPTION:
4567 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4568 run->ex.exception, run->ex.error_code);
4569 ret = -1;
4570 break;
4571 case KVM_EXIT_DEBUG:
4572 DPRINTF("kvm_exit_debug\n");
4573 qemu_mutex_lock_iothread();
4574 ret = kvm_handle_debug(cpu, &run->debug.arch);
4575 qemu_mutex_unlock_iothread();
4576 break;
4577 case KVM_EXIT_HYPERV:
4578 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4579 break;
4580 case KVM_EXIT_IOAPIC_EOI:
4581 ioapic_eoi_broadcast(run->eoi.vector);
4582 ret = 0;
4583 break;
4584 default:
4585 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4586 ret = -1;
4587 break;
4588 }
4589
4590 return ret;
4591 }
4592
4593 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4594 {
4595 X86CPU *cpu = X86_CPU(cs);
4596 CPUX86State *env = &cpu->env;
4597
4598 kvm_cpu_synchronize_state(cs);
4599 return !(env->cr[0] & CR0_PE_MASK) ||
4600 ((env->segs[R_CS].selector & 3) != 3);
4601 }
4602
4603 void kvm_arch_init_irq_routing(KVMState *s)
4604 {
4605 /* We know at this point that we're using the in-kernel
4606 * irqchip, so we can use irqfds, and on x86 we know
4607 * we can use msi via irqfd and GSI routing.
4608 */
4609 kvm_msi_via_irqfd_allowed = true;
4610 kvm_gsi_routing_allowed = true;
4611
4612 if (kvm_irqchip_is_split()) {
4613 int i;
4614
4615 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4616 MSI routes for signaling interrupts to the local apics. */
4617 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
4618 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
4619 error_report("Could not enable split IRQ mode.");
4620 exit(1);
4621 }
4622 }
4623 }
4624 }
4625
4626 int kvm_arch_irqchip_create(KVMState *s)
4627 {
4628 int ret;
4629 if (kvm_kernel_irqchip_split()) {
4630 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4631 if (ret) {
4632 error_report("Could not enable split irqchip mode: %s",
4633 strerror(-ret));
4634 exit(1);
4635 } else {
4636 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4637 kvm_split_irqchip = true;
4638 return 1;
4639 }
4640 } else {
4641 return 0;
4642 }
4643 }
4644
4645 uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
4646 {
4647 CPUX86State *env;
4648 uint64_t ext_id;
4649
4650 if (!first_cpu) {
4651 return address;
4652 }
4653 env = &X86_CPU(first_cpu)->env;
4654 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
4655 return address;
4656 }
4657
4658 /*
4659 * If the remappable format bit is set, or the upper bits are
4660 * already set in address_hi, or the low extended bits aren't
4661 * there anyway, do nothing.
4662 */
4663 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
4664 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
4665 return address;
4666 }
4667
4668 address &= ~ext_id;
4669 address |= ext_id << 35;
4670 return address;
4671 }
4672
4673 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
4674 uint64_t address, uint32_t data, PCIDevice *dev)
4675 {
4676 X86IOMMUState *iommu = x86_iommu_get_default();
4677
4678 if (iommu) {
4679 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
4680
4681 if (class->int_remap) {
4682 int ret;
4683 MSIMessage src, dst;
4684
4685 src.address = route->u.msi.address_hi;
4686 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4687 src.address |= route->u.msi.address_lo;
4688 src.data = route->u.msi.data;
4689
4690 ret = class->int_remap(iommu, &src, &dst, dev ? \
4691 pci_requester_id(dev) : \
4692 X86_IOMMU_SID_INVALID);
4693 if (ret) {
4694 trace_kvm_x86_fixup_msi_error(route->gsi);
4695 return 1;
4696 }
4697
4698 /*
4699 * Handled untranslated compatibilty format interrupt with
4700 * extended destination ID in the low bits 11-5. */
4701 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
4702
4703 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4704 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4705 route->u.msi.data = dst.data;
4706 return 0;
4707 }
4708 }
4709
4710 address = kvm_swizzle_msi_ext_dest_id(address);
4711 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
4712 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
4713 return 0;
4714 }
4715
4716 typedef struct MSIRouteEntry MSIRouteEntry;
4717
4718 struct MSIRouteEntry {
4719 PCIDevice *dev; /* Device pointer */
4720 int vector; /* MSI/MSIX vector index */
4721 int virq; /* Virtual IRQ index */
4722 QLIST_ENTRY(MSIRouteEntry) list;
4723 };
4724
4725 /* List of used GSI routes */
4726 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4727 QLIST_HEAD_INITIALIZER(msi_route_list);
4728
4729 static void kvm_update_msi_routes_all(void *private, bool global,
4730 uint32_t index, uint32_t mask)
4731 {
4732 int cnt = 0, vector;
4733 MSIRouteEntry *entry;
4734 MSIMessage msg;
4735 PCIDevice *dev;
4736
4737 /* TODO: explicit route update */
4738 QLIST_FOREACH(entry, &msi_route_list, list) {
4739 cnt++;
4740 vector = entry->vector;
4741 dev = entry->dev;
4742 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4743 msg = msix_get_message(dev, vector);
4744 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4745 msg = msi_get_message(dev, vector);
4746 } else {
4747 /*
4748 * Either MSI/MSIX is disabled for the device, or the
4749 * specific message was masked out. Skip this one.
4750 */
4751 continue;
4752 }
4753 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
4754 }
4755 kvm_irqchip_commit_routes(kvm_state);
4756 trace_kvm_x86_update_msi_routes(cnt);
4757 }
4758
4759 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4760 int vector, PCIDevice *dev)
4761 {
4762 static bool notify_list_inited = false;
4763 MSIRouteEntry *entry;
4764
4765 if (!dev) {
4766 /* These are (possibly) IOAPIC routes only used for split
4767 * kernel irqchip mode, while what we are housekeeping are
4768 * PCI devices only. */
4769 return 0;
4770 }
4771
4772 entry = g_new0(MSIRouteEntry, 1);
4773 entry->dev = dev;
4774 entry->vector = vector;
4775 entry->virq = route->gsi;
4776 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4777
4778 trace_kvm_x86_add_msi_route(route->gsi);
4779
4780 if (!notify_list_inited) {
4781 /* For the first time we do add route, add ourselves into
4782 * IOMMU's IEC notify list if needed. */
4783 X86IOMMUState *iommu = x86_iommu_get_default();
4784 if (iommu) {
4785 x86_iommu_iec_register_notifier(iommu,
4786 kvm_update_msi_routes_all,
4787 NULL);
4788 }
4789 notify_list_inited = true;
4790 }
4791 return 0;
4792 }
4793
4794 int kvm_arch_release_virq_post(int virq)
4795 {
4796 MSIRouteEntry *entry, *next;
4797 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4798 if (entry->virq == virq) {
4799 trace_kvm_x86_remove_msi_route(virq);
4800 QLIST_REMOVE(entry, list);
4801 g_free(entry);
4802 break;
4803 }
4804 }
4805 return 0;
4806 }
4807
4808 int kvm_arch_msi_data_to_gsi(uint32_t data)
4809 {
4810 abort();
4811 }
4812
4813 bool kvm_has_waitpkg(void)
4814 {
4815 return has_msr_umwait;
4816 }
4817
4818 bool kvm_arch_cpu_check_are_resettable(void)
4819 {
4820 return !sev_es_enabled();
4821 }
QEmu