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Merge remote branch 'mst/for_anthony' into staging
[qemu.git] / hw / ppc405_uc.c
blob8136cb962ba0a2e8066829839b45f8b18b6a9aac
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "ppc405.h"
27 #include "pc.h"
28 #include "qemu-timer.h"
29 #include "sysemu.h"
30 #include "qemu-log.h"
31
32 #define DEBUG_OPBA
33 #define DEBUG_SDRAM
34 #define DEBUG_GPIO
35 #define DEBUG_SERIAL
36 #define DEBUG_OCM
37 //#define DEBUG_I2C
38 #define DEBUG_GPT
39 #define DEBUG_MAL
40 #define DEBUG_CLOCKS
41 //#define DEBUG_CLOCKS_LL
42
43 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,
44 uint32_t flags)
45 {
46 ram_addr_t bdloc;
47 int i, n;
48
49 /* We put the bd structure at the top of memory */
50 if (bd->bi_memsize >= 0x01000000UL)
51 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
52 else
53 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
54 stl_phys(bdloc + 0x00, bd->bi_memstart);
55 stl_phys(bdloc + 0x04, bd->bi_memsize);
56 stl_phys(bdloc + 0x08, bd->bi_flashstart);
57 stl_phys(bdloc + 0x0C, bd->bi_flashsize);
58 stl_phys(bdloc + 0x10, bd->bi_flashoffset);
59 stl_phys(bdloc + 0x14, bd->bi_sramstart);
60 stl_phys(bdloc + 0x18, bd->bi_sramsize);
61 stl_phys(bdloc + 0x1C, bd->bi_bootflags);
62 stl_phys(bdloc + 0x20, bd->bi_ipaddr);
63 for (i = 0; i < 6; i++)
64 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
65 stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
66 stl_phys(bdloc + 0x2C, bd->bi_intfreq);
67 stl_phys(bdloc + 0x30, bd->bi_busfreq);
68 stl_phys(bdloc + 0x34, bd->bi_baudrate);
69 for (i = 0; i < 4; i++)
70 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
71 for (i = 0; i < 32; i++)
72 stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]);
73 stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
74 stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
75 for (i = 0; i < 6; i++)
76 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
77 n = 0x6A;
78 if (flags & 0x00000001) {
79 for (i = 0; i < 6; i++)
80 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
81 }
82 stl_phys(bdloc + n, bd->bi_opbfreq);
83 n += 4;
84 for (i = 0; i < 2; i++) {
85 stl_phys(bdloc + n, bd->bi_iic_fast[i]);
86 n += 4;
87 }
88
89 return bdloc;
90 }
91
92 /*****************************************************************************/
93 /* Shared peripherals */
94
95 /*****************************************************************************/
96 /* Peripheral local bus arbitrer */
97 enum {
98 PLB0_BESR = 0x084,
99 PLB0_BEAR = 0x086,
100 PLB0_ACR = 0x087,
101 };
102
103 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
104 struct ppc4xx_plb_t {
105 uint32_t acr;
106 uint32_t bear;
107 uint32_t besr;
108 };
109
110 static uint32_t dcr_read_plb (void *opaque, int dcrn)
111 {
112 ppc4xx_plb_t *plb;
113 uint32_t ret;
114
115 plb = opaque;
116 switch (dcrn) {
117 case PLB0_ACR:
118 ret = plb->acr;
119 break;
120 case PLB0_BEAR:
121 ret = plb->bear;
122 break;
123 case PLB0_BESR:
124 ret = plb->besr;
125 break;
126 default:
127 /* Avoid gcc warning */
128 ret = 0;
129 break;
130 }
131
132 return ret;
133 }
134
135 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
136 {
137 ppc4xx_plb_t *plb;
138
139 plb = opaque;
140 switch (dcrn) {
141 case PLB0_ACR:
142 /* We don't care about the actual parameters written as
143 * we don't manage any priorities on the bus
144 */
145 plb->acr = val & 0xF8000000;
146 break;
147 case PLB0_BEAR:
148 /* Read only */
149 break;
150 case PLB0_BESR:
151 /* Write-clear */
152 plb->besr &= ~val;
153 break;
154 }
155 }
156
157 static void ppc4xx_plb_reset (void *opaque)
158 {
159 ppc4xx_plb_t *plb;
160
161 plb = opaque;
162 plb->acr = 0x00000000;
163 plb->bear = 0x00000000;
164 plb->besr = 0x00000000;
165 }
166
167 static void ppc4xx_plb_init(CPUState *env)
168 {
169 ppc4xx_plb_t *plb;
170
171 plb = qemu_mallocz(sizeof(ppc4xx_plb_t));
172 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
173 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
174 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
175 qemu_register_reset(ppc4xx_plb_reset, plb);
176 }
177
178 /*****************************************************************************/
179 /* PLB to OPB bridge */
180 enum {
181 POB0_BESR0 = 0x0A0,
182 POB0_BESR1 = 0x0A2,
183 POB0_BEAR = 0x0A4,
184 };
185
186 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
187 struct ppc4xx_pob_t {
188 uint32_t bear;
189 uint32_t besr[2];
190 };
191
192 static uint32_t dcr_read_pob (void *opaque, int dcrn)
193 {
194 ppc4xx_pob_t *pob;
195 uint32_t ret;
196
197 pob = opaque;
198 switch (dcrn) {
199 case POB0_BEAR:
200 ret = pob->bear;
201 break;
202 case POB0_BESR0:
203 case POB0_BESR1:
204 ret = pob->besr[dcrn - POB0_BESR0];
205 break;
206 default:
207 /* Avoid gcc warning */
208 ret = 0;
209 break;
210 }
211
212 return ret;
213 }
214
215 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
216 {
217 ppc4xx_pob_t *pob;
218
219 pob = opaque;
220 switch (dcrn) {
221 case POB0_BEAR:
222 /* Read only */
223 break;
224 case POB0_BESR0:
225 case POB0_BESR1:
226 /* Write-clear */
227 pob->besr[dcrn - POB0_BESR0] &= ~val;
228 break;
229 }
230 }
231
232 static void ppc4xx_pob_reset (void *opaque)
233 {
234 ppc4xx_pob_t *pob;
235
236 pob = opaque;
237 /* No error */
238 pob->bear = 0x00000000;
239 pob->besr[0] = 0x0000000;
240 pob->besr[1] = 0x0000000;
241 }
242
243 static void ppc4xx_pob_init(CPUState *env)
244 {
245 ppc4xx_pob_t *pob;
246
247 pob = qemu_mallocz(sizeof(ppc4xx_pob_t));
248 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
249 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
250 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
251 qemu_register_reset(ppc4xx_pob_reset, pob);
252 }
253
254 /*****************************************************************************/
255 /* OPB arbitrer */
256 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
257 struct ppc4xx_opba_t {
258 uint8_t cr;
259 uint8_t pr;
260 };
261
262 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)
263 {
264 ppc4xx_opba_t *opba;
265 uint32_t ret;
266
267 #ifdef DEBUG_OPBA
268 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
269 #endif
270 opba = opaque;
271 switch (addr) {
272 case 0x00:
273 ret = opba->cr;
274 break;
275 case 0x01:
276 ret = opba->pr;
277 break;
278 default:
279 ret = 0x00;
280 break;
281 }
282
283 return ret;
284 }
285
286 static void opba_writeb (void *opaque,
287 target_phys_addr_t addr, uint32_t value)
288 {
289 ppc4xx_opba_t *opba;
290
291 #ifdef DEBUG_OPBA
292 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
293 value);
294 #endif
295 opba = opaque;
296 switch (addr) {
297 case 0x00:
298 opba->cr = value & 0xF8;
299 break;
300 case 0x01:
301 opba->pr = value & 0xFF;
302 break;
303 default:
304 break;
305 }
306 }
307
308 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)
309 {
310 uint32_t ret;
311
312 #ifdef DEBUG_OPBA
313 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
314 #endif
315 ret = opba_readb(opaque, addr) << 8;
316 ret |= opba_readb(opaque, addr + 1);
317
318 return ret;
319 }
320
321 static void opba_writew (void *opaque,
322 target_phys_addr_t addr, uint32_t value)
323 {
324 #ifdef DEBUG_OPBA
325 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
326 value);
327 #endif
328 opba_writeb(opaque, addr, value >> 8);
329 opba_writeb(opaque, addr + 1, value);
330 }
331
332 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)
333 {
334 uint32_t ret;
335
336 #ifdef DEBUG_OPBA
337 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
338 #endif
339 ret = opba_readb(opaque, addr) << 24;
340 ret |= opba_readb(opaque, addr + 1) << 16;
341
342 return ret;
343 }
344
345 static void opba_writel (void *opaque,
346 target_phys_addr_t addr, uint32_t value)
347 {
348 #ifdef DEBUG_OPBA
349 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
350 value);
351 #endif
352 opba_writeb(opaque, addr, value >> 24);
353 opba_writeb(opaque, addr + 1, value >> 16);
354 }
355
356 static CPUReadMemoryFunc * const opba_read[] = {
357 &opba_readb,
358 &opba_readw,
359 &opba_readl,
360 };
361
362 static CPUWriteMemoryFunc * const opba_write[] = {
363 &opba_writeb,
364 &opba_writew,
365 &opba_writel,
366 };
367
368 static void ppc4xx_opba_reset (void *opaque)
369 {
370 ppc4xx_opba_t *opba;
371
372 opba = opaque;
373 opba->cr = 0x00; /* No dynamic priorities - park disabled */
374 opba->pr = 0x11;
375 }
376
377 static void ppc4xx_opba_init(target_phys_addr_t base)
378 {
379 ppc4xx_opba_t *opba;
380 int io;
381
382 opba = qemu_mallocz(sizeof(ppc4xx_opba_t));
383 #ifdef DEBUG_OPBA
384 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
385 #endif
386 io = cpu_register_io_memory(opba_read, opba_write, opba,
387 DEVICE_NATIVE_ENDIAN);
388 cpu_register_physical_memory(base, 0x002, io);
389 qemu_register_reset(ppc4xx_opba_reset, opba);
390 }
391
392 /*****************************************************************************/
393 /* Code decompression controller */
394 /* XXX: TODO */
395
396 /*****************************************************************************/
397 /* Peripheral controller */
398 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
399 struct ppc4xx_ebc_t {
400 uint32_t addr;
401 uint32_t bcr[8];
402 uint32_t bap[8];
403 uint32_t bear;
404 uint32_t besr0;
405 uint32_t besr1;
406 uint32_t cfg;
407 };
408
409 enum {
410 EBC0_CFGADDR = 0x012,
411 EBC0_CFGDATA = 0x013,
412 };
413
414 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
415 {
416 ppc4xx_ebc_t *ebc;
417 uint32_t ret;
418
419 ebc = opaque;
420 switch (dcrn) {
421 case EBC0_CFGADDR:
422 ret = ebc->addr;
423 break;
424 case EBC0_CFGDATA:
425 switch (ebc->addr) {
426 case 0x00: /* B0CR */
427 ret = ebc->bcr[0];
428 break;
429 case 0x01: /* B1CR */
430 ret = ebc->bcr[1];
431 break;
432 case 0x02: /* B2CR */
433 ret = ebc->bcr[2];
434 break;
435 case 0x03: /* B3CR */
436 ret = ebc->bcr[3];
437 break;
438 case 0x04: /* B4CR */
439 ret = ebc->bcr[4];
440 break;
441 case 0x05: /* B5CR */
442 ret = ebc->bcr[5];
443 break;
444 case 0x06: /* B6CR */
445 ret = ebc->bcr[6];
446 break;
447 case 0x07: /* B7CR */
448 ret = ebc->bcr[7];
449 break;
450 case 0x10: /* B0AP */
451 ret = ebc->bap[0];
452 break;
453 case 0x11: /* B1AP */
454 ret = ebc->bap[1];
455 break;
456 case 0x12: /* B2AP */
457 ret = ebc->bap[2];
458 break;
459 case 0x13: /* B3AP */
460 ret = ebc->bap[3];
461 break;
462 case 0x14: /* B4AP */
463 ret = ebc->bap[4];
464 break;
465 case 0x15: /* B5AP */
466 ret = ebc->bap[5];
467 break;
468 case 0x16: /* B6AP */
469 ret = ebc->bap[6];
470 break;
471 case 0x17: /* B7AP */
472 ret = ebc->bap[7];
473 break;
474 case 0x20: /* BEAR */
475 ret = ebc->bear;
476 break;
477 case 0x21: /* BESR0 */
478 ret = ebc->besr0;
479 break;
480 case 0x22: /* BESR1 */
481 ret = ebc->besr1;
482 break;
483 case 0x23: /* CFG */
484 ret = ebc->cfg;
485 break;
486 default:
487 ret = 0x00000000;
488 break;
489 }
490 break;
491 default:
492 ret = 0x00000000;
493 break;
494 }
495
496 return ret;
497 }
498
499 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
500 {
501 ppc4xx_ebc_t *ebc;
502
503 ebc = opaque;
504 switch (dcrn) {
505 case EBC0_CFGADDR:
506 ebc->addr = val;
507 break;
508 case EBC0_CFGDATA:
509 switch (ebc->addr) {
510 case 0x00: /* B0CR */
511 break;
512 case 0x01: /* B1CR */
513 break;
514 case 0x02: /* B2CR */
515 break;
516 case 0x03: /* B3CR */
517 break;
518 case 0x04: /* B4CR */
519 break;
520 case 0x05: /* B5CR */
521 break;
522 case 0x06: /* B6CR */
523 break;
524 case 0x07: /* B7CR */
525 break;
526 case 0x10: /* B0AP */
527 break;
528 case 0x11: /* B1AP */
529 break;
530 case 0x12: /* B2AP */
531 break;
532 case 0x13: /* B3AP */
533 break;
534 case 0x14: /* B4AP */
535 break;
536 case 0x15: /* B5AP */
537 break;
538 case 0x16: /* B6AP */
539 break;
540 case 0x17: /* B7AP */
541 break;
542 case 0x20: /* BEAR */
543 break;
544 case 0x21: /* BESR0 */
545 break;
546 case 0x22: /* BESR1 */
547 break;
548 case 0x23: /* CFG */
549 break;
550 default:
551 break;
552 }
553 break;
554 default:
555 break;
556 }
557 }
558
559 static void ebc_reset (void *opaque)
560 {
561 ppc4xx_ebc_t *ebc;
562 int i;
563
564 ebc = opaque;
565 ebc->addr = 0x00000000;
566 ebc->bap[0] = 0x7F8FFE80;
567 ebc->bcr[0] = 0xFFE28000;
568 for (i = 0; i < 8; i++) {
569 ebc->bap[i] = 0x00000000;
570 ebc->bcr[i] = 0x00000000;
571 }
572 ebc->besr0 = 0x00000000;
573 ebc->besr1 = 0x00000000;
574 ebc->cfg = 0x80400000;
575 }
576
577 static void ppc405_ebc_init(CPUState *env)
578 {
579 ppc4xx_ebc_t *ebc;
580
581 ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));
582 qemu_register_reset(&ebc_reset, ebc);
583 ppc_dcr_register(env, EBC0_CFGADDR,
584 ebc, &dcr_read_ebc, &dcr_write_ebc);
585 ppc_dcr_register(env, EBC0_CFGDATA,
586 ebc, &dcr_read_ebc, &dcr_write_ebc);
587 }
588
589 /*****************************************************************************/
590 /* DMA controller */
591 enum {
592 DMA0_CR0 = 0x100,
593 DMA0_CT0 = 0x101,
594 DMA0_DA0 = 0x102,
595 DMA0_SA0 = 0x103,
596 DMA0_SG0 = 0x104,
597 DMA0_CR1 = 0x108,
598 DMA0_CT1 = 0x109,
599 DMA0_DA1 = 0x10A,
600 DMA0_SA1 = 0x10B,
601 DMA0_SG1 = 0x10C,
602 DMA0_CR2 = 0x110,
603 DMA0_CT2 = 0x111,
604 DMA0_DA2 = 0x112,
605 DMA0_SA2 = 0x113,
606 DMA0_SG2 = 0x114,
607 DMA0_CR3 = 0x118,
608 DMA0_CT3 = 0x119,
609 DMA0_DA3 = 0x11A,
610 DMA0_SA3 = 0x11B,
611 DMA0_SG3 = 0x11C,
612 DMA0_SR = 0x120,
613 DMA0_SGC = 0x123,
614 DMA0_SLP = 0x125,
615 DMA0_POL = 0x126,
616 };
617
618 typedef struct ppc405_dma_t ppc405_dma_t;
619 struct ppc405_dma_t {
620 qemu_irq irqs[4];
621 uint32_t cr[4];
622 uint32_t ct[4];
623 uint32_t da[4];
624 uint32_t sa[4];
625 uint32_t sg[4];
626 uint32_t sr;
627 uint32_t sgc;
628 uint32_t slp;
629 uint32_t pol;
630 };
631
632 static uint32_t dcr_read_dma (void *opaque, int dcrn)
633 {
634 return 0;
635 }
636
637 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
638 {
639 }
640
641 static void ppc405_dma_reset (void *opaque)
642 {
643 ppc405_dma_t *dma;
644 int i;
645
646 dma = opaque;
647 for (i = 0; i < 4; i++) {
648 dma->cr[i] = 0x00000000;
649 dma->ct[i] = 0x00000000;
650 dma->da[i] = 0x00000000;
651 dma->sa[i] = 0x00000000;
652 dma->sg[i] = 0x00000000;
653 }
654 dma->sr = 0x00000000;
655 dma->sgc = 0x00000000;
656 dma->slp = 0x7C000000;
657 dma->pol = 0x00000000;
658 }
659
660 static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
661 {
662 ppc405_dma_t *dma;
663
664 dma = qemu_mallocz(sizeof(ppc405_dma_t));
665 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
666 qemu_register_reset(&ppc405_dma_reset, dma);
667 ppc_dcr_register(env, DMA0_CR0,
668 dma, &dcr_read_dma, &dcr_write_dma);
669 ppc_dcr_register(env, DMA0_CT0,
670 dma, &dcr_read_dma, &dcr_write_dma);
671 ppc_dcr_register(env, DMA0_DA0,
672 dma, &dcr_read_dma, &dcr_write_dma);
673 ppc_dcr_register(env, DMA0_SA0,
674 dma, &dcr_read_dma, &dcr_write_dma);
675 ppc_dcr_register(env, DMA0_SG0,
676 dma, &dcr_read_dma, &dcr_write_dma);
677 ppc_dcr_register(env, DMA0_CR1,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_CT1,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_DA1,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_SA1,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_SG1,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_CR2,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_CT2,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_DA2,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_SA2,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_SG2,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_CR3,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_CT3,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_DA3,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_SA3,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_SG3,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_SR,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_SGC,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_SLP,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_POL,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 }
716
717 /*****************************************************************************/
718 /* GPIO */
719 typedef struct ppc405_gpio_t ppc405_gpio_t;
720 struct ppc405_gpio_t {
721 uint32_t or;
722 uint32_t tcr;
723 uint32_t osrh;
724 uint32_t osrl;
725 uint32_t tsrh;
726 uint32_t tsrl;
727 uint32_t odr;
728 uint32_t ir;
729 uint32_t rr1;
730 uint32_t isr1h;
731 uint32_t isr1l;
732 };
733
734 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)
735 {
736 #ifdef DEBUG_GPIO
737 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
738 #endif
739
740 return 0;
741 }
742
743 static void ppc405_gpio_writeb (void *opaque,
744 target_phys_addr_t addr, uint32_t value)
745 {
746 #ifdef DEBUG_GPIO
747 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
748 value);
749 #endif
750 }
751
752 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)
753 {
754 #ifdef DEBUG_GPIO
755 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
756 #endif
757
758 return 0;
759 }
760
761 static void ppc405_gpio_writew (void *opaque,
762 target_phys_addr_t addr, uint32_t value)
763 {
764 #ifdef DEBUG_GPIO
765 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
766 value);
767 #endif
768 }
769
770 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)
771 {
772 #ifdef DEBUG_GPIO
773 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
774 #endif
775
776 return 0;
777 }
778
779 static void ppc405_gpio_writel (void *opaque,
780 target_phys_addr_t addr, uint32_t value)
781 {
782 #ifdef DEBUG_GPIO
783 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
784 value);
785 #endif
786 }
787
788 static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
789 &ppc405_gpio_readb,
790 &ppc405_gpio_readw,
791 &ppc405_gpio_readl,
792 };
793
794 static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
795 &ppc405_gpio_writeb,
796 &ppc405_gpio_writew,
797 &ppc405_gpio_writel,
798 };
799
800 static void ppc405_gpio_reset (void *opaque)
801 {
802 }
803
804 static void ppc405_gpio_init(target_phys_addr_t base)
805 {
806 ppc405_gpio_t *gpio;
807 int io;
808
809 gpio = qemu_mallocz(sizeof(ppc405_gpio_t));
810 #ifdef DEBUG_GPIO
811 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
812 #endif
813 io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio,
814 DEVICE_NATIVE_ENDIAN);
815 cpu_register_physical_memory(base, 0x038, io);
816 qemu_register_reset(&ppc405_gpio_reset, gpio);
817 }
818
819 /*****************************************************************************/
820 /* On Chip Memory */
821 enum {
822 OCM0_ISARC = 0x018,
823 OCM0_ISACNTL = 0x019,
824 OCM0_DSARC = 0x01A,
825 OCM0_DSACNTL = 0x01B,
826 };
827
828 typedef struct ppc405_ocm_t ppc405_ocm_t;
829 struct ppc405_ocm_t {
830 target_ulong offset;
831 uint32_t isarc;
832 uint32_t isacntl;
833 uint32_t dsarc;
834 uint32_t dsacntl;
835 };
836
837 static void ocm_update_mappings (ppc405_ocm_t *ocm,
838 uint32_t isarc, uint32_t isacntl,
839 uint32_t dsarc, uint32_t dsacntl)
840 {
841 #ifdef DEBUG_OCM
842 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
843 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
844 " (%08" PRIx32 " %08" PRIx32 ")\n",
845 isarc, isacntl, dsarc, dsacntl,
846 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
847 #endif
848 if (ocm->isarc != isarc ||
849 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
850 if (ocm->isacntl & 0x80000000) {
851 /* Unmap previously assigned memory region */
852 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
853 cpu_register_physical_memory(ocm->isarc, 0x04000000,
854 IO_MEM_UNASSIGNED);
855 }
856 if (isacntl & 0x80000000) {
857 /* Map new instruction memory region */
858 #ifdef DEBUG_OCM
859 printf("OCM map ISA %08" PRIx32 "\n", isarc);
860 #endif
861 cpu_register_physical_memory(isarc, 0x04000000,
862 ocm->offset | IO_MEM_RAM);
863 }
864 }
865 if (ocm->dsarc != dsarc ||
866 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
867 if (ocm->dsacntl & 0x80000000) {
868 /* Beware not to unmap the region we just mapped */
869 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
870 /* Unmap previously assigned memory region */
871 #ifdef DEBUG_OCM
872 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
873 #endif
874 cpu_register_physical_memory(ocm->dsarc, 0x04000000,
875 IO_MEM_UNASSIGNED);
876 }
877 }
878 if (dsacntl & 0x80000000) {
879 /* Beware not to remap the region we just mapped */
880 if (!(isacntl & 0x80000000) || dsarc != isarc) {
881 /* Map new data memory region */
882 #ifdef DEBUG_OCM
883 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
884 #endif
885 cpu_register_physical_memory(dsarc, 0x04000000,
886 ocm->offset | IO_MEM_RAM);
887 }
888 }
889 }
890 }
891
892 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
893 {
894 ppc405_ocm_t *ocm;
895 uint32_t ret;
896
897 ocm = opaque;
898 switch (dcrn) {
899 case OCM0_ISARC:
900 ret = ocm->isarc;
901 break;
902 case OCM0_ISACNTL:
903 ret = ocm->isacntl;
904 break;
905 case OCM0_DSARC:
906 ret = ocm->dsarc;
907 break;
908 case OCM0_DSACNTL:
909 ret = ocm->dsacntl;
910 break;
911 default:
912 ret = 0;
913 break;
914 }
915
916 return ret;
917 }
918
919 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
920 {
921 ppc405_ocm_t *ocm;
922 uint32_t isarc, dsarc, isacntl, dsacntl;
923
924 ocm = opaque;
925 isarc = ocm->isarc;
926 dsarc = ocm->dsarc;
927 isacntl = ocm->isacntl;
928 dsacntl = ocm->dsacntl;
929 switch (dcrn) {
930 case OCM0_ISARC:
931 isarc = val & 0xFC000000;
932 break;
933 case OCM0_ISACNTL:
934 isacntl = val & 0xC0000000;
935 break;
936 case OCM0_DSARC:
937 isarc = val & 0xFC000000;
938 break;
939 case OCM0_DSACNTL:
940 isacntl = val & 0xC0000000;
941 break;
942 }
943 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
944 ocm->isarc = isarc;
945 ocm->dsarc = dsarc;
946 ocm->isacntl = isacntl;
947 ocm->dsacntl = dsacntl;
948 }
949
950 static void ocm_reset (void *opaque)
951 {
952 ppc405_ocm_t *ocm;
953 uint32_t isarc, dsarc, isacntl, dsacntl;
954
955 ocm = opaque;
956 isarc = 0x00000000;
957 isacntl = 0x00000000;
958 dsarc = 0x00000000;
959 dsacntl = 0x00000000;
960 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
961 ocm->isarc = isarc;
962 ocm->dsarc = dsarc;
963 ocm->isacntl = isacntl;
964 ocm->dsacntl = dsacntl;
965 }
966
967 static void ppc405_ocm_init(CPUState *env)
968 {
969 ppc405_ocm_t *ocm;
970
971 ocm = qemu_mallocz(sizeof(ppc405_ocm_t));
972 ocm->offset = qemu_ram_alloc(NULL, "ppc405.ocm", 4096);
973 qemu_register_reset(&ocm_reset, ocm);
974 ppc_dcr_register(env, OCM0_ISARC,
975 ocm, &dcr_read_ocm, &dcr_write_ocm);
976 ppc_dcr_register(env, OCM0_ISACNTL,
977 ocm, &dcr_read_ocm, &dcr_write_ocm);
978 ppc_dcr_register(env, OCM0_DSARC,
979 ocm, &dcr_read_ocm, &dcr_write_ocm);
980 ppc_dcr_register(env, OCM0_DSACNTL,
981 ocm, &dcr_read_ocm, &dcr_write_ocm);
982 }
983
984 /*****************************************************************************/
985 /* I2C controller */
986 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
987 struct ppc4xx_i2c_t {
988 qemu_irq irq;
989 uint8_t mdata;
990 uint8_t lmadr;
991 uint8_t hmadr;
992 uint8_t cntl;
993 uint8_t mdcntl;
994 uint8_t sts;
995 uint8_t extsts;
996 uint8_t sdata;
997 uint8_t lsadr;
998 uint8_t hsadr;
999 uint8_t clkdiv;
1000 uint8_t intrmsk;
1001 uint8_t xfrcnt;
1002 uint8_t xtcntlss;
1003 uint8_t directcntl;
1004 };
1005
1006 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)
1007 {
1008 ppc4xx_i2c_t *i2c;
1009 uint32_t ret;
1010
1011 #ifdef DEBUG_I2C
1012 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1013 #endif
1014 i2c = opaque;
1015 switch (addr) {
1016 case 0x00:
1017 // i2c_readbyte(&i2c->mdata);
1018 ret = i2c->mdata;
1019 break;
1020 case 0x02:
1021 ret = i2c->sdata;
1022 break;
1023 case 0x04:
1024 ret = i2c->lmadr;
1025 break;
1026 case 0x05:
1027 ret = i2c->hmadr;
1028 break;
1029 case 0x06:
1030 ret = i2c->cntl;
1031 break;
1032 case 0x07:
1033 ret = i2c->mdcntl;
1034 break;
1035 case 0x08:
1036 ret = i2c->sts;
1037 break;
1038 case 0x09:
1039 ret = i2c->extsts;
1040 break;
1041 case 0x0A:
1042 ret = i2c->lsadr;
1043 break;
1044 case 0x0B:
1045 ret = i2c->hsadr;
1046 break;
1047 case 0x0C:
1048 ret = i2c->clkdiv;
1049 break;
1050 case 0x0D:
1051 ret = i2c->intrmsk;
1052 break;
1053 case 0x0E:
1054 ret = i2c->xfrcnt;
1055 break;
1056 case 0x0F:
1057 ret = i2c->xtcntlss;
1058 break;
1059 case 0x10:
1060 ret = i2c->directcntl;
1061 break;
1062 default:
1063 ret = 0x00;
1064 break;
1065 }
1066 #ifdef DEBUG_I2C
1067 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1068 #endif
1069
1070 return ret;
1071 }
1072
1073 static void ppc4xx_i2c_writeb (void *opaque,
1074 target_phys_addr_t addr, uint32_t value)
1075 {
1076 ppc4xx_i2c_t *i2c;
1077
1078 #ifdef DEBUG_I2C
1079 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1080 value);
1081 #endif
1082 i2c = opaque;
1083 switch (addr) {
1084 case 0x00:
1085 i2c->mdata = value;
1086 // i2c_sendbyte(&i2c->mdata);
1087 break;
1088 case 0x02:
1089 i2c->sdata = value;
1090 break;
1091 case 0x04:
1092 i2c->lmadr = value;
1093 break;
1094 case 0x05:
1095 i2c->hmadr = value;
1096 break;
1097 case 0x06:
1098 i2c->cntl = value;
1099 break;
1100 case 0x07:
1101 i2c->mdcntl = value & 0xDF;
1102 break;
1103 case 0x08:
1104 i2c->sts &= ~(value & 0x0A);
1105 break;
1106 case 0x09:
1107 i2c->extsts &= ~(value & 0x8F);
1108 break;
1109 case 0x0A:
1110 i2c->lsadr = value;
1111 break;
1112 case 0x0B:
1113 i2c->hsadr = value;
1114 break;
1115 case 0x0C:
1116 i2c->clkdiv = value;
1117 break;
1118 case 0x0D:
1119 i2c->intrmsk = value;
1120 break;
1121 case 0x0E:
1122 i2c->xfrcnt = value & 0x77;
1123 break;
1124 case 0x0F:
1125 i2c->xtcntlss = value;
1126 break;
1127 case 0x10:
1128 i2c->directcntl = value & 0x7;
1129 break;
1130 }
1131 }
1132
1133 static uint32_t ppc4xx_i2c_readw (void *opaque, target_phys_addr_t addr)
1134 {
1135 uint32_t ret;
1136
1137 #ifdef DEBUG_I2C
1138 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1139 #endif
1140 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1141 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1142
1143 return ret;
1144 }
1145
1146 static void ppc4xx_i2c_writew (void *opaque,
1147 target_phys_addr_t addr, uint32_t value)
1148 {
1149 #ifdef DEBUG_I2C
1150 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1151 value);
1152 #endif
1153 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1154 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1155 }
1156
1157 static uint32_t ppc4xx_i2c_readl (void *opaque, target_phys_addr_t addr)
1158 {
1159 uint32_t ret;
1160
1161 #ifdef DEBUG_I2C
1162 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1163 #endif
1164 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1165 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1166 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1167 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1168
1169 return ret;
1170 }
1171
1172 static void ppc4xx_i2c_writel (void *opaque,
1173 target_phys_addr_t addr, uint32_t value)
1174 {
1175 #ifdef DEBUG_I2C
1176 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1177 value);
1178 #endif
1179 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1180 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1181 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1182 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1183 }
1184
1185 static CPUReadMemoryFunc * const i2c_read[] = {
1186 &ppc4xx_i2c_readb,
1187 &ppc4xx_i2c_readw,
1188 &ppc4xx_i2c_readl,
1189 };
1190
1191 static CPUWriteMemoryFunc * const i2c_write[] = {
1192 &ppc4xx_i2c_writeb,
1193 &ppc4xx_i2c_writew,
1194 &ppc4xx_i2c_writel,
1195 };
1196
1197 static void ppc4xx_i2c_reset (void *opaque)
1198 {
1199 ppc4xx_i2c_t *i2c;
1200
1201 i2c = opaque;
1202 i2c->mdata = 0x00;
1203 i2c->sdata = 0x00;
1204 i2c->cntl = 0x00;
1205 i2c->mdcntl = 0x00;
1206 i2c->sts = 0x00;
1207 i2c->extsts = 0x00;
1208 i2c->clkdiv = 0x00;
1209 i2c->xfrcnt = 0x00;
1210 i2c->directcntl = 0x0F;
1211 }
1212
1213 static void ppc405_i2c_init(target_phys_addr_t base, qemu_irq irq)
1214 {
1215 ppc4xx_i2c_t *i2c;
1216 int io;
1217
1218 i2c = qemu_mallocz(sizeof(ppc4xx_i2c_t));
1219 i2c->irq = irq;
1220 #ifdef DEBUG_I2C
1221 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1222 #endif
1223 io = cpu_register_io_memory(i2c_read, i2c_write, i2c,
1224 DEVICE_NATIVE_ENDIAN);
1225 cpu_register_physical_memory(base, 0x011, io);
1226 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1227 }
1228
1229 /*****************************************************************************/
1230 /* General purpose timers */
1231 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1232 struct ppc4xx_gpt_t {
1233 int64_t tb_offset;
1234 uint32_t tb_freq;
1235 struct QEMUTimer *timer;
1236 qemu_irq irqs[5];
1237 uint32_t oe;
1238 uint32_t ol;
1239 uint32_t im;
1240 uint32_t is;
1241 uint32_t ie;
1242 uint32_t comp[5];
1243 uint32_t mask[5];
1244 };
1245
1246 static uint32_t ppc4xx_gpt_readb (void *opaque, target_phys_addr_t addr)
1247 {
1248 #ifdef DEBUG_GPT
1249 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1250 #endif
1251 /* XXX: generate a bus fault */
1252 return -1;
1253 }
1254
1255 static void ppc4xx_gpt_writeb (void *opaque,
1256 target_phys_addr_t addr, uint32_t value)
1257 {
1258 #ifdef DEBUG_I2C
1259 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1260 value);
1261 #endif
1262 /* XXX: generate a bus fault */
1263 }
1264
1265 static uint32_t ppc4xx_gpt_readw (void *opaque, target_phys_addr_t addr)
1266 {
1267 #ifdef DEBUG_GPT
1268 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1269 #endif
1270 /* XXX: generate a bus fault */
1271 return -1;
1272 }
1273
1274 static void ppc4xx_gpt_writew (void *opaque,
1275 target_phys_addr_t addr, uint32_t value)
1276 {
1277 #ifdef DEBUG_I2C
1278 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1279 value);
1280 #endif
1281 /* XXX: generate a bus fault */
1282 }
1283
1284 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1285 {
1286 /* XXX: TODO */
1287 return 0;
1288 }
1289
1290 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1291 {
1292 /* XXX: TODO */
1293 }
1294
1295 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1296 {
1297 uint32_t mask;
1298 int i;
1299
1300 mask = 0x80000000;
1301 for (i = 0; i < 5; i++) {
1302 if (gpt->oe & mask) {
1303 /* Output is enabled */
1304 if (ppc4xx_gpt_compare(gpt, i)) {
1305 /* Comparison is OK */
1306 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1307 } else {
1308 /* Comparison is KO */
1309 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1310 }
1311 }
1312 mask = mask >> 1;
1313 }
1314 }
1315
1316 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1317 {
1318 uint32_t mask;
1319 int i;
1320
1321 mask = 0x00008000;
1322 for (i = 0; i < 5; i++) {
1323 if (gpt->is & gpt->im & mask)
1324 qemu_irq_raise(gpt->irqs[i]);
1325 else
1326 qemu_irq_lower(gpt->irqs[i]);
1327 mask = mask >> 1;
1328 }
1329 }
1330
1331 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1332 {
1333 /* XXX: TODO */
1334 }
1335
1336 static uint32_t ppc4xx_gpt_readl (void *opaque, target_phys_addr_t addr)
1337 {
1338 ppc4xx_gpt_t *gpt;
1339 uint32_t ret;
1340 int idx;
1341
1342 #ifdef DEBUG_GPT
1343 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1344 #endif
1345 gpt = opaque;
1346 switch (addr) {
1347 case 0x00:
1348 /* Time base counter */
1349 ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
1350 gpt->tb_freq, get_ticks_per_sec());
1351 break;
1352 case 0x10:
1353 /* Output enable */
1354 ret = gpt->oe;
1355 break;
1356 case 0x14:
1357 /* Output level */
1358 ret = gpt->ol;
1359 break;
1360 case 0x18:
1361 /* Interrupt mask */
1362 ret = gpt->im;
1363 break;
1364 case 0x1C:
1365 case 0x20:
1366 /* Interrupt status */
1367 ret = gpt->is;
1368 break;
1369 case 0x24:
1370 /* Interrupt enable */
1371 ret = gpt->ie;
1372 break;
1373 case 0x80 ... 0x90:
1374 /* Compare timer */
1375 idx = (addr - 0x80) >> 2;
1376 ret = gpt->comp[idx];
1377 break;
1378 case 0xC0 ... 0xD0:
1379 /* Compare mask */
1380 idx = (addr - 0xC0) >> 2;
1381 ret = gpt->mask[idx];
1382 break;
1383 default:
1384 ret = -1;
1385 break;
1386 }
1387
1388 return ret;
1389 }
1390
1391 static void ppc4xx_gpt_writel (void *opaque,
1392 target_phys_addr_t addr, uint32_t value)
1393 {
1394 ppc4xx_gpt_t *gpt;
1395 int idx;
1396
1397 #ifdef DEBUG_I2C
1398 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1399 value);
1400 #endif
1401 gpt = opaque;
1402 switch (addr) {
1403 case 0x00:
1404 /* Time base counter */
1405 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1406 - qemu_get_clock(vm_clock);
1407 ppc4xx_gpt_compute_timer(gpt);
1408 break;
1409 case 0x10:
1410 /* Output enable */
1411 gpt->oe = value & 0xF8000000;
1412 ppc4xx_gpt_set_outputs(gpt);
1413 break;
1414 case 0x14:
1415 /* Output level */
1416 gpt->ol = value & 0xF8000000;
1417 ppc4xx_gpt_set_outputs(gpt);
1418 break;
1419 case 0x18:
1420 /* Interrupt mask */
1421 gpt->im = value & 0x0000F800;
1422 break;
1423 case 0x1C:
1424 /* Interrupt status set */
1425 gpt->is |= value & 0x0000F800;
1426 ppc4xx_gpt_set_irqs(gpt);
1427 break;
1428 case 0x20:
1429 /* Interrupt status clear */
1430 gpt->is &= ~(value & 0x0000F800);
1431 ppc4xx_gpt_set_irqs(gpt);
1432 break;
1433 case 0x24:
1434 /* Interrupt enable */
1435 gpt->ie = value & 0x0000F800;
1436 ppc4xx_gpt_set_irqs(gpt);
1437 break;
1438 case 0x80 ... 0x90:
1439 /* Compare timer */
1440 idx = (addr - 0x80) >> 2;
1441 gpt->comp[idx] = value & 0xF8000000;
1442 ppc4xx_gpt_compute_timer(gpt);
1443 break;
1444 case 0xC0 ... 0xD0:
1445 /* Compare mask */
1446 idx = (addr - 0xC0) >> 2;
1447 gpt->mask[idx] = value & 0xF8000000;
1448 ppc4xx_gpt_compute_timer(gpt);
1449 break;
1450 }
1451 }
1452
1453 static CPUReadMemoryFunc * const gpt_read[] = {
1454 &ppc4xx_gpt_readb,
1455 &ppc4xx_gpt_readw,
1456 &ppc4xx_gpt_readl,
1457 };
1458
1459 static CPUWriteMemoryFunc * const gpt_write[] = {
1460 &ppc4xx_gpt_writeb,
1461 &ppc4xx_gpt_writew,
1462 &ppc4xx_gpt_writel,
1463 };
1464
1465 static void ppc4xx_gpt_cb (void *opaque)
1466 {
1467 ppc4xx_gpt_t *gpt;
1468
1469 gpt = opaque;
1470 ppc4xx_gpt_set_irqs(gpt);
1471 ppc4xx_gpt_set_outputs(gpt);
1472 ppc4xx_gpt_compute_timer(gpt);
1473 }
1474
1475 static void ppc4xx_gpt_reset (void *opaque)
1476 {
1477 ppc4xx_gpt_t *gpt;
1478 int i;
1479
1480 gpt = opaque;
1481 qemu_del_timer(gpt->timer);
1482 gpt->oe = 0x00000000;
1483 gpt->ol = 0x00000000;
1484 gpt->im = 0x00000000;
1485 gpt->is = 0x00000000;
1486 gpt->ie = 0x00000000;
1487 for (i = 0; i < 5; i++) {
1488 gpt->comp[i] = 0x00000000;
1489 gpt->mask[i] = 0x00000000;
1490 }
1491 }
1492
1493 static void ppc4xx_gpt_init(target_phys_addr_t base, qemu_irq irqs[5])
1494 {
1495 ppc4xx_gpt_t *gpt;
1496 int i;
1497 int io;
1498
1499 gpt = qemu_mallocz(sizeof(ppc4xx_gpt_t));
1500 for (i = 0; i < 5; i++) {
1501 gpt->irqs[i] = irqs[i];
1502 }
1503 gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
1504 #ifdef DEBUG_GPT
1505 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1506 #endif
1507 io = cpu_register_io_memory(gpt_read, gpt_write, gpt, DEVICE_NATIVE_ENDIAN);
1508 cpu_register_physical_memory(base, 0x0d4, io);
1509 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1510 }
1511
1512 /*****************************************************************************/
1513 /* MAL */
1514 enum {
1515 MAL0_CFG = 0x180,
1516 MAL0_ESR = 0x181,
1517 MAL0_IER = 0x182,
1518 MAL0_TXCASR = 0x184,
1519 MAL0_TXCARR = 0x185,
1520 MAL0_TXEOBISR = 0x186,
1521 MAL0_TXDEIR = 0x187,
1522 MAL0_RXCASR = 0x190,
1523 MAL0_RXCARR = 0x191,
1524 MAL0_RXEOBISR = 0x192,
1525 MAL0_RXDEIR = 0x193,
1526 MAL0_TXCTP0R = 0x1A0,
1527 MAL0_TXCTP1R = 0x1A1,
1528 MAL0_TXCTP2R = 0x1A2,
1529 MAL0_TXCTP3R = 0x1A3,
1530 MAL0_RXCTP0R = 0x1C0,
1531 MAL0_RXCTP1R = 0x1C1,
1532 MAL0_RCBS0 = 0x1E0,
1533 MAL0_RCBS1 = 0x1E1,
1534 };
1535
1536 typedef struct ppc40x_mal_t ppc40x_mal_t;
1537 struct ppc40x_mal_t {
1538 qemu_irq irqs[4];
1539 uint32_t cfg;
1540 uint32_t esr;
1541 uint32_t ier;
1542 uint32_t txcasr;
1543 uint32_t txcarr;
1544 uint32_t txeobisr;
1545 uint32_t txdeir;
1546 uint32_t rxcasr;
1547 uint32_t rxcarr;
1548 uint32_t rxeobisr;
1549 uint32_t rxdeir;
1550 uint32_t txctpr[4];
1551 uint32_t rxctpr[2];
1552 uint32_t rcbs[2];
1553 };
1554
1555 static void ppc40x_mal_reset (void *opaque);
1556
1557 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1558 {
1559 ppc40x_mal_t *mal;
1560 uint32_t ret;
1561
1562 mal = opaque;
1563 switch (dcrn) {
1564 case MAL0_CFG:
1565 ret = mal->cfg;
1566 break;
1567 case MAL0_ESR:
1568 ret = mal->esr;
1569 break;
1570 case MAL0_IER:
1571 ret = mal->ier;
1572 break;
1573 case MAL0_TXCASR:
1574 ret = mal->txcasr;
1575 break;
1576 case MAL0_TXCARR:
1577 ret = mal->txcarr;
1578 break;
1579 case MAL0_TXEOBISR:
1580 ret = mal->txeobisr;
1581 break;
1582 case MAL0_TXDEIR:
1583 ret = mal->txdeir;
1584 break;
1585 case MAL0_RXCASR:
1586 ret = mal->rxcasr;
1587 break;
1588 case MAL0_RXCARR:
1589 ret = mal->rxcarr;
1590 break;
1591 case MAL0_RXEOBISR:
1592 ret = mal->rxeobisr;
1593 break;
1594 case MAL0_RXDEIR:
1595 ret = mal->rxdeir;
1596 break;
1597 case MAL0_TXCTP0R:
1598 ret = mal->txctpr[0];
1599 break;
1600 case MAL0_TXCTP1R:
1601 ret = mal->txctpr[1];
1602 break;
1603 case MAL0_TXCTP2R:
1604 ret = mal->txctpr[2];
1605 break;
1606 case MAL0_TXCTP3R:
1607 ret = mal->txctpr[3];
1608 break;
1609 case MAL0_RXCTP0R:
1610 ret = mal->rxctpr[0];
1611 break;
1612 case MAL0_RXCTP1R:
1613 ret = mal->rxctpr[1];
1614 break;
1615 case MAL0_RCBS0:
1616 ret = mal->rcbs[0];
1617 break;
1618 case MAL0_RCBS1:
1619 ret = mal->rcbs[1];
1620 break;
1621 default:
1622 ret = 0;
1623 break;
1624 }
1625
1626 return ret;
1627 }
1628
1629 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1630 {
1631 ppc40x_mal_t *mal;
1632 int idx;
1633
1634 mal = opaque;
1635 switch (dcrn) {
1636 case MAL0_CFG:
1637 if (val & 0x80000000)
1638 ppc40x_mal_reset(mal);
1639 mal->cfg = val & 0x00FFC087;
1640 break;
1641 case MAL0_ESR:
1642 /* Read/clear */
1643 mal->esr &= ~val;
1644 break;
1645 case MAL0_IER:
1646 mal->ier = val & 0x0000001F;
1647 break;
1648 case MAL0_TXCASR:
1649 mal->txcasr = val & 0xF0000000;
1650 break;
1651 case MAL0_TXCARR:
1652 mal->txcarr = val & 0xF0000000;
1653 break;
1654 case MAL0_TXEOBISR:
1655 /* Read/clear */
1656 mal->txeobisr &= ~val;
1657 break;
1658 case MAL0_TXDEIR:
1659 /* Read/clear */
1660 mal->txdeir &= ~val;
1661 break;
1662 case MAL0_RXCASR:
1663 mal->rxcasr = val & 0xC0000000;
1664 break;
1665 case MAL0_RXCARR:
1666 mal->rxcarr = val & 0xC0000000;
1667 break;
1668 case MAL0_RXEOBISR:
1669 /* Read/clear */
1670 mal->rxeobisr &= ~val;
1671 break;
1672 case MAL0_RXDEIR:
1673 /* Read/clear */
1674 mal->rxdeir &= ~val;
1675 break;
1676 case MAL0_TXCTP0R:
1677 idx = 0;
1678 goto update_tx_ptr;
1679 case MAL0_TXCTP1R:
1680 idx = 1;
1681 goto update_tx_ptr;
1682 case MAL0_TXCTP2R:
1683 idx = 2;
1684 goto update_tx_ptr;
1685 case MAL0_TXCTP3R:
1686 idx = 3;
1687 update_tx_ptr:
1688 mal->txctpr[idx] = val;
1689 break;
1690 case MAL0_RXCTP0R:
1691 idx = 0;
1692 goto update_rx_ptr;
1693 case MAL0_RXCTP1R:
1694 idx = 1;
1695 update_rx_ptr:
1696 mal->rxctpr[idx] = val;
1697 break;
1698 case MAL0_RCBS0:
1699 idx = 0;
1700 goto update_rx_size;
1701 case MAL0_RCBS1:
1702 idx = 1;
1703 update_rx_size:
1704 mal->rcbs[idx] = val & 0x000000FF;
1705 break;
1706 }
1707 }
1708
1709 static void ppc40x_mal_reset (void *opaque)
1710 {
1711 ppc40x_mal_t *mal;
1712
1713 mal = opaque;
1714 mal->cfg = 0x0007C000;
1715 mal->esr = 0x00000000;
1716 mal->ier = 0x00000000;
1717 mal->rxcasr = 0x00000000;
1718 mal->rxdeir = 0x00000000;
1719 mal->rxeobisr = 0x00000000;
1720 mal->txcasr = 0x00000000;
1721 mal->txdeir = 0x00000000;
1722 mal->txeobisr = 0x00000000;
1723 }
1724
1725 static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
1726 {
1727 ppc40x_mal_t *mal;
1728 int i;
1729
1730 mal = qemu_mallocz(sizeof(ppc40x_mal_t));
1731 for (i = 0; i < 4; i++)
1732 mal->irqs[i] = irqs[i];
1733 qemu_register_reset(&ppc40x_mal_reset, mal);
1734 ppc_dcr_register(env, MAL0_CFG,
1735 mal, &dcr_read_mal, &dcr_write_mal);
1736 ppc_dcr_register(env, MAL0_ESR,
1737 mal, &dcr_read_mal, &dcr_write_mal);
1738 ppc_dcr_register(env, MAL0_IER,
1739 mal, &dcr_read_mal, &dcr_write_mal);
1740 ppc_dcr_register(env, MAL0_TXCASR,
1741 mal, &dcr_read_mal, &dcr_write_mal);
1742 ppc_dcr_register(env, MAL0_TXCARR,
1743 mal, &dcr_read_mal, &dcr_write_mal);
1744 ppc_dcr_register(env, MAL0_TXEOBISR,
1745 mal, &dcr_read_mal, &dcr_write_mal);
1746 ppc_dcr_register(env, MAL0_TXDEIR,
1747 mal, &dcr_read_mal, &dcr_write_mal);
1748 ppc_dcr_register(env, MAL0_RXCASR,
1749 mal, &dcr_read_mal, &dcr_write_mal);
1750 ppc_dcr_register(env, MAL0_RXCARR,
1751 mal, &dcr_read_mal, &dcr_write_mal);
1752 ppc_dcr_register(env, MAL0_RXEOBISR,
1753 mal, &dcr_read_mal, &dcr_write_mal);
1754 ppc_dcr_register(env, MAL0_RXDEIR,
1755 mal, &dcr_read_mal, &dcr_write_mal);
1756 ppc_dcr_register(env, MAL0_TXCTP0R,
1757 mal, &dcr_read_mal, &dcr_write_mal);
1758 ppc_dcr_register(env, MAL0_TXCTP1R,
1759 mal, &dcr_read_mal, &dcr_write_mal);
1760 ppc_dcr_register(env, MAL0_TXCTP2R,
1761 mal, &dcr_read_mal, &dcr_write_mal);
1762 ppc_dcr_register(env, MAL0_TXCTP3R,
1763 mal, &dcr_read_mal, &dcr_write_mal);
1764 ppc_dcr_register(env, MAL0_RXCTP0R,
1765 mal, &dcr_read_mal, &dcr_write_mal);
1766 ppc_dcr_register(env, MAL0_RXCTP1R,
1767 mal, &dcr_read_mal, &dcr_write_mal);
1768 ppc_dcr_register(env, MAL0_RCBS0,
1769 mal, &dcr_read_mal, &dcr_write_mal);
1770 ppc_dcr_register(env, MAL0_RCBS1,
1771 mal, &dcr_read_mal, &dcr_write_mal);
1772 }
1773
1774 /*****************************************************************************/
1775 /* SPR */
1776 void ppc40x_core_reset (CPUState *env)
1777 {
1778 target_ulong dbsr;
1779
1780 printf("Reset PowerPC core\n");
1781 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1782 /* XXX: TOFIX */
1783 #if 0
1784 cpu_reset(env);
1785 #else
1786 qemu_system_reset_request();
1787 #endif
1788 dbsr = env->spr[SPR_40x_DBSR];
1789 dbsr &= ~0x00000300;
1790 dbsr |= 0x00000100;
1791 env->spr[SPR_40x_DBSR] = dbsr;
1792 }
1793
1794 void ppc40x_chip_reset (CPUState *env)
1795 {
1796 target_ulong dbsr;
1797
1798 printf("Reset PowerPC chip\n");
1799 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1800 /* XXX: TOFIX */
1801 #if 0
1802 cpu_reset(env);
1803 #else
1804 qemu_system_reset_request();
1805 #endif
1806 /* XXX: TODO reset all internal peripherals */
1807 dbsr = env->spr[SPR_40x_DBSR];
1808 dbsr &= ~0x00000300;
1809 dbsr |= 0x00000200;
1810 env->spr[SPR_40x_DBSR] = dbsr;
1811 }
1812
1813 void ppc40x_system_reset (CPUState *env)
1814 {
1815 printf("Reset PowerPC system\n");
1816 qemu_system_reset_request();
1817 }
1818
1819 void store_40x_dbcr0 (CPUState *env, uint32_t val)
1820 {
1821 switch ((val >> 28) & 0x3) {
1822 case 0x0:
1823 /* No action */
1824 break;
1825 case 0x1:
1826 /* Core reset */
1827 ppc40x_core_reset(env);
1828 break;
1829 case 0x2:
1830 /* Chip reset */
1831 ppc40x_chip_reset(env);
1832 break;
1833 case 0x3:
1834 /* System reset */
1835 ppc40x_system_reset(env);
1836 break;
1837 }
1838 }
1839
1840 /*****************************************************************************/
1841 /* PowerPC 405CR */
1842 enum {
1843 PPC405CR_CPC0_PLLMR = 0x0B0,
1844 PPC405CR_CPC0_CR0 = 0x0B1,
1845 PPC405CR_CPC0_CR1 = 0x0B2,
1846 PPC405CR_CPC0_PSR = 0x0B4,
1847 PPC405CR_CPC0_JTAGID = 0x0B5,
1848 PPC405CR_CPC0_ER = 0x0B9,
1849 PPC405CR_CPC0_FR = 0x0BA,
1850 PPC405CR_CPC0_SR = 0x0BB,
1851 };
1852
1853 enum {
1854 PPC405CR_CPU_CLK = 0,
1855 PPC405CR_TMR_CLK = 1,
1856 PPC405CR_PLB_CLK = 2,
1857 PPC405CR_SDRAM_CLK = 3,
1858 PPC405CR_OPB_CLK = 4,
1859 PPC405CR_EXT_CLK = 5,
1860 PPC405CR_UART_CLK = 6,
1861 PPC405CR_CLK_NB = 7,
1862 };
1863
1864 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1865 struct ppc405cr_cpc_t {
1866 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1867 uint32_t sysclk;
1868 uint32_t psr;
1869 uint32_t cr0;
1870 uint32_t cr1;
1871 uint32_t jtagid;
1872 uint32_t pllmr;
1873 uint32_t er;
1874 uint32_t fr;
1875 };
1876
1877 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1878 {
1879 uint64_t VCO_out, PLL_out;
1880 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1881 int M, D0, D1, D2;
1882
1883 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1884 if (cpc->pllmr & 0x80000000) {
1885 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1886 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1887 M = D0 * D1 * D2;
1888 VCO_out = cpc->sysclk * M;
1889 if (VCO_out < 400000000 || VCO_out > 800000000) {
1890 /* PLL cannot lock */
1891 cpc->pllmr &= ~0x80000000;
1892 goto bypass_pll;
1893 }
1894 PLL_out = VCO_out / D2;
1895 } else {
1896 /* Bypass PLL */
1897 bypass_pll:
1898 M = D0;
1899 PLL_out = cpc->sysclk * M;
1900 }
1901 CPU_clk = PLL_out;
1902 if (cpc->cr1 & 0x00800000)
1903 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1904 else
1905 TMR_clk = CPU_clk;
1906 PLB_clk = CPU_clk / D0;
1907 SDRAM_clk = PLB_clk;
1908 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1909 OPB_clk = PLB_clk / D0;
1910 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1911 EXT_clk = PLB_clk / D0;
1912 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1913 UART_clk = CPU_clk / D0;
1914 /* Setup CPU clocks */
1915 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1916 /* Setup time-base clock */
1917 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1918 /* Setup PLB clock */
1919 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1920 /* Setup SDRAM clock */
1921 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1922 /* Setup OPB clock */
1923 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1924 /* Setup external clock */
1925 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1926 /* Setup UART clock */
1927 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1928 }
1929
1930 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1931 {
1932 ppc405cr_cpc_t *cpc;
1933 uint32_t ret;
1934
1935 cpc = opaque;
1936 switch (dcrn) {
1937 case PPC405CR_CPC0_PLLMR:
1938 ret = cpc->pllmr;
1939 break;
1940 case PPC405CR_CPC0_CR0:
1941 ret = cpc->cr0;
1942 break;
1943 case PPC405CR_CPC0_CR1:
1944 ret = cpc->cr1;
1945 break;
1946 case PPC405CR_CPC0_PSR:
1947 ret = cpc->psr;
1948 break;
1949 case PPC405CR_CPC0_JTAGID:
1950 ret = cpc->jtagid;
1951 break;
1952 case PPC405CR_CPC0_ER:
1953 ret = cpc->er;
1954 break;
1955 case PPC405CR_CPC0_FR:
1956 ret = cpc->fr;
1957 break;
1958 case PPC405CR_CPC0_SR:
1959 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1960 break;
1961 default:
1962 /* Avoid gcc warning */
1963 ret = 0;
1964 break;
1965 }
1966
1967 return ret;
1968 }
1969
1970 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1971 {
1972 ppc405cr_cpc_t *cpc;
1973
1974 cpc = opaque;
1975 switch (dcrn) {
1976 case PPC405CR_CPC0_PLLMR:
1977 cpc->pllmr = val & 0xFFF77C3F;
1978 break;
1979 case PPC405CR_CPC0_CR0:
1980 cpc->cr0 = val & 0x0FFFFFFE;
1981 break;
1982 case PPC405CR_CPC0_CR1:
1983 cpc->cr1 = val & 0x00800000;
1984 break;
1985 case PPC405CR_CPC0_PSR:
1986 /* Read-only */
1987 break;
1988 case PPC405CR_CPC0_JTAGID:
1989 /* Read-only */
1990 break;
1991 case PPC405CR_CPC0_ER:
1992 cpc->er = val & 0xBFFC0000;
1993 break;
1994 case PPC405CR_CPC0_FR:
1995 cpc->fr = val & 0xBFFC0000;
1996 break;
1997 case PPC405CR_CPC0_SR:
1998 /* Read-only */
1999 break;
2000 }
2001 }
2002
2003 static void ppc405cr_cpc_reset (void *opaque)
2004 {
2005 ppc405cr_cpc_t *cpc;
2006 int D;
2007
2008 cpc = opaque;
2009 /* Compute PLLMR value from PSR settings */
2010 cpc->pllmr = 0x80000000;
2011 /* PFWD */
2012 switch ((cpc->psr >> 30) & 3) {
2013 case 0:
2014 /* Bypass */
2015 cpc->pllmr &= ~0x80000000;
2016 break;
2017 case 1:
2018 /* Divide by 3 */
2019 cpc->pllmr |= 5 << 16;
2020 break;
2021 case 2:
2022 /* Divide by 4 */
2023 cpc->pllmr |= 4 << 16;
2024 break;
2025 case 3:
2026 /* Divide by 6 */
2027 cpc->pllmr |= 2 << 16;
2028 break;
2029 }
2030 /* PFBD */
2031 D = (cpc->psr >> 28) & 3;
2032 cpc->pllmr |= (D + 1) << 20;
2033 /* PT */
2034 D = (cpc->psr >> 25) & 7;
2035 switch (D) {
2036 case 0x2:
2037 cpc->pllmr |= 0x13;
2038 break;
2039 case 0x4:
2040 cpc->pllmr |= 0x15;
2041 break;
2042 case 0x5:
2043 cpc->pllmr |= 0x16;
2044 break;
2045 default:
2046 break;
2047 }
2048 /* PDC */
2049 D = (cpc->psr >> 23) & 3;
2050 cpc->pllmr |= D << 26;
2051 /* ODP */
2052 D = (cpc->psr >> 21) & 3;
2053 cpc->pllmr |= D << 10;
2054 /* EBPD */
2055 D = (cpc->psr >> 17) & 3;
2056 cpc->pllmr |= D << 24;
2057 cpc->cr0 = 0x0000003C;
2058 cpc->cr1 = 0x2B0D8800;
2059 cpc->er = 0x00000000;
2060 cpc->fr = 0x00000000;
2061 ppc405cr_clk_setup(cpc);
2062 }
2063
2064 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2065 {
2066 int D;
2067
2068 /* XXX: this should be read from IO pins */
2069 cpc->psr = 0x00000000; /* 8 bits ROM */
2070 /* PFWD */
2071 D = 0x2; /* Divide by 4 */
2072 cpc->psr |= D << 30;
2073 /* PFBD */
2074 D = 0x1; /* Divide by 2 */
2075 cpc->psr |= D << 28;
2076 /* PDC */
2077 D = 0x1; /* Divide by 2 */
2078 cpc->psr |= D << 23;
2079 /* PT */
2080 D = 0x5; /* M = 16 */
2081 cpc->psr |= D << 25;
2082 /* ODP */
2083 D = 0x1; /* Divide by 2 */
2084 cpc->psr |= D << 21;
2085 /* EBDP */
2086 D = 0x2; /* Divide by 4 */
2087 cpc->psr |= D << 17;
2088 }
2089
2090 static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
2091 uint32_t sysclk)
2092 {
2093 ppc405cr_cpc_t *cpc;
2094
2095 cpc = qemu_mallocz(sizeof(ppc405cr_cpc_t));
2096 memcpy(cpc->clk_setup, clk_setup,
2097 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2098 cpc->sysclk = sysclk;
2099 cpc->jtagid = 0x42051049;
2100 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2101 &dcr_read_crcpc, &dcr_write_crcpc);
2102 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2103 &dcr_read_crcpc, &dcr_write_crcpc);
2104 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2105 &dcr_read_crcpc, &dcr_write_crcpc);
2106 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2107 &dcr_read_crcpc, &dcr_write_crcpc);
2108 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2109 &dcr_read_crcpc, &dcr_write_crcpc);
2110 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2111 &dcr_read_crcpc, &dcr_write_crcpc);
2112 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2113 &dcr_read_crcpc, &dcr_write_crcpc);
2114 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2115 &dcr_read_crcpc, &dcr_write_crcpc);
2116 ppc405cr_clk_init(cpc);
2117 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2118 }
2119
2120 CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
2121 target_phys_addr_t ram_sizes[4],
2122 uint32_t sysclk, qemu_irq **picp,
2123 int do_init)
2124 {
2125 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2126 qemu_irq dma_irqs[4];
2127 CPUState *env;
2128 qemu_irq *pic, *irqs;
2129
2130 memset(clk_setup, 0, sizeof(clk_setup));
2131 env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2132 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2133 /* Memory mapped devices registers */
2134 /* PLB arbitrer */
2135 ppc4xx_plb_init(env);
2136 /* PLB to OPB bridge */
2137 ppc4xx_pob_init(env);
2138 /* OBP arbitrer */
2139 ppc4xx_opba_init(0xef600600);
2140 /* Universal interrupt controller */
2141 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2142 irqs[PPCUIC_OUTPUT_INT] =
2143 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2144 irqs[PPCUIC_OUTPUT_CINT] =
2145 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2146 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2147 *picp = pic;
2148 /* SDRAM controller */
2149 ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
2150 /* External bus controller */
2151 ppc405_ebc_init(env);
2152 /* DMA controller */
2153 dma_irqs[0] = pic[26];
2154 dma_irqs[1] = pic[25];
2155 dma_irqs[2] = pic[24];
2156 dma_irqs[3] = pic[23];
2157 ppc405_dma_init(env, dma_irqs);
2158 /* Serial ports */
2159 if (serial_hds[0] != NULL) {
2160 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2161 serial_hds[0], 1, 1);
2162 }
2163 if (serial_hds[1] != NULL) {
2164 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2165 serial_hds[1], 1, 1);
2166 }
2167 /* IIC controller */
2168 ppc405_i2c_init(0xef600500, pic[2]);
2169 /* GPIO */
2170 ppc405_gpio_init(0xef600700);
2171 /* CPU control */
2172 ppc405cr_cpc_init(env, clk_setup, sysclk);
2173
2174 return env;
2175 }
2176
2177 /*****************************************************************************/
2178 /* PowerPC 405EP */
2179 /* CPU control */
2180 enum {
2181 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2182 PPC405EP_CPC0_BOOT = 0x0F1,
2183 PPC405EP_CPC0_EPCTL = 0x0F3,
2184 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2185 PPC405EP_CPC0_UCR = 0x0F5,
2186 PPC405EP_CPC0_SRR = 0x0F6,
2187 PPC405EP_CPC0_JTAGID = 0x0F7,
2188 PPC405EP_CPC0_PCI = 0x0F9,
2189 #if 0
2190 PPC405EP_CPC0_ER = xxx,
2191 PPC405EP_CPC0_FR = xxx,
2192 PPC405EP_CPC0_SR = xxx,
2193 #endif
2194 };
2195
2196 enum {
2197 PPC405EP_CPU_CLK = 0,
2198 PPC405EP_PLB_CLK = 1,
2199 PPC405EP_OPB_CLK = 2,
2200 PPC405EP_EBC_CLK = 3,
2201 PPC405EP_MAL_CLK = 4,
2202 PPC405EP_PCI_CLK = 5,
2203 PPC405EP_UART0_CLK = 6,
2204 PPC405EP_UART1_CLK = 7,
2205 PPC405EP_CLK_NB = 8,
2206 };
2207
2208 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2209 struct ppc405ep_cpc_t {
2210 uint32_t sysclk;
2211 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2212 uint32_t boot;
2213 uint32_t epctl;
2214 uint32_t pllmr[2];
2215 uint32_t ucr;
2216 uint32_t srr;
2217 uint32_t jtagid;
2218 uint32_t pci;
2219 /* Clock and power management */
2220 uint32_t er;
2221 uint32_t fr;
2222 uint32_t sr;
2223 };
2224
2225 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2226 {
2227 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2228 uint32_t UART0_clk, UART1_clk;
2229 uint64_t VCO_out, PLL_out;
2230 int M, D;
2231
2232 VCO_out = 0;
2233 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2234 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2235 #ifdef DEBUG_CLOCKS_LL
2236 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2237 #endif
2238 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2239 #ifdef DEBUG_CLOCKS_LL
2240 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2241 #endif
2242 VCO_out = cpc->sysclk * M * D;
2243 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2244 /* Error - unlock the PLL */
2245 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2246 #if 0
2247 cpc->pllmr[1] &= ~0x80000000;
2248 goto pll_bypass;
2249 #endif
2250 }
2251 PLL_out = VCO_out / D;
2252 /* Pretend the PLL is locked */
2253 cpc->boot |= 0x00000001;
2254 } else {
2255 #if 0
2256 pll_bypass:
2257 #endif
2258 PLL_out = cpc->sysclk;
2259 if (cpc->pllmr[1] & 0x40000000) {
2260 /* Pretend the PLL is not locked */
2261 cpc->boot &= ~0x00000001;
2262 }
2263 }
2264 /* Now, compute all other clocks */
2265 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2266 #ifdef DEBUG_CLOCKS_LL
2267 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2268 #endif
2269 CPU_clk = PLL_out / D;
2270 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2271 #ifdef DEBUG_CLOCKS_LL
2272 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2273 #endif
2274 PLB_clk = CPU_clk / D;
2275 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2276 #ifdef DEBUG_CLOCKS_LL
2277 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2278 #endif
2279 OPB_clk = PLB_clk / D;
2280 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2281 #ifdef DEBUG_CLOCKS_LL
2282 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2283 #endif
2284 EBC_clk = PLB_clk / D;
2285 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2286 #ifdef DEBUG_CLOCKS_LL
2287 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2288 #endif
2289 MAL_clk = PLB_clk / D;
2290 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2291 #ifdef DEBUG_CLOCKS_LL
2292 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2293 #endif
2294 PCI_clk = PLB_clk / D;
2295 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2296 #ifdef DEBUG_CLOCKS_LL
2297 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2298 #endif
2299 UART0_clk = PLL_out / D;
2300 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2301 #ifdef DEBUG_CLOCKS_LL
2302 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2303 #endif
2304 UART1_clk = PLL_out / D;
2305 #ifdef DEBUG_CLOCKS
2306 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2307 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2308 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2309 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2310 " UART1 %" PRIu32 "\n",
2311 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2312 UART0_clk, UART1_clk);
2313 #endif
2314 /* Setup CPU clocks */
2315 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2316 /* Setup PLB clock */
2317 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2318 /* Setup OPB clock */
2319 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2320 /* Setup external clock */
2321 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2322 /* Setup MAL clock */
2323 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2324 /* Setup PCI clock */
2325 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2326 /* Setup UART0 clock */
2327 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2328 /* Setup UART1 clock */
2329 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2330 }
2331
2332 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2333 {
2334 ppc405ep_cpc_t *cpc;
2335 uint32_t ret;
2336
2337 cpc = opaque;
2338 switch (dcrn) {
2339 case PPC405EP_CPC0_BOOT:
2340 ret = cpc->boot;
2341 break;
2342 case PPC405EP_CPC0_EPCTL:
2343 ret = cpc->epctl;
2344 break;
2345 case PPC405EP_CPC0_PLLMR0:
2346 ret = cpc->pllmr[0];
2347 break;
2348 case PPC405EP_CPC0_PLLMR1:
2349 ret = cpc->pllmr[1];
2350 break;
2351 case PPC405EP_CPC0_UCR:
2352 ret = cpc->ucr;
2353 break;
2354 case PPC405EP_CPC0_SRR:
2355 ret = cpc->srr;
2356 break;
2357 case PPC405EP_CPC0_JTAGID:
2358 ret = cpc->jtagid;
2359 break;
2360 case PPC405EP_CPC0_PCI:
2361 ret = cpc->pci;
2362 break;
2363 default:
2364 /* Avoid gcc warning */
2365 ret = 0;
2366 break;
2367 }
2368
2369 return ret;
2370 }
2371
2372 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2373 {
2374 ppc405ep_cpc_t *cpc;
2375
2376 cpc = opaque;
2377 switch (dcrn) {
2378 case PPC405EP_CPC0_BOOT:
2379 /* Read-only register */
2380 break;
2381 case PPC405EP_CPC0_EPCTL:
2382 /* Don't care for now */
2383 cpc->epctl = val & 0xC00000F3;
2384 break;
2385 case PPC405EP_CPC0_PLLMR0:
2386 cpc->pllmr[0] = val & 0x00633333;
2387 ppc405ep_compute_clocks(cpc);
2388 break;
2389 case PPC405EP_CPC0_PLLMR1:
2390 cpc->pllmr[1] = val & 0xC0F73FFF;
2391 ppc405ep_compute_clocks(cpc);
2392 break;
2393 case PPC405EP_CPC0_UCR:
2394 /* UART control - don't care for now */
2395 cpc->ucr = val & 0x003F7F7F;
2396 break;
2397 case PPC405EP_CPC0_SRR:
2398 cpc->srr = val;
2399 break;
2400 case PPC405EP_CPC0_JTAGID:
2401 /* Read-only */
2402 break;
2403 case PPC405EP_CPC0_PCI:
2404 cpc->pci = val;
2405 break;
2406 }
2407 }
2408
2409 static void ppc405ep_cpc_reset (void *opaque)
2410 {
2411 ppc405ep_cpc_t *cpc = opaque;
2412
2413 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2414 cpc->epctl = 0x00000000;
2415 cpc->pllmr[0] = 0x00011010;
2416 cpc->pllmr[1] = 0x40000000;
2417 cpc->ucr = 0x00000000;
2418 cpc->srr = 0x00040000;
2419 cpc->pci = 0x00000000;
2420 cpc->er = 0x00000000;
2421 cpc->fr = 0x00000000;
2422 cpc->sr = 0x00000000;
2423 ppc405ep_compute_clocks(cpc);
2424 }
2425
2426 /* XXX: sysclk should be between 25 and 100 MHz */
2427 static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
2428 uint32_t sysclk)
2429 {
2430 ppc405ep_cpc_t *cpc;
2431
2432 cpc = qemu_mallocz(sizeof(ppc405ep_cpc_t));
2433 memcpy(cpc->clk_setup, clk_setup,
2434 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2435 cpc->jtagid = 0x20267049;
2436 cpc->sysclk = sysclk;
2437 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2438 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2439 &dcr_read_epcpc, &dcr_write_epcpc);
2440 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2441 &dcr_read_epcpc, &dcr_write_epcpc);
2442 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2443 &dcr_read_epcpc, &dcr_write_epcpc);
2444 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2445 &dcr_read_epcpc, &dcr_write_epcpc);
2446 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2447 &dcr_read_epcpc, &dcr_write_epcpc);
2448 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2449 &dcr_read_epcpc, &dcr_write_epcpc);
2450 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2451 &dcr_read_epcpc, &dcr_write_epcpc);
2452 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2453 &dcr_read_epcpc, &dcr_write_epcpc);
2454 #if 0
2455 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2456 &dcr_read_epcpc, &dcr_write_epcpc);
2457 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2458 &dcr_read_epcpc, &dcr_write_epcpc);
2459 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2460 &dcr_read_epcpc, &dcr_write_epcpc);
2461 #endif
2462 }
2463
2464 CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
2465 target_phys_addr_t ram_sizes[2],
2466 uint32_t sysclk, qemu_irq **picp,
2467 int do_init)
2468 {
2469 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2470 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2471 CPUState *env;
2472 qemu_irq *pic, *irqs;
2473
2474 memset(clk_setup, 0, sizeof(clk_setup));
2475 /* init CPUs */
2476 env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2477 &tlb_clk_setup, sysclk);
2478 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2479 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2480 /* Internal devices init */
2481 /* Memory mapped devices registers */
2482 /* PLB arbitrer */
2483 ppc4xx_plb_init(env);
2484 /* PLB to OPB bridge */
2485 ppc4xx_pob_init(env);
2486 /* OBP arbitrer */
2487 ppc4xx_opba_init(0xef600600);
2488 /* Universal interrupt controller */
2489 irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2490 irqs[PPCUIC_OUTPUT_INT] =
2491 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2492 irqs[PPCUIC_OUTPUT_CINT] =
2493 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2494 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2495 *picp = pic;
2496 /* SDRAM controller */
2497 /* XXX 405EP has no ECC interrupt */
2498 ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
2499 /* External bus controller */
2500 ppc405_ebc_init(env);
2501 /* DMA controller */
2502 dma_irqs[0] = pic[5];
2503 dma_irqs[1] = pic[6];
2504 dma_irqs[2] = pic[7];
2505 dma_irqs[3] = pic[8];
2506 ppc405_dma_init(env, dma_irqs);
2507 /* IIC controller */
2508 ppc405_i2c_init(0xef600500, pic[2]);
2509 /* GPIO */
2510 ppc405_gpio_init(0xef600700);
2511 /* Serial ports */
2512 if (serial_hds[0] != NULL) {
2513 serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
2514 serial_hds[0], 1, 1);
2515 }
2516 if (serial_hds[1] != NULL) {
2517 serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
2518 serial_hds[1], 1, 1);
2519 }
2520 /* OCM */
2521 ppc405_ocm_init(env);
2522 /* GPT */
2523 gpt_irqs[0] = pic[19];
2524 gpt_irqs[1] = pic[20];
2525 gpt_irqs[2] = pic[21];
2526 gpt_irqs[3] = pic[22];
2527 gpt_irqs[4] = pic[23];
2528 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2529 /* PCI */
2530 /* Uses pic[3], pic[16], pic[18] */
2531 /* MAL */
2532 mal_irqs[0] = pic[11];
2533 mal_irqs[1] = pic[12];
2534 mal_irqs[2] = pic[13];
2535 mal_irqs[3] = pic[14];
2536 ppc405_mal_init(env, mal_irqs);
2537 /* Ethernet */
2538 /* Uses pic[9], pic[15], pic[17] */
2539 /* CPU control */
2540 ppc405ep_cpc_init(env, clk_setup, sysclk);
2541
2542 return env;
2543 }
QEmu