hw/pci-host/i440fx.c

   1 /*
   2  * QEMU i440FX PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/pci-host/i440fx.h"
  30 #include "hw/qdev-properties.h"
  31 #include "hw/sysbus.h"
  32 #include "qapi/error.h"
  33 #include "migration/vmstate.h"
  34 #include "qapi/visitor.h"
  35 #include "qemu/error-report.h"
  36
  37 /*
  38  * I440FX chipset data sheet.
  39  * https://wiki.qemu.org/File:29054901.pdf
  40  */
  41
  42 #define I440FX_PCI_HOST_BRIDGE(obj) \
  43     OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
  44
  45 typedef struct I440FXState {
  46     PCIHostState parent_obj;
  47     Range pci_hole;
  48     uint64_t pci_hole64_size;
  49     bool pci_hole64_fix;
  50     uint32_t short_root_bus;
  51 } I440FXState;
  52
  53 #define I440FX_PAM      0x59
  54 #define I440FX_PAM_SIZE 7
  55 #define I440FX_SMRAM    0x72
  56
  57 /* Keep it 2G to comply with older win32 guests */
  58 #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
  59
  60 /* Older coreboot versions (4.0 and older) read a config register that doesn't
  61  * exist in real hardware, to get the RAM size from QEMU.
  62  */
  63 #define I440FX_COREBOOT_RAM_SIZE 0x57
  64
  65 static void i440fx_update_memory_mappings(PCII440FXState *d)
  66 {
  67     int i;
  68     PCIDevice *pd = PCI_DEVICE(d);
  69
  70     memory_region_transaction_begin();
  71     for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
  72         pam_update(&d->pam_regions[i], i,
  73                    pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
  74     }
  75     memory_region_set_enabled(&d->smram_region,
  76                               !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
  77     memory_region_set_enabled(&d->smram,
  78                               pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
  79     memory_region_transaction_commit();
  80 }
  81
  82
  83 static void i440fx_write_config(PCIDevice *dev,
  84                                 uint32_t address, uint32_t val, int len)
  85 {
  86     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
  87
  88     /* XXX: implement SMRAM.D_LOCK */
  89     pci_default_write_config(dev, address, val, len);
  90     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
  91         range_covers_byte(address, len, I440FX_SMRAM)) {
  92         i440fx_update_memory_mappings(d);
  93     }
  94 }
  95
  96 static int i440fx_post_load(void *opaque, int version_id)
  97 {
  98     PCII440FXState *d = opaque;
  99
 100     i440fx_update_memory_mappings(d);
 101     return 0;
 102 }
 103
 104 static const VMStateDescription vmstate_i440fx = {
 105     .name = "I440FX",
 106     .version_id = 3,
 107     .minimum_version_id = 3,
 108     .post_load = i440fx_post_load,
 109     .fields = (VMStateField[]) {
 110         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
 111         /* Used to be smm_enabled, which was basically always zero because
 112          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
 113          */
 114         VMSTATE_UNUSED(1),
 115         VMSTATE_END_OF_LIST()
 116     }
 117 };
 118
 119 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
 120                                               const char *name, void *opaque,
 121                                               Error **errp)
 122 {
 123     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 124     uint64_t val64;
 125     uint32_t value;
 126
 127     val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
 128     value = val64;
 129     assert(value == val64);
 130     visit_type_uint32(v, name, &value, errp);
 131 }
 132
 133 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
 134                                             const char *name, void *opaque,
 135                                             Error **errp)
 136 {
 137     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 138     uint64_t val64;
 139     uint32_t value;
 140
 141     val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
 142     value = val64;
 143     assert(value == val64);
 144     visit_type_uint32(v, name, &value, errp);
 145 }
 146
 147 /*
 148  * The 64bit PCI hole start is set by the Guest firmware
 149  * as the address of the first 64bit PCI MEM resource.
 150  * If no PCI device has resources on the 64bit area,
 151  * the 64bit PCI hole will start after "over 4G RAM" and the
 152  * reserved space for memory hotplug if any.
 153  */
 154 static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
 155 {
 156     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 157     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 158     Range w64;
 159     uint64_t value;
 160
 161     pci_bus_get_w64_range(h->bus, &w64);
 162     value = range_is_empty(&w64) ? 0 : range_lob(&w64);
 163     if (!value && s->pci_hole64_fix) {
 164         value = pc_pci_hole64_start();
 165     }
 166     return value;
 167 }
 168
 169 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
 170                                                 const char *name,
 171                                                 void *opaque, Error **errp)
 172 {
 173     uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
 174
 175     visit_type_uint64(v, name, &hole64_start, errp);
 176 }
 177
 178 /*
 179  * The 64bit PCI hole end is set by the Guest firmware
 180  * as the address of the last 64bit PCI MEM resource.
 181  * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
 182  * that can be configured by the user.
 183  */
 184 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
 185                                               const char *name, void *opaque,
 186                                               Error **errp)
 187 {
 188     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 189     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 190     uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
 191     Range w64;
 192     uint64_t value, hole64_end;
 193
 194     pci_bus_get_w64_range(h->bus, &w64);
 195     value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
 196     hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
 197     if (s->pci_hole64_fix && value < hole64_end) {
 198         value = hole64_end;
 199     }
 200     visit_type_uint64(v, name, &value, errp);
 201 }
 202
 203 static void i440fx_pcihost_initfn(Object *obj)
 204 {
 205     PCIHostState *s = PCI_HOST_BRIDGE(obj);
 206
 207     memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
 208                           "pci-conf-idx", 4);
 209     memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
 210                           "pci-conf-data", 4);
 211
 212     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
 213                         i440fx_pcihost_get_pci_hole_start,
 214                         NULL, NULL, NULL, NULL);
 215
 216     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
 217                         i440fx_pcihost_get_pci_hole_end,
 218                         NULL, NULL, NULL, NULL);
 219
 220     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
 221                         i440fx_pcihost_get_pci_hole64_start,
 222                         NULL, NULL, NULL, NULL);
 223
 224     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
 225                         i440fx_pcihost_get_pci_hole64_end,
 226                         NULL, NULL, NULL, NULL);
 227 }
 228
 229 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
 230 {
 231     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 232     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 233
 234     sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
 235     sysbus_init_ioports(sbd, 0xcf8, 4);
 236
 237     sysbus_add_io(sbd, 0xcfc, &s->data_mem);
 238     sysbus_init_ioports(sbd, 0xcfc, 4);
 239
 240     /* register i440fx 0xcf8 port as coalesced pio */
 241     memory_region_set_flush_coalesced(&s->data_mem);
 242     memory_region_add_coalescing(&s->conf_mem, 0, 4);
 243 }
 244
 245 static void i440fx_realize(PCIDevice *dev, Error **errp)
 246 {
 247     dev->config[I440FX_SMRAM] = 0x02;
 248
 249     if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
 250         warn_report("i440fx doesn't support emulated iommu");
 251     }
 252 }
 253
 254 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 255                     PCII440FXState **pi440fx_state,
 256                     MemoryRegion *address_space_mem,
 257                     MemoryRegion *address_space_io,
 258                     ram_addr_t ram_size,
 259                     ram_addr_t below_4g_mem_size,
 260                     ram_addr_t above_4g_mem_size,
 261                     MemoryRegion *pci_address_space,
 262                     MemoryRegion *ram_memory)
 263 {
 264     DeviceState *dev;
 265     PCIBus *b;
 266     PCIDevice *d;
 267     PCIHostState *s;
 268     PCII440FXState *f;
 269     unsigned i;
 270     I440FXState *i440fx;
 271
 272     dev = qdev_create(NULL, host_type);
 273     s = PCI_HOST_BRIDGE(dev);
 274     b = pci_root_bus_new(dev, NULL, pci_address_space,
 275                          address_space_io, 0, TYPE_PCI_BUS);
 276     s->bus = b;
 277     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 278     qdev_init_nofail(dev);
 279
 280     d = pci_create_simple(b, 0, pci_type);
 281     *pi440fx_state = I440FX_PCI_DEVICE(d);
 282     f = *pi440fx_state;
 283     f->system_memory = address_space_mem;
 284     f->pci_address_space = pci_address_space;
 285     f->ram_memory = ram_memory;
 286
 287     i440fx = I440FX_PCI_HOST_BRIDGE(dev);
 288     range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
 289                      IO_APIC_DEFAULT_ADDRESS - 1);
 290
 291     /* setup pci memory mapping */
 292     pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
 293                            f->pci_address_space);
 294
 295     /* if *disabled* show SMRAM to all CPUs */
 296     memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 297                              f->pci_address_space, 0xa0000, 0x20000);
 298     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 299                                         &f->smram_region, 1);
 300     memory_region_set_enabled(&f->smram_region, true);
 301
 302     /* smram, as seen by SMM CPUs */
 303     memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
 304     memory_region_set_enabled(&f->smram, true);
 305     memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
 306                              f->ram_memory, 0xa0000, 0x20000);
 307     memory_region_set_enabled(&f->low_smram, true);
 308     memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
 309     object_property_add_const_link(qdev_get_machine(), "smram",
 310                                    OBJECT(&f->smram), &error_abort);
 311
 312     init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 313              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 314     for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
 315         init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 316                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 317                  PAM_EXPAN_SIZE);
 318     }
 319
 320     ram_size = ram_size / 8 / 1024 / 1024;
 321     if (ram_size > 255) {
 322         ram_size = 255;
 323     }
 324     d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
 325
 326     i440fx_update_memory_mappings(f);
 327
 328     return b;
 329 }
 330
 331 PCIBus *find_i440fx(void)
 332 {
 333     PCIHostState *s = OBJECT_CHECK(PCIHostState,
 334                                    object_resolve_path("/machine/i440fx", NULL),
 335                                    TYPE_PCI_HOST_BRIDGE);
 336     return s ? s->bus : NULL;
 337 }
 338
 339 static void i440fx_class_init(ObjectClass *klass, void *data)
 340 {
 341     DeviceClass *dc = DEVICE_CLASS(klass);
 342     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 343
 344     k->realize = i440fx_realize;
 345     k->config_write = i440fx_write_config;
 346     k->vendor_id = PCI_VENDOR_ID_INTEL;
 347     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 348     k->revision = 0x02;
 349     k->class_id = PCI_CLASS_BRIDGE_HOST;
 350     dc->desc = "Host bridge";
 351     dc->vmsd = &vmstate_i440fx;
 352     /*
 353      * PCI-facing part of the host bridge, not usable without the
 354      * host-facing part, which can't be device_add'ed, yet.
 355      */
 356     dc->user_creatable = false;
 357     dc->hotpluggable   = false;
 358 }
 359
 360 static const TypeInfo i440fx_info = {
 361     .name          = TYPE_I440FX_PCI_DEVICE,
 362     .parent        = TYPE_PCI_DEVICE,
 363     .instance_size = sizeof(PCII440FXState),
 364     .class_init    = i440fx_class_init,
 365     .interfaces = (InterfaceInfo[]) {
 366         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 367         { },
 368     },
 369 };
 370
 371 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 372                                                 PCIBus *rootbus)
 373 {
 374     I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
 375
 376     /* For backwards compat with old device paths */
 377     if (s->short_root_bus) {
 378         return "0000";
 379     }
 380     return "0000:00";
 381 }
 382
 383 static Property i440fx_props[] = {
 384     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
 385                      pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
 386     DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
 387     DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
 388     DEFINE_PROP_END_OF_LIST(),
 389 };
 390
 391 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 392 {
 393     DeviceClass *dc = DEVICE_CLASS(klass);
 394     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 395
 396     hc->root_bus_path = i440fx_pcihost_root_bus_path;
 397     dc->realize = i440fx_pcihost_realize;
 398     dc->fw_name = "pci";
 399     device_class_set_props(dc, i440fx_props);
 400     /* Reason: needs to be wired up by pc_init1 */
 401     dc->user_creatable = false;
 402 }
 403
 404 static const TypeInfo i440fx_pcihost_info = {
 405     .name          = TYPE_I440FX_PCI_HOST_BRIDGE,
 406     .parent        = TYPE_PCI_HOST_BRIDGE,
 407     .instance_size = sizeof(I440FXState),
 408     .instance_init = i440fx_pcihost_initfn,
 409     .class_init    = i440fx_pcihost_class_init,
 410 };
 411
 412 static void i440fx_register_types(void)
 413 {
 414     type_register_static(&i440fx_info);
 415     type_register_static(&i440fx_pcihost_info);
 416 }
 417
 418 type_init(i440fx_register_types)