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bios-tables-test: tell people how to update
[qemu.git] / hw / arm / aspeed_soc.c
blob696c7fda14b74fb6951a9423b1cf65cc6f7000c3
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "cpu.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
20 #include "qemu/log.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
24 #include "net/net.h"
25 #include "sysemu/sysemu.h"
26
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
28
29 static const hwaddr aspeed_soc_ast2400_memmap[] = {
30 [ASPEED_IOMEM] = 0x1E600000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_EHCI1] = 0x1E6A1000,
34 [ASPEED_VIC] = 0x1E6C0000,
35 [ASPEED_SDMC] = 0x1E6E0000,
36 [ASPEED_SCU] = 0x1E6E2000,
37 [ASPEED_XDMA] = 0x1E6E7000,
38 [ASPEED_VIDEO] = 0x1E700000,
39 [ASPEED_ADC] = 0x1E6E9000,
40 [ASPEED_SRAM] = 0x1E720000,
41 [ASPEED_SDHCI] = 0x1E740000,
42 [ASPEED_GPIO] = 0x1E780000,
43 [ASPEED_RTC] = 0x1E781000,
44 [ASPEED_TIMER1] = 0x1E782000,
45 [ASPEED_WDT] = 0x1E785000,
46 [ASPEED_PWM] = 0x1E786000,
47 [ASPEED_LPC] = 0x1E789000,
48 [ASPEED_IBT] = 0x1E789140,
49 [ASPEED_I2C] = 0x1E78A000,
50 [ASPEED_ETH1] = 0x1E660000,
51 [ASPEED_ETH2] = 0x1E680000,
52 [ASPEED_UART1] = 0x1E783000,
53 [ASPEED_UART5] = 0x1E784000,
54 [ASPEED_VUART] = 0x1E787000,
55 [ASPEED_SDRAM] = 0x40000000,
56 };
57
58 static const hwaddr aspeed_soc_ast2500_memmap[] = {
59 [ASPEED_IOMEM] = 0x1E600000,
60 [ASPEED_FMC] = 0x1E620000,
61 [ASPEED_SPI1] = 0x1E630000,
62 [ASPEED_SPI2] = 0x1E631000,
63 [ASPEED_EHCI1] = 0x1E6A1000,
64 [ASPEED_EHCI2] = 0x1E6A3000,
65 [ASPEED_VIC] = 0x1E6C0000,
66 [ASPEED_SDMC] = 0x1E6E0000,
67 [ASPEED_SCU] = 0x1E6E2000,
68 [ASPEED_XDMA] = 0x1E6E7000,
69 [ASPEED_ADC] = 0x1E6E9000,
70 [ASPEED_VIDEO] = 0x1E700000,
71 [ASPEED_SRAM] = 0x1E720000,
72 [ASPEED_SDHCI] = 0x1E740000,
73 [ASPEED_GPIO] = 0x1E780000,
74 [ASPEED_RTC] = 0x1E781000,
75 [ASPEED_TIMER1] = 0x1E782000,
76 [ASPEED_WDT] = 0x1E785000,
77 [ASPEED_PWM] = 0x1E786000,
78 [ASPEED_LPC] = 0x1E789000,
79 [ASPEED_IBT] = 0x1E789140,
80 [ASPEED_I2C] = 0x1E78A000,
81 [ASPEED_ETH1] = 0x1E660000,
82 [ASPEED_ETH2] = 0x1E680000,
83 [ASPEED_UART1] = 0x1E783000,
84 [ASPEED_UART5] = 0x1E784000,
85 [ASPEED_VUART] = 0x1E787000,
86 [ASPEED_SDRAM] = 0x80000000,
87 };
88
89 static const int aspeed_soc_ast2400_irqmap[] = {
90 [ASPEED_UART1] = 9,
91 [ASPEED_UART2] = 32,
92 [ASPEED_UART3] = 33,
93 [ASPEED_UART4] = 34,
94 [ASPEED_UART5] = 10,
95 [ASPEED_VUART] = 8,
96 [ASPEED_FMC] = 19,
97 [ASPEED_EHCI1] = 5,
98 [ASPEED_EHCI2] = 13,
99 [ASPEED_SDMC] = 0,
100 [ASPEED_SCU] = 21,
101 [ASPEED_ADC] = 31,
102 [ASPEED_GPIO] = 20,
103 [ASPEED_RTC] = 22,
104 [ASPEED_TIMER1] = 16,
105 [ASPEED_TIMER2] = 17,
106 [ASPEED_TIMER3] = 18,
107 [ASPEED_TIMER4] = 35,
108 [ASPEED_TIMER5] = 36,
109 [ASPEED_TIMER6] = 37,
110 [ASPEED_TIMER7] = 38,
111 [ASPEED_TIMER8] = 39,
112 [ASPEED_WDT] = 27,
113 [ASPEED_PWM] = 28,
114 [ASPEED_LPC] = 8,
115 [ASPEED_IBT] = 8, /* LPC */
116 [ASPEED_I2C] = 12,
117 [ASPEED_ETH1] = 2,
118 [ASPEED_ETH2] = 3,
119 [ASPEED_XDMA] = 6,
120 [ASPEED_SDHCI] = 26,
121 };
122
123 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
124
125 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
126 {
127 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
128
129 return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
130 }
131
132 static void aspeed_soc_init(Object *obj)
133 {
134 AspeedSoCState *s = ASPEED_SOC(obj);
135 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
136 int i;
137 char socname[8];
138 char typename[64];
139
140 if (sscanf(sc->name, "%7s", socname) != 1) {
141 g_assert_not_reached();
142 }
143
144 for (i = 0; i < sc->num_cpus; i++) {
145 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
146 sizeof(s->cpu[i]), sc->cpu_type,
147 &error_abort, NULL);
148 }
149
150 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
151 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
152 typename);
153 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
154 sc->silicon_rev);
155 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
156 "hw-strap1", &error_abort);
157 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
158 "hw-strap2", &error_abort);
159 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
160 "hw-prot-key", &error_abort);
161
162 sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
163 TYPE_ASPEED_VIC);
164
165 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
166 TYPE_ASPEED_RTC);
167
168 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
169 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
170 sizeof(s->timerctrl), typename);
171
172 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
173 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
174 typename);
175
176 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
177 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
178 typename);
179 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
180 &error_abort);
181
182 for (i = 0; i < sc->spis_num; i++) {
183 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
184 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
185 sizeof(s->spi[i]), typename);
186 }
187
188 for (i = 0; i < sc->ehcis_num; i++) {
189 sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]),
190 sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI);
191 }
192
193 snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
194 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
195 typename);
196 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
197 "ram-size", &error_abort);
198 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
199 "max-ram-size", &error_abort);
200
201 for (i = 0; i < sc->wdts_num; i++) {
202 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
203 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
204 sizeof(s->wdt[i]), typename);
205 }
206
207 for (i = 0; i < sc->macs_num; i++) {
208 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
209 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
210 }
211
212 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
213 TYPE_ASPEED_XDMA);
214
215 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
216 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
217 typename);
218
219 sysbus_init_child_obj(obj, "sdc", OBJECT(&s->sdhci), sizeof(s->sdhci),
220 TYPE_ASPEED_SDHCI);
221
222 object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
223
224 /* Init sd card slot class here so that they're under the correct parent */
225 for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
226 sysbus_init_child_obj(obj, "sdhci[*]", OBJECT(&s->sdhci.slots[i]),
227 sizeof(s->sdhci.slots[i]), TYPE_SYSBUS_SDHCI);
228 }
229 }
230
231 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
232 {
233 int i;
234 AspeedSoCState *s = ASPEED_SOC(dev);
235 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
236 Error *err = NULL, *local_err = NULL;
237
238 /* IO space */
239 create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
240 ASPEED_SOC_IOMEM_SIZE);
241
242 /* Video engine stub */
243 create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
244 0x1000);
245
246 if (s->num_cpus > sc->num_cpus) {
247 warn_report("%s: invalid number of CPUs %d, using default %d",
248 sc->name, s->num_cpus, sc->num_cpus);
249 s->num_cpus = sc->num_cpus;
250 }
251
252 /* CPU */
253 for (i = 0; i < s->num_cpus; i++) {
254 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
255 if (err) {
256 error_propagate(errp, err);
257 return;
258 }
259 }
260
261 /* SRAM */
262 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
263 sc->sram_size, &err);
264 if (err) {
265 error_propagate(errp, err);
266 return;
267 }
268 memory_region_add_subregion(get_system_memory(),
269 sc->memmap[ASPEED_SRAM], &s->sram);
270
271 /* SCU */
272 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
273 if (err) {
274 error_propagate(errp, err);
275 return;
276 }
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
278
279 /* VIC */
280 object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
281 if (err) {
282 error_propagate(errp, err);
283 return;
284 }
285 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
286 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
287 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
288 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
289 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
290
291 /* RTC */
292 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
293 if (err) {
294 error_propagate(errp, err);
295 return;
296 }
297 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
298 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
299 aspeed_soc_get_irq(s, ASPEED_RTC));
300
301 /* Timer */
302 object_property_set_link(OBJECT(&s->timerctrl),
303 OBJECT(&s->scu), "scu", &error_abort);
304 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
305 if (err) {
306 error_propagate(errp, err);
307 return;
308 }
309 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
310 sc->memmap[ASPEED_TIMER1]);
311 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
312 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
313 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
314 }
315
316 /* UART - attach an 8250 to the IO space as our UART5 */
317 if (serial_hd(0)) {
318 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
319 serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
320 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
321 }
322
323 /* I2C */
324 object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
325 if (err) {
326 error_propagate(errp, err);
327 return;
328 }
329 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
330 if (err) {
331 error_propagate(errp, err);
332 return;
333 }
334 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
335 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
336 aspeed_soc_get_irq(s, ASPEED_I2C));
337
338 /* FMC, The number of CS is set at the board level */
339 object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
340 if (err) {
341 error_propagate(errp, err);
342 return;
343 }
344 object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
345 "sdram-base", &err);
346 if (err) {
347 error_propagate(errp, err);
348 return;
349 }
350 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
351 if (err) {
352 error_propagate(errp, err);
353 return;
354 }
355 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
356 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
357 s->fmc.ctrl->flash_window_base);
358 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
359 aspeed_soc_get_irq(s, ASPEED_FMC));
360
361 /* SPI */
362 for (i = 0; i < sc->spis_num; i++) {
363 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
364 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
365 &local_err);
366 error_propagate(&err, local_err);
367 if (err) {
368 error_propagate(errp, err);
369 return;
370 }
371 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
372 sc->memmap[ASPEED_SPI1 + i]);
373 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
374 s->spi[i].ctrl->flash_window_base);
375 }
376
377 /* EHCI */
378 for (i = 0; i < sc->ehcis_num; i++) {
379 object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", &err);
380 if (err) {
381 error_propagate(errp, err);
382 return;
383 }
384 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
385 sc->memmap[ASPEED_EHCI1 + i]);
386 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
387 aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
388 }
389
390 /* SDMC - SDRAM Memory Controller */
391 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
392 if (err) {
393 error_propagate(errp, err);
394 return;
395 }
396 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
397
398 /* Watch dog */
399 for (i = 0; i < sc->wdts_num; i++) {
400 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
401
402 object_property_set_link(OBJECT(&s->wdt[i]),
403 OBJECT(&s->scu), "scu", &error_abort);
404 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
405 if (err) {
406 error_propagate(errp, err);
407 return;
408 }
409 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
410 sc->memmap[ASPEED_WDT] + i * awc->offset);
411 }
412
413 /* Net */
414 for (i = 0; i < nb_nics && i < sc->macs_num; i++) {
415 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
416 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
417 &err);
418 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
419 &local_err);
420 error_propagate(&err, local_err);
421 if (err) {
422 error_propagate(errp, err);
423 return;
424 }
425 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
426 sc->memmap[ASPEED_ETH1 + i]);
427 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
428 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
429 }
430
431 /* XDMA */
432 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
433 if (err) {
434 error_propagate(errp, err);
435 return;
436 }
437 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
438 sc->memmap[ASPEED_XDMA]);
439 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
440 aspeed_soc_get_irq(s, ASPEED_XDMA));
441
442 /* GPIO */
443 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
444 if (err) {
445 error_propagate(errp, err);
446 return;
447 }
448 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
449 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
450 aspeed_soc_get_irq(s, ASPEED_GPIO));
451
452 /* SDHCI */
453 object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
454 if (err) {
455 error_propagate(errp, err);
456 return;
457 }
458 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
459 sc->memmap[ASPEED_SDHCI]);
460 sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
461 aspeed_soc_get_irq(s, ASPEED_SDHCI));
462 }
463 static Property aspeed_soc_properties[] = {
464 DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
465 DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
466 MemoryRegion *),
467 DEFINE_PROP_END_OF_LIST(),
468 };
469
470 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
471 {
472 DeviceClass *dc = DEVICE_CLASS(oc);
473
474 dc->realize = aspeed_soc_realize;
475 /* Reason: Uses serial_hds and nd_table in realize() directly */
476 dc->user_creatable = false;
477 device_class_set_props(dc, aspeed_soc_properties);
478 }
479
480 static const TypeInfo aspeed_soc_type_info = {
481 .name = TYPE_ASPEED_SOC,
482 .parent = TYPE_DEVICE,
483 .instance_size = sizeof(AspeedSoCState),
484 .class_size = sizeof(AspeedSoCClass),
485 .class_init = aspeed_soc_class_init,
486 .abstract = true,
487 };
488
489 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
490 {
491 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
492
493 sc->name = "ast2400-a1";
494 sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
495 sc->silicon_rev = AST2400_A1_SILICON_REV;
496 sc->sram_size = 0x8000;
497 sc->spis_num = 1;
498 sc->ehcis_num = 1;
499 sc->wdts_num = 2;
500 sc->macs_num = 2;
501 sc->irqmap = aspeed_soc_ast2400_irqmap;
502 sc->memmap = aspeed_soc_ast2400_memmap;
503 sc->num_cpus = 1;
504 }
505
506 static const TypeInfo aspeed_soc_ast2400_type_info = {
507 .name = "ast2400-a1",
508 .parent = TYPE_ASPEED_SOC,
509 .instance_init = aspeed_soc_init,
510 .instance_size = sizeof(AspeedSoCState),
511 .class_init = aspeed_soc_ast2400_class_init,
512 };
513
514 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
515 {
516 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
517
518 sc->name = "ast2500-a1";
519 sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
520 sc->silicon_rev = AST2500_A1_SILICON_REV;
521 sc->sram_size = 0x9000;
522 sc->spis_num = 2;
523 sc->ehcis_num = 2;
524 sc->wdts_num = 3;
525 sc->macs_num = 2;
526 sc->irqmap = aspeed_soc_ast2500_irqmap;
527 sc->memmap = aspeed_soc_ast2500_memmap;
528 sc->num_cpus = 1;
529 }
530
531 static const TypeInfo aspeed_soc_ast2500_type_info = {
532 .name = "ast2500-a1",
533 .parent = TYPE_ASPEED_SOC,
534 .instance_init = aspeed_soc_init,
535 .instance_size = sizeof(AspeedSoCState),
536 .class_init = aspeed_soc_ast2500_class_init,
537 };
538 static void aspeed_soc_register_types(void)
539 {
540 type_register_static(&aspeed_soc_type_info);
541 type_register_static(&aspeed_soc_ast2400_type_info);
542 type_register_static(&aspeed_soc_ast2500_type_info);
543 };
544
545 type_init(aspeed_soc_register_types)
QEmu