target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27
  28 enum {
  29     TLBRET_DIRTY = -4,
  30     TLBRET_INVALID = -3,
  31     TLBRET_NOMATCH = -2,
  32     TLBRET_BADADDR = -1,
  33     TLBRET_MATCH = 0
  34 };
  35
  36 #if !defined(CONFIG_USER_ONLY)
  37
  38 /* no MMU emulation */
  39 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  40                         target_ulong address, int rw, int access_type)
  41 {
  42     *physical = address;
  43     *prot = PAGE_READ | PAGE_WRITE;
  44     return TLBRET_MATCH;
  45 }
  46
  47 /* fixed mapping MMU emulation */
  48 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  49                            target_ulong address, int rw, int access_type)
  50 {
  51     if (address <= (int32_t)0x7FFFFFFFUL) {
  52         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  53             *physical = address + 0x40000000UL;
  54         else
  55             *physical = address;
  56     } else if (address <= (int32_t)0xBFFFFFFFUL)
  57         *physical = address & 0x1FFFFFFF;
  58     else
  59         *physical = address;
  60
  61     *prot = PAGE_READ | PAGE_WRITE;
  62     return TLBRET_MATCH;
  63 }
  64
  65 /* MIPS32/MIPS64 R4000-style MMU emulation */
  66 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
  67                      target_ulong address, int rw, int access_type)
  68 {
  69     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  70     int i;
  71
  72     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  73         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  74         /* 1k pages are not supported. */
  75         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  76         target_ulong tag = address & ~mask;
  77         target_ulong VPN = tlb->VPN & ~mask;
  78 #if defined(TARGET_MIPS64)
  79         tag &= env->SEGMask;
  80 #endif
  81
  82         /* Check ASID, virtual page number & size */
  83         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  84             /* TLB match */
  85             int n = !!(address & mask & ~(mask >> 1));
  86             /* Check access rights */
  87             if (!(n ? tlb->V1 : tlb->V0))
  88                 return TLBRET_INVALID;
  89             if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
  90                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  91                 *prot = PAGE_READ;
  92                 if (n ? tlb->D1 : tlb->D0)
  93                     *prot |= PAGE_WRITE;
  94                 return TLBRET_MATCH;
  95             }
  96             return TLBRET_DIRTY;
  97         }
  98     }
  99     return TLBRET_NOMATCH;
 100 }
 101
 102 static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
 103                                 int *prot, target_ulong address,
 104                                 int rw, int access_type)
 105 {
 106     /* User mode can only access useg/xuseg */
 107     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 108     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 109     int kernel_mode = !user_mode && !supervisor_mode;
 110 #if defined(TARGET_MIPS64)
 111     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 112     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 113     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 114 #endif
 115     int ret = TLBRET_MATCH;
 116
 117 #if 0
 118     qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
 119 #endif
 120
 121     if (address <= (int32_t)0x7FFFFFFFUL) {
 122         /* useg */
 123         if (env->CP0_Status & (1 << CP0St_ERL)) {
 124             *physical = address & 0xFFFFFFFF;
 125             *prot = PAGE_READ | PAGE_WRITE;
 126         } else {
 127             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 128         }
 129 #if defined(TARGET_MIPS64)
 130     } else if (address < 0x4000000000000000ULL) {
 131         /* xuseg */
 132         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 133             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 134         } else {
 135             ret = TLBRET_BADADDR;
 136         }
 137     } else if (address < 0x8000000000000000ULL) {
 138         /* xsseg */
 139         if ((supervisor_mode || kernel_mode) &&
 140             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 141             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 142         } else {
 143             ret = TLBRET_BADADDR;
 144         }
 145     } else if (address < 0xC000000000000000ULL) {
 146         /* xkphys */
 147         if (kernel_mode && KX &&
 148             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 149             *physical = address & env->PAMask;
 150             *prot = PAGE_READ | PAGE_WRITE;
 151         } else {
 152             ret = TLBRET_BADADDR;
 153         }
 154     } else if (address < 0xFFFFFFFF80000000ULL) {
 155         /* xkseg */
 156         if (kernel_mode && KX &&
 157             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 158             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 159         } else {
 160             ret = TLBRET_BADADDR;
 161         }
 162 #endif
 163     } else if (address < (int32_t)0xA0000000UL) {
 164         /* kseg0 */
 165         if (kernel_mode) {
 166             *physical = address - (int32_t)0x80000000UL;
 167             *prot = PAGE_READ | PAGE_WRITE;
 168         } else {
 169             ret = TLBRET_BADADDR;
 170         }
 171     } else if (address < (int32_t)0xC0000000UL) {
 172         /* kseg1 */
 173         if (kernel_mode) {
 174             *physical = address - (int32_t)0xA0000000UL;
 175             *prot = PAGE_READ | PAGE_WRITE;
 176         } else {
 177             ret = TLBRET_BADADDR;
 178         }
 179     } else if (address < (int32_t)0xE0000000UL) {
 180         /* sseg (kseg2) */
 181         if (supervisor_mode || kernel_mode) {
 182             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 183         } else {
 184             ret = TLBRET_BADADDR;
 185         }
 186     } else {
 187         /* kseg3 */
 188         /* XXX: debug segment is not emulated */
 189         if (kernel_mode) {
 190             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 191         } else {
 192             ret = TLBRET_BADADDR;
 193         }
 194     }
 195 #if 0
 196     qemu_log(TARGET_FMT_lx " %d %d => %" HWADDR_PRIx " %d (%d)\n",
 197             address, rw, access_type, *physical, *prot, ret);
 198 #endif
 199
 200     return ret;
 201 }
 202 #endif
 203
 204 static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
 205                                 int rw, int tlb_error)
 206 {
 207     CPUState *cs = CPU(mips_env_get_cpu(env));
 208     int exception = 0, error_code = 0;
 209
 210     switch (tlb_error) {
 211     default:
 212     case TLBRET_BADADDR:
 213         /* Reference to kernel address from user mode or supervisor mode */
 214         /* Reference to supervisor address from user mode */
 215         if (rw)
 216             exception = EXCP_AdES;
 217         else
 218             exception = EXCP_AdEL;
 219         break;
 220     case TLBRET_NOMATCH:
 221         /* No TLB match for a mapped address */
 222         if (rw)
 223             exception = EXCP_TLBS;
 224         else
 225             exception = EXCP_TLBL;
 226         error_code = 1;
 227         break;
 228     case TLBRET_INVALID:
 229         /* TLB match with no valid bit */
 230         if (rw)
 231             exception = EXCP_TLBS;
 232         else
 233             exception = EXCP_TLBL;
 234         break;
 235     case TLBRET_DIRTY:
 236         /* TLB match but 'D' bit is cleared */
 237         exception = EXCP_LTLBL;
 238         break;
 239
 240     }
 241     /* Raise exception */
 242     env->CP0_BadVAddr = address;
 243     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 244                        ((address >> 9) & 0x007ffff0);
 245     env->CP0_EntryHi =
 246         (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 247 #if defined(TARGET_MIPS64)
 248     env->CP0_EntryHi &= env->SEGMask;
 249     env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 250                         ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 251                         ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 252 #endif
 253     cs->exception_index = exception;
 254     env->error_code = error_code;
 255 }
 256
 257 #if !defined(CONFIG_USER_ONLY)
 258 hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 259 {
 260     MIPSCPU *cpu = MIPS_CPU(cs);
 261     hwaddr phys_addr;
 262     int prot;
 263
 264     if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0,
 265                              ACCESS_INT) != 0) {
 266         return -1;
 267     }
 268     return phys_addr;
 269 }
 270 #endif
 271
 272 int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
 273                               int mmu_idx)
 274 {
 275     MIPSCPU *cpu = MIPS_CPU(cs);
 276     CPUMIPSState *env = &cpu->env;
 277 #if !defined(CONFIG_USER_ONLY)
 278     hwaddr physical;
 279     int prot;
 280     int access_type;
 281 #endif
 282     int ret = 0;
 283
 284 #if 0
 285     log_cpu_state(cs, 0);
 286 #endif
 287     qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
 288               __func__, env->active_tc.PC, address, rw, mmu_idx);
 289
 290     rw &= 1;
 291
 292     /* data access */
 293 #if !defined(CONFIG_USER_ONLY)
 294     /* XXX: put correct access by using cpu_restore_state()
 295        correctly */
 296     access_type = ACCESS_INT;
 297     ret = get_physical_address(env, &physical, &prot,
 298                                address, rw, access_type);
 299     qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
 300              " prot %d\n",
 301              __func__, address, ret, physical, prot);
 302     if (ret == TLBRET_MATCH) {
 303         tlb_set_page(cs, address & TARGET_PAGE_MASK,
 304                      physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 305                      mmu_idx, TARGET_PAGE_SIZE);
 306         ret = 0;
 307     } else if (ret < 0)
 308 #endif
 309     {
 310         raise_mmu_exception(env, address, rw, ret);
 311         ret = 1;
 312     }
 313
 314     return ret;
 315 }
 316
 317 #if !defined(CONFIG_USER_ONLY)
 318 hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
 319 {
 320     hwaddr physical;
 321     int prot;
 322     int access_type;
 323     int ret = 0;
 324
 325     rw &= 1;
 326
 327     /* data access */
 328     access_type = ACCESS_INT;
 329     ret = get_physical_address(env, &physical, &prot,
 330                                address, rw, access_type);
 331     if (ret != TLBRET_MATCH) {
 332         raise_mmu_exception(env, address, rw, ret);
 333         return -1LL;
 334     } else {
 335         return physical;
 336     }
 337 }
 338 #endif
 339
 340 static const char * const excp_names[EXCP_LAST + 1] = {
 341     [EXCP_RESET] = "reset",
 342     [EXCP_SRESET] = "soft reset",
 343     [EXCP_DSS] = "debug single step",
 344     [EXCP_DINT] = "debug interrupt",
 345     [EXCP_NMI] = "non-maskable interrupt",
 346     [EXCP_MCHECK] = "machine check",
 347     [EXCP_EXT_INTERRUPT] = "interrupt",
 348     [EXCP_DFWATCH] = "deferred watchpoint",
 349     [EXCP_DIB] = "debug instruction breakpoint",
 350     [EXCP_IWATCH] = "instruction fetch watchpoint",
 351     [EXCP_AdEL] = "address error load",
 352     [EXCP_AdES] = "address error store",
 353     [EXCP_TLBF] = "TLB refill",
 354     [EXCP_IBE] = "instruction bus error",
 355     [EXCP_DBp] = "debug breakpoint",
 356     [EXCP_SYSCALL] = "syscall",
 357     [EXCP_BREAK] = "break",
 358     [EXCP_CpU] = "coprocessor unusable",
 359     [EXCP_RI] = "reserved instruction",
 360     [EXCP_OVERFLOW] = "arithmetic overflow",
 361     [EXCP_TRAP] = "trap",
 362     [EXCP_FPE] = "floating point",
 363     [EXCP_DDBS] = "debug data break store",
 364     [EXCP_DWATCH] = "data watchpoint",
 365     [EXCP_LTLBL] = "TLB modify",
 366     [EXCP_TLBL] = "TLB load",
 367     [EXCP_TLBS] = "TLB store",
 368     [EXCP_DBE] = "data bus error",
 369     [EXCP_DDBL] = "debug data break load",
 370     [EXCP_THREAD] = "thread",
 371     [EXCP_MDMX] = "MDMX",
 372     [EXCP_C2E] = "precise coprocessor 2",
 373     [EXCP_CACHE] = "cache error",
 374 };
 375
 376 target_ulong exception_resume_pc (CPUMIPSState *env)
 377 {
 378     target_ulong bad_pc;
 379     target_ulong isa_mode;
 380
 381     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 382     bad_pc = env->active_tc.PC | isa_mode;
 383     if (env->hflags & MIPS_HFLAG_BMASK) {
 384         /* If the exception was raised from a delay slot, come back to
 385            the jump.  */
 386         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 387     }
 388
 389     return bad_pc;
 390 }
 391
 392 #if !defined(CONFIG_USER_ONLY)
 393 static void set_hflags_for_handler (CPUMIPSState *env)
 394 {
 395     /* Exception handlers are entered in 32-bit mode.  */
 396     env->hflags &= ~(MIPS_HFLAG_M16);
 397     /* ...except that microMIPS lets you choose.  */
 398     if (env->insn_flags & ASE_MICROMIPS) {
 399         env->hflags |= (!!(env->CP0_Config3
 400                            & (1 << CP0C3_ISA_ON_EXC))
 401                         << MIPS_HFLAG_M16_SHIFT);
 402     }
 403 }
 404 #endif
 405
 406 void mips_cpu_do_interrupt(CPUState *cs)
 407 {
 408 #if !defined(CONFIG_USER_ONLY)
 409     MIPSCPU *cpu = MIPS_CPU(cs);
 410     CPUMIPSState *env = &cpu->env;
 411     target_ulong offset;
 412     int cause = -1;
 413     const char *name;
 414
 415     if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
 416         if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
 417             name = "unknown";
 418         } else {
 419             name = excp_names[cs->exception_index];
 420         }
 421
 422         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
 423                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 424     }
 425     if (cs->exception_index == EXCP_EXT_INTERRUPT &&
 426         (env->hflags & MIPS_HFLAG_DM)) {
 427         cs->exception_index = EXCP_DINT;
 428     }
 429     offset = 0x180;
 430     switch (cs->exception_index) {
 431     case EXCP_DSS:
 432         env->CP0_Debug |= 1 << CP0DB_DSS;
 433         /* Debug single step cannot be raised inside a delay slot and
 434            resume will always occur on the next instruction
 435            (but we assume the pc has always been updated during
 436            code translation). */
 437         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 438         goto enter_debug_mode;
 439     case EXCP_DINT:
 440         env->CP0_Debug |= 1 << CP0DB_DINT;
 441         goto set_DEPC;
 442     case EXCP_DIB:
 443         env->CP0_Debug |= 1 << CP0DB_DIB;
 444         goto set_DEPC;
 445     case EXCP_DBp:
 446         env->CP0_Debug |= 1 << CP0DB_DBp;
 447         goto set_DEPC;
 448     case EXCP_DDBS:
 449         env->CP0_Debug |= 1 << CP0DB_DDBS;
 450         goto set_DEPC;
 451     case EXCP_DDBL:
 452         env->CP0_Debug |= 1 << CP0DB_DDBL;
 453     set_DEPC:
 454         env->CP0_DEPC = exception_resume_pc(env);
 455         env->hflags &= ~MIPS_HFLAG_BMASK;
 456  enter_debug_mode:
 457         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 458         env->hflags &= ~(MIPS_HFLAG_KSU);
 459         /* EJTAG probe trap enable is not implemented... */
 460         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 461             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 462         env->active_tc.PC = (int32_t)0xBFC00480;
 463         set_hflags_for_handler(env);
 464         break;
 465     case EXCP_RESET:
 466         cpu_reset(CPU(cpu));
 467         break;
 468     case EXCP_SRESET:
 469         env->CP0_Status |= (1 << CP0St_SR);
 470         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 471         goto set_error_EPC;
 472     case EXCP_NMI:
 473         env->CP0_Status |= (1 << CP0St_NMI);
 474  set_error_EPC:
 475         env->CP0_ErrorEPC = exception_resume_pc(env);
 476         env->hflags &= ~MIPS_HFLAG_BMASK;
 477         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 478         env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 479         env->hflags &= ~(MIPS_HFLAG_KSU);
 480         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 481             env->CP0_Cause &= ~(1U << CP0Ca_BD);
 482         env->active_tc.PC = (int32_t)0xBFC00000;
 483         set_hflags_for_handler(env);
 484         break;
 485     case EXCP_EXT_INTERRUPT:
 486         cause = 0;
 487         if (env->CP0_Cause & (1 << CP0Ca_IV))
 488             offset = 0x200;
 489
 490         if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
 491             /* Vectored Interrupts.  */
 492             unsigned int spacing;
 493             unsigned int vector;
 494             unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
 495
 496             pending &= env->CP0_Status >> 8;
 497             /* Compute the Vector Spacing.  */
 498             spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
 499             spacing <<= 5;
 500
 501             if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
 502                 /* For VInt mode, the MIPS computes the vector internally.  */
 503                 for (vector = 7; vector > 0; vector--) {
 504                     if (pending & (1 << vector)) {
 505                         /* Found it.  */
 506                         break;
 507                     }
 508                 }
 509             } else {
 510                 /* For VEIC mode, the external interrupt controller feeds the
 511                    vector through the CP0Cause IP lines.  */
 512                 vector = pending;
 513             }
 514             offset = 0x200 + vector * spacing;
 515         }
 516         goto set_EPC;
 517     case EXCP_LTLBL:
 518         cause = 1;
 519         goto set_EPC;
 520     case EXCP_TLBL:
 521         cause = 2;
 522         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 523 #if defined(TARGET_MIPS64)
 524             int R = env->CP0_BadVAddr >> 62;
 525             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 526             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 527             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 528
 529             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 530                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 531                 offset = 0x080;
 532             else
 533 #endif
 534                 offset = 0x000;
 535         }
 536         goto set_EPC;
 537     case EXCP_TLBS:
 538         cause = 3;
 539         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 540 #if defined(TARGET_MIPS64)
 541             int R = env->CP0_BadVAddr >> 62;
 542             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 543             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 544             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 545
 546             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 547                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 548                 offset = 0x080;
 549             else
 550 #endif
 551                 offset = 0x000;
 552         }
 553         goto set_EPC;
 554     case EXCP_AdEL:
 555         cause = 4;
 556         goto set_EPC;
 557     case EXCP_AdES:
 558         cause = 5;
 559         goto set_EPC;
 560     case EXCP_IBE:
 561         cause = 6;
 562         goto set_EPC;
 563     case EXCP_DBE:
 564         cause = 7;
 565         goto set_EPC;
 566     case EXCP_SYSCALL:
 567         cause = 8;
 568         goto set_EPC;
 569     case EXCP_BREAK:
 570         cause = 9;
 571         goto set_EPC;
 572     case EXCP_RI:
 573         cause = 10;
 574         goto set_EPC;
 575     case EXCP_CpU:
 576         cause = 11;
 577         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 578                          (env->error_code << CP0Ca_CE);
 579         goto set_EPC;
 580     case EXCP_OVERFLOW:
 581         cause = 12;
 582         goto set_EPC;
 583     case EXCP_TRAP:
 584         cause = 13;
 585         goto set_EPC;
 586     case EXCP_FPE:
 587         cause = 15;
 588         goto set_EPC;
 589     case EXCP_C2E:
 590         cause = 18;
 591         goto set_EPC;
 592     case EXCP_MDMX:
 593         cause = 22;
 594         goto set_EPC;
 595     case EXCP_DWATCH:
 596         cause = 23;
 597         /* XXX: TODO: manage defered watch exceptions */
 598         goto set_EPC;
 599     case EXCP_MCHECK:
 600         cause = 24;
 601         goto set_EPC;
 602     case EXCP_THREAD:
 603         cause = 25;
 604         goto set_EPC;
 605     case EXCP_DSPDIS:
 606         cause = 26;
 607         goto set_EPC;
 608     case EXCP_CACHE:
 609         cause = 30;
 610         if (env->CP0_Status & (1 << CP0St_BEV)) {
 611             offset = 0x100;
 612         } else {
 613             offset = 0x20000100;
 614         }
 615  set_EPC:
 616         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 617             env->CP0_EPC = exception_resume_pc(env);
 618             if (env->hflags & MIPS_HFLAG_BMASK) {
 619                 env->CP0_Cause |= (1U << CP0Ca_BD);
 620             } else {
 621                 env->CP0_Cause &= ~(1U << CP0Ca_BD);
 622             }
 623             env->CP0_Status |= (1 << CP0St_EXL);
 624             env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 625             env->hflags &= ~(MIPS_HFLAG_KSU);
 626         }
 627         env->hflags &= ~MIPS_HFLAG_BMASK;
 628         if (env->CP0_Status & (1 << CP0St_BEV)) {
 629             env->active_tc.PC = (int32_t)0xBFC00200;
 630         } else {
 631             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 632         }
 633         env->active_tc.PC += offset;
 634         set_hflags_for_handler(env);
 635         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 636         break;
 637     default:
 638         qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
 639         printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
 640         exit(1);
 641     }
 642     if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
 643         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 644                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 645                 __func__, env->active_tc.PC, env->CP0_EPC, cause,
 646                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 647                 env->CP0_DEPC);
 648     }
 649 #endif
 650     cs->exception_index = EXCP_NONE;
 651 }
 652
 653 #if !defined(CONFIG_USER_ONLY)
 654 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
 655 {
 656     MIPSCPU *cpu = mips_env_get_cpu(env);
 657     CPUState *cs;
 658     r4k_tlb_t *tlb;
 659     target_ulong addr;
 660     target_ulong end;
 661     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 662     target_ulong mask;
 663
 664     tlb = &env->tlb->mmu.r4k.tlb[idx];
 665     /* The qemu TLB is flushed when the ASID changes, so no need to
 666        flush these entries again.  */
 667     if (tlb->G == 0 && tlb->ASID != ASID) {
 668         return;
 669     }
 670
 671     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 672         /* For tlbwr, we can shadow the discarded entry into
 673            a new (fake) TLB entry, as long as the guest can not
 674            tell that it's there.  */
 675         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 676         env->tlb->tlb_in_use++;
 677         return;
 678     }
 679
 680     /* 1k pages are not supported. */
 681     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 682     if (tlb->V0) {
 683         cs = CPU(cpu);
 684         addr = tlb->VPN & ~mask;
 685 #if defined(TARGET_MIPS64)
 686         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 687             addr |= 0x3FFFFF0000000000ULL;
 688         }
 689 #endif
 690         end = addr | (mask >> 1);
 691         while (addr < end) {
 692             tlb_flush_page(cs, addr);
 693             addr += TARGET_PAGE_SIZE;
 694         }
 695     }
 696     if (tlb->V1) {
 697         cs = CPU(cpu);
 698         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 699 #if defined(TARGET_MIPS64)
 700         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 701             addr |= 0x3FFFFF0000000000ULL;
 702         }
 703 #endif
 704         end = addr | mask;
 705         while (addr - 1 < end) {
 706             tlb_flush_page(cs, addr);
 707             addr += TARGET_PAGE_SIZE;
 708         }
 709     }
 710 }
 711 #endif