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tcg: Optimize brcond2 and setcond2 ne/eq
[qemu.git] / target-i386 / seg_helper.c
blob3cf862ee600bf8e47c4375aa81a65c8c5bcfb1e4
1 /*
2 * x86 segmentation related helpers:
3 * TSS, interrupts, system calls, jumps and call/task gates, descriptors
4 *
5 * Copyright (c) 2003 Fabrice Bellard
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "qemu/log.h"
23 #include "helper.h"
24
25 //#define DEBUG_PCALL
26
27 #if !defined(CONFIG_USER_ONLY)
28 #include "exec/softmmu_exec.h"
29 #endif /* !defined(CONFIG_USER_ONLY) */
30
31 #ifdef DEBUG_PCALL
32 # define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__)
33 # define LOG_PCALL_STATE(cpu) \
34 log_cpu_state_mask(CPU_LOG_PCALL, (cpu), CPU_DUMP_CCOP)
35 #else
36 # define LOG_PCALL(...) do { } while (0)
37 # define LOG_PCALL_STATE(cpu) do { } while (0)
38 #endif
39
40 /* return non zero if error */
41 static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr,
42 uint32_t *e2_ptr, int selector)
43 {
44 SegmentCache *dt;
45 int index;
46 target_ulong ptr;
47
48 if (selector & 0x4) {
49 dt = &env->ldt;
50 } else {
51 dt = &env->gdt;
52 }
53 index = selector & ~7;
54 if ((index + 7) > dt->limit) {
55 return -1;
56 }
57 ptr = dt->base + index;
58 *e1_ptr = cpu_ldl_kernel(env, ptr);
59 *e2_ptr = cpu_ldl_kernel(env, ptr + 4);
60 return 0;
61 }
62
63 static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
64 {
65 unsigned int limit;
66
67 limit = (e1 & 0xffff) | (e2 & 0x000f0000);
68 if (e2 & DESC_G_MASK) {
69 limit = (limit << 12) | 0xfff;
70 }
71 return limit;
72 }
73
74 static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
75 {
76 return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000);
77 }
78
79 static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1,
80 uint32_t e2)
81 {
82 sc->base = get_seg_base(e1, e2);
83 sc->limit = get_seg_limit(e1, e2);
84 sc->flags = e2;
85 }
86
87 /* init the segment cache in vm86 mode. */
88 static inline void load_seg_vm(CPUX86State *env, int seg, int selector)
89 {
90 selector &= 0xffff;
91 cpu_x86_load_seg_cache(env, seg, selector,
92 (selector << 4), 0xffff, 0);
93 }
94
95 static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
96 uint32_t *esp_ptr, int dpl)
97 {
98 X86CPU *cpu = x86_env_get_cpu(env);
99 int type, index, shift;
100
101 #if 0
102 {
103 int i;
104 printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
105 for (i = 0; i < env->tr.limit; i++) {
106 printf("%02x ", env->tr.base[i]);
107 if ((i & 7) == 7) {
108 printf("\n");
109 }
110 }
111 printf("\n");
112 }
113 #endif
114
115 if (!(env->tr.flags & DESC_P_MASK)) {
116 cpu_abort(CPU(cpu), "invalid tss");
117 }
118 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
119 if ((type & 7) != 1) {
120 cpu_abort(CPU(cpu), "invalid tss type");
121 }
122 shift = type >> 3;
123 index = (dpl * 4 + 2) << shift;
124 if (index + (4 << shift) - 1 > env->tr.limit) {
125 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
126 }
127 if (shift == 0) {
128 *esp_ptr = cpu_lduw_kernel(env, env->tr.base + index);
129 *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 2);
130 } else {
131 *esp_ptr = cpu_ldl_kernel(env, env->tr.base + index);
132 *ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 4);
133 }
134 }
135
136 /* XXX: merge with load_seg() */
137 static void tss_load_seg(CPUX86State *env, int seg_reg, int selector)
138 {
139 uint32_t e1, e2;
140 int rpl, dpl, cpl;
141
142 if ((selector & 0xfffc) != 0) {
143 if (load_segment(env, &e1, &e2, selector) != 0) {
144 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
145 }
146 if (!(e2 & DESC_S_MASK)) {
147 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
148 }
149 rpl = selector & 3;
150 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
151 cpl = env->hflags & HF_CPL_MASK;
152 if (seg_reg == R_CS) {
153 if (!(e2 & DESC_CS_MASK)) {
154 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
155 }
156 /* XXX: is it correct? */
157 if (dpl != rpl) {
158 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
159 }
160 if ((e2 & DESC_C_MASK) && dpl > rpl) {
161 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
162 }
163 } else if (seg_reg == R_SS) {
164 /* SS must be writable data */
165 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
166 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
167 }
168 if (dpl != cpl || dpl != rpl) {
169 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
170 }
171 } else {
172 /* not readable code */
173 if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
174 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
175 }
176 /* if data or non conforming code, checks the rights */
177 if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) {
178 if (dpl < cpl || dpl < rpl) {
179 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
180 }
181 }
182 }
183 if (!(e2 & DESC_P_MASK)) {
184 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
185 }
186 cpu_x86_load_seg_cache(env, seg_reg, selector,
187 get_seg_base(e1, e2),
188 get_seg_limit(e1, e2),
189 e2);
190 } else {
191 if (seg_reg == R_SS || seg_reg == R_CS) {
192 raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
193 }
194 }
195 }
196
197 #define SWITCH_TSS_JMP 0
198 #define SWITCH_TSS_IRET 1
199 #define SWITCH_TSS_CALL 2
200
201 /* XXX: restore CPU state in registers (PowerPC case) */
202 static void switch_tss(CPUX86State *env, int tss_selector,
203 uint32_t e1, uint32_t e2, int source,
204 uint32_t next_eip)
205 {
206 int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
207 target_ulong tss_base;
208 uint32_t new_regs[8], new_segs[6];
209 uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap;
210 uint32_t old_eflags, eflags_mask;
211 SegmentCache *dt;
212 int index;
213 target_ulong ptr;
214
215 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
216 LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
217 source);
218
219 /* if task gate, we read the TSS segment and we load it */
220 if (type == 5) {
221 if (!(e2 & DESC_P_MASK)) {
222 raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
223 }
224 tss_selector = e1 >> 16;
225 if (tss_selector & 4) {
226 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
227 }
228 if (load_segment(env, &e1, &e2, tss_selector) != 0) {
229 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
230 }
231 if (e2 & DESC_S_MASK) {
232 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
233 }
234 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
235 if ((type & 7) != 1) {
236 raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
237 }
238 }
239
240 if (!(e2 & DESC_P_MASK)) {
241 raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
242 }
243
244 if (type & 8) {
245 tss_limit_max = 103;
246 } else {
247 tss_limit_max = 43;
248 }
249 tss_limit = get_seg_limit(e1, e2);
250 tss_base = get_seg_base(e1, e2);
251 if ((tss_selector & 4) != 0 ||
252 tss_limit < tss_limit_max) {
253 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
254 }
255 old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
256 if (old_type & 8) {
257 old_tss_limit_max = 103;
258 } else {
259 old_tss_limit_max = 43;
260 }
261
262 /* read all the registers from the new TSS */
263 if (type & 8) {
264 /* 32 bit */
265 new_cr3 = cpu_ldl_kernel(env, tss_base + 0x1c);
266 new_eip = cpu_ldl_kernel(env, tss_base + 0x20);
267 new_eflags = cpu_ldl_kernel(env, tss_base + 0x24);
268 for (i = 0; i < 8; i++) {
269 new_regs[i] = cpu_ldl_kernel(env, tss_base + (0x28 + i * 4));
270 }
271 for (i = 0; i < 6; i++) {
272 new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x48 + i * 4));
273 }
274 new_ldt = cpu_lduw_kernel(env, tss_base + 0x60);
275 new_trap = cpu_ldl_kernel(env, tss_base + 0x64);
276 } else {
277 /* 16 bit */
278 new_cr3 = 0;
279 new_eip = cpu_lduw_kernel(env, tss_base + 0x0e);
280 new_eflags = cpu_lduw_kernel(env, tss_base + 0x10);
281 for (i = 0; i < 8; i++) {
282 new_regs[i] = cpu_lduw_kernel(env, tss_base + (0x12 + i * 2)) |
283 0xffff0000;
284 }
285 for (i = 0; i < 4; i++) {
286 new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x22 + i * 4));
287 }
288 new_ldt = cpu_lduw_kernel(env, tss_base + 0x2a);
289 new_segs[R_FS] = 0;
290 new_segs[R_GS] = 0;
291 new_trap = 0;
292 }
293 /* XXX: avoid a compiler warning, see
294 http://support.amd.com/us/Processor_TechDocs/24593.pdf
295 chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
296 (void)new_trap;
297
298 /* NOTE: we must avoid memory exceptions during the task switch,
299 so we make dummy accesses before */
300 /* XXX: it can still fail in some cases, so a bigger hack is
301 necessary to valid the TLB after having done the accesses */
302
303 v1 = cpu_ldub_kernel(env, env->tr.base);
304 v2 = cpu_ldub_kernel(env, env->tr.base + old_tss_limit_max);
305 cpu_stb_kernel(env, env->tr.base, v1);
306 cpu_stb_kernel(env, env->tr.base + old_tss_limit_max, v2);
307
308 /* clear busy bit (it is restartable) */
309 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
310 target_ulong ptr;
311 uint32_t e2;
312
313 ptr = env->gdt.base + (env->tr.selector & ~7);
314 e2 = cpu_ldl_kernel(env, ptr + 4);
315 e2 &= ~DESC_TSS_BUSY_MASK;
316 cpu_stl_kernel(env, ptr + 4, e2);
317 }
318 old_eflags = cpu_compute_eflags(env);
319 if (source == SWITCH_TSS_IRET) {
320 old_eflags &= ~NT_MASK;
321 }
322
323 /* save the current state in the old TSS */
324 if (type & 8) {
325 /* 32 bit */
326 cpu_stl_kernel(env, env->tr.base + 0x20, next_eip);
327 cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
328 cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]);
329 cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]);
330 cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]);
331 cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]);
332 cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]);
333 cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]);
334 cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI]);
335 cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI]);
336 for (i = 0; i < 6; i++) {
337 cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4),
338 env->segs[i].selector);
339 }
340 } else {
341 /* 16 bit */
342 cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip);
343 cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
344 cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]);
345 cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]);
346 cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]);
347 cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]);
348 cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]);
349 cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]);
350 cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI]);
351 cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI]);
352 for (i = 0; i < 4; i++) {
353 cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4),
354 env->segs[i].selector);
355 }
356 }
357
358 /* now if an exception occurs, it will occurs in the next task
359 context */
360
361 if (source == SWITCH_TSS_CALL) {
362 cpu_stw_kernel(env, tss_base, env->tr.selector);
363 new_eflags |= NT_MASK;
364 }
365
366 /* set busy bit */
367 if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
368 target_ulong ptr;
369 uint32_t e2;
370
371 ptr = env->gdt.base + (tss_selector & ~7);
372 e2 = cpu_ldl_kernel(env, ptr + 4);
373 e2 |= DESC_TSS_BUSY_MASK;
374 cpu_stl_kernel(env, ptr + 4, e2);
375 }
376
377 /* set the new CPU state */
378 /* from this point, any exception which occurs can give problems */
379 env->cr[0] |= CR0_TS_MASK;
380 env->hflags |= HF_TS_MASK;
381 env->tr.selector = tss_selector;
382 env->tr.base = tss_base;
383 env->tr.limit = tss_limit;
384 env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK;
385
386 if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) {
387 cpu_x86_update_cr3(env, new_cr3);
388 }
389
390 /* load all registers without an exception, then reload them with
391 possible exception */
392 env->eip = new_eip;
393 eflags_mask = TF_MASK | AC_MASK | ID_MASK |
394 IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK;
395 if (!(type & 8)) {
396 eflags_mask &= 0xffff;
397 }
398 cpu_load_eflags(env, new_eflags, eflags_mask);
399 /* XXX: what to do in 16 bit case? */
400 env->regs[R_EAX] = new_regs[0];
401 env->regs[R_ECX] = new_regs[1];
402 env->regs[R_EDX] = new_regs[2];
403 env->regs[R_EBX] = new_regs[3];
404 env->regs[R_ESP] = new_regs[4];
405 env->regs[R_EBP] = new_regs[5];
406 env->regs[R_ESI] = new_regs[6];
407 env->regs[R_EDI] = new_regs[7];
408 if (new_eflags & VM_MASK) {
409 for (i = 0; i < 6; i++) {
410 load_seg_vm(env, i, new_segs[i]);
411 }
412 } else {
413 /* first just selectors as the rest may trigger exceptions */
414 for (i = 0; i < 6; i++) {
415 cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0);
416 }
417 }
418
419 env->ldt.selector = new_ldt & ~4;
420 env->ldt.base = 0;
421 env->ldt.limit = 0;
422 env->ldt.flags = 0;
423
424 /* load the LDT */
425 if (new_ldt & 4) {
426 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
427 }
428
429 if ((new_ldt & 0xfffc) != 0) {
430 dt = &env->gdt;
431 index = new_ldt & ~7;
432 if ((index + 7) > dt->limit) {
433 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
434 }
435 ptr = dt->base + index;
436 e1 = cpu_ldl_kernel(env, ptr);
437 e2 = cpu_ldl_kernel(env, ptr + 4);
438 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
439 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
440 }
441 if (!(e2 & DESC_P_MASK)) {
442 raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
443 }
444 load_seg_cache_raw_dt(&env->ldt, e1, e2);
445 }
446
447 /* load the segments */
448 if (!(new_eflags & VM_MASK)) {
449 tss_load_seg(env, R_CS, new_segs[R_CS]);
450 tss_load_seg(env, R_SS, new_segs[R_SS]);
451 tss_load_seg(env, R_ES, new_segs[R_ES]);
452 tss_load_seg(env, R_DS, new_segs[R_DS]);
453 tss_load_seg(env, R_FS, new_segs[R_FS]);
454 tss_load_seg(env, R_GS, new_segs[R_GS]);
455 }
456
457 /* check that env->eip is in the CS segment limits */
458 if (new_eip > env->segs[R_CS].limit) {
459 /* XXX: different exception if CALL? */
460 raise_exception_err(env, EXCP0D_GPF, 0);
461 }
462
463 #ifndef CONFIG_USER_ONLY
464 /* reset local breakpoints */
465 if (env->dr[7] & DR7_LOCAL_BP_MASK) {
466 for (i = 0; i < DR7_MAX_BP; i++) {
467 if (hw_local_breakpoint_enabled(env->dr[7], i) &&
468 !hw_global_breakpoint_enabled(env->dr[7], i)) {
469 hw_breakpoint_remove(env, i);
470 }
471 }
472 env->dr[7] &= ~DR7_LOCAL_BP_MASK;
473 }
474 #endif
475 }
476
477 static inline unsigned int get_sp_mask(unsigned int e2)
478 {
479 if (e2 & DESC_B_MASK) {
480 return 0xffffffff;
481 } else {
482 return 0xffff;
483 }
484 }
485
486 static int exception_has_error_code(int intno)
487 {
488 switch (intno) {
489 case 8:
490 case 10:
491 case 11:
492 case 12:
493 case 13:
494 case 14:
495 case 17:
496 return 1;
497 }
498 return 0;
499 }
500
501 #ifdef TARGET_X86_64
502 #define SET_ESP(val, sp_mask) \
503 do { \
504 if ((sp_mask) == 0xffff) { \
505 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
506 ((val) & 0xffff); \
507 } else if ((sp_mask) == 0xffffffffLL) { \
508 env->regs[R_ESP] = (uint32_t)(val); \
509 } else { \
510 env->regs[R_ESP] = (val); \
511 } \
512 } while (0)
513 #else
514 #define SET_ESP(val, sp_mask) \
515 do { \
516 env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \
517 ((val) & (sp_mask)); \
518 } while (0)
519 #endif
520
521 /* in 64-bit machines, this can overflow. So this segment addition macro
522 * can be used to trim the value to 32-bit whenever needed */
523 #define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
524
525 /* XXX: add a is_user flag to have proper security support */
526 #define PUSHW(ssp, sp, sp_mask, val) \
527 { \
528 sp -= 2; \
529 cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \
530 }
531
532 #define PUSHL(ssp, sp, sp_mask, val) \
533 { \
534 sp -= 4; \
535 cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \
536 }
537
538 #define POPW(ssp, sp, sp_mask, val) \
539 { \
540 val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \
541 sp += 2; \
542 }
543
544 #define POPL(ssp, sp, sp_mask, val) \
545 { \
546 val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \
547 sp += 4; \
548 }
549
550 /* protected mode interrupt */
551 static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
552 int error_code, unsigned int next_eip,
553 int is_hw)
554 {
555 SegmentCache *dt;
556 target_ulong ptr, ssp;
557 int type, dpl, selector, ss_dpl, cpl;
558 int has_error_code, new_stack, shift;
559 uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0;
560 uint32_t old_eip, sp_mask;
561
562 has_error_code = 0;
563 if (!is_int && !is_hw) {
564 has_error_code = exception_has_error_code(intno);
565 }
566 if (is_int) {
567 old_eip = next_eip;
568 } else {
569 old_eip = env->eip;
570 }
571
572 dt = &env->idt;
573 if (intno * 8 + 7 > dt->limit) {
574 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
575 }
576 ptr = dt->base + intno * 8;
577 e1 = cpu_ldl_kernel(env, ptr);
578 e2 = cpu_ldl_kernel(env, ptr + 4);
579 /* check gate type */
580 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
581 switch (type) {
582 case 5: /* task gate */
583 /* must do that check here to return the correct error code */
584 if (!(e2 & DESC_P_MASK)) {
585 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
586 }
587 switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
588 if (has_error_code) {
589 int type;
590 uint32_t mask;
591
592 /* push the error code */
593 type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
594 shift = type >> 3;
595 if (env->segs[R_SS].flags & DESC_B_MASK) {
596 mask = 0xffffffff;
597 } else {
598 mask = 0xffff;
599 }
600 esp = (env->regs[R_ESP] - (2 << shift)) & mask;
601 ssp = env->segs[R_SS].base + esp;
602 if (shift) {
603 cpu_stl_kernel(env, ssp, error_code);
604 } else {
605 cpu_stw_kernel(env, ssp, error_code);
606 }
607 SET_ESP(esp, mask);
608 }
609 return;
610 case 6: /* 286 interrupt gate */
611 case 7: /* 286 trap gate */
612 case 14: /* 386 interrupt gate */
613 case 15: /* 386 trap gate */
614 break;
615 default:
616 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
617 break;
618 }
619 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
620 cpl = env->hflags & HF_CPL_MASK;
621 /* check privilege if software int */
622 if (is_int && dpl < cpl) {
623 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
624 }
625 /* check valid bit */
626 if (!(e2 & DESC_P_MASK)) {
627 raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2);
628 }
629 selector = e1 >> 16;
630 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
631 if ((selector & 0xfffc) == 0) {
632 raise_exception_err(env, EXCP0D_GPF, 0);
633 }
634 if (load_segment(env, &e1, &e2, selector) != 0) {
635 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
636 }
637 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
638 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
639 }
640 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
641 if (dpl > cpl) {
642 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
643 }
644 if (!(e2 & DESC_P_MASK)) {
645 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
646 }
647 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
648 /* to inner privilege */
649 get_ss_esp_from_tss(env, &ss, &esp, dpl);
650 if ((ss & 0xfffc) == 0) {
651 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
652 }
653 if ((ss & 3) != dpl) {
654 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
655 }
656 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
657 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
658 }
659 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
660 if (ss_dpl != dpl) {
661 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
662 }
663 if (!(ss_e2 & DESC_S_MASK) ||
664 (ss_e2 & DESC_CS_MASK) ||
665 !(ss_e2 & DESC_W_MASK)) {
666 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
667 }
668 if (!(ss_e2 & DESC_P_MASK)) {
669 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
670 }
671 new_stack = 1;
672 sp_mask = get_sp_mask(ss_e2);
673 ssp = get_seg_base(ss_e1, ss_e2);
674 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
675 /* to same privilege */
676 if (env->eflags & VM_MASK) {
677 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
678 }
679 new_stack = 0;
680 sp_mask = get_sp_mask(env->segs[R_SS].flags);
681 ssp = env->segs[R_SS].base;
682 esp = env->regs[R_ESP];
683 dpl = cpl;
684 } else {
685 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
686 new_stack = 0; /* avoid warning */
687 sp_mask = 0; /* avoid warning */
688 ssp = 0; /* avoid warning */
689 esp = 0; /* avoid warning */
690 }
691
692 shift = type >> 3;
693
694 #if 0
695 /* XXX: check that enough room is available */
696 push_size = 6 + (new_stack << 2) + (has_error_code << 1);
697 if (env->eflags & VM_MASK) {
698 push_size += 8;
699 }
700 push_size <<= shift;
701 #endif
702 if (shift == 1) {
703 if (new_stack) {
704 if (env->eflags & VM_MASK) {
705 PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector);
706 PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector);
707 PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector);
708 PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector);
709 }
710 PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector);
711 PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]);
712 }
713 PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env));
714 PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector);
715 PUSHL(ssp, esp, sp_mask, old_eip);
716 if (has_error_code) {
717 PUSHL(ssp, esp, sp_mask, error_code);
718 }
719 } else {
720 if (new_stack) {
721 if (env->eflags & VM_MASK) {
722 PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector);
723 PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector);
724 PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector);
725 PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector);
726 }
727 PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector);
728 PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]);
729 }
730 PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env));
731 PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector);
732 PUSHW(ssp, esp, sp_mask, old_eip);
733 if (has_error_code) {
734 PUSHW(ssp, esp, sp_mask, error_code);
735 }
736 }
737
738 /* interrupt gate clear IF mask */
739 if ((type & 1) == 0) {
740 env->eflags &= ~IF_MASK;
741 }
742 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
743
744 if (new_stack) {
745 if (env->eflags & VM_MASK) {
746 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0);
747 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0);
748 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0);
749 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0);
750 }
751 ss = (ss & ~3) | dpl;
752 cpu_x86_load_seg_cache(env, R_SS, ss,
753 ssp, get_seg_limit(ss_e1, ss_e2), ss_e2);
754 }
755 SET_ESP(esp, sp_mask);
756
757 selector = (selector & ~3) | dpl;
758 cpu_x86_load_seg_cache(env, R_CS, selector,
759 get_seg_base(e1, e2),
760 get_seg_limit(e1, e2),
761 e2);
762 env->eip = offset;
763 }
764
765 #ifdef TARGET_X86_64
766
767 #define PUSHQ(sp, val) \
768 { \
769 sp -= 8; \
770 cpu_stq_kernel(env, sp, (val)); \
771 }
772
773 #define POPQ(sp, val) \
774 { \
775 val = cpu_ldq_kernel(env, sp); \
776 sp += 8; \
777 }
778
779 static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
780 {
781 X86CPU *cpu = x86_env_get_cpu(env);
782 int index;
783
784 #if 0
785 printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
786 env->tr.base, env->tr.limit);
787 #endif
788
789 if (!(env->tr.flags & DESC_P_MASK)) {
790 cpu_abort(CPU(cpu), "invalid tss");
791 }
792 index = 8 * level + 4;
793 if ((index + 7) > env->tr.limit) {
794 raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
795 }
796 return cpu_ldq_kernel(env, env->tr.base + index);
797 }
798
799 /* 64 bit interrupt */
800 static void do_interrupt64(CPUX86State *env, int intno, int is_int,
801 int error_code, target_ulong next_eip, int is_hw)
802 {
803 SegmentCache *dt;
804 target_ulong ptr;
805 int type, dpl, selector, cpl, ist;
806 int has_error_code, new_stack;
807 uint32_t e1, e2, e3, ss;
808 target_ulong old_eip, esp, offset;
809
810 has_error_code = 0;
811 if (!is_int && !is_hw) {
812 has_error_code = exception_has_error_code(intno);
813 }
814 if (is_int) {
815 old_eip = next_eip;
816 } else {
817 old_eip = env->eip;
818 }
819
820 dt = &env->idt;
821 if (intno * 16 + 15 > dt->limit) {
822 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
823 }
824 ptr = dt->base + intno * 16;
825 e1 = cpu_ldl_kernel(env, ptr);
826 e2 = cpu_ldl_kernel(env, ptr + 4);
827 e3 = cpu_ldl_kernel(env, ptr + 8);
828 /* check gate type */
829 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
830 switch (type) {
831 case 14: /* 386 interrupt gate */
832 case 15: /* 386 trap gate */
833 break;
834 default:
835 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
836 break;
837 }
838 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
839 cpl = env->hflags & HF_CPL_MASK;
840 /* check privilege if software int */
841 if (is_int && dpl < cpl) {
842 raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2);
843 }
844 /* check valid bit */
845 if (!(e2 & DESC_P_MASK)) {
846 raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2);
847 }
848 selector = e1 >> 16;
849 offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff);
850 ist = e2 & 7;
851 if ((selector & 0xfffc) == 0) {
852 raise_exception_err(env, EXCP0D_GPF, 0);
853 }
854
855 if (load_segment(env, &e1, &e2, selector) != 0) {
856 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
857 }
858 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
859 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
860 }
861 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
862 if (dpl > cpl) {
863 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
864 }
865 if (!(e2 & DESC_P_MASK)) {
866 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
867 }
868 if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
869 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
870 }
871 if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) {
872 /* to inner privilege */
873 if (ist != 0) {
874 esp = get_rsp_from_tss(env, ist + 3);
875 } else {
876 esp = get_rsp_from_tss(env, dpl);
877 }
878 esp &= ~0xfLL; /* align stack */
879 ss = 0;
880 new_stack = 1;
881 } else if ((e2 & DESC_C_MASK) || dpl == cpl) {
882 /* to same privilege */
883 if (env->eflags & VM_MASK) {
884 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
885 }
886 new_stack = 0;
887 if (ist != 0) {
888 esp = get_rsp_from_tss(env, ist + 3);
889 } else {
890 esp = env->regs[R_ESP];
891 }
892 esp &= ~0xfLL; /* align stack */
893 dpl = cpl;
894 } else {
895 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
896 new_stack = 0; /* avoid warning */
897 esp = 0; /* avoid warning */
898 }
899
900 PUSHQ(esp, env->segs[R_SS].selector);
901 PUSHQ(esp, env->regs[R_ESP]);
902 PUSHQ(esp, cpu_compute_eflags(env));
903 PUSHQ(esp, env->segs[R_CS].selector);
904 PUSHQ(esp, old_eip);
905 if (has_error_code) {
906 PUSHQ(esp, error_code);
907 }
908
909 /* interrupt gate clear IF mask */
910 if ((type & 1) == 0) {
911 env->eflags &= ~IF_MASK;
912 }
913 env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK);
914
915 if (new_stack) {
916 ss = 0 | dpl;
917 cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0);
918 }
919 env->regs[R_ESP] = esp;
920
921 selector = (selector & ~3) | dpl;
922 cpu_x86_load_seg_cache(env, R_CS, selector,
923 get_seg_base(e1, e2),
924 get_seg_limit(e1, e2),
925 e2);
926 env->eip = offset;
927 }
928 #endif
929
930 #ifdef TARGET_X86_64
931 #if defined(CONFIG_USER_ONLY)
932 void helper_syscall(CPUX86State *env, int next_eip_addend)
933 {
934 CPUState *cs = CPU(x86_env_get_cpu(env));
935
936 cs->exception_index = EXCP_SYSCALL;
937 env->exception_next_eip = env->eip + next_eip_addend;
938 cpu_loop_exit(cs);
939 }
940 #else
941 void helper_syscall(CPUX86State *env, int next_eip_addend)
942 {
943 int selector;
944
945 if (!(env->efer & MSR_EFER_SCE)) {
946 raise_exception_err(env, EXCP06_ILLOP, 0);
947 }
948 selector = (env->star >> 32) & 0xffff;
949 if (env->hflags & HF_LMA_MASK) {
950 int code64;
951
952 env->regs[R_ECX] = env->eip + next_eip_addend;
953 env->regs[11] = cpu_compute_eflags(env);
954
955 code64 = env->hflags & HF_CS64_MASK;
956
957 env->eflags &= ~env->fmask;
958 cpu_load_eflags(env, env->eflags, 0);
959 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
960 0, 0xffffffff,
961 DESC_G_MASK | DESC_P_MASK |
962 DESC_S_MASK |
963 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
964 DESC_L_MASK);
965 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
966 0, 0xffffffff,
967 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
968 DESC_S_MASK |
969 DESC_W_MASK | DESC_A_MASK);
970 if (code64) {
971 env->eip = env->lstar;
972 } else {
973 env->eip = env->cstar;
974 }
975 } else {
976 env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend);
977
978 env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
979 cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
980 0, 0xffffffff,
981 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
982 DESC_S_MASK |
983 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
984 cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
985 0, 0xffffffff,
986 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
987 DESC_S_MASK |
988 DESC_W_MASK | DESC_A_MASK);
989 env->eip = (uint32_t)env->star;
990 }
991 }
992 #endif
993 #endif
994
995 #ifdef TARGET_X86_64
996 void helper_sysret(CPUX86State *env, int dflag)
997 {
998 int cpl, selector;
999
1000 if (!(env->efer & MSR_EFER_SCE)) {
1001 raise_exception_err(env, EXCP06_ILLOP, 0);
1002 }
1003 cpl = env->hflags & HF_CPL_MASK;
1004 if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) {
1005 raise_exception_err(env, EXCP0D_GPF, 0);
1006 }
1007 selector = (env->star >> 48) & 0xffff;
1008 if (env->hflags & HF_LMA_MASK) {
1009 cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
1010 | ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK |
1011 NT_MASK);
1012 if (dflag == 2) {
1013 cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3,
1014 0, 0xffffffff,
1015 DESC_G_MASK | DESC_P_MASK |
1016 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1017 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
1018 DESC_L_MASK);
1019 env->eip = env->regs[R_ECX];
1020 } else {
1021 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1022 0, 0xffffffff,
1023 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1024 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1025 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1026 env->eip = (uint32_t)env->regs[R_ECX];
1027 }
1028 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1029 0, 0xffffffff,
1030 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1031 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1032 DESC_W_MASK | DESC_A_MASK);
1033 } else {
1034 env->eflags |= IF_MASK;
1035 cpu_x86_load_seg_cache(env, R_CS, selector | 3,
1036 0, 0xffffffff,
1037 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1038 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1039 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
1040 env->eip = (uint32_t)env->regs[R_ECX];
1041 cpu_x86_load_seg_cache(env, R_SS, selector + 8,
1042 0, 0xffffffff,
1043 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
1044 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
1045 DESC_W_MASK | DESC_A_MASK);
1046 }
1047 }
1048 #endif
1049
1050 /* real mode interrupt */
1051 static void do_interrupt_real(CPUX86State *env, int intno, int is_int,
1052 int error_code, unsigned int next_eip)
1053 {
1054 SegmentCache *dt;
1055 target_ulong ptr, ssp;
1056 int selector;
1057 uint32_t offset, esp;
1058 uint32_t old_cs, old_eip;
1059
1060 /* real mode (simpler!) */
1061 dt = &env->idt;
1062 if (intno * 4 + 3 > dt->limit) {
1063 raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2);
1064 }
1065 ptr = dt->base + intno * 4;
1066 offset = cpu_lduw_kernel(env, ptr);
1067 selector = cpu_lduw_kernel(env, ptr + 2);
1068 esp = env->regs[R_ESP];
1069 ssp = env->segs[R_SS].base;
1070 if (is_int) {
1071 old_eip = next_eip;
1072 } else {
1073 old_eip = env->eip;
1074 }
1075 old_cs = env->segs[R_CS].selector;
1076 /* XXX: use SS segment size? */
1077 PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
1078 PUSHW(ssp, esp, 0xffff, old_cs);
1079 PUSHW(ssp, esp, 0xffff, old_eip);
1080
1081 /* update processor state */
1082 env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff);
1083 env->eip = offset;
1084 env->segs[R_CS].selector = selector;
1085 env->segs[R_CS].base = (selector << 4);
1086 env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK);
1087 }
1088
1089 #if defined(CONFIG_USER_ONLY)
1090 /* fake user mode interrupt */
1091 static void do_interrupt_user(CPUX86State *env, int intno, int is_int,
1092 int error_code, target_ulong next_eip)
1093 {
1094 SegmentCache *dt;
1095 target_ulong ptr;
1096 int dpl, cpl, shift;
1097 uint32_t e2;
1098
1099 dt = &env->idt;
1100 if (env->hflags & HF_LMA_MASK) {
1101 shift = 4;
1102 } else {
1103 shift = 3;
1104 }
1105 ptr = dt->base + (intno << shift);
1106 e2 = cpu_ldl_kernel(env, ptr + 4);
1107
1108 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1109 cpl = env->hflags & HF_CPL_MASK;
1110 /* check privilege if software int */
1111 if (is_int && dpl < cpl) {
1112 raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2);
1113 }
1114
1115 /* Since we emulate only user space, we cannot do more than
1116 exiting the emulation with the suitable exception and error
1117 code */
1118 if (is_int) {
1119 env->eip = next_eip;
1120 }
1121 }
1122
1123 #else
1124
1125 static void handle_even_inj(CPUX86State *env, int intno, int is_int,
1126 int error_code, int is_hw, int rm)
1127 {
1128 CPUState *cs = CPU(x86_env_get_cpu(env));
1129 uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
1130 control.event_inj));
1131
1132 if (!(event_inj & SVM_EVTINJ_VALID)) {
1133 int type;
1134
1135 if (is_int) {
1136 type = SVM_EVTINJ_TYPE_SOFT;
1137 } else {
1138 type = SVM_EVTINJ_TYPE_EXEPT;
1139 }
1140 event_inj = intno | type | SVM_EVTINJ_VALID;
1141 if (!rm && exception_has_error_code(intno)) {
1142 event_inj |= SVM_EVTINJ_VALID_ERR;
1143 stl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
1144 control.event_inj_err),
1145 error_code);
1146 }
1147 stl_phys(cs->as,
1148 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1149 event_inj);
1150 }
1151 }
1152 #endif
1153
1154 /*
1155 * Begin execution of an interruption. is_int is TRUE if coming from
1156 * the int instruction. next_eip is the env->eip value AFTER the interrupt
1157 * instruction. It is only relevant if is_int is TRUE.
1158 */
1159 static void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
1160 int error_code, target_ulong next_eip, int is_hw)
1161 {
1162 CPUX86State *env = &cpu->env;
1163
1164 if (qemu_loglevel_mask(CPU_LOG_INT)) {
1165 if ((env->cr[0] & CR0_PE_MASK)) {
1166 static int count;
1167
1168 qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
1169 " pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
1170 count, intno, error_code, is_int,
1171 env->hflags & HF_CPL_MASK,
1172 env->segs[R_CS].selector, env->eip,
1173 (int)env->segs[R_CS].base + env->eip,
1174 env->segs[R_SS].selector, env->regs[R_ESP]);
1175 if (intno == 0x0e) {
1176 qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]);
1177 } else {
1178 qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]);
1179 }
1180 qemu_log("\n");
1181 log_cpu_state(CPU(cpu), CPU_DUMP_CCOP);
1182 #if 0
1183 {
1184 int i;
1185 target_ulong ptr;
1186
1187 qemu_log(" code=");
1188 ptr = env->segs[R_CS].base + env->eip;
1189 for (i = 0; i < 16; i++) {
1190 qemu_log(" %02x", ldub(ptr + i));
1191 }
1192 qemu_log("\n");
1193 }
1194 #endif
1195 count++;
1196 }
1197 }
1198 if (env->cr[0] & CR0_PE_MASK) {
1199 #if !defined(CONFIG_USER_ONLY)
1200 if (env->hflags & HF_SVMI_MASK) {
1201 handle_even_inj(env, intno, is_int, error_code, is_hw, 0);
1202 }
1203 #endif
1204 #ifdef TARGET_X86_64
1205 if (env->hflags & HF_LMA_MASK) {
1206 do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw);
1207 } else
1208 #endif
1209 {
1210 do_interrupt_protected(env, intno, is_int, error_code, next_eip,
1211 is_hw);
1212 }
1213 } else {
1214 #if !defined(CONFIG_USER_ONLY)
1215 if (env->hflags & HF_SVMI_MASK) {
1216 handle_even_inj(env, intno, is_int, error_code, is_hw, 1);
1217 }
1218 #endif
1219 do_interrupt_real(env, intno, is_int, error_code, next_eip);
1220 }
1221
1222 #if !defined(CONFIG_USER_ONLY)
1223 if (env->hflags & HF_SVMI_MASK) {
1224 CPUState *cs = CPU(cpu);
1225 uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb +
1226 offsetof(struct vmcb,
1227 control.event_inj));
1228
1229 stl_phys(cs->as,
1230 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1231 event_inj & ~SVM_EVTINJ_VALID);
1232 }
1233 #endif
1234 }
1235
1236 void x86_cpu_do_interrupt(CPUState *cs)
1237 {
1238 X86CPU *cpu = X86_CPU(cs);
1239 CPUX86State *env = &cpu->env;
1240
1241 #if defined(CONFIG_USER_ONLY)
1242 /* if user mode only, we simulate a fake exception
1243 which will be handled outside the cpu execution
1244 loop */
1245 do_interrupt_user(env, cs->exception_index,
1246 env->exception_is_int,
1247 env->error_code,
1248 env->exception_next_eip);
1249 /* successfully delivered */
1250 env->old_exception = -1;
1251 #else
1252 /* simulate a real cpu exception. On i386, it can
1253 trigger new exceptions, but we do not handle
1254 double or triple faults yet. */
1255 do_interrupt_all(cpu, cs->exception_index,
1256 env->exception_is_int,
1257 env->error_code,
1258 env->exception_next_eip, 0);
1259 /* successfully delivered */
1260 env->old_exception = -1;
1261 #endif
1262 }
1263
1264 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw)
1265 {
1266 do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw);
1267 }
1268
1269 void helper_enter_level(CPUX86State *env, int level, int data32,
1270 target_ulong t1)
1271 {
1272 target_ulong ssp;
1273 uint32_t esp_mask, esp, ebp;
1274
1275 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1276 ssp = env->segs[R_SS].base;
1277 ebp = env->regs[R_EBP];
1278 esp = env->regs[R_ESP];
1279 if (data32) {
1280 /* 32 bit */
1281 esp -= 4;
1282 while (--level) {
1283 esp -= 4;
1284 ebp -= 4;
1285 cpu_stl_data(env, ssp + (esp & esp_mask),
1286 cpu_ldl_data(env, ssp + (ebp & esp_mask)));
1287 }
1288 esp -= 4;
1289 cpu_stl_data(env, ssp + (esp & esp_mask), t1);
1290 } else {
1291 /* 16 bit */
1292 esp -= 2;
1293 while (--level) {
1294 esp -= 2;
1295 ebp -= 2;
1296 cpu_stw_data(env, ssp + (esp & esp_mask),
1297 cpu_lduw_data(env, ssp + (ebp & esp_mask)));
1298 }
1299 esp -= 2;
1300 cpu_stw_data(env, ssp + (esp & esp_mask), t1);
1301 }
1302 }
1303
1304 #ifdef TARGET_X86_64
1305 void helper_enter64_level(CPUX86State *env, int level, int data64,
1306 target_ulong t1)
1307 {
1308 target_ulong esp, ebp;
1309
1310 ebp = env->regs[R_EBP];
1311 esp = env->regs[R_ESP];
1312
1313 if (data64) {
1314 /* 64 bit */
1315 esp -= 8;
1316 while (--level) {
1317 esp -= 8;
1318 ebp -= 8;
1319 cpu_stq_data(env, esp, cpu_ldq_data(env, ebp));
1320 }
1321 esp -= 8;
1322 cpu_stq_data(env, esp, t1);
1323 } else {
1324 /* 16 bit */
1325 esp -= 2;
1326 while (--level) {
1327 esp -= 2;
1328 ebp -= 2;
1329 cpu_stw_data(env, esp, cpu_lduw_data(env, ebp));
1330 }
1331 esp -= 2;
1332 cpu_stw_data(env, esp, t1);
1333 }
1334 }
1335 #endif
1336
1337 void helper_lldt(CPUX86State *env, int selector)
1338 {
1339 SegmentCache *dt;
1340 uint32_t e1, e2;
1341 int index, entry_limit;
1342 target_ulong ptr;
1343
1344 selector &= 0xffff;
1345 if ((selector & 0xfffc) == 0) {
1346 /* XXX: NULL selector case: invalid LDT */
1347 env->ldt.base = 0;
1348 env->ldt.limit = 0;
1349 } else {
1350 if (selector & 0x4) {
1351 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1352 }
1353 dt = &env->gdt;
1354 index = selector & ~7;
1355 #ifdef TARGET_X86_64
1356 if (env->hflags & HF_LMA_MASK) {
1357 entry_limit = 15;
1358 } else
1359 #endif
1360 {
1361 entry_limit = 7;
1362 }
1363 if ((index + entry_limit) > dt->limit) {
1364 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1365 }
1366 ptr = dt->base + index;
1367 e1 = cpu_ldl_kernel(env, ptr);
1368 e2 = cpu_ldl_kernel(env, ptr + 4);
1369 if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) {
1370 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1371 }
1372 if (!(e2 & DESC_P_MASK)) {
1373 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1374 }
1375 #ifdef TARGET_X86_64
1376 if (env->hflags & HF_LMA_MASK) {
1377 uint32_t e3;
1378
1379 e3 = cpu_ldl_kernel(env, ptr + 8);
1380 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1381 env->ldt.base |= (target_ulong)e3 << 32;
1382 } else
1383 #endif
1384 {
1385 load_seg_cache_raw_dt(&env->ldt, e1, e2);
1386 }
1387 }
1388 env->ldt.selector = selector;
1389 }
1390
1391 void helper_ltr(CPUX86State *env, int selector)
1392 {
1393 SegmentCache *dt;
1394 uint32_t e1, e2;
1395 int index, type, entry_limit;
1396 target_ulong ptr;
1397
1398 selector &= 0xffff;
1399 if ((selector & 0xfffc) == 0) {
1400 /* NULL selector case: invalid TR */
1401 env->tr.base = 0;
1402 env->tr.limit = 0;
1403 env->tr.flags = 0;
1404 } else {
1405 if (selector & 0x4) {
1406 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1407 }
1408 dt = &env->gdt;
1409 index = selector & ~7;
1410 #ifdef TARGET_X86_64
1411 if (env->hflags & HF_LMA_MASK) {
1412 entry_limit = 15;
1413 } else
1414 #endif
1415 {
1416 entry_limit = 7;
1417 }
1418 if ((index + entry_limit) > dt->limit) {
1419 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1420 }
1421 ptr = dt->base + index;
1422 e1 = cpu_ldl_kernel(env, ptr);
1423 e2 = cpu_ldl_kernel(env, ptr + 4);
1424 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1425 if ((e2 & DESC_S_MASK) ||
1426 (type != 1 && type != 9)) {
1427 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1428 }
1429 if (!(e2 & DESC_P_MASK)) {
1430 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1431 }
1432 #ifdef TARGET_X86_64
1433 if (env->hflags & HF_LMA_MASK) {
1434 uint32_t e3, e4;
1435
1436 e3 = cpu_ldl_kernel(env, ptr + 8);
1437 e4 = cpu_ldl_kernel(env, ptr + 12);
1438 if ((e4 >> DESC_TYPE_SHIFT) & 0xf) {
1439 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1440 }
1441 load_seg_cache_raw_dt(&env->tr, e1, e2);
1442 env->tr.base |= (target_ulong)e3 << 32;
1443 } else
1444 #endif
1445 {
1446 load_seg_cache_raw_dt(&env->tr, e1, e2);
1447 }
1448 e2 |= DESC_TSS_BUSY_MASK;
1449 cpu_stl_kernel(env, ptr + 4, e2);
1450 }
1451 env->tr.selector = selector;
1452 }
1453
1454 /* only works if protected mode and not VM86. seg_reg must be != R_CS */
1455 void helper_load_seg(CPUX86State *env, int seg_reg, int selector)
1456 {
1457 uint32_t e1, e2;
1458 int cpl, dpl, rpl;
1459 SegmentCache *dt;
1460 int index;
1461 target_ulong ptr;
1462
1463 selector &= 0xffff;
1464 cpl = env->hflags & HF_CPL_MASK;
1465 if ((selector & 0xfffc) == 0) {
1466 /* null selector case */
1467 if (seg_reg == R_SS
1468 #ifdef TARGET_X86_64
1469 && (!(env->hflags & HF_CS64_MASK) || cpl == 3)
1470 #endif
1471 ) {
1472 raise_exception_err(env, EXCP0D_GPF, 0);
1473 }
1474 cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0);
1475 } else {
1476
1477 if (selector & 0x4) {
1478 dt = &env->ldt;
1479 } else {
1480 dt = &env->gdt;
1481 }
1482 index = selector & ~7;
1483 if ((index + 7) > dt->limit) {
1484 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1485 }
1486 ptr = dt->base + index;
1487 e1 = cpu_ldl_kernel(env, ptr);
1488 e2 = cpu_ldl_kernel(env, ptr + 4);
1489
1490 if (!(e2 & DESC_S_MASK)) {
1491 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1492 }
1493 rpl = selector & 3;
1494 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1495 if (seg_reg == R_SS) {
1496 /* must be writable segment */
1497 if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
1498 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1499 }
1500 if (rpl != cpl || dpl != cpl) {
1501 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1502 }
1503 } else {
1504 /* must be readable segment */
1505 if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
1506 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1507 }
1508
1509 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1510 /* if not conforming code, test rights */
1511 if (dpl < cpl || dpl < rpl) {
1512 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1513 }
1514 }
1515 }
1516
1517 if (!(e2 & DESC_P_MASK)) {
1518 if (seg_reg == R_SS) {
1519 raise_exception_err(env, EXCP0C_STACK, selector & 0xfffc);
1520 } else {
1521 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1522 }
1523 }
1524
1525 /* set the access bit if not already set */
1526 if (!(e2 & DESC_A_MASK)) {
1527 e2 |= DESC_A_MASK;
1528 cpu_stl_kernel(env, ptr + 4, e2);
1529 }
1530
1531 cpu_x86_load_seg_cache(env, seg_reg, selector,
1532 get_seg_base(e1, e2),
1533 get_seg_limit(e1, e2),
1534 e2);
1535 #if 0
1536 qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
1537 selector, (unsigned long)sc->base, sc->limit, sc->flags);
1538 #endif
1539 }
1540 }
1541
1542 /* protected mode jump */
1543 void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
1544 int next_eip_addend)
1545 {
1546 int gate_cs, type;
1547 uint32_t e1, e2, cpl, dpl, rpl, limit;
1548 target_ulong next_eip;
1549
1550 if ((new_cs & 0xfffc) == 0) {
1551 raise_exception_err(env, EXCP0D_GPF, 0);
1552 }
1553 if (load_segment(env, &e1, &e2, new_cs) != 0) {
1554 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1555 }
1556 cpl = env->hflags & HF_CPL_MASK;
1557 if (e2 & DESC_S_MASK) {
1558 if (!(e2 & DESC_CS_MASK)) {
1559 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1560 }
1561 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1562 if (e2 & DESC_C_MASK) {
1563 /* conforming code segment */
1564 if (dpl > cpl) {
1565 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1566 }
1567 } else {
1568 /* non conforming code segment */
1569 rpl = new_cs & 3;
1570 if (rpl > cpl) {
1571 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1572 }
1573 if (dpl != cpl) {
1574 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1575 }
1576 }
1577 if (!(e2 & DESC_P_MASK)) {
1578 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1579 }
1580 limit = get_seg_limit(e1, e2);
1581 if (new_eip > limit &&
1582 !(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) {
1583 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1584 }
1585 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1586 get_seg_base(e1, e2), limit, e2);
1587 env->eip = new_eip;
1588 } else {
1589 /* jump to call or task gate */
1590 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1591 rpl = new_cs & 3;
1592 cpl = env->hflags & HF_CPL_MASK;
1593 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
1594 switch (type) {
1595 case 1: /* 286 TSS */
1596 case 9: /* 386 TSS */
1597 case 5: /* task gate */
1598 if (dpl < cpl || dpl < rpl) {
1599 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1600 }
1601 next_eip = env->eip + next_eip_addend;
1602 switch_tss(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip);
1603 CC_OP = CC_OP_EFLAGS;
1604 break;
1605 case 4: /* 286 call gate */
1606 case 12: /* 386 call gate */
1607 if ((dpl < cpl) || (dpl < rpl)) {
1608 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1609 }
1610 if (!(e2 & DESC_P_MASK)) {
1611 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1612 }
1613 gate_cs = e1 >> 16;
1614 new_eip = (e1 & 0xffff);
1615 if (type == 12) {
1616 new_eip |= (e2 & 0xffff0000);
1617 }
1618 if (load_segment(env, &e1, &e2, gate_cs) != 0) {
1619 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1620 }
1621 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1622 /* must be code segment */
1623 if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
1624 (DESC_S_MASK | DESC_CS_MASK))) {
1625 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1626 }
1627 if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
1628 (!(e2 & DESC_C_MASK) && (dpl != cpl))) {
1629 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1630 }
1631 if (!(e2 & DESC_P_MASK)) {
1632 raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
1633 }
1634 limit = get_seg_limit(e1, e2);
1635 if (new_eip > limit) {
1636 raise_exception_err(env, EXCP0D_GPF, 0);
1637 }
1638 cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
1639 get_seg_base(e1, e2), limit, e2);
1640 env->eip = new_eip;
1641 break;
1642 default:
1643 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1644 break;
1645 }
1646 }
1647 }
1648
1649 /* real mode call */
1650 void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1,
1651 int shift, int next_eip)
1652 {
1653 int new_eip;
1654 uint32_t esp, esp_mask;
1655 target_ulong ssp;
1656
1657 new_eip = new_eip1;
1658 esp = env->regs[R_ESP];
1659 esp_mask = get_sp_mask(env->segs[R_SS].flags);
1660 ssp = env->segs[R_SS].base;
1661 if (shift) {
1662 PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector);
1663 PUSHL(ssp, esp, esp_mask, next_eip);
1664 } else {
1665 PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector);
1666 PUSHW(ssp, esp, esp_mask, next_eip);
1667 }
1668
1669 SET_ESP(esp, esp_mask);
1670 env->eip = new_eip;
1671 env->segs[R_CS].selector = new_cs;
1672 env->segs[R_CS].base = (new_cs << 4);
1673 }
1674
1675 /* protected mode call */
1676 void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip,
1677 int shift, int next_eip_addend)
1678 {
1679 int new_stack, i;
1680 uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count;
1681 uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask;
1682 uint32_t val, limit, old_sp_mask;
1683 target_ulong ssp, old_ssp, next_eip;
1684
1685 next_eip = env->eip + next_eip_addend;
1686 LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
1687 LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
1688 if ((new_cs & 0xfffc) == 0) {
1689 raise_exception_err(env, EXCP0D_GPF, 0);
1690 }
1691 if (load_segment(env, &e1, &e2, new_cs) != 0) {
1692 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1693 }
1694 cpl = env->hflags & HF_CPL_MASK;
1695 LOG_PCALL("desc=%08x:%08x\n", e1, e2);
1696 if (e2 & DESC_S_MASK) {
1697 if (!(e2 & DESC_CS_MASK)) {
1698 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1699 }
1700 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1701 if (e2 & DESC_C_MASK) {
1702 /* conforming code segment */
1703 if (dpl > cpl) {
1704 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1705 }
1706 } else {
1707 /* non conforming code segment */
1708 rpl = new_cs & 3;
1709 if (rpl > cpl) {
1710 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1711 }
1712 if (dpl != cpl) {
1713 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1714 }
1715 }
1716 if (!(e2 & DESC_P_MASK)) {
1717 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1718 }
1719
1720 #ifdef TARGET_X86_64
1721 /* XXX: check 16/32 bit cases in long mode */
1722 if (shift == 2) {
1723 target_ulong rsp;
1724
1725 /* 64 bit case */
1726 rsp = env->regs[R_ESP];
1727 PUSHQ(rsp, env->segs[R_CS].selector);
1728 PUSHQ(rsp, next_eip);
1729 /* from this point, not restartable */
1730 env->regs[R_ESP] = rsp;
1731 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1732 get_seg_base(e1, e2),
1733 get_seg_limit(e1, e2), e2);
1734 env->eip = new_eip;
1735 } else
1736 #endif
1737 {
1738 sp = env->regs[R_ESP];
1739 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1740 ssp = env->segs[R_SS].base;
1741 if (shift) {
1742 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1743 PUSHL(ssp, sp, sp_mask, next_eip);
1744 } else {
1745 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1746 PUSHW(ssp, sp, sp_mask, next_eip);
1747 }
1748
1749 limit = get_seg_limit(e1, e2);
1750 if (new_eip > limit) {
1751 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1752 }
1753 /* from this point, not restartable */
1754 SET_ESP(sp, sp_mask);
1755 cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
1756 get_seg_base(e1, e2), limit, e2);
1757 env->eip = new_eip;
1758 }
1759 } else {
1760 /* check gate type */
1761 type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
1762 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1763 rpl = new_cs & 3;
1764 switch (type) {
1765 case 1: /* available 286 TSS */
1766 case 9: /* available 386 TSS */
1767 case 5: /* task gate */
1768 if (dpl < cpl || dpl < rpl) {
1769 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1770 }
1771 switch_tss(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip);
1772 CC_OP = CC_OP_EFLAGS;
1773 return;
1774 case 4: /* 286 call gate */
1775 case 12: /* 386 call gate */
1776 break;
1777 default:
1778 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1779 break;
1780 }
1781 shift = type >> 3;
1782
1783 if (dpl < cpl || dpl < rpl) {
1784 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
1785 }
1786 /* check valid bit */
1787 if (!(e2 & DESC_P_MASK)) {
1788 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
1789 }
1790 selector = e1 >> 16;
1791 offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff);
1792 param_count = e2 & 0x1f;
1793 if ((selector & 0xfffc) == 0) {
1794 raise_exception_err(env, EXCP0D_GPF, 0);
1795 }
1796
1797 if (load_segment(env, &e1, &e2, selector) != 0) {
1798 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1799 }
1800 if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
1801 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1802 }
1803 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1804 if (dpl > cpl) {
1805 raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
1806 }
1807 if (!(e2 & DESC_P_MASK)) {
1808 raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
1809 }
1810
1811 if (!(e2 & DESC_C_MASK) && dpl < cpl) {
1812 /* to inner privilege */
1813 get_ss_esp_from_tss(env, &ss, &sp, dpl);
1814 LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
1815 TARGET_FMT_lx "\n", ss, sp, param_count,
1816 env->regs[R_ESP]);
1817 if ((ss & 0xfffc) == 0) {
1818 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1819 }
1820 if ((ss & 3) != dpl) {
1821 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1822 }
1823 if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) {
1824 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1825 }
1826 ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
1827 if (ss_dpl != dpl) {
1828 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1829 }
1830 if (!(ss_e2 & DESC_S_MASK) ||
1831 (ss_e2 & DESC_CS_MASK) ||
1832 !(ss_e2 & DESC_W_MASK)) {
1833 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1834 }
1835 if (!(ss_e2 & DESC_P_MASK)) {
1836 raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
1837 }
1838
1839 /* push_size = ((param_count * 2) + 8) << shift; */
1840
1841 old_sp_mask = get_sp_mask(env->segs[R_SS].flags);
1842 old_ssp = env->segs[R_SS].base;
1843
1844 sp_mask = get_sp_mask(ss_e2);
1845 ssp = get_seg_base(ss_e1, ss_e2);
1846 if (shift) {
1847 PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector);
1848 PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]);
1849 for (i = param_count - 1; i >= 0; i--) {
1850 val = cpu_ldl_kernel(env, old_ssp +
1851 ((env->regs[R_ESP] + i * 4) &
1852 old_sp_mask));
1853 PUSHL(ssp, sp, sp_mask, val);
1854 }
1855 } else {
1856 PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector);
1857 PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]);
1858 for (i = param_count - 1; i >= 0; i--) {
1859 val = cpu_lduw_kernel(env, old_ssp +
1860 ((env->regs[R_ESP] + i * 2) &
1861 old_sp_mask));
1862 PUSHW(ssp, sp, sp_mask, val);
1863 }
1864 }
1865 new_stack = 1;
1866 } else {
1867 /* to same privilege */
1868 sp = env->regs[R_ESP];
1869 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1870 ssp = env->segs[R_SS].base;
1871 /* push_size = (4 << shift); */
1872 new_stack = 0;
1873 }
1874
1875 if (shift) {
1876 PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector);
1877 PUSHL(ssp, sp, sp_mask, next_eip);
1878 } else {
1879 PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector);
1880 PUSHW(ssp, sp, sp_mask, next_eip);
1881 }
1882
1883 /* from this point, not restartable */
1884
1885 if (new_stack) {
1886 ss = (ss & ~3) | dpl;
1887 cpu_x86_load_seg_cache(env, R_SS, ss,
1888 ssp,
1889 get_seg_limit(ss_e1, ss_e2),
1890 ss_e2);
1891 }
1892
1893 selector = (selector & ~3) | dpl;
1894 cpu_x86_load_seg_cache(env, R_CS, selector,
1895 get_seg_base(e1, e2),
1896 get_seg_limit(e1, e2),
1897 e2);
1898 SET_ESP(sp, sp_mask);
1899 env->eip = offset;
1900 }
1901 }
1902
1903 /* real and vm86 mode iret */
1904 void helper_iret_real(CPUX86State *env, int shift)
1905 {
1906 uint32_t sp, new_cs, new_eip, new_eflags, sp_mask;
1907 target_ulong ssp;
1908 int eflags_mask;
1909
1910 sp_mask = 0xffff; /* XXXX: use SS segment size? */
1911 sp = env->regs[R_ESP];
1912 ssp = env->segs[R_SS].base;
1913 if (shift == 1) {
1914 /* 32 bits */
1915 POPL(ssp, sp, sp_mask, new_eip);
1916 POPL(ssp, sp, sp_mask, new_cs);
1917 new_cs &= 0xffff;
1918 POPL(ssp, sp, sp_mask, new_eflags);
1919 } else {
1920 /* 16 bits */
1921 POPW(ssp, sp, sp_mask, new_eip);
1922 POPW(ssp, sp, sp_mask, new_cs);
1923 POPW(ssp, sp, sp_mask, new_eflags);
1924 }
1925 env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask);
1926 env->segs[R_CS].selector = new_cs;
1927 env->segs[R_CS].base = (new_cs << 4);
1928 env->eip = new_eip;
1929 if (env->eflags & VM_MASK) {
1930 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK |
1931 NT_MASK;
1932 } else {
1933 eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK |
1934 RF_MASK | NT_MASK;
1935 }
1936 if (shift == 0) {
1937 eflags_mask &= 0xffff;
1938 }
1939 cpu_load_eflags(env, new_eflags, eflags_mask);
1940 env->hflags2 &= ~HF2_NMI_MASK;
1941 }
1942
1943 static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl)
1944 {
1945 int dpl;
1946 uint32_t e2;
1947
1948 /* XXX: on x86_64, we do not want to nullify FS and GS because
1949 they may still contain a valid base. I would be interested to
1950 know how a real x86_64 CPU behaves */
1951 if ((seg_reg == R_FS || seg_reg == R_GS) &&
1952 (env->segs[seg_reg].selector & 0xfffc) == 0) {
1953 return;
1954 }
1955
1956 e2 = env->segs[seg_reg].flags;
1957 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
1958 if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
1959 /* data or non conforming code segment */
1960 if (dpl < cpl) {
1961 cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0);
1962 }
1963 }
1964 }
1965
1966 /* protected mode iret */
1967 static inline void helper_ret_protected(CPUX86State *env, int shift,
1968 int is_iret, int addend)
1969 {
1970 uint32_t new_cs, new_eflags, new_ss;
1971 uint32_t new_es, new_ds, new_fs, new_gs;
1972 uint32_t e1, e2, ss_e1, ss_e2;
1973 int cpl, dpl, rpl, eflags_mask, iopl;
1974 target_ulong ssp, sp, new_eip, new_esp, sp_mask;
1975
1976 #ifdef TARGET_X86_64
1977 if (shift == 2) {
1978 sp_mask = -1;
1979 } else
1980 #endif
1981 {
1982 sp_mask = get_sp_mask(env->segs[R_SS].flags);
1983 }
1984 sp = env->regs[R_ESP];
1985 ssp = env->segs[R_SS].base;
1986 new_eflags = 0; /* avoid warning */
1987 #ifdef TARGET_X86_64
1988 if (shift == 2) {
1989 POPQ(sp, new_eip);
1990 POPQ(sp, new_cs);
1991 new_cs &= 0xffff;
1992 if (is_iret) {
1993 POPQ(sp, new_eflags);
1994 }
1995 } else
1996 #endif
1997 {
1998 if (shift == 1) {
1999 /* 32 bits */
2000 POPL(ssp, sp, sp_mask, new_eip);
2001 POPL(ssp, sp, sp_mask, new_cs);
2002 new_cs &= 0xffff;
2003 if (is_iret) {
2004 POPL(ssp, sp, sp_mask, new_eflags);
2005 if (new_eflags & VM_MASK) {
2006 goto return_to_vm86;
2007 }
2008 }
2009 } else {
2010 /* 16 bits */
2011 POPW(ssp, sp, sp_mask, new_eip);
2012 POPW(ssp, sp, sp_mask, new_cs);
2013 if (is_iret) {
2014 POPW(ssp, sp, sp_mask, new_eflags);
2015 }
2016 }
2017 }
2018 LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
2019 new_cs, new_eip, shift, addend);
2020 LOG_PCALL_STATE(CPU(x86_env_get_cpu(env)));
2021 if ((new_cs & 0xfffc) == 0) {
2022 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2023 }
2024 if (load_segment(env, &e1, &e2, new_cs) != 0) {
2025 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2026 }
2027 if (!(e2 & DESC_S_MASK) ||
2028 !(e2 & DESC_CS_MASK)) {
2029 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2030 }
2031 cpl = env->hflags & HF_CPL_MASK;
2032 rpl = new_cs & 3;
2033 if (rpl < cpl) {
2034 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2035 }
2036 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2037 if (e2 & DESC_C_MASK) {
2038 if (dpl > rpl) {
2039 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2040 }
2041 } else {
2042 if (dpl != rpl) {
2043 raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
2044 }
2045 }
2046 if (!(e2 & DESC_P_MASK)) {
2047 raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
2048 }
2049
2050 sp += addend;
2051 if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
2052 ((env->hflags & HF_CS64_MASK) && !is_iret))) {
2053 /* return to same privilege level */
2054 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2055 get_seg_base(e1, e2),
2056 get_seg_limit(e1, e2),
2057 e2);
2058 } else {
2059 /* return to different privilege level */
2060 #ifdef TARGET_X86_64
2061 if (shift == 2) {
2062 POPQ(sp, new_esp);
2063 POPQ(sp, new_ss);
2064 new_ss &= 0xffff;
2065 } else
2066 #endif
2067 {
2068 if (shift == 1) {
2069 /* 32 bits */
2070 POPL(ssp, sp, sp_mask, new_esp);
2071 POPL(ssp, sp, sp_mask, new_ss);
2072 new_ss &= 0xffff;
2073 } else {
2074 /* 16 bits */
2075 POPW(ssp, sp, sp_mask, new_esp);
2076 POPW(ssp, sp, sp_mask, new_ss);
2077 }
2078 }
2079 LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
2080 new_ss, new_esp);
2081 if ((new_ss & 0xfffc) == 0) {
2082 #ifdef TARGET_X86_64
2083 /* NULL ss is allowed in long mode if cpl != 3 */
2084 /* XXX: test CS64? */
2085 if ((env->hflags & HF_LMA_MASK) && rpl != 3) {
2086 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2087 0, 0xffffffff,
2088 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2089 DESC_S_MASK | (rpl << DESC_DPL_SHIFT) |
2090 DESC_W_MASK | DESC_A_MASK);
2091 ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
2092 } else
2093 #endif
2094 {
2095 raise_exception_err(env, EXCP0D_GPF, 0);
2096 }
2097 } else {
2098 if ((new_ss & 3) != rpl) {
2099 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2100 }
2101 if (load_segment(env, &ss_e1, &ss_e2, new_ss) != 0) {
2102 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2103 }
2104 if (!(ss_e2 & DESC_S_MASK) ||
2105 (ss_e2 & DESC_CS_MASK) ||
2106 !(ss_e2 & DESC_W_MASK)) {
2107 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2108 }
2109 dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
2110 if (dpl != rpl) {
2111 raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
2112 }
2113 if (!(ss_e2 & DESC_P_MASK)) {
2114 raise_exception_err(env, EXCP0B_NOSEG, new_ss & 0xfffc);
2115 }
2116 cpu_x86_load_seg_cache(env, R_SS, new_ss,
2117 get_seg_base(ss_e1, ss_e2),
2118 get_seg_limit(ss_e1, ss_e2),
2119 ss_e2);
2120 }
2121
2122 cpu_x86_load_seg_cache(env, R_CS, new_cs,
2123 get_seg_base(e1, e2),
2124 get_seg_limit(e1, e2),
2125 e2);
2126 sp = new_esp;
2127 #ifdef TARGET_X86_64
2128 if (env->hflags & HF_CS64_MASK) {
2129 sp_mask = -1;
2130 } else
2131 #endif
2132 {
2133 sp_mask = get_sp_mask(ss_e2);
2134 }
2135
2136 /* validate data segments */
2137 validate_seg(env, R_ES, rpl);
2138 validate_seg(env, R_DS, rpl);
2139 validate_seg(env, R_FS, rpl);
2140 validate_seg(env, R_GS, rpl);
2141
2142 sp += addend;
2143 }
2144 SET_ESP(sp, sp_mask);
2145 env->eip = new_eip;
2146 if (is_iret) {
2147 /* NOTE: 'cpl' is the _old_ CPL */
2148 eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK;
2149 if (cpl == 0) {
2150 eflags_mask |= IOPL_MASK;
2151 }
2152 iopl = (env->eflags >> IOPL_SHIFT) & 3;
2153 if (cpl <= iopl) {
2154 eflags_mask |= IF_MASK;
2155 }
2156 if (shift == 0) {
2157 eflags_mask &= 0xffff;
2158 }
2159 cpu_load_eflags(env, new_eflags, eflags_mask);
2160 }
2161 return;
2162
2163 return_to_vm86:
2164 POPL(ssp, sp, sp_mask, new_esp);
2165 POPL(ssp, sp, sp_mask, new_ss);
2166 POPL(ssp, sp, sp_mask, new_es);
2167 POPL(ssp, sp, sp_mask, new_ds);
2168 POPL(ssp, sp, sp_mask, new_fs);
2169 POPL(ssp, sp, sp_mask, new_gs);
2170
2171 /* modify processor state */
2172 cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK |
2173 IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK |
2174 VIP_MASK);
2175 load_seg_vm(env, R_CS, new_cs & 0xffff);
2176 load_seg_vm(env, R_SS, new_ss & 0xffff);
2177 load_seg_vm(env, R_ES, new_es & 0xffff);
2178 load_seg_vm(env, R_DS, new_ds & 0xffff);
2179 load_seg_vm(env, R_FS, new_fs & 0xffff);
2180 load_seg_vm(env, R_GS, new_gs & 0xffff);
2181
2182 env->eip = new_eip & 0xffff;
2183 env->regs[R_ESP] = new_esp;
2184 }
2185
2186 void helper_iret_protected(CPUX86State *env, int shift, int next_eip)
2187 {
2188 int tss_selector, type;
2189 uint32_t e1, e2;
2190
2191 /* specific case for TSS */
2192 if (env->eflags & NT_MASK) {
2193 #ifdef TARGET_X86_64
2194 if (env->hflags & HF_LMA_MASK) {
2195 raise_exception_err(env, EXCP0D_GPF, 0);
2196 }
2197 #endif
2198 tss_selector = cpu_lduw_kernel(env, env->tr.base + 0);
2199 if (tss_selector & 4) {
2200 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2201 }
2202 if (load_segment(env, &e1, &e2, tss_selector) != 0) {
2203 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2204 }
2205 type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
2206 /* NOTE: we check both segment and busy TSS */
2207 if (type != 3) {
2208 raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
2209 }
2210 switch_tss(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip);
2211 } else {
2212 helper_ret_protected(env, shift, 1, 0);
2213 }
2214 env->hflags2 &= ~HF2_NMI_MASK;
2215 }
2216
2217 void helper_lret_protected(CPUX86State *env, int shift, int addend)
2218 {
2219 helper_ret_protected(env, shift, 0, addend);
2220 }
2221
2222 void helper_sysenter(CPUX86State *env)
2223 {
2224 if (env->sysenter_cs == 0) {
2225 raise_exception_err(env, EXCP0D_GPF, 0);
2226 }
2227 env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK);
2228
2229 #ifdef TARGET_X86_64
2230 if (env->hflags & HF_LMA_MASK) {
2231 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2232 0, 0xffffffff,
2233 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2234 DESC_S_MASK |
2235 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2236 DESC_L_MASK);
2237 } else
2238 #endif
2239 {
2240 cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
2241 0, 0xffffffff,
2242 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2243 DESC_S_MASK |
2244 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2245 }
2246 cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc,
2247 0, 0xffffffff,
2248 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2249 DESC_S_MASK |
2250 DESC_W_MASK | DESC_A_MASK);
2251 env->regs[R_ESP] = env->sysenter_esp;
2252 env->eip = env->sysenter_eip;
2253 }
2254
2255 void helper_sysexit(CPUX86State *env, int dflag)
2256 {
2257 int cpl;
2258
2259 cpl = env->hflags & HF_CPL_MASK;
2260 if (env->sysenter_cs == 0 || cpl != 0) {
2261 raise_exception_err(env, EXCP0D_GPF, 0);
2262 }
2263 #ifdef TARGET_X86_64
2264 if (dflag == 2) {
2265 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) |
2266 3, 0, 0xffffffff,
2267 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2268 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2269 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
2270 DESC_L_MASK);
2271 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) |
2272 3, 0, 0xffffffff,
2273 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2274 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2275 DESC_W_MASK | DESC_A_MASK);
2276 } else
2277 #endif
2278 {
2279 cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) |
2280 3, 0, 0xffffffff,
2281 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2282 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2283 DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
2284 cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) |
2285 3, 0, 0xffffffff,
2286 DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
2287 DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
2288 DESC_W_MASK | DESC_A_MASK);
2289 }
2290 env->regs[R_ESP] = env->regs[R_ECX];
2291 env->eip = env->regs[R_EDX];
2292 }
2293
2294 target_ulong helper_lsl(CPUX86State *env, target_ulong selector1)
2295 {
2296 unsigned int limit;
2297 uint32_t e1, e2, eflags, selector;
2298 int rpl, dpl, cpl, type;
2299
2300 selector = selector1 & 0xffff;
2301 eflags = cpu_cc_compute_all(env, CC_OP);
2302 if ((selector & 0xfffc) == 0) {
2303 goto fail;
2304 }
2305 if (load_segment(env, &e1, &e2, selector) != 0) {
2306 goto fail;
2307 }
2308 rpl = selector & 3;
2309 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2310 cpl = env->hflags & HF_CPL_MASK;
2311 if (e2 & DESC_S_MASK) {
2312 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2313 /* conforming */
2314 } else {
2315 if (dpl < cpl || dpl < rpl) {
2316 goto fail;
2317 }
2318 }
2319 } else {
2320 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2321 switch (type) {
2322 case 1:
2323 case 2:
2324 case 3:
2325 case 9:
2326 case 11:
2327 break;
2328 default:
2329 goto fail;
2330 }
2331 if (dpl < cpl || dpl < rpl) {
2332 fail:
2333 CC_SRC = eflags & ~CC_Z;
2334 return 0;
2335 }
2336 }
2337 limit = get_seg_limit(e1, e2);
2338 CC_SRC = eflags | CC_Z;
2339 return limit;
2340 }
2341
2342 target_ulong helper_lar(CPUX86State *env, target_ulong selector1)
2343 {
2344 uint32_t e1, e2, eflags, selector;
2345 int rpl, dpl, cpl, type;
2346
2347 selector = selector1 & 0xffff;
2348 eflags = cpu_cc_compute_all(env, CC_OP);
2349 if ((selector & 0xfffc) == 0) {
2350 goto fail;
2351 }
2352 if (load_segment(env, &e1, &e2, selector) != 0) {
2353 goto fail;
2354 }
2355 rpl = selector & 3;
2356 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2357 cpl = env->hflags & HF_CPL_MASK;
2358 if (e2 & DESC_S_MASK) {
2359 if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
2360 /* conforming */
2361 } else {
2362 if (dpl < cpl || dpl < rpl) {
2363 goto fail;
2364 }
2365 }
2366 } else {
2367 type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
2368 switch (type) {
2369 case 1:
2370 case 2:
2371 case 3:
2372 case 4:
2373 case 5:
2374 case 9:
2375 case 11:
2376 case 12:
2377 break;
2378 default:
2379 goto fail;
2380 }
2381 if (dpl < cpl || dpl < rpl) {
2382 fail:
2383 CC_SRC = eflags & ~CC_Z;
2384 return 0;
2385 }
2386 }
2387 CC_SRC = eflags | CC_Z;
2388 return e2 & 0x00f0ff00;
2389 }
2390
2391 void helper_verr(CPUX86State *env, target_ulong selector1)
2392 {
2393 uint32_t e1, e2, eflags, selector;
2394 int rpl, dpl, cpl;
2395
2396 selector = selector1 & 0xffff;
2397 eflags = cpu_cc_compute_all(env, CC_OP);
2398 if ((selector & 0xfffc) == 0) {
2399 goto fail;
2400 }
2401 if (load_segment(env, &e1, &e2, selector) != 0) {
2402 goto fail;
2403 }
2404 if (!(e2 & DESC_S_MASK)) {
2405 goto fail;
2406 }
2407 rpl = selector & 3;
2408 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2409 cpl = env->hflags & HF_CPL_MASK;
2410 if (e2 & DESC_CS_MASK) {
2411 if (!(e2 & DESC_R_MASK)) {
2412 goto fail;
2413 }
2414 if (!(e2 & DESC_C_MASK)) {
2415 if (dpl < cpl || dpl < rpl) {
2416 goto fail;
2417 }
2418 }
2419 } else {
2420 if (dpl < cpl || dpl < rpl) {
2421 fail:
2422 CC_SRC = eflags & ~CC_Z;
2423 return;
2424 }
2425 }
2426 CC_SRC = eflags | CC_Z;
2427 }
2428
2429 void helper_verw(CPUX86State *env, target_ulong selector1)
2430 {
2431 uint32_t e1, e2, eflags, selector;
2432 int rpl, dpl, cpl;
2433
2434 selector = selector1 & 0xffff;
2435 eflags = cpu_cc_compute_all(env, CC_OP);
2436 if ((selector & 0xfffc) == 0) {
2437 goto fail;
2438 }
2439 if (load_segment(env, &e1, &e2, selector) != 0) {
2440 goto fail;
2441 }
2442 if (!(e2 & DESC_S_MASK)) {
2443 goto fail;
2444 }
2445 rpl = selector & 3;
2446 dpl = (e2 >> DESC_DPL_SHIFT) & 3;
2447 cpl = env->hflags & HF_CPL_MASK;
2448 if (e2 & DESC_CS_MASK) {
2449 goto fail;
2450 } else {
2451 if (dpl < cpl || dpl < rpl) {
2452 goto fail;
2453 }
2454 if (!(e2 & DESC_W_MASK)) {
2455 fail:
2456 CC_SRC = eflags & ~CC_Z;
2457 return;
2458 }
2459 }
2460 CC_SRC = eflags | CC_Z;
2461 }
2462
2463 #if defined(CONFIG_USER_ONLY)
2464 void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector)
2465 {
2466 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
2467 selector &= 0xffff;
2468 cpu_x86_load_seg_cache(env, seg_reg, selector,
2469 (selector << 4), 0xffff, 0);
2470 } else {
2471 helper_load_seg(env, seg_reg, selector);
2472 }
2473 }
2474 #endif
QEmu