hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "hw/hw.h"
  22 #include "hw/i386/pc.h"
  23 #include "hw/isa/apm.h"
  24 #include "hw/i2c/pm_smbus.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/acpi/acpi.h"
  27 #include "sysemu/sysemu.h"
  28 #include "qemu/range.h"
  29 #include "exec/ioport.h"
  30 #include "hw/nvram/fw_cfg.h"
  31 #include "exec/address-spaces.h"
  32 #include "hw/acpi/piix4.h"
  33 #include "hw/acpi/pcihp.h"
  34 #include "hw/acpi/cpu_hotplug.h"
  35 #include "hw/hotplug.h"
  36
  37 //#define DEBUG
  38
  39 #ifdef DEBUG
  40 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  41 #else
  42 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  43 #endif
  44
  45 #define GPE_BASE 0xafe0
  46 #define GPE_LEN 4
  47
  48 struct pci_status {
  49     uint32_t up; /* deprecated, maintained for migration compatibility */
  50     uint32_t down;
  51 };
  52
  53 typedef struct PIIX4PMState {
  54     /*< private >*/
  55     PCIDevice parent_obj;
  56     /*< public >*/
  57
  58     MemoryRegion io;
  59     uint32_t io_base;
  60
  61     MemoryRegion io_gpe;
  62     ACPIREGS ar;
  63
  64     APMState apm;
  65
  66     PMSMBus smb;
  67     uint32_t smb_io_base;
  68
  69     qemu_irq irq;
  70     qemu_irq smi_irq;
  71     int kvm_enabled;
  72     Notifier machine_ready;
  73     Notifier powerdown_notifier;
  74
  75     AcpiPciHpState acpi_pci_hotplug;
  76     bool use_acpi_pci_hotplug;
  77
  78     uint8_t disable_s3;
  79     uint8_t disable_s4;
  80     uint8_t s4_val;
  81
  82     AcpiCpuHotplug gpe_cpu;
  83     Notifier cpu_added_notifier;
  84 } PIIX4PMState;
  85
  86 #define TYPE_PIIX4_PM "PIIX4_PM"
  87
  88 #define PIIX4_PM(obj) \
  89     OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
  90
  91 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
  92                                            PCIBus *bus, PIIX4PMState *s);
  93
  94 #define ACPI_ENABLE 0xf1
  95 #define ACPI_DISABLE 0xf0
  96
  97 static void pm_tmr_timer(ACPIREGS *ar)
  98 {
  99     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 100     acpi_update_sci(&s->ar, s->irq);
 101 }
 102
 103 static void apm_ctrl_changed(uint32_t val, void *arg)
 104 {
 105     PIIX4PMState *s = arg;
 106     PCIDevice *d = PCI_DEVICE(s);
 107
 108     /* ACPI specs 3.0, 4.7.2.5 */
 109     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 110
 111     if (d->config[0x5b] & (1 << 1)) {
 112         if (s->smi_irq) {
 113             qemu_irq_raise(s->smi_irq);
 114         }
 115     }
 116 }
 117
 118 static void pm_io_space_update(PIIX4PMState *s)
 119 {
 120     PCIDevice *d = PCI_DEVICE(s);
 121
 122     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 123     s->io_base &= 0xffc0;
 124
 125     memory_region_transaction_begin();
 126     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 127     memory_region_set_address(&s->io, s->io_base);
 128     memory_region_transaction_commit();
 129 }
 130
 131 static void smbus_io_space_update(PIIX4PMState *s)
 132 {
 133     PCIDevice *d = PCI_DEVICE(s);
 134
 135     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 136     s->smb_io_base &= 0xffc0;
 137
 138     memory_region_transaction_begin();
 139     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 140     memory_region_set_address(&s->smb.io, s->smb_io_base);
 141     memory_region_transaction_commit();
 142 }
 143
 144 static void pm_write_config(PCIDevice *d,
 145                             uint32_t address, uint32_t val, int len)
 146 {
 147     pci_default_write_config(d, address, val, len);
 148     if (range_covers_byte(address, len, 0x80) ||
 149         ranges_overlap(address, len, 0x40, 4)) {
 150         pm_io_space_update((PIIX4PMState *)d);
 151     }
 152     if (range_covers_byte(address, len, 0xd2) ||
 153         ranges_overlap(address, len, 0x90, 4)) {
 154         smbus_io_space_update((PIIX4PMState *)d);
 155     }
 156 }
 157
 158 static int vmstate_acpi_post_load(void *opaque, int version_id)
 159 {
 160     PIIX4PMState *s = opaque;
 161
 162     pm_io_space_update(s);
 163     return 0;
 164 }
 165
 166 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 167  {                                                                   \
 168      .name       = (stringify(_field)),                              \
 169      .version_id = 0,                                                \
 170      .info       = &vmstate_info_uint16,                             \
 171      .size       = sizeof(uint16_t),                                 \
 172      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 173      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 174  }
 175
 176 static const VMStateDescription vmstate_gpe = {
 177     .name = "gpe",
 178     .version_id = 1,
 179     .minimum_version_id = 1,
 180     .fields = (VMStateField[]) {
 181         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 182         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 183         VMSTATE_END_OF_LIST()
 184     }
 185 };
 186
 187 static const VMStateDescription vmstate_pci_status = {
 188     .name = "pci_status",
 189     .version_id = 1,
 190     .minimum_version_id = 1,
 191     .fields = (VMStateField[]) {
 192         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 193         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 194         VMSTATE_END_OF_LIST()
 195     }
 196 };
 197
 198 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 199 {
 200     PIIX4PMState *s = opaque;
 201     int ret, i;
 202     uint16_t temp;
 203
 204     ret = pci_device_load(PCI_DEVICE(s), f);
 205     if (ret < 0) {
 206         return ret;
 207     }
 208     qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 209     qemu_get_be16s(f, &s->ar.pm1.evt.en);
 210     qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 211
 212     ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
 213     if (ret) {
 214         return ret;
 215     }
 216
 217     timer_get(f, s->ar.tmr.timer);
 218     qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 219
 220     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 221     for (i = 0; i < 3; i++) {
 222         qemu_get_be16s(f, &temp);
 223     }
 224
 225     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 226     for (i = 0; i < 3; i++) {
 227         qemu_get_be16s(f, &temp);
 228     }
 229
 230     ret = vmstate_load_state(f, &vmstate_pci_status,
 231         &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
 232     return ret;
 233 }
 234
 235 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 236 {
 237     PIIX4PMState *s = opaque;
 238     return s->use_acpi_pci_hotplug;
 239 }
 240
 241 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
 242 {
 243     PIIX4PMState *s = opaque;
 244     return !s->use_acpi_pci_hotplug;
 245 }
 246
 247 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 248  * To support incoming qemu-kvm 1.2 migration, change version_id
 249  * and minimum_version_id to 2 below (which breaks migration from
 250  * qemu 1.2).
 251  *
 252  */
 253 static const VMStateDescription vmstate_acpi = {
 254     .name = "piix4_pm",
 255     .version_id = 3,
 256     .minimum_version_id = 3,
 257     .minimum_version_id_old = 1,
 258     .load_state_old = acpi_load_old,
 259     .post_load = vmstate_acpi_post_load,
 260     .fields = (VMStateField[]) {
 261         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 262         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 263         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 264         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 265         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 266         VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
 267         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 268         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 269         VMSTATE_STRUCT_TEST(
 270             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 271             PIIX4PMState,
 272             vmstate_test_no_use_acpi_pci_hotplug,
 273             2, vmstate_pci_status,
 274             struct AcpiPciHpPciStatus),
 275         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 276                             vmstate_test_use_acpi_pci_hotplug),
 277         VMSTATE_END_OF_LIST()
 278     }
 279 };
 280
 281 static void piix4_reset(void *opaque)
 282 {
 283     PIIX4PMState *s = opaque;
 284     PCIDevice *d = PCI_DEVICE(s);
 285     uint8_t *pci_conf = d->config;
 286
 287     pci_conf[0x58] = 0;
 288     pci_conf[0x59] = 0;
 289     pci_conf[0x5a] = 0;
 290     pci_conf[0x5b] = 0;
 291
 292     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 293     pci_conf[0x80] = 0;
 294
 295     if (s->kvm_enabled) {
 296         /* Mark SMM as already inited (until KVM supports SMM). */
 297         pci_conf[0x5B] = 0x02;
 298     }
 299     pm_io_space_update(s);
 300     acpi_pcihp_reset(&s->acpi_pci_hotplug);
 301 }
 302
 303 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 304 {
 305     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 306
 307     assert(s != NULL);
 308     acpi_pm1_evt_power_down(&s->ar);
 309 }
 310
 311 static void piix4_pci_device_plug_cb(HotplugHandler *hotplug_dev,
 312                                      DeviceState *dev, Error **errp)
 313 {
 314     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 315     acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, errp);
 316 }
 317
 318 static void piix4_pci_device_unplug_cb(HotplugHandler *hotplug_dev,
 319                                        DeviceState *dev, Error **errp)
 320 {
 321     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 322     acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
 323                                 errp);
 324 }
 325
 326 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
 327 {
 328     PIIX4PMState *s = opaque;
 329
 330     qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort);
 331 }
 332
 333 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 334 {
 335     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 336     PCIDevice *d = PCI_DEVICE(s);
 337     MemoryRegion *io_as = pci_address_space_io(d);
 338     uint8_t *pci_conf;
 339
 340     pci_conf = d->config;
 341     pci_conf[0x5f] = 0x10 |
 342         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 343     pci_conf[0x63] = 0x60;
 344     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 345         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 346
 347     if (s->use_acpi_pci_hotplug) {
 348         pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
 349     } else {
 350         piix4_update_bus_hotplug(d->bus, s);
 351     }
 352 }
 353
 354 static void piix4_pm_add_propeties(PIIX4PMState *s)
 355 {
 356     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 357     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 358     static const uint32_t gpe0_blk = GPE_BASE;
 359     static const uint32_t gpe0_blk_len = GPE_LEN;
 360     static const uint16_t sci_int = 9;
 361
 362     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 363                                   &acpi_enable_cmd, NULL);
 364     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 365                                   &acpi_disable_cmd, NULL);
 366     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 367                                   &gpe0_blk, NULL);
 368     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 369                                   &gpe0_blk_len, NULL);
 370     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 371                                   &sci_int, NULL);
 372     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 373                                   &s->io_base, NULL);
 374 }
 375
 376 static int piix4_pm_initfn(PCIDevice *dev)
 377 {
 378     PIIX4PMState *s = PIIX4_PM(dev);
 379     uint8_t *pci_conf;
 380
 381     pci_conf = dev->config;
 382     pci_conf[0x06] = 0x80;
 383     pci_conf[0x07] = 0x02;
 384     pci_conf[0x09] = 0x00;
 385     pci_conf[0x3d] = 0x01; // interrupt pin 1
 386
 387     /* APM */
 388     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 389
 390     if (s->kvm_enabled) {
 391         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 392          * support SMM mode. */
 393         pci_conf[0x5B] = 0x02;
 394     }
 395
 396     /* XXX: which specification is used ? The i82731AB has different
 397        mappings */
 398     pci_conf[0x90] = s->smb_io_base | 1;
 399     pci_conf[0x91] = s->smb_io_base >> 8;
 400     pci_conf[0xd2] = 0x09;
 401     pm_smbus_init(DEVICE(dev), &s->smb);
 402     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 403     memory_region_add_subregion(pci_address_space_io(dev),
 404                                 s->smb_io_base, &s->smb.io);
 405
 406     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 407     memory_region_set_enabled(&s->io, false);
 408     memory_region_add_subregion(pci_address_space_io(dev),
 409                                 0, &s->io);
 410
 411     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 412     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 413     acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val);
 414     acpi_gpe_init(&s->ar, GPE_LEN);
 415
 416     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 417     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 418
 419     s->machine_ready.notify = piix4_pm_machine_ready;
 420     qemu_add_machine_init_done_notifier(&s->machine_ready);
 421     qemu_register_reset(piix4_reset, s);
 422
 423     piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
 424
 425     piix4_pm_add_propeties(s);
 426     return 0;
 427 }
 428
 429 Object *piix4_pm_find(void)
 430 {
 431     bool ambig;
 432     Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
 433
 434     if (ambig || !o) {
 435         return NULL;
 436     }
 437     return o;
 438 }
 439
 440 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 441                       qemu_irq sci_irq, qemu_irq smi_irq,
 442                       int kvm_enabled, FWCfgState *fw_cfg)
 443 {
 444     DeviceState *dev;
 445     PIIX4PMState *s;
 446
 447     dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
 448     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 449
 450     s = PIIX4_PM(dev);
 451     s->irq = sci_irq;
 452     s->smi_irq = smi_irq;
 453     s->kvm_enabled = kvm_enabled;
 454
 455     qdev_init_nofail(dev);
 456
 457     if (fw_cfg) {
 458         uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
 459         suspend[3] = 1 | ((!s->disable_s3) << 7);
 460         suspend[4] = s->s4_val | ((!s->disable_s4) << 7);
 461
 462         fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
 463     }
 464
 465     return s->smb.smbus;
 466 }
 467
 468 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 469 {
 470     PIIX4PMState *s = opaque;
 471     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 472
 473     PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
 474     return val;
 475 }
 476
 477 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 478                        unsigned width)
 479 {
 480     PIIX4PMState *s = opaque;
 481
 482     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 483     acpi_update_sci(&s->ar, s->irq);
 484
 485     PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
 486 }
 487
 488 static const MemoryRegionOps piix4_gpe_ops = {
 489     .read = gpe_readb,
 490     .write = gpe_writeb,
 491     .valid.min_access_size = 1,
 492     .valid.max_access_size = 4,
 493     .impl.min_access_size = 1,
 494     .impl.max_access_size = 1,
 495     .endianness = DEVICE_LITTLE_ENDIAN,
 496 };
 497
 498 static void piix4_cpu_added_req(Notifier *n, void *opaque)
 499 {
 500     PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier);
 501
 502     assert(s != NULL);
 503     AcpiCpuHotplug_add(&s->ar.gpe, &s->gpe_cpu, CPU(opaque));
 504     acpi_update_sci(&s->ar, s->irq);
 505 }
 506
 507 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 508                                            PCIBus *bus, PIIX4PMState *s)
 509 {
 510     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 511                           "acpi-gpe0", GPE_LEN);
 512     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 513
 514     acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent,
 515                     s->use_acpi_pci_hotplug);
 516
 517     AcpiCpuHotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 518                         PIIX4_CPU_HOTPLUG_IO_BASE);
 519     s->cpu_added_notifier.notify = piix4_cpu_added_req;
 520     qemu_register_cpu_added_notifier(&s->cpu_added_notifier);
 521 }
 522
 523 static Property piix4_pm_properties[] = {
 524     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 525     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 526     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 527     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 528     DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 529                      use_acpi_pci_hotplug, true),
 530     DEFINE_PROP_END_OF_LIST(),
 531 };
 532
 533 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 534 {
 535     DeviceClass *dc = DEVICE_CLASS(klass);
 536     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 537     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 538
 539     k->init = piix4_pm_initfn;
 540     k->config_write = pm_write_config;
 541     k->vendor_id = PCI_VENDOR_ID_INTEL;
 542     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 543     k->revision = 0x03;
 544     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 545     dc->desc = "PM";
 546     dc->vmsd = &vmstate_acpi;
 547     dc->props = piix4_pm_properties;
 548     /*
 549      * Reason: part of PIIX4 southbridge, needs to be wired up,
 550      * e.g. by mips_malta_init()
 551      */
 552     dc->cannot_instantiate_with_device_add_yet = true;
 553     dc->hotpluggable = false;
 554     hc->plug = piix4_pci_device_plug_cb;
 555     hc->unplug = piix4_pci_device_unplug_cb;
 556 }
 557
 558 static const TypeInfo piix4_pm_info = {
 559     .name          = TYPE_PIIX4_PM,
 560     .parent        = TYPE_PCI_DEVICE,
 561     .instance_size = sizeof(PIIX4PMState),
 562     .class_init    = piix4_pm_class_init,
 563     .interfaces = (InterfaceInfo[]) {
 564         { TYPE_HOTPLUG_HANDLER },
 565         { }
 566     }
 567 };
 568
 569 static void piix4_pm_register_types(void)
 570 {
 571     type_register_static(&piix4_pm_info);
 572 }
 573
 574 type_init(piix4_pm_register_types)