4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2009, 2010, 2011
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on piix.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu/osdep.h"
34 #include "qapi/error.h"
35 #include "qapi/visitor.h"
36 #include "qemu/range.h"
37 #include "hw/dma/i8257.h"
38 #include "hw/isa/isa.h"
39 #include "migration/vmstate.h"
41 #include "hw/isa/apm.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci/pci_bridge.h"
44 #include "hw/i386/ich9.h"
45 #include "hw/acpi/acpi.h"
46 #include "hw/acpi/ich9.h"
47 #include "hw/pci/pci_bus.h"
48 #include "hw/qdev-properties.h"
49 #include "sysemu/runstate.h"
50 #include "sysemu/sysemu.h"
51 #include "hw/core/cpu.h"
52 #include "hw/nvram/fw_cfg.h"
53 #include "qemu/cutils.h"
54 #include "hw/acpi/acpi_aml_interface.h"
57 /*****************************************************************************/
58 /* ICH9 LPC PCI to ISA bridge */
60 static void ich9_lpc_reset(DeviceState
*qdev
);
62 /* chipset configuration register
63 * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
65 * Although it's not pci configuration space, it's little endian as Intel.
68 static void ich9_cc_update_ir(uint8_t irr
[PCI_NUM_PINS
], uint16_t ir
)
71 for (intx
= 0; intx
< PCI_NUM_PINS
; intx
++) {
72 irr
[intx
] = (ir
>> (intx
* ICH9_CC_DIR_SHIFT
)) & ICH9_CC_DIR_MASK
;
76 static void ich9_cc_update(ICH9LPCState
*lpc
)
81 const int reg_offsets
[] = {
92 /* D{25 - 31}IR, but D30IR is read only to 0. */
93 for (slot
= 25, offset
= reg_offsets
; slot
< 32; slot
++, offset
++) {
97 ich9_cc_update_ir(lpc
->irr
[slot
],
98 pci_get_word(lpc
->chip_config
+ *offset
));
102 * D30: DMI2PCI bridge
103 * It is arbitrarily decided how INTx lines of PCI devices behind
104 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
105 * INT[A-D] are connected to PIRQ[E-H]
107 for (pci_intx
= 0; pci_intx
< PCI_NUM_PINS
; pci_intx
++) {
108 lpc
->irr
[30][pci_intx
] = pci_intx
+ 4;
112 static void ich9_cc_init(ICH9LPCState
*lpc
)
117 /* the default irq routing is arbitrary as long as it matches with
118 * acpi irq routing table.
119 * The one that is incompatible with piix_pci(= bochs) one is
120 * intentionally chosen to let the users know that the different
123 * int[A-D] -> pirq[E-F]
124 * avoid pirq A-D because they are used for pci express port
126 for (slot
= 0; slot
< PCI_SLOT_MAX
; slot
++) {
127 for (intx
= 0; intx
< PCI_NUM_PINS
; intx
++) {
128 lpc
->irr
[slot
][intx
] = (slot
+ intx
) % 4 + 4;
134 static void ich9_cc_reset(ICH9LPCState
*lpc
)
136 uint8_t *c
= lpc
->chip_config
;
138 memset(lpc
->chip_config
, 0, sizeof(lpc
->chip_config
));
140 pci_set_long(c
+ ICH9_CC_D31IR
, ICH9_CC_DIR_DEFAULT
);
141 pci_set_long(c
+ ICH9_CC_D30IR
, ICH9_CC_D30IR_DEFAULT
);
142 pci_set_long(c
+ ICH9_CC_D29IR
, ICH9_CC_DIR_DEFAULT
);
143 pci_set_long(c
+ ICH9_CC_D28IR
, ICH9_CC_DIR_DEFAULT
);
144 pci_set_long(c
+ ICH9_CC_D27IR
, ICH9_CC_DIR_DEFAULT
);
145 pci_set_long(c
+ ICH9_CC_D26IR
, ICH9_CC_DIR_DEFAULT
);
146 pci_set_long(c
+ ICH9_CC_D25IR
, ICH9_CC_DIR_DEFAULT
);
147 pci_set_long(c
+ ICH9_CC_GCS
, ICH9_CC_GCS_DEFAULT
);
152 static void ich9_cc_addr_len(uint64_t *addr
, unsigned *len
)
154 *addr
&= ICH9_CC_ADDR_MASK
;
155 if (*addr
+ *len
>= ICH9_CC_SIZE
) {
156 *len
= ICH9_CC_SIZE
- *addr
;
160 /* val: little endian */
161 static void ich9_cc_write(void *opaque
, hwaddr addr
,
162 uint64_t val
, unsigned len
)
164 ICH9LPCState
*lpc
= (ICH9LPCState
*)opaque
;
166 trace_ich9_cc_write(addr
, val
, len
);
167 ich9_cc_addr_len(&addr
, &len
);
168 memcpy(lpc
->chip_config
+ addr
, &val
, len
);
169 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc
->d
));
173 /* return value: little endian */
174 static uint64_t ich9_cc_read(void *opaque
, hwaddr addr
,
177 ICH9LPCState
*lpc
= (ICH9LPCState
*)opaque
;
180 ich9_cc_addr_len(&addr
, &len
);
181 memcpy(&val
, lpc
->chip_config
+ addr
, len
);
182 trace_ich9_cc_read(addr
, val
, len
);
188 static void ich9_lpc_rout(uint8_t pirq_rout
, int *pic_irq
, int *pic_dis
)
190 *pic_irq
= pirq_rout
& ICH9_LPC_PIRQ_ROUT_MASK
;
191 *pic_dis
= pirq_rout
& ICH9_LPC_PIRQ_ROUT_IRQEN
;
194 static void ich9_lpc_pic_irq(ICH9LPCState
*lpc
, int pirq_num
,
195 int *pic_irq
, int *pic_dis
)
198 case 0 ... 3: /* A-D */
199 ich9_lpc_rout(lpc
->d
.config
[ICH9_LPC_PIRQA_ROUT
+ pirq_num
],
202 case 4 ... 7: /* E-H */
203 ich9_lpc_rout(lpc
->d
.config
[ICH9_LPC_PIRQE_ROUT
+ (pirq_num
- 4)],
212 /* gsi: i8259+ioapic irq 0-15, otherwise assert */
213 static void ich9_lpc_update_pic(ICH9LPCState
*lpc
, int gsi
)
217 assert(gsi
< ICH9_LPC_PIC_NUM_PINS
);
219 /* The pic level is the logical OR of all the PCI irqs mapped to it */
221 for (i
= 0; i
< ICH9_LPC_NB_PIRQS
; i
++) {
224 ich9_lpc_pic_irq(lpc
, i
, &tmp_irq
, &tmp_dis
);
225 if (!tmp_dis
&& tmp_irq
== gsi
) {
226 pic_level
|= pci_bus_get_irq_level(pci_get_bus(&lpc
->d
), i
);
229 if (gsi
== lpc
->sci_gsi
) {
230 pic_level
|= lpc
->sci_level
;
233 qemu_set_irq(lpc
->gsi
[gsi
], pic_level
);
236 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
237 static int ich9_pirq_to_gsi(int pirq
)
239 return pirq
+ ICH9_LPC_PIC_NUM_PINS
;
242 static int ich9_gsi_to_pirq(int gsi
)
244 return gsi
- ICH9_LPC_PIC_NUM_PINS
;
247 /* gsi: ioapic irq 16-23, otherwise assert */
248 static void ich9_lpc_update_apic(ICH9LPCState
*lpc
, int gsi
)
252 assert(gsi
>= ICH9_LPC_PIC_NUM_PINS
);
254 level
|= pci_bus_get_irq_level(pci_get_bus(&lpc
->d
), ich9_gsi_to_pirq(gsi
));
255 if (gsi
== lpc
->sci_gsi
) {
256 level
|= lpc
->sci_level
;
259 qemu_set_irq(lpc
->gsi
[gsi
], level
);
262 void ich9_lpc_set_irq(void *opaque
, int pirq
, int level
)
264 ICH9LPCState
*lpc
= opaque
;
265 int pic_irq
, pic_dis
;
268 assert(pirq
< ICH9_LPC_NB_PIRQS
);
270 ich9_lpc_update_apic(lpc
, ich9_pirq_to_gsi(pirq
));
271 ich9_lpc_pic_irq(lpc
, pirq
, &pic_irq
, &pic_dis
);
272 ich9_lpc_update_pic(lpc
, pic_irq
);
275 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to
276 * a given device irq pin.
278 int ich9_lpc_map_irq(PCIDevice
*pci_dev
, int intx
)
280 BusState
*bus
= qdev_get_parent_bus(&pci_dev
->qdev
);
281 PCIBus
*pci_bus
= PCI_BUS(bus
);
282 PCIDevice
*lpc_pdev
=
283 pci_bus
->devices
[PCI_DEVFN(ICH9_LPC_DEV
, ICH9_LPC_FUNC
)];
284 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(lpc_pdev
);
286 return lpc
->irr
[PCI_SLOT(pci_dev
->devfn
)][intx
];
289 PCIINTxRoute
ich9_route_intx_pin_to_irq(void *opaque
, int pirq_pin
)
291 ICH9LPCState
*lpc
= opaque
;
296 assert(0 <= pirq_pin
);
297 assert(pirq_pin
< ICH9_LPC_NB_PIRQS
);
299 route
.mode
= PCI_INTX_ENABLED
;
300 ich9_lpc_pic_irq(lpc
, pirq_pin
, &pic_irq
, &pic_dis
);
302 if (pic_irq
< ICH9_LPC_PIC_NUM_PINS
) {
305 route
.mode
= PCI_INTX_DISABLED
;
309 route
.irq
= ich9_pirq_to_gsi(pirq_pin
);
315 void ich9_generate_smi(void)
317 cpu_interrupt(first_cpu
, CPU_INTERRUPT_SMI
);
320 /* Returns -1 on error, IRQ number on success */
321 static int ich9_lpc_sci_irq(ICH9LPCState
*lpc
)
323 uint8_t sel
= lpc
->d
.config
[ICH9_LPC_ACPI_CTRL
] &
324 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK
;
326 case ICH9_LPC_ACPI_CTRL_9
:
328 case ICH9_LPC_ACPI_CTRL_10
:
330 case ICH9_LPC_ACPI_CTRL_11
:
332 case ICH9_LPC_ACPI_CTRL_20
:
334 case ICH9_LPC_ACPI_CTRL_21
:
338 qemu_log_mask(LOG_GUEST_ERROR
,
339 "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel
);
345 static void ich9_set_sci(void *opaque
, int irq_num
, int level
)
347 ICH9LPCState
*lpc
= opaque
;
350 assert(irq_num
== 0);
352 if (level
== lpc
->sci_level
) {
355 lpc
->sci_level
= level
;
362 if (irq
>= ICH9_LPC_PIC_NUM_PINS
) {
363 ich9_lpc_update_apic(lpc
, irq
);
365 ich9_lpc_update_pic(lpc
, irq
);
369 static void smi_features_ok_callback(void *opaque
)
371 ICH9LPCState
*lpc
= opaque
;
372 uint64_t guest_features
;
373 uint64_t guest_cpu_hotplug_features
;
375 if (lpc
->smi_features_ok
) {
376 /* negotiation already complete, features locked */
380 memcpy(&guest_features
, lpc
->smi_guest_features_le
, sizeof guest_features
);
381 le64_to_cpus(&guest_features
);
382 if (guest_features
& ~lpc
->smi_host_features
) {
383 /* guest requests invalid features, leave @features_ok at zero */
387 guest_cpu_hotplug_features
= guest_features
&
388 (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT
) |
389 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT
));
390 if (!(guest_features
& BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT
)) &&
391 guest_cpu_hotplug_features
) {
393 * cpu hot-[un]plug with SMI requires SMI broadcast,
394 * leave @features_ok at zero
399 if (guest_cpu_hotplug_features
==
400 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT
)) {
401 /* cpu hot-unplug is unsupported without cpu-hotplug */
405 /* valid feature subset requested, lock it down, report success */
406 lpc
->smi_negotiated_features
= guest_features
;
407 lpc
->smi_features_ok
= 1;
410 void ich9_lpc_pm_init(PCIDevice
*lpc_pci
, bool smm_enabled
)
412 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(lpc_pci
);
414 FWCfgState
*fw_cfg
= fw_cfg_find();
416 sci_irq
= qemu_allocate_irq(ich9_set_sci
, lpc
, 0);
417 ich9_pm_init(lpc_pci
, &lpc
->pm
, smm_enabled
, sci_irq
);
419 if (lpc
->smi_host_features
&& fw_cfg
) {
420 uint64_t host_features_le
;
422 host_features_le
= cpu_to_le64(lpc
->smi_host_features
);
423 memcpy(lpc
->smi_host_features_le
, &host_features_le
,
424 sizeof host_features_le
);
425 fw_cfg_add_file(fw_cfg
, "etc/smi/supported-features",
426 lpc
->smi_host_features_le
,
427 sizeof lpc
->smi_host_features_le
);
429 /* The other two guest-visible fields are cleared on device reset, we
430 * just link them into fw_cfg here.
432 fw_cfg_add_file_callback(fw_cfg
, "etc/smi/requested-features",
434 lpc
->smi_guest_features_le
,
435 sizeof lpc
->smi_guest_features_le
,
437 fw_cfg_add_file_callback(fw_cfg
, "etc/smi/features-ok",
438 smi_features_ok_callback
, NULL
, lpc
,
439 &lpc
->smi_features_ok
,
440 sizeof lpc
->smi_features_ok
,
444 ich9_lpc_reset(DEVICE(lpc
));
449 static void ich9_apm_ctrl_changed(uint32_t val
, void *arg
)
451 ICH9LPCState
*lpc
= arg
;
453 /* ACPI specs 3.0, 4.7.2.5 */
454 acpi_pm1_cnt_update(&lpc
->pm
.acpi_regs
,
455 val
== ICH9_APM_ACPI_ENABLE
,
456 val
== ICH9_APM_ACPI_DISABLE
);
457 if (val
== ICH9_APM_ACPI_ENABLE
|| val
== ICH9_APM_ACPI_DISABLE
) {
461 /* SMI_EN = PMBASE + 30. SMI control and enable register */
462 if (lpc
->pm
.smi_en
& ICH9_PMIO_SMI_EN_APMC_EN
) {
463 if (lpc
->smi_negotiated_features
&
464 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT
)) {
467 cpu_interrupt(cs
, CPU_INTERRUPT_SMI
);
470 cpu_interrupt(current_cpu
, CPU_INTERRUPT_SMI
);
477 ich9_lpc_pmbase_sci_update(ICH9LPCState
*lpc
)
479 uint32_t pm_io_base
= pci_get_long(lpc
->d
.config
+ ICH9_LPC_PMBASE
);
480 uint8_t acpi_cntl
= pci_get_long(lpc
->d
.config
+ ICH9_LPC_ACPI_CTRL
);
483 if (acpi_cntl
& ICH9_LPC_ACPI_CTRL_ACPI_EN
) {
484 pm_io_base
&= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK
;
489 ich9_pm_iospace_update(&lpc
->pm
, pm_io_base
);
491 new_gsi
= ich9_lpc_sci_irq(lpc
);
495 if (lpc
->sci_level
&& new_gsi
!= lpc
->sci_gsi
) {
496 qemu_set_irq(lpc
->pm
.irq
, 0);
497 lpc
->sci_gsi
= new_gsi
;
498 qemu_set_irq(lpc
->pm
.irq
, 1);
500 lpc
->sci_gsi
= new_gsi
;
504 static void ich9_lpc_rcba_update(ICH9LPCState
*lpc
, uint32_t rcba_old
)
506 uint32_t rcba
= pci_get_long(lpc
->d
.config
+ ICH9_LPC_RCBA
);
508 if (rcba_old
& ICH9_LPC_RCBA_EN
) {
509 memory_region_del_subregion(get_system_memory(), &lpc
->rcrb_mem
);
511 if (rcba
& ICH9_LPC_RCBA_EN
) {
512 memory_region_add_subregion_overlap(get_system_memory(),
513 rcba
& ICH9_LPC_RCBA_BA_MASK
,
518 /* config:GEN_PMCON* */
520 ich9_lpc_pmcon_update(ICH9LPCState
*lpc
)
522 uint16_t gen_pmcon_1
= pci_get_word(lpc
->d
.config
+ ICH9_LPC_GEN_PMCON_1
);
525 if (gen_pmcon_1
& ICH9_LPC_GEN_PMCON_1_SMI_LOCK
) {
526 wmask
= pci_get_word(lpc
->d
.wmask
+ ICH9_LPC_GEN_PMCON_1
);
527 wmask
&= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK
;
528 pci_set_word(lpc
->d
.wmask
+ ICH9_LPC_GEN_PMCON_1
, wmask
);
529 lpc
->pm
.smi_en_wmask
&= ~1;
533 static int ich9_lpc_post_load(void *opaque
, int version_id
)
535 ICH9LPCState
*lpc
= opaque
;
537 ich9_lpc_pmbase_sci_update(lpc
);
538 ich9_lpc_rcba_update(lpc
, 0 /* disabled ICH9_LPC_RCBA_EN */);
539 ich9_lpc_pmcon_update(lpc
);
543 static void ich9_lpc_config_write(PCIDevice
*d
,
544 uint32_t addr
, uint32_t val
, int len
)
546 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(d
);
547 uint32_t rcba_old
= pci_get_long(d
->config
+ ICH9_LPC_RCBA
);
549 pci_default_write_config(d
, addr
, val
, len
);
550 if (ranges_overlap(addr
, len
, ICH9_LPC_PMBASE
, 4) ||
551 ranges_overlap(addr
, len
, ICH9_LPC_ACPI_CTRL
, 1)) {
552 ich9_lpc_pmbase_sci_update(lpc
);
554 if (ranges_overlap(addr
, len
, ICH9_LPC_RCBA
, 4)) {
555 ich9_lpc_rcba_update(lpc
, rcba_old
);
557 if (ranges_overlap(addr
, len
, ICH9_LPC_PIRQA_ROUT
, 4)) {
558 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc
->d
));
560 if (ranges_overlap(addr
, len
, ICH9_LPC_PIRQE_ROUT
, 4)) {
561 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc
->d
));
563 if (ranges_overlap(addr
, len
, ICH9_LPC_GEN_PMCON_1
, 8)) {
564 ich9_lpc_pmcon_update(lpc
);
568 static void ich9_lpc_reset(DeviceState
*qdev
)
570 PCIDevice
*d
= PCI_DEVICE(qdev
);
571 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(d
);
572 uint32_t rcba_old
= pci_get_long(d
->config
+ ICH9_LPC_RCBA
);
575 for (i
= 0; i
< 4; i
++) {
576 pci_set_byte(d
->config
+ ICH9_LPC_PIRQA_ROUT
+ i
,
577 ICH9_LPC_PIRQ_ROUT_DEFAULT
);
579 for (i
= 0; i
< 4; i
++) {
580 pci_set_byte(d
->config
+ ICH9_LPC_PIRQE_ROUT
+ i
,
581 ICH9_LPC_PIRQ_ROUT_DEFAULT
);
583 pci_set_byte(d
->config
+ ICH9_LPC_ACPI_CTRL
, ICH9_LPC_ACPI_CTRL_DEFAULT
);
585 pci_set_long(d
->config
+ ICH9_LPC_PMBASE
, ICH9_LPC_PMBASE_DEFAULT
);
586 pci_set_long(d
->config
+ ICH9_LPC_RCBA
, ICH9_LPC_RCBA_DEFAULT
);
590 ich9_lpc_pmbase_sci_update(lpc
);
591 ich9_lpc_rcba_update(lpc
, rcba_old
);
596 memset(lpc
->smi_guest_features_le
, 0, sizeof lpc
->smi_guest_features_le
);
597 lpc
->smi_features_ok
= 0;
598 lpc
->smi_negotiated_features
= 0;
601 /* root complex register block is mapped into memory space */
602 static const MemoryRegionOps rcrb_mmio_ops
= {
603 .read
= ich9_cc_read
,
604 .write
= ich9_cc_write
,
605 .endianness
= DEVICE_LITTLE_ENDIAN
,
608 static void ich9_lpc_machine_ready(Notifier
*n
, void *opaque
)
610 ICH9LPCState
*s
= container_of(n
, ICH9LPCState
, machine_ready
);
611 MemoryRegion
*io_as
= pci_address_space_io(&s
->d
);
614 pci_conf
= s
->d
.config
;
615 if (memory_region_present(io_as
, 0x3f8)) {
617 pci_conf
[0x82] |= 0x01;
619 if (memory_region_present(io_as
, 0x2f8)) {
621 pci_conf
[0x82] |= 0x02;
623 if (memory_region_present(io_as
, 0x378)) {
625 pci_conf
[0x82] |= 0x04;
627 if (memory_region_present(io_as
, 0x3f2)) {
629 pci_conf
[0x82] |= 0x08;
634 static void ich9_rst_cnt_write(void *opaque
, hwaddr addr
, uint64_t val
,
637 ICH9LPCState
*lpc
= opaque
;
640 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
643 lpc
->rst_cnt
= val
& 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
646 static uint64_t ich9_rst_cnt_read(void *opaque
, hwaddr addr
, unsigned len
)
648 ICH9LPCState
*lpc
= opaque
;
653 static const MemoryRegionOps ich9_rst_cnt_ops
= {
654 .read
= ich9_rst_cnt_read
,
655 .write
= ich9_rst_cnt_write
,
656 .endianness
= DEVICE_LITTLE_ENDIAN
659 static void ich9_lpc_initfn(Object
*obj
)
661 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(obj
);
663 static const uint8_t acpi_enable_cmd
= ICH9_APM_ACPI_ENABLE
;
664 static const uint8_t acpi_disable_cmd
= ICH9_APM_ACPI_DISABLE
;
666 object_property_add_uint8_ptr(obj
, ACPI_PM_PROP_SCI_INT
,
667 &lpc
->sci_gsi
, OBJ_PROP_FLAG_READ
);
668 object_property_add_uint8_ptr(OBJECT(lpc
), ACPI_PM_PROP_ACPI_ENABLE_CMD
,
669 &acpi_enable_cmd
, OBJ_PROP_FLAG_READ
);
670 object_property_add_uint8_ptr(OBJECT(lpc
), ACPI_PM_PROP_ACPI_DISABLE_CMD
,
671 &acpi_disable_cmd
, OBJ_PROP_FLAG_READ
);
672 object_property_add_uint64_ptr(obj
, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP
,
673 &lpc
->smi_negotiated_features
,
676 ich9_pm_add_properties(obj
, &lpc
->pm
);
679 static void ich9_lpc_realize(PCIDevice
*d
, Error
**errp
)
681 ICH9LPCState
*lpc
= ICH9_LPC_DEVICE(d
);
682 DeviceState
*dev
= DEVICE(d
);
685 if ((lpc
->smi_host_features
& BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT
)) &&
686 !(lpc
->smi_host_features
& BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT
))) {
688 * smi_features_ok_callback() throws an error on this.
690 * So bail out here instead of advertizing the invalid
691 * configuration and get obscure firmware failures from that.
693 error_setg(errp
, "cpu hot-unplug requires cpu hot-plug");
697 isa_bus
= isa_bus_new(DEVICE(d
), get_system_memory(), get_system_io(),
703 pci_set_long(d
->wmask
+ ICH9_LPC_PMBASE
,
704 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK
);
705 pci_set_byte(d
->wmask
+ ICH9_LPC_PMBASE
,
706 ICH9_LPC_ACPI_CTRL_ACPI_EN
|
707 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK
);
709 memory_region_init_io(&lpc
->rcrb_mem
, OBJECT(d
), &rcrb_mmio_ops
, lpc
,
710 "lpc-rcrb-mmio", ICH9_CC_SIZE
);
712 lpc
->isa_bus
= isa_bus
;
715 apm_init(d
, &lpc
->apm
, ich9_apm_ctrl_changed
, lpc
);
717 lpc
->machine_ready
.notify
= ich9_lpc_machine_ready
;
718 qemu_add_machine_init_done_notifier(&lpc
->machine_ready
);
720 memory_region_init_io(&lpc
->rst_cnt_mem
, OBJECT(d
), &ich9_rst_cnt_ops
, lpc
,
721 "lpc-reset-control", 1);
722 memory_region_add_subregion_overlap(pci_address_space_io(d
),
723 ICH9_RST_CNT_IOPORT
, &lpc
->rst_cnt_mem
,
726 qdev_init_gpio_out_named(dev
, lpc
->gsi
, ICH9_GPIO_GSI
, GSI_NUM_PINS
);
728 isa_bus_irqs(isa_bus
, lpc
->gsi
);
730 i8257_dma_init(isa_bus
, 0);
733 static bool ich9_rst_cnt_needed(void *opaque
)
735 ICH9LPCState
*lpc
= opaque
;
737 return (lpc
->rst_cnt
!= 0);
740 static const VMStateDescription vmstate_ich9_rst_cnt
= {
741 .name
= "ICH9LPC/rst_cnt",
743 .minimum_version_id
= 1,
744 .needed
= ich9_rst_cnt_needed
,
745 .fields
= (VMStateField
[]) {
746 VMSTATE_UINT8(rst_cnt
, ICH9LPCState
),
747 VMSTATE_END_OF_LIST()
751 static bool ich9_smi_feat_needed(void *opaque
)
753 ICH9LPCState
*lpc
= opaque
;
755 return !buffer_is_zero(lpc
->smi_guest_features_le
,
756 sizeof lpc
->smi_guest_features_le
) ||
757 lpc
->smi_features_ok
;
760 static const VMStateDescription vmstate_ich9_smi_feat
= {
761 .name
= "ICH9LPC/smi_feat",
763 .minimum_version_id
= 1,
764 .needed
= ich9_smi_feat_needed
,
765 .fields
= (VMStateField
[]) {
766 VMSTATE_UINT8_ARRAY(smi_guest_features_le
, ICH9LPCState
,
768 VMSTATE_UINT8(smi_features_ok
, ICH9LPCState
),
769 VMSTATE_UINT64(smi_negotiated_features
, ICH9LPCState
),
770 VMSTATE_END_OF_LIST()
774 static const VMStateDescription vmstate_ich9_lpc
= {
777 .minimum_version_id
= 1,
778 .post_load
= ich9_lpc_post_load
,
779 .fields
= (VMStateField
[]) {
780 VMSTATE_PCI_DEVICE(d
, ICH9LPCState
),
781 VMSTATE_STRUCT(apm
, ICH9LPCState
, 0, vmstate_apm
, APMState
),
782 VMSTATE_STRUCT(pm
, ICH9LPCState
, 0, vmstate_ich9_pm
, ICH9LPCPMRegs
),
783 VMSTATE_UINT8_ARRAY(chip_config
, ICH9LPCState
, ICH9_CC_SIZE
),
784 VMSTATE_UINT32(sci_level
, ICH9LPCState
),
785 VMSTATE_END_OF_LIST()
787 .subsections
= (const VMStateDescription
*[]) {
788 &vmstate_ich9_rst_cnt
,
789 &vmstate_ich9_smi_feat
,
794 static Property ich9_lpc_properties
[] = {
795 DEFINE_PROP_BOOL("noreboot", ICH9LPCState
, pin_strap
.spkr_hi
, false),
796 DEFINE_PROP_BOOL("smm-compat", ICH9LPCState
, pm
.smm_compat
, false),
797 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState
, smi_host_features
,
798 ICH9_LPC_SMI_F_BROADCAST_BIT
, true),
799 DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState
, smi_host_features
,
800 ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT
, true),
801 DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState
, smi_host_features
,
802 ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT
, true),
803 DEFINE_PROP_END_OF_LIST(),
806 static void ich9_send_gpe(AcpiDeviceIf
*adev
, AcpiEventStatusBits ev
)
808 ICH9LPCState
*s
= ICH9_LPC_DEVICE(adev
);
810 acpi_send_gpe_event(&s
->pm
.acpi_regs
, s
->pm
.irq
, ev
);
813 static void build_ich9_isa_aml(AcpiDevAmlIf
*adev
, Aml
*scope
)
817 ICH9LPCState
*s
= ICH9_LPC_DEVICE(adev
);
818 BusState
*bus
= BUS(s
->isa_bus
);
819 Aml
*sb_scope
= aml_scope("\\_SB");
821 /* ICH9 PCI to ISA irq remapping */
822 aml_append(scope
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
823 aml_int(0x60), 0x0C));
824 /* Fields declarion has to happen *after* operation region */
825 field
= aml_field("PCI0.SF8.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
826 aml_append(field
, aml_named_field("PRQA", 8));
827 aml_append(field
, aml_named_field("PRQB", 8));
828 aml_append(field
, aml_named_field("PRQC", 8));
829 aml_append(field
, aml_named_field("PRQD", 8));
830 aml_append(field
, aml_reserved_field(0x20));
831 aml_append(field
, aml_named_field("PRQE", 8));
832 aml_append(field
, aml_named_field("PRQF", 8));
833 aml_append(field
, aml_named_field("PRQG", 8));
834 aml_append(field
, aml_named_field("PRQH", 8));
835 aml_append(sb_scope
, field
);
836 aml_append(scope
, sb_scope
);
838 QTAILQ_FOREACH(kid
, &bus
->children
, sibling
) {
839 call_dev_aml_func(DEVICE(kid
->child
), scope
);
843 static void ich9_lpc_class_init(ObjectClass
*klass
, void *data
)
845 DeviceClass
*dc
= DEVICE_CLASS(klass
);
846 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
847 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(klass
);
848 AcpiDeviceIfClass
*adevc
= ACPI_DEVICE_IF_CLASS(klass
);
849 AcpiDevAmlIfClass
*amldevc
= ACPI_DEV_AML_IF_CLASS(klass
);
851 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
852 dc
->reset
= ich9_lpc_reset
;
853 k
->realize
= ich9_lpc_realize
;
854 dc
->vmsd
= &vmstate_ich9_lpc
;
855 device_class_set_props(dc
, ich9_lpc_properties
);
856 k
->config_write
= ich9_lpc_config_write
;
857 dc
->desc
= "ICH9 LPC bridge";
858 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
859 k
->device_id
= PCI_DEVICE_ID_INTEL_ICH9_8
;
860 k
->revision
= ICH9_A2_LPC_REVISION
;
861 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
863 * Reason: part of ICH9 southbridge, needs to be wired up by
866 dc
->user_creatable
= false;
867 hc
->pre_plug
= ich9_pm_device_pre_plug_cb
;
868 hc
->plug
= ich9_pm_device_plug_cb
;
869 hc
->unplug_request
= ich9_pm_device_unplug_request_cb
;
870 hc
->unplug
= ich9_pm_device_unplug_cb
;
871 adevc
->ospm_status
= ich9_pm_ospm_status
;
872 adevc
->send_event
= ich9_send_gpe
;
873 adevc
->madt_cpu
= pc_madt_cpu_entry
;
874 amldevc
->build_dev_aml
= build_ich9_isa_aml
;
877 static const TypeInfo ich9_lpc_info
= {
878 .name
= TYPE_ICH9_LPC_DEVICE
,
879 .parent
= TYPE_PCI_DEVICE
,
880 .instance_size
= sizeof(ICH9LPCState
),
881 .instance_init
= ich9_lpc_initfn
,
882 .class_init
= ich9_lpc_class_init
,
883 .interfaces
= (InterfaceInfo
[]) {
884 { TYPE_HOTPLUG_HANDLER
},
885 { TYPE_ACPI_DEVICE_IF
},
886 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
887 { TYPE_ACPI_DEV_AML_IF
},
892 static void ich9_lpc_register(void)
894 type_register_static(&ich9_lpc_info
);
897 type_init(ich9_lpc_register
);