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PCI: Bus number from the bridge, not the device
[qemu.git] / hw / pxa2xx.c
blob6e046450dfd2794d474e10ae8fdcc944cd92dfa2
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licenced under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "ssi.h"
16 #include "qemu-timer.h"
17 #include "qemu-char.h"
18 #include "blockdev.h"
19
20 static struct {
21 target_phys_addr_t io_base;
22 int irqn;
23 } pxa255_serial[] = {
24 { 0x40100000, PXA2XX_PIC_FFUART },
25 { 0x40200000, PXA2XX_PIC_BTUART },
26 { 0x40700000, PXA2XX_PIC_STUART },
27 { 0x41600000, PXA25X_PIC_HWUART },
28 { 0, 0 }
29 }, pxa270_serial[] = {
30 { 0x40100000, PXA2XX_PIC_FFUART },
31 { 0x40200000, PXA2XX_PIC_BTUART },
32 { 0x40700000, PXA2XX_PIC_STUART },
33 { 0, 0 }
34 };
35
36 typedef struct PXASSPDef {
37 target_phys_addr_t io_base;
38 int irqn;
39 } PXASSPDef;
40
41 #if 0
42 static PXASSPDef pxa250_ssp[] = {
43 { 0x41000000, PXA2XX_PIC_SSP },
44 { 0, 0 }
45 };
46 #endif
47
48 static PXASSPDef pxa255_ssp[] = {
49 { 0x41000000, PXA2XX_PIC_SSP },
50 { 0x41400000, PXA25X_PIC_NSSP },
51 { 0, 0 }
52 };
53
54 #if 0
55 static PXASSPDef pxa26x_ssp[] = {
56 { 0x41000000, PXA2XX_PIC_SSP },
57 { 0x41400000, PXA25X_PIC_NSSP },
58 { 0x41500000, PXA26X_PIC_ASSP },
59 { 0, 0 }
60 };
61 #endif
62
63 static PXASSPDef pxa27x_ssp[] = {
64 { 0x41000000, PXA2XX_PIC_SSP },
65 { 0x41700000, PXA27X_PIC_SSP2 },
66 { 0x41900000, PXA2XX_PIC_SSP3 },
67 { 0, 0 }
68 };
69
70 #define PMCR 0x00 /* Power Manager Control register */
71 #define PSSR 0x04 /* Power Manager Sleep Status register */
72 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
73 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
74 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
75 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
76 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
77 #define PCFR 0x1c /* Power Manager General Configuration register */
78 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
79 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
80 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
81 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
82 #define RCSR 0x30 /* Reset Controller Status register */
83 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
84 #define PTSR 0x38 /* Power Manager Standby Configuration register */
85 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
86 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
87 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
88 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
89 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
90 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
91
92 static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
93 {
94 PXA2xxState *s = (PXA2xxState *) opaque;
95
96 switch (addr) {
97 case PMCR ... PCMD31:
98 if (addr & 3)
99 goto fail;
100
101 return s->pm_regs[addr >> 2];
102 default:
103 fail:
104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
105 break;
106 }
107 return 0;
108 }
109
110 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
111 uint32_t value)
112 {
113 PXA2xxState *s = (PXA2xxState *) opaque;
114
115 switch (addr) {
116 case PMCR:
117 s->pm_regs[addr >> 2] &= 0x15 & ~(value & 0x2a);
118 s->pm_regs[addr >> 2] |= value & 0x15;
119 break;
120
121 case PSSR: /* Read-clean registers */
122 case RCSR:
123 case PKSR:
124 s->pm_regs[addr >> 2] &= ~value;
125 break;
126
127 default: /* Read-write registers */
128 if (!(addr & 3)) {
129 s->pm_regs[addr >> 2] = value;
130 break;
131 }
132
133 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
134 break;
135 }
136 }
137
138 static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = {
139 pxa2xx_pm_read,
140 pxa2xx_pm_read,
141 pxa2xx_pm_read,
142 };
143
144 static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = {
145 pxa2xx_pm_write,
146 pxa2xx_pm_write,
147 pxa2xx_pm_write,
148 };
149
150 static void pxa2xx_pm_save(QEMUFile *f, void *opaque)
151 {
152 PXA2xxState *s = (PXA2xxState *) opaque;
153 int i;
154
155 for (i = 0; i < 0x40; i ++)
156 qemu_put_be32s(f, &s->pm_regs[i]);
157 }
158
159 static int pxa2xx_pm_load(QEMUFile *f, void *opaque, int version_id)
160 {
161 PXA2xxState *s = (PXA2xxState *) opaque;
162 int i;
163
164 for (i = 0; i < 0x40; i ++)
165 qemu_get_be32s(f, &s->pm_regs[i]);
166
167 return 0;
168 }
169
170 #define CCCR 0x00 /* Core Clock Configuration register */
171 #define CKEN 0x04 /* Clock Enable register */
172 #define OSCC 0x08 /* Oscillator Configuration register */
173 #define CCSR 0x0c /* Core Clock Status register */
174
175 static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
176 {
177 PXA2xxState *s = (PXA2xxState *) opaque;
178
179 switch (addr) {
180 case CCCR:
181 case CKEN:
182 case OSCC:
183 return s->cm_regs[addr >> 2];
184
185 case CCSR:
186 return s->cm_regs[CCCR >> 2] | (3 << 28);
187
188 default:
189 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
190 break;
191 }
192 return 0;
193 }
194
195 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
196 uint32_t value)
197 {
198 PXA2xxState *s = (PXA2xxState *) opaque;
199
200 switch (addr) {
201 case CCCR:
202 case CKEN:
203 s->cm_regs[addr >> 2] = value;
204 break;
205
206 case OSCC:
207 s->cm_regs[addr >> 2] &= ~0x6c;
208 s->cm_regs[addr >> 2] |= value & 0x6e;
209 if ((value >> 1) & 1) /* OON */
210 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
211 break;
212
213 default:
214 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
215 break;
216 }
217 }
218
219 static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = {
220 pxa2xx_cm_read,
221 pxa2xx_cm_read,
222 pxa2xx_cm_read,
223 };
224
225 static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = {
226 pxa2xx_cm_write,
227 pxa2xx_cm_write,
228 pxa2xx_cm_write,
229 };
230
231 static void pxa2xx_cm_save(QEMUFile *f, void *opaque)
232 {
233 PXA2xxState *s = (PXA2xxState *) opaque;
234 int i;
235
236 for (i = 0; i < 4; i ++)
237 qemu_put_be32s(f, &s->cm_regs[i]);
238 qemu_put_be32s(f, &s->clkcfg);
239 qemu_put_be32s(f, &s->pmnc);
240 }
241
242 static int pxa2xx_cm_load(QEMUFile *f, void *opaque, int version_id)
243 {
244 PXA2xxState *s = (PXA2xxState *) opaque;
245 int i;
246
247 for (i = 0; i < 4; i ++)
248 qemu_get_be32s(f, &s->cm_regs[i]);
249 qemu_get_be32s(f, &s->clkcfg);
250 qemu_get_be32s(f, &s->pmnc);
251
252 return 0;
253 }
254
255 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
256 {
257 PXA2xxState *s = (PXA2xxState *) opaque;
258
259 switch (reg) {
260 case 6: /* Clock Configuration register */
261 return s->clkcfg;
262
263 case 7: /* Power Mode register */
264 return 0;
265
266 default:
267 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
268 break;
269 }
270 return 0;
271 }
272
273 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
274 uint32_t value)
275 {
276 PXA2xxState *s = (PXA2xxState *) opaque;
277 static const char *pwrmode[8] = {
278 "Normal", "Idle", "Deep-idle", "Standby",
279 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
280 };
281
282 switch (reg) {
283 case 6: /* Clock Configuration register */
284 s->clkcfg = value & 0xf;
285 if (value & 2)
286 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
287 break;
288
289 case 7: /* Power Mode register */
290 if (value & 8)
291 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
292 switch (value & 7) {
293 case 0:
294 /* Do nothing */
295 break;
296
297 case 1:
298 /* Idle */
299 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
300 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
301 break;
302 }
303 /* Fall through. */
304
305 case 2:
306 /* Deep-Idle */
307 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
308 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
309 goto message;
310
311 case 3:
312 s->env->uncached_cpsr =
313 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
314 s->env->cp15.c1_sys = 0;
315 s->env->cp15.c1_coproc = 0;
316 s->env->cp15.c2_base0 = 0;
317 s->env->cp15.c3 = 0;
318 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
319 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
320
321 /*
322 * The scratch-pad register is almost universally used
323 * for storing the return address on suspend. For the
324 * lack of a resuming bootloader, perform a jump
325 * directly to that address.
326 */
327 memset(s->env->regs, 0, 4 * 15);
328 s->env->regs[15] = s->pm_regs[PSPR >> 2];
329
330 #if 0
331 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
332 cpu_physical_memory_write(0, &buffer, 4);
333 buffer = s->pm_regs[PSPR >> 2];
334 cpu_physical_memory_write(8, &buffer, 4);
335 #endif
336
337 /* Suspend */
338 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
339
340 goto message;
341
342 default:
343 message:
344 printf("%s: machine entered %s mode\n", __FUNCTION__,
345 pwrmode[value & 7]);
346 }
347 break;
348
349 default:
350 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
351 break;
352 }
353 }
354
355 /* Performace Monitoring Registers */
356 #define CPPMNC 0 /* Performance Monitor Control register */
357 #define CPCCNT 1 /* Clock Counter register */
358 #define CPINTEN 4 /* Interrupt Enable register */
359 #define CPFLAG 5 /* Overflow Flag register */
360 #define CPEVTSEL 8 /* Event Selection register */
361
362 #define CPPMN0 0 /* Performance Count register 0 */
363 #define CPPMN1 1 /* Performance Count register 1 */
364 #define CPPMN2 2 /* Performance Count register 2 */
365 #define CPPMN3 3 /* Performance Count register 3 */
366
367 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
368 {
369 PXA2xxState *s = (PXA2xxState *) opaque;
370
371 switch (reg) {
372 case CPPMNC:
373 return s->pmnc;
374 case CPCCNT:
375 if (s->pmnc & 1)
376 return qemu_get_clock(vm_clock);
377 else
378 return 0;
379 case CPINTEN:
380 case CPFLAG:
381 case CPEVTSEL:
382 return 0;
383
384 default:
385 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
386 break;
387 }
388 return 0;
389 }
390
391 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
392 uint32_t value)
393 {
394 PXA2xxState *s = (PXA2xxState *) opaque;
395
396 switch (reg) {
397 case CPPMNC:
398 s->pmnc = value;
399 break;
400
401 case CPCCNT:
402 case CPINTEN:
403 case CPFLAG:
404 case CPEVTSEL:
405 break;
406
407 default:
408 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
409 break;
410 }
411 }
412
413 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
414 {
415 switch (crm) {
416 case 0:
417 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
418 case 1:
419 return pxa2xx_perf_read(opaque, op2, reg, crm);
420 case 2:
421 switch (reg) {
422 case CPPMN0:
423 case CPPMN1:
424 case CPPMN2:
425 case CPPMN3:
426 return 0;
427 }
428 /* Fall through */
429 default:
430 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
431 break;
432 }
433 return 0;
434 }
435
436 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
437 uint32_t value)
438 {
439 switch (crm) {
440 case 0:
441 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
442 break;
443 case 1:
444 pxa2xx_perf_write(opaque, op2, reg, crm, value);
445 break;
446 case 2:
447 switch (reg) {
448 case CPPMN0:
449 case CPPMN1:
450 case CPPMN2:
451 case CPPMN3:
452 return;
453 }
454 /* Fall through */
455 default:
456 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
457 break;
458 }
459 }
460
461 #define MDCNFG 0x00 /* SDRAM Configuration register */
462 #define MDREFR 0x04 /* SDRAM Refresh Control register */
463 #define MSC0 0x08 /* Static Memory Control register 0 */
464 #define MSC1 0x0c /* Static Memory Control register 1 */
465 #define MSC2 0x10 /* Static Memory Control register 2 */
466 #define MECR 0x14 /* Expansion Memory Bus Config register */
467 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
468 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
469 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
470 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
471 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
472 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
473 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
474 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
475 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
476 #define ARB_CNTL 0x48 /* Arbiter Control register */
477 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
478 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
479 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
480 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
481 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
482 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
483 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
484
485 static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
486 {
487 PXA2xxState *s = (PXA2xxState *) opaque;
488
489 switch (addr) {
490 case MDCNFG ... SA1110:
491 if ((addr & 3) == 0)
492 return s->mm_regs[addr >> 2];
493
494 default:
495 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
496 break;
497 }
498 return 0;
499 }
500
501 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
502 uint32_t value)
503 {
504 PXA2xxState *s = (PXA2xxState *) opaque;
505
506 switch (addr) {
507 case MDCNFG ... SA1110:
508 if ((addr & 3) == 0) {
509 s->mm_regs[addr >> 2] = value;
510 break;
511 }
512
513 default:
514 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
515 break;
516 }
517 }
518
519 static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = {
520 pxa2xx_mm_read,
521 pxa2xx_mm_read,
522 pxa2xx_mm_read,
523 };
524
525 static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = {
526 pxa2xx_mm_write,
527 pxa2xx_mm_write,
528 pxa2xx_mm_write,
529 };
530
531 static void pxa2xx_mm_save(QEMUFile *f, void *opaque)
532 {
533 PXA2xxState *s = (PXA2xxState *) opaque;
534 int i;
535
536 for (i = 0; i < 0x1a; i ++)
537 qemu_put_be32s(f, &s->mm_regs[i]);
538 }
539
540 static int pxa2xx_mm_load(QEMUFile *f, void *opaque, int version_id)
541 {
542 PXA2xxState *s = (PXA2xxState *) opaque;
543 int i;
544
545 for (i = 0; i < 0x1a; i ++)
546 qemu_get_be32s(f, &s->mm_regs[i]);
547
548 return 0;
549 }
550
551 /* Synchronous Serial Ports */
552 typedef struct {
553 SysBusDevice busdev;
554 qemu_irq irq;
555 int enable;
556 SSIBus *bus;
557
558 uint32_t sscr[2];
559 uint32_t sspsp;
560 uint32_t ssto;
561 uint32_t ssitr;
562 uint32_t sssr;
563 uint8_t sstsa;
564 uint8_t ssrsa;
565 uint8_t ssacd;
566
567 uint32_t rx_fifo[16];
568 int rx_level;
569 int rx_start;
570 } PXA2xxSSPState;
571
572 #define SSCR0 0x00 /* SSP Control register 0 */
573 #define SSCR1 0x04 /* SSP Control register 1 */
574 #define SSSR 0x08 /* SSP Status register */
575 #define SSITR 0x0c /* SSP Interrupt Test register */
576 #define SSDR 0x10 /* SSP Data register */
577 #define SSTO 0x28 /* SSP Time-Out register */
578 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
579 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
580 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
581 #define SSTSS 0x38 /* SSP Time Slot Status register */
582 #define SSACD 0x3c /* SSP Audio Clock Divider register */
583
584 /* Bitfields for above registers */
585 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
586 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
587 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
588 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
589 #define SSCR0_SSE (1 << 7)
590 #define SSCR0_RIM (1 << 22)
591 #define SSCR0_TIM (1 << 23)
592 #define SSCR0_MOD (1 << 31)
593 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
594 #define SSCR1_RIE (1 << 0)
595 #define SSCR1_TIE (1 << 1)
596 #define SSCR1_LBM (1 << 2)
597 #define SSCR1_MWDS (1 << 5)
598 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
599 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
600 #define SSCR1_EFWR (1 << 14)
601 #define SSCR1_PINTE (1 << 18)
602 #define SSCR1_TINTE (1 << 19)
603 #define SSCR1_RSRE (1 << 20)
604 #define SSCR1_TSRE (1 << 21)
605 #define SSCR1_EBCEI (1 << 29)
606 #define SSITR_INT (7 << 5)
607 #define SSSR_TNF (1 << 2)
608 #define SSSR_RNE (1 << 3)
609 #define SSSR_TFS (1 << 5)
610 #define SSSR_RFS (1 << 6)
611 #define SSSR_ROR (1 << 7)
612 #define SSSR_PINT (1 << 18)
613 #define SSSR_TINT (1 << 19)
614 #define SSSR_EOC (1 << 20)
615 #define SSSR_TUR (1 << 21)
616 #define SSSR_BCE (1 << 23)
617 #define SSSR_RW 0x00bc0080
618
619 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
620 {
621 int level = 0;
622
623 level |= s->ssitr & SSITR_INT;
624 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
625 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
626 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
627 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
628 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
629 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
630 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
631 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
632 qemu_set_irq(s->irq, !!level);
633 }
634
635 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
636 {
637 s->sssr &= ~(0xf << 12); /* Clear RFL */
638 s->sssr &= ~(0xf << 8); /* Clear TFL */
639 s->sssr &= ~SSSR_TFS;
640 s->sssr &= ~SSSR_TNF;
641 if (s->enable) {
642 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
643 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
644 s->sssr |= SSSR_RFS;
645 else
646 s->sssr &= ~SSSR_RFS;
647 if (s->rx_level)
648 s->sssr |= SSSR_RNE;
649 else
650 s->sssr &= ~SSSR_RNE;
651 /* TX FIFO is never filled, so it is always in underrun
652 condition if SSP is enabled */
653 s->sssr |= SSSR_TFS;
654 s->sssr |= SSSR_TNF;
655 }
656
657 pxa2xx_ssp_int_update(s);
658 }
659
660 static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr)
661 {
662 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
663 uint32_t retval;
664
665 switch (addr) {
666 case SSCR0:
667 return s->sscr[0];
668 case SSCR1:
669 return s->sscr[1];
670 case SSPSP:
671 return s->sspsp;
672 case SSTO:
673 return s->ssto;
674 case SSITR:
675 return s->ssitr;
676 case SSSR:
677 return s->sssr | s->ssitr;
678 case SSDR:
679 if (!s->enable)
680 return 0xffffffff;
681 if (s->rx_level < 1) {
682 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
683 return 0xffffffff;
684 }
685 s->rx_level --;
686 retval = s->rx_fifo[s->rx_start ++];
687 s->rx_start &= 0xf;
688 pxa2xx_ssp_fifo_update(s);
689 return retval;
690 case SSTSA:
691 return s->sstsa;
692 case SSRSA:
693 return s->ssrsa;
694 case SSTSS:
695 return 0;
696 case SSACD:
697 return s->ssacd;
698 default:
699 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
700 break;
701 }
702 return 0;
703 }
704
705 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
706 uint32_t value)
707 {
708 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
709
710 switch (addr) {
711 case SSCR0:
712 s->sscr[0] = value & 0xc7ffffff;
713 s->enable = value & SSCR0_SSE;
714 if (value & SSCR0_MOD)
715 printf("%s: Attempt to use network mode\n", __FUNCTION__);
716 if (s->enable && SSCR0_DSS(value) < 4)
717 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
718 SSCR0_DSS(value));
719 if (!(value & SSCR0_SSE)) {
720 s->sssr = 0;
721 s->ssitr = 0;
722 s->rx_level = 0;
723 }
724 pxa2xx_ssp_fifo_update(s);
725 break;
726
727 case SSCR1:
728 s->sscr[1] = value;
729 if (value & (SSCR1_LBM | SSCR1_EFWR))
730 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
731 pxa2xx_ssp_fifo_update(s);
732 break;
733
734 case SSPSP:
735 s->sspsp = value;
736 break;
737
738 case SSTO:
739 s->ssto = value;
740 break;
741
742 case SSITR:
743 s->ssitr = value & SSITR_INT;
744 pxa2xx_ssp_int_update(s);
745 break;
746
747 case SSSR:
748 s->sssr &= ~(value & SSSR_RW);
749 pxa2xx_ssp_int_update(s);
750 break;
751
752 case SSDR:
753 if (SSCR0_UWIRE(s->sscr[0])) {
754 if (s->sscr[1] & SSCR1_MWDS)
755 value &= 0xffff;
756 else
757 value &= 0xff;
758 } else
759 /* Note how 32bits overflow does no harm here */
760 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
761
762 /* Data goes from here to the Tx FIFO and is shifted out from
763 * there directly to the slave, no need to buffer it.
764 */
765 if (s->enable) {
766 uint32_t readval;
767 readval = ssi_transfer(s->bus, value);
768 if (s->rx_level < 0x10) {
769 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
770 } else {
771 s->sssr |= SSSR_ROR;
772 }
773 }
774 pxa2xx_ssp_fifo_update(s);
775 break;
776
777 case SSTSA:
778 s->sstsa = value;
779 break;
780
781 case SSRSA:
782 s->ssrsa = value;
783 break;
784
785 case SSACD:
786 s->ssacd = value;
787 break;
788
789 default:
790 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
791 break;
792 }
793 }
794
795 static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = {
796 pxa2xx_ssp_read,
797 pxa2xx_ssp_read,
798 pxa2xx_ssp_read,
799 };
800
801 static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = {
802 pxa2xx_ssp_write,
803 pxa2xx_ssp_write,
804 pxa2xx_ssp_write,
805 };
806
807 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
808 {
809 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
810 int i;
811
812 qemu_put_be32(f, s->enable);
813
814 qemu_put_be32s(f, &s->sscr[0]);
815 qemu_put_be32s(f, &s->sscr[1]);
816 qemu_put_be32s(f, &s->sspsp);
817 qemu_put_be32s(f, &s->ssto);
818 qemu_put_be32s(f, &s->ssitr);
819 qemu_put_be32s(f, &s->sssr);
820 qemu_put_8s(f, &s->sstsa);
821 qemu_put_8s(f, &s->ssrsa);
822 qemu_put_8s(f, &s->ssacd);
823
824 qemu_put_byte(f, s->rx_level);
825 for (i = 0; i < s->rx_level; i ++)
826 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
827 }
828
829 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
830 {
831 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
832 int i;
833
834 s->enable = qemu_get_be32(f);
835
836 qemu_get_be32s(f, &s->sscr[0]);
837 qemu_get_be32s(f, &s->sscr[1]);
838 qemu_get_be32s(f, &s->sspsp);
839 qemu_get_be32s(f, &s->ssto);
840 qemu_get_be32s(f, &s->ssitr);
841 qemu_get_be32s(f, &s->sssr);
842 qemu_get_8s(f, &s->sstsa);
843 qemu_get_8s(f, &s->ssrsa);
844 qemu_get_8s(f, &s->ssacd);
845
846 s->rx_level = qemu_get_byte(f);
847 s->rx_start = 0;
848 for (i = 0; i < s->rx_level; i ++)
849 s->rx_fifo[i] = qemu_get_byte(f);
850
851 return 0;
852 }
853
854 static int pxa2xx_ssp_init(SysBusDevice *dev)
855 {
856 int iomemtype;
857 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
858
859 sysbus_init_irq(dev, &s->irq);
860
861 iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn,
862 pxa2xx_ssp_writefn, s);
863 sysbus_init_mmio(dev, 0x1000, iomemtype);
864 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
865 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
866
867 s->bus = ssi_create_bus(&dev->qdev, "ssi");
868 return 0;
869 }
870
871 /* Real-Time Clock */
872 #define RCNR 0x00 /* RTC Counter register */
873 #define RTAR 0x04 /* RTC Alarm register */
874 #define RTSR 0x08 /* RTC Status register */
875 #define RTTR 0x0c /* RTC Timer Trim register */
876 #define RDCR 0x10 /* RTC Day Counter register */
877 #define RYCR 0x14 /* RTC Year Counter register */
878 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
879 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
880 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
881 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
882 #define SWCR 0x28 /* RTC Stopwatch Counter register */
883 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
884 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
885 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
886 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
887
888 static inline void pxa2xx_rtc_int_update(PXA2xxState *s)
889 {
890 qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
891 }
892
893 static void pxa2xx_rtc_hzupdate(PXA2xxState *s)
894 {
895 int64_t rt = qemu_get_clock(rt_clock);
896 s->last_rcnr += ((rt - s->last_hz) << 15) /
897 (1000 * ((s->rttr & 0xffff) + 1));
898 s->last_rdcr += ((rt - s->last_hz) << 15) /
899 (1000 * ((s->rttr & 0xffff) + 1));
900 s->last_hz = rt;
901 }
902
903 static void pxa2xx_rtc_swupdate(PXA2xxState *s)
904 {
905 int64_t rt = qemu_get_clock(rt_clock);
906 if (s->rtsr & (1 << 12))
907 s->last_swcr += (rt - s->last_sw) / 10;
908 s->last_sw = rt;
909 }
910
911 static void pxa2xx_rtc_piupdate(PXA2xxState *s)
912 {
913 int64_t rt = qemu_get_clock(rt_clock);
914 if (s->rtsr & (1 << 15))
915 s->last_swcr += rt - s->last_pi;
916 s->last_pi = rt;
917 }
918
919 static inline void pxa2xx_rtc_alarm_update(PXA2xxState *s,
920 uint32_t rtsr)
921 {
922 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
923 qemu_mod_timer(s->rtc_hz, s->last_hz +
924 (((s->rtar - s->last_rcnr) * 1000 *
925 ((s->rttr & 0xffff) + 1)) >> 15));
926 else
927 qemu_del_timer(s->rtc_hz);
928
929 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
930 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
931 (((s->rdar1 - s->last_rdcr) * 1000 *
932 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
933 else
934 qemu_del_timer(s->rtc_rdal1);
935
936 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
937 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
938 (((s->rdar2 - s->last_rdcr) * 1000 *
939 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
940 else
941 qemu_del_timer(s->rtc_rdal2);
942
943 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
944 qemu_mod_timer(s->rtc_swal1, s->last_sw +
945 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
946 else
947 qemu_del_timer(s->rtc_swal1);
948
949 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
950 qemu_mod_timer(s->rtc_swal2, s->last_sw +
951 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
952 else
953 qemu_del_timer(s->rtc_swal2);
954
955 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
956 qemu_mod_timer(s->rtc_pi, s->last_pi +
957 (s->piar & 0xffff) - s->last_rtcpicr);
958 else
959 qemu_del_timer(s->rtc_pi);
960 }
961
962 static inline void pxa2xx_rtc_hz_tick(void *opaque)
963 {
964 PXA2xxState *s = (PXA2xxState *) opaque;
965 s->rtsr |= (1 << 0);
966 pxa2xx_rtc_alarm_update(s, s->rtsr);
967 pxa2xx_rtc_int_update(s);
968 }
969
970 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
971 {
972 PXA2xxState *s = (PXA2xxState *) opaque;
973 s->rtsr |= (1 << 4);
974 pxa2xx_rtc_alarm_update(s, s->rtsr);
975 pxa2xx_rtc_int_update(s);
976 }
977
978 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
979 {
980 PXA2xxState *s = (PXA2xxState *) opaque;
981 s->rtsr |= (1 << 6);
982 pxa2xx_rtc_alarm_update(s, s->rtsr);
983 pxa2xx_rtc_int_update(s);
984 }
985
986 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
987 {
988 PXA2xxState *s = (PXA2xxState *) opaque;
989 s->rtsr |= (1 << 8);
990 pxa2xx_rtc_alarm_update(s, s->rtsr);
991 pxa2xx_rtc_int_update(s);
992 }
993
994 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
995 {
996 PXA2xxState *s = (PXA2xxState *) opaque;
997 s->rtsr |= (1 << 10);
998 pxa2xx_rtc_alarm_update(s, s->rtsr);
999 pxa2xx_rtc_int_update(s);
1000 }
1001
1002 static inline void pxa2xx_rtc_pi_tick(void *opaque)
1003 {
1004 PXA2xxState *s = (PXA2xxState *) opaque;
1005 s->rtsr |= (1 << 13);
1006 pxa2xx_rtc_piupdate(s);
1007 s->last_rtcpicr = 0;
1008 pxa2xx_rtc_alarm_update(s, s->rtsr);
1009 pxa2xx_rtc_int_update(s);
1010 }
1011
1012 static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
1013 {
1014 PXA2xxState *s = (PXA2xxState *) opaque;
1015
1016 switch (addr) {
1017 case RTTR:
1018 return s->rttr;
1019 case RTSR:
1020 return s->rtsr;
1021 case RTAR:
1022 return s->rtar;
1023 case RDAR1:
1024 return s->rdar1;
1025 case RDAR2:
1026 return s->rdar2;
1027 case RYAR1:
1028 return s->ryar1;
1029 case RYAR2:
1030 return s->ryar2;
1031 case SWAR1:
1032 return s->swar1;
1033 case SWAR2:
1034 return s->swar2;
1035 case PIAR:
1036 return s->piar;
1037 case RCNR:
1038 return s->last_rcnr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1039 (1000 * ((s->rttr & 0xffff) + 1));
1040 case RDCR:
1041 return s->last_rdcr + ((qemu_get_clock(rt_clock) - s->last_hz) << 15) /
1042 (1000 * ((s->rttr & 0xffff) + 1));
1043 case RYCR:
1044 return s->last_rycr;
1045 case SWCR:
1046 if (s->rtsr & (1 << 12))
1047 return s->last_swcr + (qemu_get_clock(rt_clock) - s->last_sw) / 10;
1048 else
1049 return s->last_swcr;
1050 default:
1051 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1052 break;
1053 }
1054 return 0;
1055 }
1056
1057 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1058 uint32_t value)
1059 {
1060 PXA2xxState *s = (PXA2xxState *) opaque;
1061
1062 switch (addr) {
1063 case RTTR:
1064 if (!(s->rttr & (1 << 31))) {
1065 pxa2xx_rtc_hzupdate(s);
1066 s->rttr = value;
1067 pxa2xx_rtc_alarm_update(s, s->rtsr);
1068 }
1069 break;
1070
1071 case RTSR:
1072 if ((s->rtsr ^ value) & (1 << 15))
1073 pxa2xx_rtc_piupdate(s);
1074
1075 if ((s->rtsr ^ value) & (1 << 12))
1076 pxa2xx_rtc_swupdate(s);
1077
1078 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1079 pxa2xx_rtc_alarm_update(s, value);
1080
1081 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1082 pxa2xx_rtc_int_update(s);
1083 break;
1084
1085 case RTAR:
1086 s->rtar = value;
1087 pxa2xx_rtc_alarm_update(s, s->rtsr);
1088 break;
1089
1090 case RDAR1:
1091 s->rdar1 = value;
1092 pxa2xx_rtc_alarm_update(s, s->rtsr);
1093 break;
1094
1095 case RDAR2:
1096 s->rdar2 = value;
1097 pxa2xx_rtc_alarm_update(s, s->rtsr);
1098 break;
1099
1100 case RYAR1:
1101 s->ryar1 = value;
1102 pxa2xx_rtc_alarm_update(s, s->rtsr);
1103 break;
1104
1105 case RYAR2:
1106 s->ryar2 = value;
1107 pxa2xx_rtc_alarm_update(s, s->rtsr);
1108 break;
1109
1110 case SWAR1:
1111 pxa2xx_rtc_swupdate(s);
1112 s->swar1 = value;
1113 s->last_swcr = 0;
1114 pxa2xx_rtc_alarm_update(s, s->rtsr);
1115 break;
1116
1117 case SWAR2:
1118 s->swar2 = value;
1119 pxa2xx_rtc_alarm_update(s, s->rtsr);
1120 break;
1121
1122 case PIAR:
1123 s->piar = value;
1124 pxa2xx_rtc_alarm_update(s, s->rtsr);
1125 break;
1126
1127 case RCNR:
1128 pxa2xx_rtc_hzupdate(s);
1129 s->last_rcnr = value;
1130 pxa2xx_rtc_alarm_update(s, s->rtsr);
1131 break;
1132
1133 case RDCR:
1134 pxa2xx_rtc_hzupdate(s);
1135 s->last_rdcr = value;
1136 pxa2xx_rtc_alarm_update(s, s->rtsr);
1137 break;
1138
1139 case RYCR:
1140 s->last_rycr = value;
1141 break;
1142
1143 case SWCR:
1144 pxa2xx_rtc_swupdate(s);
1145 s->last_swcr = value;
1146 pxa2xx_rtc_alarm_update(s, s->rtsr);
1147 break;
1148
1149 case RTCPICR:
1150 pxa2xx_rtc_piupdate(s);
1151 s->last_rtcpicr = value & 0xffff;
1152 pxa2xx_rtc_alarm_update(s, s->rtsr);
1153 break;
1154
1155 default:
1156 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1157 }
1158 }
1159
1160 static CPUReadMemoryFunc * const pxa2xx_rtc_readfn[] = {
1161 pxa2xx_rtc_read,
1162 pxa2xx_rtc_read,
1163 pxa2xx_rtc_read,
1164 };
1165
1166 static CPUWriteMemoryFunc * const pxa2xx_rtc_writefn[] = {
1167 pxa2xx_rtc_write,
1168 pxa2xx_rtc_write,
1169 pxa2xx_rtc_write,
1170 };
1171
1172 static void pxa2xx_rtc_init(PXA2xxState *s)
1173 {
1174 struct tm tm;
1175 int wom;
1176
1177 s->rttr = 0x7fff;
1178 s->rtsr = 0;
1179
1180 qemu_get_timedate(&tm, 0);
1181 wom = ((tm.tm_mday - 1) / 7) + 1;
1182
1183 s->last_rcnr = (uint32_t) mktimegm(&tm);
1184 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1185 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1186 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1187 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1188 s->last_swcr = (tm.tm_hour << 19) |
1189 (tm.tm_min << 13) | (tm.tm_sec << 7);
1190 s->last_rtcpicr = 0;
1191 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
1192
1193 s->rtc_hz = qemu_new_timer(rt_clock, pxa2xx_rtc_hz_tick, s);
1194 s->rtc_rdal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1195 s->rtc_rdal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1196 s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
1197 s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
1198 s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
1199 }
1200
1201 static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
1202 {
1203 PXA2xxState *s = (PXA2xxState *) opaque;
1204
1205 pxa2xx_rtc_hzupdate(s);
1206 pxa2xx_rtc_piupdate(s);
1207 pxa2xx_rtc_swupdate(s);
1208
1209 qemu_put_be32s(f, &s->rttr);
1210 qemu_put_be32s(f, &s->rtsr);
1211 qemu_put_be32s(f, &s->rtar);
1212 qemu_put_be32s(f, &s->rdar1);
1213 qemu_put_be32s(f, &s->rdar2);
1214 qemu_put_be32s(f, &s->ryar1);
1215 qemu_put_be32s(f, &s->ryar2);
1216 qemu_put_be32s(f, &s->swar1);
1217 qemu_put_be32s(f, &s->swar2);
1218 qemu_put_be32s(f, &s->piar);
1219 qemu_put_be32s(f, &s->last_rcnr);
1220 qemu_put_be32s(f, &s->last_rdcr);
1221 qemu_put_be32s(f, &s->last_rycr);
1222 qemu_put_be32s(f, &s->last_swcr);
1223 qemu_put_be32s(f, &s->last_rtcpicr);
1224 qemu_put_sbe64s(f, &s->last_hz);
1225 qemu_put_sbe64s(f, &s->last_sw);
1226 qemu_put_sbe64s(f, &s->last_pi);
1227 }
1228
1229 static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
1230 {
1231 PXA2xxState *s = (PXA2xxState *) opaque;
1232
1233 qemu_get_be32s(f, &s->rttr);
1234 qemu_get_be32s(f, &s->rtsr);
1235 qemu_get_be32s(f, &s->rtar);
1236 qemu_get_be32s(f, &s->rdar1);
1237 qemu_get_be32s(f, &s->rdar2);
1238 qemu_get_be32s(f, &s->ryar1);
1239 qemu_get_be32s(f, &s->ryar2);
1240 qemu_get_be32s(f, &s->swar1);
1241 qemu_get_be32s(f, &s->swar2);
1242 qemu_get_be32s(f, &s->piar);
1243 qemu_get_be32s(f, &s->last_rcnr);
1244 qemu_get_be32s(f, &s->last_rdcr);
1245 qemu_get_be32s(f, &s->last_rycr);
1246 qemu_get_be32s(f, &s->last_swcr);
1247 qemu_get_be32s(f, &s->last_rtcpicr);
1248 qemu_get_sbe64s(f, &s->last_hz);
1249 qemu_get_sbe64s(f, &s->last_sw);
1250 qemu_get_sbe64s(f, &s->last_pi);
1251
1252 pxa2xx_rtc_alarm_update(s, s->rtsr);
1253
1254 return 0;
1255 }
1256
1257 /* I2C Interface */
1258 typedef struct {
1259 i2c_slave i2c;
1260 PXA2xxI2CState *host;
1261 } PXA2xxI2CSlaveState;
1262
1263 struct PXA2xxI2CState {
1264 PXA2xxI2CSlaveState *slave;
1265 i2c_bus *bus;
1266 qemu_irq irq;
1267 target_phys_addr_t offset;
1268
1269 uint16_t control;
1270 uint16_t status;
1271 uint8_t ibmr;
1272 uint8_t data;
1273 };
1274
1275 #define IBMR 0x80 /* I2C Bus Monitor register */
1276 #define IDBR 0x88 /* I2C Data Buffer register */
1277 #define ICR 0x90 /* I2C Control register */
1278 #define ISR 0x98 /* I2C Status register */
1279 #define ISAR 0xa0 /* I2C Slave Address register */
1280
1281 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1282 {
1283 uint16_t level = 0;
1284 level |= s->status & s->control & (1 << 10); /* BED */
1285 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1286 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1287 level |= s->status & (1 << 9); /* SAD */
1288 qemu_set_irq(s->irq, !!level);
1289 }
1290
1291 /* These are only stubs now. */
1292 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1293 {
1294 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1295 PXA2xxI2CState *s = slave->host;
1296
1297 switch (event) {
1298 case I2C_START_SEND:
1299 s->status |= (1 << 9); /* set SAD */
1300 s->status &= ~(1 << 0); /* clear RWM */
1301 break;
1302 case I2C_START_RECV:
1303 s->status |= (1 << 9); /* set SAD */
1304 s->status |= 1 << 0; /* set RWM */
1305 break;
1306 case I2C_FINISH:
1307 s->status |= (1 << 4); /* set SSD */
1308 break;
1309 case I2C_NACK:
1310 s->status |= 1 << 1; /* set ACKNAK */
1311 break;
1312 }
1313 pxa2xx_i2c_update(s);
1314 }
1315
1316 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1317 {
1318 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1319 PXA2xxI2CState *s = slave->host;
1320 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1321 return 0;
1322
1323 if (s->status & (1 << 0)) { /* RWM */
1324 s->status |= 1 << 6; /* set ITE */
1325 }
1326 pxa2xx_i2c_update(s);
1327
1328 return s->data;
1329 }
1330
1331 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1332 {
1333 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1334 PXA2xxI2CState *s = slave->host;
1335 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1336 return 1;
1337
1338 if (!(s->status & (1 << 0))) { /* RWM */
1339 s->status |= 1 << 7; /* set IRF */
1340 s->data = data;
1341 }
1342 pxa2xx_i2c_update(s);
1343
1344 return 1;
1345 }
1346
1347 static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
1348 {
1349 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1350
1351 addr -= s->offset;
1352 switch (addr) {
1353 case ICR:
1354 return s->control;
1355 case ISR:
1356 return s->status | (i2c_bus_busy(s->bus) << 2);
1357 case ISAR:
1358 return s->slave->i2c.address;
1359 case IDBR:
1360 return s->data;
1361 case IBMR:
1362 if (s->status & (1 << 2))
1363 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1364 else
1365 s->ibmr = 0;
1366 return s->ibmr;
1367 default:
1368 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1369 break;
1370 }
1371 return 0;
1372 }
1373
1374 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1375 uint32_t value)
1376 {
1377 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1378 int ack;
1379
1380 addr -= s->offset;
1381 switch (addr) {
1382 case ICR:
1383 s->control = value & 0xfff7;
1384 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1385 /* TODO: slave mode */
1386 if (value & (1 << 0)) { /* START condition */
1387 if (s->data & 1)
1388 s->status |= 1 << 0; /* set RWM */
1389 else
1390 s->status &= ~(1 << 0); /* clear RWM */
1391 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1392 } else {
1393 if (s->status & (1 << 0)) { /* RWM */
1394 s->data = i2c_recv(s->bus);
1395 if (value & (1 << 2)) /* ACKNAK */
1396 i2c_nack(s->bus);
1397 ack = 1;
1398 } else
1399 ack = !i2c_send(s->bus, s->data);
1400 }
1401
1402 if (value & (1 << 1)) /* STOP condition */
1403 i2c_end_transfer(s->bus);
1404
1405 if (ack) {
1406 if (value & (1 << 0)) /* START condition */
1407 s->status |= 1 << 6; /* set ITE */
1408 else
1409 if (s->status & (1 << 0)) /* RWM */
1410 s->status |= 1 << 7; /* set IRF */
1411 else
1412 s->status |= 1 << 6; /* set ITE */
1413 s->status &= ~(1 << 1); /* clear ACKNAK */
1414 } else {
1415 s->status |= 1 << 6; /* set ITE */
1416 s->status |= 1 << 10; /* set BED */
1417 s->status |= 1 << 1; /* set ACKNAK */
1418 }
1419 }
1420 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1421 if (value & (1 << 4)) /* MA */
1422 i2c_end_transfer(s->bus);
1423 pxa2xx_i2c_update(s);
1424 break;
1425
1426 case ISR:
1427 s->status &= ~(value & 0x07f0);
1428 pxa2xx_i2c_update(s);
1429 break;
1430
1431 case ISAR:
1432 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1433 break;
1434
1435 case IDBR:
1436 s->data = value & 0xff;
1437 break;
1438
1439 default:
1440 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1441 }
1442 }
1443
1444 static CPUReadMemoryFunc * const pxa2xx_i2c_readfn[] = {
1445 pxa2xx_i2c_read,
1446 pxa2xx_i2c_read,
1447 pxa2xx_i2c_read,
1448 };
1449
1450 static CPUWriteMemoryFunc * const pxa2xx_i2c_writefn[] = {
1451 pxa2xx_i2c_write,
1452 pxa2xx_i2c_write,
1453 pxa2xx_i2c_write,
1454 };
1455
1456 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1457 .name = "pxa2xx_i2c_slave",
1458 .version_id = 1,
1459 .minimum_version_id = 1,
1460 .minimum_version_id_old = 1,
1461 .fields = (VMStateField []) {
1462 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1463 VMSTATE_END_OF_LIST()
1464 }
1465 };
1466
1467 static const VMStateDescription vmstate_pxa2xx_i2c = {
1468 .name = "pxa2xx_i2c",
1469 .version_id = 1,
1470 .minimum_version_id = 1,
1471 .minimum_version_id_old = 1,
1472 .fields = (VMStateField []) {
1473 VMSTATE_UINT16(control, PXA2xxI2CState),
1474 VMSTATE_UINT16(status, PXA2xxI2CState),
1475 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1476 VMSTATE_UINT8(data, PXA2xxI2CState),
1477 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1478 vmstate_pxa2xx_i2c, PXA2xxI2CSlaveState *),
1479 VMSTATE_END_OF_LIST()
1480 }
1481 };
1482
1483 static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
1484 {
1485 /* Nothing to do. */
1486 return 0;
1487 }
1488
1489 static I2CSlaveInfo pxa2xx_i2c_slave_info = {
1490 .qdev.name = "pxa2xx-i2c-slave",
1491 .qdev.size = sizeof(PXA2xxI2CSlaveState),
1492 .init = pxa2xx_i2c_slave_init,
1493 .event = pxa2xx_i2c_event,
1494 .recv = pxa2xx_i2c_rx,
1495 .send = pxa2xx_i2c_tx
1496 };
1497
1498 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1499 qemu_irq irq, uint32_t region_size)
1500 {
1501 int iomemtype;
1502 DeviceState *dev;
1503 PXA2xxI2CState *s = qemu_mallocz(sizeof(PXA2xxI2CState));
1504
1505 /* FIXME: Should the slave device really be on a separate bus? */
1506 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1507 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1508 s->slave->host = s;
1509
1510 s->irq = irq;
1511 s->bus = i2c_init_bus(NULL, "i2c");
1512 s->offset = base - (base & (~region_size) & TARGET_PAGE_MASK);
1513
1514 iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn,
1515 pxa2xx_i2c_writefn, s);
1516 cpu_register_physical_memory(base & ~region_size,
1517 region_size + 1, iomemtype);
1518
1519 vmstate_register(NULL, base, &vmstate_pxa2xx_i2c, s);
1520
1521 return s;
1522 }
1523
1524 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1525 {
1526 return s->bus;
1527 }
1528
1529 /* PXA Inter-IC Sound Controller */
1530 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1531 {
1532 i2s->rx_len = 0;
1533 i2s->tx_len = 0;
1534 i2s->fifo_len = 0;
1535 i2s->clk = 0x1a;
1536 i2s->control[0] = 0x00;
1537 i2s->control[1] = 0x00;
1538 i2s->status = 0x00;
1539 i2s->mask = 0x00;
1540 }
1541
1542 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1543 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1544 #define SACR_DREC(val) (val & (1 << 3))
1545 #define SACR_DPRL(val) (val & (1 << 4))
1546
1547 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1548 {
1549 int rfs, tfs;
1550 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1551 !SACR_DREC(i2s->control[1]);
1552 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1553 i2s->enable && !SACR_DPRL(i2s->control[1]);
1554
1555 pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
1556 pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
1557
1558 i2s->status &= 0xe0;
1559 if (i2s->fifo_len < 16 || !i2s->enable)
1560 i2s->status |= 1 << 0; /* TNF */
1561 if (i2s->rx_len)
1562 i2s->status |= 1 << 1; /* RNE */
1563 if (i2s->enable)
1564 i2s->status |= 1 << 2; /* BSY */
1565 if (tfs)
1566 i2s->status |= 1 << 3; /* TFS */
1567 if (rfs)
1568 i2s->status |= 1 << 4; /* RFS */
1569 if (!(i2s->tx_len && i2s->enable))
1570 i2s->status |= i2s->fifo_len << 8; /* TFL */
1571 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1572
1573 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1574 }
1575
1576 #define SACR0 0x00 /* Serial Audio Global Control register */
1577 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1578 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1579 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1580 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1581 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1582 #define SADR 0x80 /* Serial Audio Data register */
1583
1584 static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
1585 {
1586 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1587
1588 switch (addr) {
1589 case SACR0:
1590 return s->control[0];
1591 case SACR1:
1592 return s->control[1];
1593 case SASR0:
1594 return s->status;
1595 case SAIMR:
1596 return s->mask;
1597 case SAICR:
1598 return 0;
1599 case SADIV:
1600 return s->clk;
1601 case SADR:
1602 if (s->rx_len > 0) {
1603 s->rx_len --;
1604 pxa2xx_i2s_update(s);
1605 return s->codec_in(s->opaque);
1606 }
1607 return 0;
1608 default:
1609 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1610 break;
1611 }
1612 return 0;
1613 }
1614
1615 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1616 uint32_t value)
1617 {
1618 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1619 uint32_t *sample;
1620
1621 switch (addr) {
1622 case SACR0:
1623 if (value & (1 << 3)) /* RST */
1624 pxa2xx_i2s_reset(s);
1625 s->control[0] = value & 0xff3d;
1626 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1627 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1628 s->codec_out(s->opaque, *sample);
1629 s->status &= ~(1 << 7); /* I2SOFF */
1630 }
1631 if (value & (1 << 4)) /* EFWR */
1632 printf("%s: Attempt to use special function\n", __FUNCTION__);
1633 s->enable = ((value ^ 4) & 5) == 5; /* ENB && !RST*/
1634 pxa2xx_i2s_update(s);
1635 break;
1636 case SACR1:
1637 s->control[1] = value & 0x0039;
1638 if (value & (1 << 5)) /* ENLBF */
1639 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1640 if (value & (1 << 4)) /* DPRL */
1641 s->fifo_len = 0;
1642 pxa2xx_i2s_update(s);
1643 break;
1644 case SAIMR:
1645 s->mask = value & 0x0078;
1646 pxa2xx_i2s_update(s);
1647 break;
1648 case SAICR:
1649 s->status &= ~(value & (3 << 5));
1650 pxa2xx_i2s_update(s);
1651 break;
1652 case SADIV:
1653 s->clk = value & 0x007f;
1654 break;
1655 case SADR:
1656 if (s->tx_len && s->enable) {
1657 s->tx_len --;
1658 pxa2xx_i2s_update(s);
1659 s->codec_out(s->opaque, value);
1660 } else if (s->fifo_len < 16) {
1661 s->fifo[s->fifo_len ++] = value;
1662 pxa2xx_i2s_update(s);
1663 }
1664 break;
1665 default:
1666 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1667 }
1668 }
1669
1670 static CPUReadMemoryFunc * const pxa2xx_i2s_readfn[] = {
1671 pxa2xx_i2s_read,
1672 pxa2xx_i2s_read,
1673 pxa2xx_i2s_read,
1674 };
1675
1676 static CPUWriteMemoryFunc * const pxa2xx_i2s_writefn[] = {
1677 pxa2xx_i2s_write,
1678 pxa2xx_i2s_write,
1679 pxa2xx_i2s_write,
1680 };
1681
1682 static void pxa2xx_i2s_save(QEMUFile *f, void *opaque)
1683 {
1684 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1685
1686 qemu_put_be32s(f, &s->control[0]);
1687 qemu_put_be32s(f, &s->control[1]);
1688 qemu_put_be32s(f, &s->status);
1689 qemu_put_be32s(f, &s->mask);
1690 qemu_put_be32s(f, &s->clk);
1691
1692 qemu_put_be32(f, s->enable);
1693 qemu_put_be32(f, s->rx_len);
1694 qemu_put_be32(f, s->tx_len);
1695 qemu_put_be32(f, s->fifo_len);
1696 }
1697
1698 static int pxa2xx_i2s_load(QEMUFile *f, void *opaque, int version_id)
1699 {
1700 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1701
1702 qemu_get_be32s(f, &s->control[0]);
1703 qemu_get_be32s(f, &s->control[1]);
1704 qemu_get_be32s(f, &s->status);
1705 qemu_get_be32s(f, &s->mask);
1706 qemu_get_be32s(f, &s->clk);
1707
1708 s->enable = qemu_get_be32(f);
1709 s->rx_len = qemu_get_be32(f);
1710 s->tx_len = qemu_get_be32(f);
1711 s->fifo_len = qemu_get_be32(f);
1712
1713 return 0;
1714 }
1715
1716 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1717 {
1718 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1719 uint32_t *sample;
1720
1721 /* Signal FIFO errors */
1722 if (s->enable && s->tx_len)
1723 s->status |= 1 << 5; /* TUR */
1724 if (s->enable && s->rx_len)
1725 s->status |= 1 << 6; /* ROR */
1726
1727 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1728 * handle the cases where it makes a difference. */
1729 s->tx_len = tx - s->fifo_len;
1730 s->rx_len = rx;
1731 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1732 if (s->enable)
1733 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1734 s->codec_out(s->opaque, *sample);
1735 pxa2xx_i2s_update(s);
1736 }
1737
1738 static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
1739 qemu_irq irq, PXA2xxDMAState *dma)
1740 {
1741 int iomemtype;
1742 PXA2xxI2SState *s = (PXA2xxI2SState *)
1743 qemu_mallocz(sizeof(PXA2xxI2SState));
1744
1745 s->irq = irq;
1746 s->dma = dma;
1747 s->data_req = pxa2xx_i2s_data_req;
1748
1749 pxa2xx_i2s_reset(s);
1750
1751 iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn,
1752 pxa2xx_i2s_writefn, s);
1753 cpu_register_physical_memory(base, 0x100000, iomemtype);
1754
1755 register_savevm(NULL, "pxa2xx_i2s", base, 0,
1756 pxa2xx_i2s_save, pxa2xx_i2s_load, s);
1757
1758 return s;
1759 }
1760
1761 /* PXA Fast Infra-red Communications Port */
1762 struct PXA2xxFIrState {
1763 qemu_irq irq;
1764 PXA2xxDMAState *dma;
1765 int enable;
1766 CharDriverState *chr;
1767
1768 uint8_t control[3];
1769 uint8_t status[2];
1770
1771 int rx_len;
1772 int rx_start;
1773 uint8_t rx_fifo[64];
1774 };
1775
1776 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1777 {
1778 s->control[0] = 0x00;
1779 s->control[1] = 0x00;
1780 s->control[2] = 0x00;
1781 s->status[0] = 0x00;
1782 s->status[1] = 0x00;
1783 s->enable = 0;
1784 }
1785
1786 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1787 {
1788 static const int tresh[4] = { 8, 16, 32, 0 };
1789 int intr = 0;
1790 if ((s->control[0] & (1 << 4)) && /* RXE */
1791 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1792 s->status[0] |= 1 << 4; /* RFS */
1793 else
1794 s->status[0] &= ~(1 << 4); /* RFS */
1795 if (s->control[0] & (1 << 3)) /* TXE */
1796 s->status[0] |= 1 << 3; /* TFS */
1797 else
1798 s->status[0] &= ~(1 << 3); /* TFS */
1799 if (s->rx_len)
1800 s->status[1] |= 1 << 2; /* RNE */
1801 else
1802 s->status[1] &= ~(1 << 2); /* RNE */
1803 if (s->control[0] & (1 << 4)) /* RXE */
1804 s->status[1] |= 1 << 0; /* RSY */
1805 else
1806 s->status[1] &= ~(1 << 0); /* RSY */
1807
1808 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1809 (s->status[0] & (1 << 4)); /* RFS */
1810 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1811 (s->status[0] & (1 << 3)); /* TFS */
1812 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1813 (s->status[0] & (1 << 6)); /* EOC */
1814 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1815 (s->status[0] & (1 << 1)); /* TUR */
1816 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1817
1818 pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
1819 pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
1820
1821 qemu_set_irq(s->irq, intr && s->enable);
1822 }
1823
1824 #define ICCR0 0x00 /* FICP Control register 0 */
1825 #define ICCR1 0x04 /* FICP Control register 1 */
1826 #define ICCR2 0x08 /* FICP Control register 2 */
1827 #define ICDR 0x0c /* FICP Data register */
1828 #define ICSR0 0x14 /* FICP Status register 0 */
1829 #define ICSR1 0x18 /* FICP Status register 1 */
1830 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1831
1832 static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr)
1833 {
1834 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1835 uint8_t ret;
1836
1837 switch (addr) {
1838 case ICCR0:
1839 return s->control[0];
1840 case ICCR1:
1841 return s->control[1];
1842 case ICCR2:
1843 return s->control[2];
1844 case ICDR:
1845 s->status[0] &= ~0x01;
1846 s->status[1] &= ~0x72;
1847 if (s->rx_len) {
1848 s->rx_len --;
1849 ret = s->rx_fifo[s->rx_start ++];
1850 s->rx_start &= 63;
1851 pxa2xx_fir_update(s);
1852 return ret;
1853 }
1854 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1855 break;
1856 case ICSR0:
1857 return s->status[0];
1858 case ICSR1:
1859 return s->status[1] | (1 << 3); /* TNF */
1860 case ICFOR:
1861 return s->rx_len;
1862 default:
1863 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1864 break;
1865 }
1866 return 0;
1867 }
1868
1869 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1870 uint32_t value)
1871 {
1872 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1873 uint8_t ch;
1874
1875 switch (addr) {
1876 case ICCR0:
1877 s->control[0] = value;
1878 if (!(value & (1 << 4))) /* RXE */
1879 s->rx_len = s->rx_start = 0;
1880 if (!(value & (1 << 3))) { /* TXE */
1881 /* Nop */
1882 }
1883 s->enable = value & 1; /* ITR */
1884 if (!s->enable)
1885 s->status[0] = 0;
1886 pxa2xx_fir_update(s);
1887 break;
1888 case ICCR1:
1889 s->control[1] = value;
1890 break;
1891 case ICCR2:
1892 s->control[2] = value & 0x3f;
1893 pxa2xx_fir_update(s);
1894 break;
1895 case ICDR:
1896 if (s->control[2] & (1 << 2)) /* TXP */
1897 ch = value;
1898 else
1899 ch = ~value;
1900 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1901 qemu_chr_write(s->chr, &ch, 1);
1902 break;
1903 case ICSR0:
1904 s->status[0] &= ~(value & 0x66);
1905 pxa2xx_fir_update(s);
1906 break;
1907 case ICFOR:
1908 break;
1909 default:
1910 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1911 }
1912 }
1913
1914 static CPUReadMemoryFunc * const pxa2xx_fir_readfn[] = {
1915 pxa2xx_fir_read,
1916 pxa2xx_fir_read,
1917 pxa2xx_fir_read,
1918 };
1919
1920 static CPUWriteMemoryFunc * const pxa2xx_fir_writefn[] = {
1921 pxa2xx_fir_write,
1922 pxa2xx_fir_write,
1923 pxa2xx_fir_write,
1924 };
1925
1926 static int pxa2xx_fir_is_empty(void *opaque)
1927 {
1928 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1929 return (s->rx_len < 64);
1930 }
1931
1932 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1933 {
1934 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1935 if (!(s->control[0] & (1 << 4))) /* RXE */
1936 return;
1937
1938 while (size --) {
1939 s->status[1] |= 1 << 4; /* EOF */
1940 if (s->rx_len >= 64) {
1941 s->status[1] |= 1 << 6; /* ROR */
1942 break;
1943 }
1944
1945 if (s->control[2] & (1 << 3)) /* RXP */
1946 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1947 else
1948 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1949 }
1950
1951 pxa2xx_fir_update(s);
1952 }
1953
1954 static void pxa2xx_fir_event(void *opaque, int event)
1955 {
1956 }
1957
1958 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1959 {
1960 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1961 int i;
1962
1963 qemu_put_be32(f, s->enable);
1964
1965 qemu_put_8s(f, &s->control[0]);
1966 qemu_put_8s(f, &s->control[1]);
1967 qemu_put_8s(f, &s->control[2]);
1968 qemu_put_8s(f, &s->status[0]);
1969 qemu_put_8s(f, &s->status[1]);
1970
1971 qemu_put_byte(f, s->rx_len);
1972 for (i = 0; i < s->rx_len; i ++)
1973 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1974 }
1975
1976 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1977 {
1978 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1979 int i;
1980
1981 s->enable = qemu_get_be32(f);
1982
1983 qemu_get_8s(f, &s->control[0]);
1984 qemu_get_8s(f, &s->control[1]);
1985 qemu_get_8s(f, &s->control[2]);
1986 qemu_get_8s(f, &s->status[0]);
1987 qemu_get_8s(f, &s->status[1]);
1988
1989 s->rx_len = qemu_get_byte(f);
1990 s->rx_start = 0;
1991 for (i = 0; i < s->rx_len; i ++)
1992 s->rx_fifo[i] = qemu_get_byte(f);
1993
1994 return 0;
1995 }
1996
1997 static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
1998 qemu_irq irq, PXA2xxDMAState *dma,
1999 CharDriverState *chr)
2000 {
2001 int iomemtype;
2002 PXA2xxFIrState *s = (PXA2xxFIrState *)
2003 qemu_mallocz(sizeof(PXA2xxFIrState));
2004
2005 s->irq = irq;
2006 s->dma = dma;
2007 s->chr = chr;
2008
2009 pxa2xx_fir_reset(s);
2010
2011 iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn,
2012 pxa2xx_fir_writefn, s);
2013 cpu_register_physical_memory(base, 0x1000, iomemtype);
2014
2015 if (chr)
2016 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2017 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2018
2019 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2020 pxa2xx_fir_load, s);
2021
2022 return s;
2023 }
2024
2025 static void pxa2xx_reset(void *opaque, int line, int level)
2026 {
2027 PXA2xxState *s = (PXA2xxState *) opaque;
2028
2029 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2030 cpu_reset(s->env);
2031 /* TODO: reset peripherals */
2032 }
2033 }
2034
2035 /* Initialise a PXA270 integrated chip (ARM based core). */
2036 PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
2037 {
2038 PXA2xxState *s;
2039 int iomemtype, i;
2040 DriveInfo *dinfo;
2041 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2042
2043 if (revision && strncmp(revision, "pxa27", 5)) {
2044 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2045 exit(1);
2046 }
2047 if (!revision)
2048 revision = "pxa270";
2049
2050 s->env = cpu_init(revision);
2051 if (!s->env) {
2052 fprintf(stderr, "Unable to find CPU definition\n");
2053 exit(1);
2054 }
2055 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2056
2057 /* SDRAM & Internal Memory Storage */
2058 cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
2059 sdram_size, qemu_ram_alloc(NULL, "pxa270.sdram",
2060 sdram_size) | IO_MEM_RAM);
2061 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE,
2062 0x40000, qemu_ram_alloc(NULL, "pxa270.internal",
2063 0x40000) | IO_MEM_RAM);
2064
2065 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2066
2067 s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2068
2069 pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
2070 s->pic[PXA27X_PIC_OST_4_11]);
2071
2072 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2073
2074 dinfo = drive_get(IF_SD, 0, 0);
2075 if (!dinfo) {
2076 fprintf(stderr, "qemu: missing SecureDigital device\n");
2077 exit(1);
2078 }
2079 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2080 s->pic[PXA2XX_PIC_MMC], s->dma);
2081
2082 for (i = 0; pxa270_serial[i].io_base; i ++)
2083 if (serial_hds[i])
2084 #ifdef TARGET_WORDS_BIGENDIAN
2085 serial_mm_init(pxa270_serial[i].io_base, 2,
2086 s->pic[pxa270_serial[i].irqn], 14857000/16,
2087 serial_hds[i], 1, 1);
2088 #else
2089 serial_mm_init(pxa270_serial[i].io_base, 2,
2090 s->pic[pxa270_serial[i].irqn], 14857000/16,
2091 serial_hds[i], 1, 0);
2092 #endif
2093 else
2094 break;
2095 if (serial_hds[i])
2096 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2097 s->dma, serial_hds[i]);
2098
2099 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
2100
2101 s->cm_base = 0x41300000;
2102 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2103 s->clkcfg = 0x00000009; /* Turbo mode active */
2104 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2105 pxa2xx_cm_writefn, s);
2106 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2107 register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2108
2109 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2110
2111 s->mm_base = 0x48000000;
2112 s->mm_regs[MDMRS >> 2] = 0x00020002;
2113 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2114 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2115 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2116 pxa2xx_mm_writefn, s);
2117 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2118 register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2119
2120 s->pm_base = 0x40f00000;
2121 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2122 pxa2xx_pm_writefn, s);
2123 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2124 register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2125
2126 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2127 s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2128 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2129 DeviceState *dev;
2130 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2131 s->pic[pxa27x_ssp[i].irqn]);
2132 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2133 }
2134
2135 if (usb_enabled) {
2136 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2137 s->pic[PXA2XX_PIC_USBH1]);
2138 }
2139
2140 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2141 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2142
2143 s->rtc_base = 0x40900000;
2144 iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
2145 pxa2xx_rtc_writefn, s);
2146 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2147 pxa2xx_rtc_init(s);
2148 register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
2149 pxa2xx_rtc_load, s);
2150
2151 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2152 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2153
2154 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2155
2156 s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
2157
2158 /* GPIO1 resets the processor */
2159 /* The handler can be overridden by board-specific code */
2160 pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
2161 return s;
2162 }
2163
2164 /* Initialise a PXA255 integrated chip (ARM based core). */
2165 PXA2xxState *pxa255_init(unsigned int sdram_size)
2166 {
2167 PXA2xxState *s;
2168 int iomemtype, i;
2169 DriveInfo *dinfo;
2170
2171 s = (PXA2xxState *) qemu_mallocz(sizeof(PXA2xxState));
2172
2173 s->env = cpu_init("pxa255");
2174 if (!s->env) {
2175 fprintf(stderr, "Unable to find CPU definition\n");
2176 exit(1);
2177 }
2178 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2179
2180 /* SDRAM & Internal Memory Storage */
2181 cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,
2182 qemu_ram_alloc(NULL, "pxa255.sdram",
2183 sdram_size) | IO_MEM_RAM);
2184 cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE,
2185 qemu_ram_alloc(NULL, "pxa255.internal",
2186 PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM);
2187
2188 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2189
2190 s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
2191
2192 pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
2193
2194 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2195
2196 dinfo = drive_get(IF_SD, 0, 0);
2197 if (!dinfo) {
2198 fprintf(stderr, "qemu: missing SecureDigital device\n");
2199 exit(1);
2200 }
2201 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2202 s->pic[PXA2XX_PIC_MMC], s->dma);
2203
2204 for (i = 0; pxa255_serial[i].io_base; i ++)
2205 if (serial_hds[i]) {
2206 #ifdef TARGET_WORDS_BIGENDIAN
2207 serial_mm_init(pxa255_serial[i].io_base, 2,
2208 s->pic[pxa255_serial[i].irqn], 14745600/16,
2209 serial_hds[i], 1, 1);
2210 #else
2211 serial_mm_init(pxa255_serial[i].io_base, 2,
2212 s->pic[pxa255_serial[i].irqn], 14745600/16,
2213 serial_hds[i], 1, 0);
2214 #endif
2215 } else {
2216 break;
2217 }
2218 if (serial_hds[i])
2219 s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
2220 s->dma, serial_hds[i]);
2221
2222 s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
2223
2224 s->cm_base = 0x41300000;
2225 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2226 s->clkcfg = 0x00000009; /* Turbo mode active */
2227 iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn,
2228 pxa2xx_cm_writefn, s);
2229 cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype);
2230 register_savevm(NULL, "pxa2xx_cm", 0, 0, pxa2xx_cm_save, pxa2xx_cm_load, s);
2231
2232 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2233
2234 s->mm_base = 0x48000000;
2235 s->mm_regs[MDMRS >> 2] = 0x00020002;
2236 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2237 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2238 iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn,
2239 pxa2xx_mm_writefn, s);
2240 cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype);
2241 register_savevm(NULL, "pxa2xx_mm", 0, 0, pxa2xx_mm_save, pxa2xx_mm_load, s);
2242
2243 s->pm_base = 0x40f00000;
2244 iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn,
2245 pxa2xx_pm_writefn, s);
2246 cpu_register_physical_memory(s->pm_base, 0x100, iomemtype);
2247 register_savevm(NULL, "pxa2xx_pm", 0, 0, pxa2xx_pm_save, pxa2xx_pm_load, s);
2248
2249 for (i = 0; pxa255_ssp[i].io_base; i ++);
2250 s->ssp = (SSIBus **)qemu_mallocz(sizeof(SSIBus *) * i);
2251 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2252 DeviceState *dev;
2253 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2254 s->pic[pxa255_ssp[i].irqn]);
2255 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2256 }
2257
2258 if (usb_enabled) {
2259 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2260 s->pic[PXA2XX_PIC_USBH1]);
2261 }
2262
2263 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2264 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2265
2266 s->rtc_base = 0x40900000;
2267 iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn,
2268 pxa2xx_rtc_writefn, s);
2269 cpu_register_physical_memory(s->rtc_base, 0x1000, iomemtype);
2270 pxa2xx_rtc_init(s);
2271 register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
2272 pxa2xx_rtc_load, s);
2273
2274 s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
2275 s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
2276
2277 s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
2278
2279 /* GPIO1 resets the processor */
2280 /* The handler can be overridden by board-specific code */
2281 pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
2282 return s;
2283 }
2284
2285 static void pxa2xx_register_devices(void)
2286 {
2287 i2c_register_slave(&pxa2xx_i2c_slave_info);
2288 sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init);
2289 }
2290
2291 device_init(pxa2xx_register_devices)
QEmu